1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 *
7 * Heavily based on Mediatek's pinctrl driver
8 */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/seq_file.h>
24 #include <linux/slab.h>
25
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32
33 #include "../core.h"
34 #include "../pinconf.h"
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
37
38 #define STM32_GPIO_MODER 0x00
39 #define STM32_GPIO_TYPER 0x04
40 #define STM32_GPIO_SPEEDR 0x08
41 #define STM32_GPIO_PUPDR 0x0c
42 #define STM32_GPIO_IDR 0x10
43 #define STM32_GPIO_ODR 0x14
44 #define STM32_GPIO_BSRR 0x18
45 #define STM32_GPIO_LCKR 0x1c
46 #define STM32_GPIO_AFRL 0x20
47 #define STM32_GPIO_AFRH 0x24
48 #define STM32_GPIO_SECCFGR 0x30
49
50 /* custom bitfield to backup pin status */
51 #define STM32_GPIO_BKP_MODE_SHIFT 0
52 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
53 #define STM32_GPIO_BKP_ALT_SHIFT 2
54 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
55 #define STM32_GPIO_BKP_SPEED_SHIFT 6
56 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
57 #define STM32_GPIO_BKP_PUPD_SHIFT 8
58 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
59 #define STM32_GPIO_BKP_TYPE 10
60 #define STM32_GPIO_BKP_VAL 11
61
62 #define STM32_GPIO_PINS_PER_BANK 16
63 #define STM32_GPIO_IRQ_LINE 16
64
65 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
66
67 #define gpio_range_to_bank(chip) \
68 container_of(chip, struct stm32_gpio_bank, range)
69
70 #define HWSPNLCK_TIMEOUT 1000 /* usec */
71
72 static const char * const stm32_gpio_functions[] = {
73 "gpio", "af0", "af1",
74 "af2", "af3", "af4",
75 "af5", "af6", "af7",
76 "af8", "af9", "af10",
77 "af11", "af12", "af13",
78 "af14", "af15", "analog",
79 };
80
81 struct stm32_pinctrl_group {
82 const char *name;
83 unsigned long config;
84 unsigned pin;
85 };
86
87 struct stm32_gpio_bank {
88 void __iomem *base;
89 struct clk *clk;
90 struct reset_control *rstc;
91 spinlock_t lock;
92 struct gpio_chip gpio_chip;
93 struct pinctrl_gpio_range range;
94 struct fwnode_handle *fwnode;
95 struct irq_domain *domain;
96 u32 bank_nr;
97 u32 bank_ioport_nr;
98 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
99 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
100 bool secure_control;
101 };
102
103 struct stm32_pinctrl {
104 struct device *dev;
105 struct pinctrl_dev *pctl_dev;
106 struct pinctrl_desc pctl_desc;
107 struct stm32_pinctrl_group *groups;
108 unsigned ngroups;
109 const char **grp_names;
110 struct stm32_gpio_bank *banks;
111 unsigned nbanks;
112 const struct stm32_pinctrl_match_data *match_data;
113 struct irq_domain *domain;
114 struct regmap *regmap;
115 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
116 struct hwspinlock *hwlock;
117 struct stm32_desc_pin *pins;
118 u32 npins;
119 u32 pkg;
120 u16 irqmux_map;
121 spinlock_t irqmux_lock;
122 };
123
stm32_gpio_pin(int gpio)124 static inline int stm32_gpio_pin(int gpio)
125 {
126 return gpio % STM32_GPIO_PINS_PER_BANK;
127 }
128
stm32_gpio_get_mode(u32 function)129 static inline u32 stm32_gpio_get_mode(u32 function)
130 {
131 switch (function) {
132 case STM32_PIN_GPIO:
133 return 0;
134 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
135 return 2;
136 case STM32_PIN_ANALOG:
137 return 3;
138 }
139
140 return 0;
141 }
142
stm32_gpio_get_alt(u32 function)143 static inline u32 stm32_gpio_get_alt(u32 function)
144 {
145 switch (function) {
146 case STM32_PIN_GPIO:
147 return 0;
148 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
149 return function - 1;
150 case STM32_PIN_ANALOG:
151 return 0;
152 }
153
154 return 0;
155 }
156
stm32_gpio_backup_value(struct stm32_gpio_bank * bank,u32 offset,u32 value)157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
158 u32 offset, u32 value)
159 {
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
162 }
163
stm32_gpio_backup_mode(struct stm32_gpio_bank * bank,u32 offset,u32 mode,u32 alt)164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
165 u32 mode, u32 alt)
166 {
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
168 STM32_GPIO_BKP_ALT_MASK);
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
171 }
172
stm32_gpio_backup_driving(struct stm32_gpio_bank * bank,u32 offset,u32 drive)173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
174 u32 drive)
175 {
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
178 }
179
stm32_gpio_backup_speed(struct stm32_gpio_bank * bank,u32 offset,u32 speed)180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
181 u32 speed)
182 {
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
185 }
186
stm32_gpio_backup_bias(struct stm32_gpio_bank * bank,u32 offset,u32 bias)187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
188 u32 bias)
189 {
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
192 }
193
194 /* GPIO functions */
195
__stm32_gpio_set(struct stm32_gpio_bank * bank,unsigned offset,int value)196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
197 unsigned offset, int value)
198 {
199 stm32_gpio_backup_value(bank, offset, value);
200
201 if (!value)
202 offset += STM32_GPIO_PINS_PER_BANK;
203
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
205 }
206
stm32_gpio_request(struct gpio_chip * chip,unsigned offset)207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
208 {
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 struct pinctrl_gpio_range *range;
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
213
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
215 if (!range) {
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
217 return -EINVAL;
218 }
219
220 return pinctrl_gpio_request(chip->base + offset);
221 }
222
stm32_gpio_free(struct gpio_chip * chip,unsigned offset)223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
224 {
225 pinctrl_gpio_free(chip->base + offset);
226 }
227
stm32_gpio_get(struct gpio_chip * chip,unsigned offset)228 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
229 {
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
231
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
233 }
234
stm32_gpio_set(struct gpio_chip * chip,unsigned offset,int value)235 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
236 {
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
238
239 __stm32_gpio_set(bank, offset, value);
240 }
241
stm32_gpio_direction_input(struct gpio_chip * chip,unsigned offset)242 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
243 {
244 return pinctrl_gpio_direction_input(chip->base + offset);
245 }
246
stm32_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)247 static int stm32_gpio_direction_output(struct gpio_chip *chip,
248 unsigned offset, int value)
249 {
250 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
251
252 __stm32_gpio_set(bank, offset, value);
253 pinctrl_gpio_direction_output(chip->base + offset);
254
255 return 0;
256 }
257
258
stm32_gpio_to_irq(struct gpio_chip * chip,unsigned int offset)259 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
260 {
261 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
262 struct irq_fwspec fwspec;
263
264 fwspec.fwnode = bank->fwnode;
265 fwspec.param_count = 2;
266 fwspec.param[0] = offset;
267 fwspec.param[1] = IRQ_TYPE_NONE;
268
269 return irq_create_fwspec_mapping(&fwspec);
270 }
271
stm32_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)272 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
273 {
274 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
275 int pin = stm32_gpio_pin(offset);
276 int ret;
277 u32 mode, alt;
278
279 stm32_pmx_get_mode(bank, pin, &mode, &alt);
280 if ((alt == 0) && (mode == 0))
281 ret = GPIO_LINE_DIRECTION_IN;
282 else if ((alt == 0) && (mode == 1))
283 ret = GPIO_LINE_DIRECTION_OUT;
284 else
285 ret = -EINVAL;
286
287 return ret;
288 }
289
stm32_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)290 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
291 unsigned long *valid_mask,
292 unsigned int ngpios)
293 {
294 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
295 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
296 unsigned int i;
297 u32 sec;
298
299 /* All gpio are valid per default */
300 bitmap_fill(valid_mask, ngpios);
301
302 if (bank->secure_control) {
303 /* Tag secured pins as invalid */
304 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
305
306 for (i = 0; i < ngpios; i++) {
307 if (sec & BIT(i)) {
308 clear_bit(i, valid_mask);
309 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
310 }
311 }
312 }
313
314 return 0;
315 }
316
317 static const struct gpio_chip stm32_gpio_template = {
318 .request = stm32_gpio_request,
319 .free = stm32_gpio_free,
320 .get = stm32_gpio_get,
321 .set = stm32_gpio_set,
322 .direction_input = stm32_gpio_direction_input,
323 .direction_output = stm32_gpio_direction_output,
324 .to_irq = stm32_gpio_to_irq,
325 .get_direction = stm32_gpio_get_direction,
326 .set_config = gpiochip_generic_config,
327 .init_valid_mask = stm32_gpio_init_valid_mask,
328 };
329
stm32_gpio_irq_trigger(struct irq_data * d)330 static void stm32_gpio_irq_trigger(struct irq_data *d)
331 {
332 struct stm32_gpio_bank *bank = d->domain->host_data;
333 int level;
334
335 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
336 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
337 return;
338
339 /* If level interrupt type then retrig */
340 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
341 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
342 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
343 irq_chip_retrigger_hierarchy(d);
344 }
345
stm32_gpio_irq_eoi(struct irq_data * d)346 static void stm32_gpio_irq_eoi(struct irq_data *d)
347 {
348 irq_chip_eoi_parent(d);
349 stm32_gpio_irq_trigger(d);
350 };
351
stm32_gpio_set_type(struct irq_data * d,unsigned int type)352 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
353 {
354 struct stm32_gpio_bank *bank = d->domain->host_data;
355 u32 parent_type;
356
357 switch (type) {
358 case IRQ_TYPE_EDGE_RISING:
359 case IRQ_TYPE_EDGE_FALLING:
360 case IRQ_TYPE_EDGE_BOTH:
361 parent_type = type;
362 break;
363 case IRQ_TYPE_LEVEL_HIGH:
364 parent_type = IRQ_TYPE_EDGE_RISING;
365 break;
366 case IRQ_TYPE_LEVEL_LOW:
367 parent_type = IRQ_TYPE_EDGE_FALLING;
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 bank->irq_type[d->hwirq] = type;
374
375 return irq_chip_set_type_parent(d, parent_type);
376 };
377
stm32_gpio_irq_request_resources(struct irq_data * irq_data)378 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
379 {
380 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
381 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
382 int ret;
383
384 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
385 if (ret)
386 return ret;
387
388 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
389 if (ret) {
390 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
391 irq_data->hwirq);
392 return ret;
393 }
394
395 return 0;
396 }
397
stm32_gpio_irq_release_resources(struct irq_data * irq_data)398 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
399 {
400 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
401
402 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
403 }
404
stm32_gpio_irq_unmask(struct irq_data * d)405 static void stm32_gpio_irq_unmask(struct irq_data *d)
406 {
407 irq_chip_unmask_parent(d);
408 stm32_gpio_irq_trigger(d);
409 }
410
411 static struct irq_chip stm32_gpio_irq_chip = {
412 .name = "stm32gpio",
413 .irq_eoi = stm32_gpio_irq_eoi,
414 .irq_ack = irq_chip_ack_parent,
415 .irq_mask = irq_chip_mask_parent,
416 .irq_unmask = stm32_gpio_irq_unmask,
417 .irq_set_type = stm32_gpio_set_type,
418 .irq_set_wake = irq_chip_set_wake_parent,
419 .irq_request_resources = stm32_gpio_irq_request_resources,
420 .irq_release_resources = stm32_gpio_irq_release_resources,
421 };
422
stm32_gpio_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)423 static int stm32_gpio_domain_translate(struct irq_domain *d,
424 struct irq_fwspec *fwspec,
425 unsigned long *hwirq,
426 unsigned int *type)
427 {
428 if ((fwspec->param_count != 2) ||
429 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
430 return -EINVAL;
431
432 *hwirq = fwspec->param[0];
433 *type = fwspec->param[1];
434 return 0;
435 }
436
stm32_gpio_domain_activate(struct irq_domain * d,struct irq_data * irq_data,bool reserve)437 static int stm32_gpio_domain_activate(struct irq_domain *d,
438 struct irq_data *irq_data, bool reserve)
439 {
440 struct stm32_gpio_bank *bank = d->host_data;
441 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
442 int ret = 0;
443
444 if (pctl->hwlock) {
445 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
446 HWSPNLCK_TIMEOUT);
447 if (ret) {
448 dev_err(pctl->dev, "Can't get hwspinlock\n");
449 return ret;
450 }
451 }
452
453 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
454
455 if (pctl->hwlock)
456 hwspin_unlock_in_atomic(pctl->hwlock);
457
458 return ret;
459 }
460
stm32_gpio_domain_alloc(struct irq_domain * d,unsigned int virq,unsigned int nr_irqs,void * data)461 static int stm32_gpio_domain_alloc(struct irq_domain *d,
462 unsigned int virq,
463 unsigned int nr_irqs, void *data)
464 {
465 struct stm32_gpio_bank *bank = d->host_data;
466 struct irq_fwspec *fwspec = data;
467 struct irq_fwspec parent_fwspec;
468 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
469 irq_hw_number_t hwirq = fwspec->param[0];
470 unsigned long flags;
471 int ret = 0;
472
473 /*
474 * Check first that the IRQ MUX of that line is free.
475 * gpio irq mux is shared between several banks, protect with a lock
476 */
477 spin_lock_irqsave(&pctl->irqmux_lock, flags);
478
479 if (pctl->irqmux_map & BIT(hwirq)) {
480 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
481 ret = -EBUSY;
482 } else {
483 pctl->irqmux_map |= BIT(hwirq);
484 }
485
486 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
487 if (ret)
488 return ret;
489
490 parent_fwspec.fwnode = d->parent->fwnode;
491 parent_fwspec.param_count = 2;
492 parent_fwspec.param[0] = fwspec->param[0];
493 parent_fwspec.param[1] = fwspec->param[1];
494
495 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
496 bank);
497
498 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
499 }
500
stm32_gpio_domain_free(struct irq_domain * d,unsigned int virq,unsigned int nr_irqs)501 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
502 unsigned int nr_irqs)
503 {
504 struct stm32_gpio_bank *bank = d->host_data;
505 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
506 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
507 unsigned long flags, hwirq = irq_data->hwirq;
508
509 irq_domain_free_irqs_common(d, virq, nr_irqs);
510
511 spin_lock_irqsave(&pctl->irqmux_lock, flags);
512 pctl->irqmux_map &= ~BIT(hwirq);
513 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
514 }
515
516 static const struct irq_domain_ops stm32_gpio_domain_ops = {
517 .translate = stm32_gpio_domain_translate,
518 .alloc = stm32_gpio_domain_alloc,
519 .free = stm32_gpio_domain_free,
520 .activate = stm32_gpio_domain_activate,
521 };
522
523 /* Pinctrl functions */
524 static struct stm32_pinctrl_group *
stm32_pctrl_find_group_by_pin(struct stm32_pinctrl * pctl,u32 pin)525 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
526 {
527 int i;
528
529 for (i = 0; i < pctl->ngroups; i++) {
530 struct stm32_pinctrl_group *grp = pctl->groups + i;
531
532 if (grp->pin == pin)
533 return grp;
534 }
535
536 return NULL;
537 }
538
stm32_pctrl_is_function_valid(struct stm32_pinctrl * pctl,u32 pin_num,u32 fnum)539 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
540 u32 pin_num, u32 fnum)
541 {
542 int i, k;
543
544 for (i = 0; i < pctl->npins; i++) {
545 const struct stm32_desc_pin *pin = pctl->pins + i;
546 const struct stm32_desc_function *func = pin->functions;
547
548 if (pin->pin.number != pin_num)
549 continue;
550
551 for (k = 0; k < STM32_CONFIG_NUM; k++) {
552 if (func->num == fnum)
553 return true;
554 func++;
555 }
556
557 break;
558 }
559
560 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
561
562 return false;
563 }
564
stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl * pctl,u32 pin,u32 fnum,struct stm32_pinctrl_group * grp,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)565 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
566 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
567 struct pinctrl_map **map, unsigned *reserved_maps,
568 unsigned *num_maps)
569 {
570 if (*num_maps == *reserved_maps)
571 return -ENOSPC;
572
573 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
574 (*map)[*num_maps].data.mux.group = grp->name;
575
576 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
577 return -EINVAL;
578
579 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
580 (*num_maps)++;
581
582 return 0;
583 }
584
stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * node,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)585 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
586 struct device_node *node,
587 struct pinctrl_map **map,
588 unsigned *reserved_maps,
589 unsigned *num_maps)
590 {
591 struct stm32_pinctrl *pctl;
592 struct stm32_pinctrl_group *grp;
593 struct property *pins;
594 u32 pinfunc, pin, func;
595 unsigned long *configs;
596 unsigned int num_configs;
597 bool has_config = 0;
598 unsigned reserve = 0;
599 int num_pins, num_funcs, maps_per_pin, i, err = 0;
600
601 pctl = pinctrl_dev_get_drvdata(pctldev);
602
603 pins = of_find_property(node, "pinmux", NULL);
604 if (!pins) {
605 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
606 node);
607 return -EINVAL;
608 }
609
610 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
611 &num_configs);
612 if (err)
613 return err;
614
615 if (num_configs)
616 has_config = 1;
617
618 num_pins = pins->length / sizeof(u32);
619 num_funcs = num_pins;
620 maps_per_pin = 0;
621 if (num_funcs)
622 maps_per_pin++;
623 if (has_config && num_pins >= 1)
624 maps_per_pin++;
625
626 if (!num_pins || !maps_per_pin) {
627 err = -EINVAL;
628 goto exit;
629 }
630
631 reserve = num_pins * maps_per_pin;
632
633 err = pinctrl_utils_reserve_map(pctldev, map,
634 reserved_maps, num_maps, reserve);
635 if (err)
636 goto exit;
637
638 for (i = 0; i < num_pins; i++) {
639 err = of_property_read_u32_index(node, "pinmux",
640 i, &pinfunc);
641 if (err)
642 goto exit;
643
644 pin = STM32_GET_PIN_NO(pinfunc);
645 func = STM32_GET_PIN_FUNC(pinfunc);
646
647 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
648 err = -EINVAL;
649 goto exit;
650 }
651
652 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
653 if (!grp) {
654 dev_err(pctl->dev, "unable to match pin %d to group\n",
655 pin);
656 err = -EINVAL;
657 goto exit;
658 }
659
660 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
661 reserved_maps, num_maps);
662 if (err)
663 goto exit;
664
665 if (has_config) {
666 err = pinctrl_utils_add_map_configs(pctldev, map,
667 reserved_maps, num_maps, grp->name,
668 configs, num_configs,
669 PIN_MAP_TYPE_CONFIGS_GROUP);
670 if (err)
671 goto exit;
672 }
673 }
674
675 exit:
676 kfree(configs);
677 return err;
678 }
679
stm32_pctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)680 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
681 struct device_node *np_config,
682 struct pinctrl_map **map, unsigned *num_maps)
683 {
684 struct device_node *np;
685 unsigned reserved_maps;
686 int ret;
687
688 *map = NULL;
689 *num_maps = 0;
690 reserved_maps = 0;
691
692 for_each_child_of_node(np_config, np) {
693 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
694 &reserved_maps, num_maps);
695 if (ret < 0) {
696 pinctrl_utils_free_map(pctldev, *map, *num_maps);
697 of_node_put(np);
698 return ret;
699 }
700 }
701
702 return 0;
703 }
704
stm32_pctrl_get_groups_count(struct pinctrl_dev * pctldev)705 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
706 {
707 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
708
709 return pctl->ngroups;
710 }
711
stm32_pctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned group)712 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
713 unsigned group)
714 {
715 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
716
717 return pctl->groups[group].name;
718 }
719
stm32_pctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)720 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
721 unsigned group,
722 const unsigned **pins,
723 unsigned *num_pins)
724 {
725 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
726
727 *pins = (unsigned *)&pctl->groups[group].pin;
728 *num_pins = 1;
729
730 return 0;
731 }
732
733 static const struct pinctrl_ops stm32_pctrl_ops = {
734 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
735 .dt_free_map = pinctrl_utils_free_map,
736 .get_groups_count = stm32_pctrl_get_groups_count,
737 .get_group_name = stm32_pctrl_get_group_name,
738 .get_group_pins = stm32_pctrl_get_group_pins,
739 };
740
741
742 /* Pinmux functions */
743
stm32_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)744 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
745 {
746 return ARRAY_SIZE(stm32_gpio_functions);
747 }
748
stm32_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)749 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
750 unsigned selector)
751 {
752 return stm32_gpio_functions[selector];
753 }
754
stm32_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)755 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
756 unsigned function,
757 const char * const **groups,
758 unsigned * const num_groups)
759 {
760 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
761
762 *groups = pctl->grp_names;
763 *num_groups = pctl->ngroups;
764
765 return 0;
766 }
767
stm32_pmx_set_mode(struct stm32_gpio_bank * bank,int pin,u32 mode,u32 alt)768 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
769 int pin, u32 mode, u32 alt)
770 {
771 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
772 u32 val;
773 int alt_shift = (pin % 8) * 4;
774 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
775 unsigned long flags;
776 int err = 0;
777
778 spin_lock_irqsave(&bank->lock, flags);
779
780 if (pctl->hwlock) {
781 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
782 HWSPNLCK_TIMEOUT);
783 if (err) {
784 dev_err(pctl->dev, "Can't get hwspinlock\n");
785 goto unlock;
786 }
787 }
788
789 val = readl_relaxed(bank->base + alt_offset);
790 val &= ~GENMASK(alt_shift + 3, alt_shift);
791 val |= (alt << alt_shift);
792 writel_relaxed(val, bank->base + alt_offset);
793
794 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
795 val &= ~GENMASK(pin * 2 + 1, pin * 2);
796 val |= mode << (pin * 2);
797 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
798
799 if (pctl->hwlock)
800 hwspin_unlock_in_atomic(pctl->hwlock);
801
802 stm32_gpio_backup_mode(bank, pin, mode, alt);
803
804 unlock:
805 spin_unlock_irqrestore(&bank->lock, flags);
806
807 return err;
808 }
809
stm32_pmx_get_mode(struct stm32_gpio_bank * bank,int pin,u32 * mode,u32 * alt)810 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
811 u32 *alt)
812 {
813 u32 val;
814 int alt_shift = (pin % 8) * 4;
815 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
816 unsigned long flags;
817
818 spin_lock_irqsave(&bank->lock, flags);
819
820 val = readl_relaxed(bank->base + alt_offset);
821 val &= GENMASK(alt_shift + 3, alt_shift);
822 *alt = val >> alt_shift;
823
824 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
825 val &= GENMASK(pin * 2 + 1, pin * 2);
826 *mode = val >> (pin * 2);
827
828 spin_unlock_irqrestore(&bank->lock, flags);
829 }
830
stm32_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned group)831 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
832 unsigned function,
833 unsigned group)
834 {
835 bool ret;
836 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
837 struct stm32_pinctrl_group *g = pctl->groups + group;
838 struct pinctrl_gpio_range *range;
839 struct stm32_gpio_bank *bank;
840 u32 mode, alt;
841 int pin;
842
843 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
844 if (!ret)
845 return -EINVAL;
846
847 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
848 if (!range) {
849 dev_err(pctl->dev, "No gpio range defined.\n");
850 return -EINVAL;
851 }
852
853 bank = gpiochip_get_data(range->gc);
854 pin = stm32_gpio_pin(g->pin);
855
856 mode = stm32_gpio_get_mode(function);
857 alt = stm32_gpio_get_alt(function);
858
859 return stm32_pmx_set_mode(bank, pin, mode, alt);
860 }
861
stm32_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned gpio,bool input)862 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
863 struct pinctrl_gpio_range *range, unsigned gpio,
864 bool input)
865 {
866 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
867 int pin = stm32_gpio_pin(gpio);
868
869 return stm32_pmx_set_mode(bank, pin, !input, 0);
870 }
871
stm32_pmx_request(struct pinctrl_dev * pctldev,unsigned int gpio)872 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
873 {
874 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
875 struct pinctrl_gpio_range *range;
876
877 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
878 if (!range) {
879 dev_err(pctl->dev, "No gpio range defined.\n");
880 return -EINVAL;
881 }
882
883 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
884 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
885 return -EACCES;
886 }
887
888 return 0;
889 }
890
891 static const struct pinmux_ops stm32_pmx_ops = {
892 .get_functions_count = stm32_pmx_get_funcs_cnt,
893 .get_function_name = stm32_pmx_get_func_name,
894 .get_function_groups = stm32_pmx_get_func_groups,
895 .set_mux = stm32_pmx_set_mux,
896 .gpio_set_direction = stm32_pmx_gpio_set_direction,
897 .request = stm32_pmx_request,
898 .strict = true,
899 };
900
901 /* Pinconf functions */
902
stm32_pconf_set_driving(struct stm32_gpio_bank * bank,unsigned offset,u32 drive)903 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
904 unsigned offset, u32 drive)
905 {
906 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
907 unsigned long flags;
908 u32 val;
909 int err = 0;
910
911 spin_lock_irqsave(&bank->lock, flags);
912
913 if (pctl->hwlock) {
914 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
915 HWSPNLCK_TIMEOUT);
916 if (err) {
917 dev_err(pctl->dev, "Can't get hwspinlock\n");
918 goto unlock;
919 }
920 }
921
922 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
923 val &= ~BIT(offset);
924 val |= drive << offset;
925 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
926
927 if (pctl->hwlock)
928 hwspin_unlock_in_atomic(pctl->hwlock);
929
930 stm32_gpio_backup_driving(bank, offset, drive);
931
932 unlock:
933 spin_unlock_irqrestore(&bank->lock, flags);
934
935 return err;
936 }
937
stm32_pconf_get_driving(struct stm32_gpio_bank * bank,unsigned int offset)938 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
939 unsigned int offset)
940 {
941 unsigned long flags;
942 u32 val;
943
944 spin_lock_irqsave(&bank->lock, flags);
945
946 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
947 val &= BIT(offset);
948
949 spin_unlock_irqrestore(&bank->lock, flags);
950
951 return (val >> offset);
952 }
953
stm32_pconf_set_speed(struct stm32_gpio_bank * bank,unsigned offset,u32 speed)954 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
955 unsigned offset, u32 speed)
956 {
957 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
958 unsigned long flags;
959 u32 val;
960 int err = 0;
961
962 spin_lock_irqsave(&bank->lock, flags);
963
964 if (pctl->hwlock) {
965 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
966 HWSPNLCK_TIMEOUT);
967 if (err) {
968 dev_err(pctl->dev, "Can't get hwspinlock\n");
969 goto unlock;
970 }
971 }
972
973 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
974 val &= ~GENMASK(offset * 2 + 1, offset * 2);
975 val |= speed << (offset * 2);
976 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
977
978 if (pctl->hwlock)
979 hwspin_unlock_in_atomic(pctl->hwlock);
980
981 stm32_gpio_backup_speed(bank, offset, speed);
982
983 unlock:
984 spin_unlock_irqrestore(&bank->lock, flags);
985
986 return err;
987 }
988
stm32_pconf_get_speed(struct stm32_gpio_bank * bank,unsigned int offset)989 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
990 unsigned int offset)
991 {
992 unsigned long flags;
993 u32 val;
994
995 spin_lock_irqsave(&bank->lock, flags);
996
997 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
998 val &= GENMASK(offset * 2 + 1, offset * 2);
999
1000 spin_unlock_irqrestore(&bank->lock, flags);
1001
1002 return (val >> (offset * 2));
1003 }
1004
stm32_pconf_set_bias(struct stm32_gpio_bank * bank,unsigned offset,u32 bias)1005 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1006 unsigned offset, u32 bias)
1007 {
1008 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1009 unsigned long flags;
1010 u32 val;
1011 int err = 0;
1012
1013 spin_lock_irqsave(&bank->lock, flags);
1014
1015 if (pctl->hwlock) {
1016 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1017 HWSPNLCK_TIMEOUT);
1018 if (err) {
1019 dev_err(pctl->dev, "Can't get hwspinlock\n");
1020 goto unlock;
1021 }
1022 }
1023
1024 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1025 val &= ~GENMASK(offset * 2 + 1, offset * 2);
1026 val |= bias << (offset * 2);
1027 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1028
1029 if (pctl->hwlock)
1030 hwspin_unlock_in_atomic(pctl->hwlock);
1031
1032 stm32_gpio_backup_bias(bank, offset, bias);
1033
1034 unlock:
1035 spin_unlock_irqrestore(&bank->lock, flags);
1036
1037 return err;
1038 }
1039
stm32_pconf_get_bias(struct stm32_gpio_bank * bank,unsigned int offset)1040 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1041 unsigned int offset)
1042 {
1043 unsigned long flags;
1044 u32 val;
1045
1046 spin_lock_irqsave(&bank->lock, flags);
1047
1048 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1049 val &= GENMASK(offset * 2 + 1, offset * 2);
1050
1051 spin_unlock_irqrestore(&bank->lock, flags);
1052
1053 return (val >> (offset * 2));
1054 }
1055
stm32_pconf_get(struct stm32_gpio_bank * bank,unsigned int offset,bool dir)1056 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1057 unsigned int offset, bool dir)
1058 {
1059 unsigned long flags;
1060 u32 val;
1061
1062 spin_lock_irqsave(&bank->lock, flags);
1063
1064 if (dir)
1065 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1066 BIT(offset));
1067 else
1068 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1069 BIT(offset));
1070
1071 spin_unlock_irqrestore(&bank->lock, flags);
1072
1073 return val;
1074 }
1075
stm32_pconf_parse_conf(struct pinctrl_dev * pctldev,unsigned int pin,enum pin_config_param param,enum pin_config_param arg)1076 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1077 unsigned int pin, enum pin_config_param param,
1078 enum pin_config_param arg)
1079 {
1080 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1081 struct pinctrl_gpio_range *range;
1082 struct stm32_gpio_bank *bank;
1083 int offset, ret = 0;
1084
1085 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1086 if (!range) {
1087 dev_err(pctl->dev, "No gpio range defined.\n");
1088 return -EINVAL;
1089 }
1090
1091 bank = gpiochip_get_data(range->gc);
1092 offset = stm32_gpio_pin(pin);
1093
1094 if (!gpiochip_line_is_valid(range->gc, offset)) {
1095 dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1096 return -EACCES;
1097 }
1098
1099 switch (param) {
1100 case PIN_CONFIG_DRIVE_PUSH_PULL:
1101 ret = stm32_pconf_set_driving(bank, offset, 0);
1102 break;
1103 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1104 ret = stm32_pconf_set_driving(bank, offset, 1);
1105 break;
1106 case PIN_CONFIG_SLEW_RATE:
1107 ret = stm32_pconf_set_speed(bank, offset, arg);
1108 break;
1109 case PIN_CONFIG_BIAS_DISABLE:
1110 ret = stm32_pconf_set_bias(bank, offset, 0);
1111 break;
1112 case PIN_CONFIG_BIAS_PULL_UP:
1113 ret = stm32_pconf_set_bias(bank, offset, 1);
1114 break;
1115 case PIN_CONFIG_BIAS_PULL_DOWN:
1116 ret = stm32_pconf_set_bias(bank, offset, 2);
1117 break;
1118 case PIN_CONFIG_OUTPUT:
1119 __stm32_gpio_set(bank, offset, arg);
1120 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1121 break;
1122 default:
1123 ret = -ENOTSUPP;
1124 }
1125
1126 return ret;
1127 }
1128
stm32_pconf_group_get(struct pinctrl_dev * pctldev,unsigned group,unsigned long * config)1129 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1130 unsigned group,
1131 unsigned long *config)
1132 {
1133 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1134
1135 *config = pctl->groups[group].config;
1136
1137 return 0;
1138 }
1139
stm32_pconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)1140 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1141 unsigned long *configs, unsigned num_configs)
1142 {
1143 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1144 struct stm32_pinctrl_group *g = &pctl->groups[group];
1145 int i, ret;
1146
1147 for (i = 0; i < num_configs; i++) {
1148 mutex_lock(&pctldev->mutex);
1149 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1150 pinconf_to_config_param(configs[i]),
1151 pinconf_to_config_argument(configs[i]));
1152 mutex_unlock(&pctldev->mutex);
1153 if (ret < 0)
1154 return ret;
1155
1156 g->config = configs[i];
1157 }
1158
1159 return 0;
1160 }
1161
stm32_pconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1162 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1163 unsigned long *configs, unsigned int num_configs)
1164 {
1165 int i, ret;
1166
1167 for (i = 0; i < num_configs; i++) {
1168 ret = stm32_pconf_parse_conf(pctldev, pin,
1169 pinconf_to_config_param(configs[i]),
1170 pinconf_to_config_argument(configs[i]));
1171 if (ret < 0)
1172 return ret;
1173 }
1174
1175 return 0;
1176 }
1177
1178 static struct stm32_desc_pin *
stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl * pctl,unsigned int pin_number)1179 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1180 unsigned int pin_number)
1181 {
1182 struct stm32_desc_pin *pins = pctl->pins;
1183 int i;
1184
1185 for (i = 0; i < pctl->npins; i++) {
1186 if (pins->pin.number == pin_number)
1187 return pins;
1188 pins++;
1189 }
1190 return NULL;
1191 }
1192
stm32_pconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)1193 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1194 struct seq_file *s,
1195 unsigned int pin)
1196 {
1197 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1198 const struct stm32_desc_pin *pin_desc;
1199 struct pinctrl_gpio_range *range;
1200 struct stm32_gpio_bank *bank;
1201 int offset;
1202 u32 mode, alt, drive, speed, bias;
1203 static const char * const modes[] = {
1204 "input", "output", "alternate", "analog" };
1205 static const char * const speeds[] = {
1206 "low", "medium", "high", "very high" };
1207 static const char * const biasing[] = {
1208 "floating", "pull up", "pull down", "" };
1209 bool val;
1210
1211 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1212 if (!range)
1213 return;
1214
1215 bank = gpiochip_get_data(range->gc);
1216 offset = stm32_gpio_pin(pin);
1217
1218 if (!gpiochip_line_is_valid(range->gc, offset)) {
1219 seq_puts(s, "NO ACCESS");
1220 return;
1221 }
1222
1223 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1224 bias = stm32_pconf_get_bias(bank, offset);
1225
1226 seq_printf(s, "%s ", modes[mode]);
1227
1228 switch (mode) {
1229 /* input */
1230 case 0:
1231 val = stm32_pconf_get(bank, offset, true);
1232 seq_printf(s, "- %s - %s",
1233 val ? "high" : "low",
1234 biasing[bias]);
1235 break;
1236
1237 /* output */
1238 case 1:
1239 drive = stm32_pconf_get_driving(bank, offset);
1240 speed = stm32_pconf_get_speed(bank, offset);
1241 val = stm32_pconf_get(bank, offset, false);
1242 seq_printf(s, "- %s - %s - %s - %s %s",
1243 val ? "high" : "low",
1244 drive ? "open drain" : "push pull",
1245 biasing[bias],
1246 speeds[speed], "speed");
1247 break;
1248
1249 /* alternate */
1250 case 2:
1251 drive = stm32_pconf_get_driving(bank, offset);
1252 speed = stm32_pconf_get_speed(bank, offset);
1253 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1254 if (!pin_desc)
1255 return;
1256
1257 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1258 pin_desc->functions[alt + 1].name,
1259 drive ? "open drain" : "push pull",
1260 biasing[bias],
1261 speeds[speed], "speed");
1262 break;
1263
1264 /* analog */
1265 case 3:
1266 break;
1267 }
1268 }
1269
1270 static const struct pinconf_ops stm32_pconf_ops = {
1271 .pin_config_group_get = stm32_pconf_group_get,
1272 .pin_config_group_set = stm32_pconf_group_set,
1273 .pin_config_set = stm32_pconf_set,
1274 .pin_config_dbg_show = stm32_pconf_dbg_show,
1275 };
1276
stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl * pctl,struct stm32_gpio_bank * bank,unsigned int offset)1277 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1278 struct stm32_gpio_bank *bank,
1279 unsigned int offset)
1280 {
1281 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1282 struct stm32_desc_pin *pin_desc;
1283 int i;
1284
1285 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1286 if (stm32_pin_nb < pctl->npins) {
1287 pin_desc = pctl->pins + stm32_pin_nb;
1288 if (pin_desc->pin.number == stm32_pin_nb)
1289 return pin_desc;
1290 }
1291
1292 /* Otherwise, loop all array to find the pin with the right number */
1293 for (i = 0; i < pctl->npins; i++) {
1294 pin_desc = pctl->pins + i;
1295 if (pin_desc->pin.number == stm32_pin_nb)
1296 return pin_desc;
1297 }
1298 return NULL;
1299 }
1300
stm32_gpiolib_register_bank(struct stm32_pinctrl * pctl,struct fwnode_handle * fwnode)1301 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1302 {
1303 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1304 int bank_ioport_nr;
1305 struct pinctrl_gpio_range *range = &bank->range;
1306 struct fwnode_reference_args args;
1307 struct device *dev = pctl->dev;
1308 struct resource res;
1309 int npins = STM32_GPIO_PINS_PER_BANK;
1310 int bank_nr, err, i = 0;
1311 struct stm32_desc_pin *stm32_pin;
1312 char **names;
1313
1314 if (!IS_ERR(bank->rstc))
1315 reset_control_deassert(bank->rstc);
1316
1317 if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1318 return -ENODEV;
1319
1320 bank->base = devm_ioremap_resource(dev, &res);
1321 if (IS_ERR(bank->base))
1322 return PTR_ERR(bank->base);
1323
1324 err = clk_prepare_enable(bank->clk);
1325 if (err) {
1326 dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1327 return err;
1328 }
1329
1330 bank->gpio_chip = stm32_gpio_template;
1331
1332 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1333
1334 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1335 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1336 bank->gpio_chip.base = args.args[1];
1337
1338 /* get the last defined gpio line (offset + nb of pins) */
1339 npins = args.args[0] + args.args[2];
1340 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1341 npins = max(npins, (int)(args.args[0] + args.args[2]));
1342 } else {
1343 bank_nr = pctl->nbanks;
1344 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1345 range->name = bank->gpio_chip.label;
1346 range->id = bank_nr;
1347 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1348 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1349 range->npins = npins;
1350 range->gc = &bank->gpio_chip;
1351 pinctrl_add_gpio_range(pctl->pctl_dev,
1352 &pctl->banks[bank_nr].range);
1353 }
1354
1355 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1356 bank_ioport_nr = bank_nr;
1357
1358 bank->gpio_chip.base = -1;
1359
1360 bank->gpio_chip.ngpio = npins;
1361 bank->gpio_chip.fwnode = fwnode;
1362 bank->gpio_chip.parent = dev;
1363 bank->bank_nr = bank_nr;
1364 bank->bank_ioport_nr = bank_ioport_nr;
1365 bank->secure_control = pctl->match_data->secure_control;
1366 spin_lock_init(&bank->lock);
1367
1368 if (pctl->domain) {
1369 /* create irq hierarchical domain */
1370 bank->fwnode = fwnode;
1371
1372 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1373 bank->fwnode, &stm32_gpio_domain_ops,
1374 bank);
1375
1376 if (!bank->domain) {
1377 err = -ENODEV;
1378 goto err_clk;
1379 }
1380 }
1381
1382 names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
1383 if (!names) {
1384 err = -ENOMEM;
1385 goto err_clk;
1386 }
1387
1388 for (i = 0; i < npins; i++) {
1389 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1390 if (stm32_pin && stm32_pin->pin.name)
1391 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
1392 else
1393 names[i] = NULL;
1394 }
1395
1396 bank->gpio_chip.names = (const char * const *)names;
1397
1398 err = gpiochip_add_data(&bank->gpio_chip, bank);
1399 if (err) {
1400 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1401 goto err_clk;
1402 }
1403
1404 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1405 return 0;
1406
1407 err_clk:
1408 clk_disable_unprepare(bank->clk);
1409 return err;
1410 }
1411
stm32_pctrl_get_irq_domain(struct platform_device * pdev)1412 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1413 {
1414 struct device_node *np = pdev->dev.of_node;
1415 struct device_node *parent;
1416 struct irq_domain *domain;
1417
1418 if (!of_property_present(np, "interrupt-parent"))
1419 return NULL;
1420
1421 parent = of_irq_find_parent(np);
1422 if (!parent)
1423 return ERR_PTR(-ENXIO);
1424
1425 domain = irq_find_host(parent);
1426 of_node_put(parent);
1427 if (!domain)
1428 /* domain not registered yet */
1429 return ERR_PTR(-EPROBE_DEFER);
1430
1431 return domain;
1432 }
1433
stm32_pctrl_dt_setup_irq(struct platform_device * pdev,struct stm32_pinctrl * pctl)1434 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1435 struct stm32_pinctrl *pctl)
1436 {
1437 struct device_node *np = pdev->dev.of_node;
1438 struct device *dev = &pdev->dev;
1439 struct regmap *rm;
1440 int offset, ret, i;
1441 int mask, mask_width;
1442
1443 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1444 if (IS_ERR(pctl->regmap))
1445 return PTR_ERR(pctl->regmap);
1446
1447 rm = pctl->regmap;
1448
1449 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1450 if (ret)
1451 return ret;
1452
1453 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1454 if (ret)
1455 mask = SYSCFG_IRQMUX_MASK;
1456
1457 mask_width = fls(mask);
1458
1459 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1460 struct reg_field mux;
1461
1462 mux.reg = offset + (i / 4) * 4;
1463 mux.lsb = (i % 4) * mask_width;
1464 mux.msb = mux.lsb + mask_width - 1;
1465
1466 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1467 i, mux.reg, mux.lsb, mux.msb);
1468
1469 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1470 if (IS_ERR(pctl->irqmux[i]))
1471 return PTR_ERR(pctl->irqmux[i]);
1472 }
1473
1474 return 0;
1475 }
1476
stm32_pctrl_build_state(struct platform_device * pdev)1477 static int stm32_pctrl_build_state(struct platform_device *pdev)
1478 {
1479 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1480 int i;
1481
1482 pctl->ngroups = pctl->npins;
1483
1484 /* Allocate groups */
1485 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1486 sizeof(*pctl->groups), GFP_KERNEL);
1487 if (!pctl->groups)
1488 return -ENOMEM;
1489
1490 /* We assume that one pin is one group, use pin name as group name. */
1491 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1492 sizeof(*pctl->grp_names), GFP_KERNEL);
1493 if (!pctl->grp_names)
1494 return -ENOMEM;
1495
1496 for (i = 0; i < pctl->npins; i++) {
1497 const struct stm32_desc_pin *pin = pctl->pins + i;
1498 struct stm32_pinctrl_group *group = pctl->groups + i;
1499
1500 group->name = pin->pin.name;
1501 group->pin = pin->pin.number;
1502 pctl->grp_names[i] = pin->pin.name;
1503 }
1504
1505 return 0;
1506 }
1507
stm32_pctrl_create_pins_tab(struct stm32_pinctrl * pctl,struct stm32_desc_pin * pins)1508 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1509 struct stm32_desc_pin *pins)
1510 {
1511 const struct stm32_desc_pin *p;
1512 int i, nb_pins_available = 0;
1513
1514 for (i = 0; i < pctl->match_data->npins; i++) {
1515 p = pctl->match_data->pins + i;
1516 if (pctl->pkg && !(pctl->pkg & p->pkg))
1517 continue;
1518 pins->pin = p->pin;
1519 memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1520 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1521 pins++;
1522 nb_pins_available++;
1523 }
1524
1525 pctl->npins = nb_pins_available;
1526
1527 return 0;
1528 }
1529
stm32_pctl_probe(struct platform_device * pdev)1530 int stm32_pctl_probe(struct platform_device *pdev)
1531 {
1532 const struct stm32_pinctrl_match_data *match_data;
1533 struct fwnode_handle *child;
1534 struct device *dev = &pdev->dev;
1535 struct stm32_pinctrl *pctl;
1536 struct pinctrl_pin_desc *pins;
1537 int i, ret, hwlock_id;
1538 unsigned int banks;
1539
1540 match_data = device_get_match_data(dev);
1541 if (!match_data)
1542 return -EINVAL;
1543
1544 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1545 if (!pctl)
1546 return -ENOMEM;
1547
1548 platform_set_drvdata(pdev, pctl);
1549
1550 /* check for IRQ controller (may require deferred probe) */
1551 pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1552 if (IS_ERR(pctl->domain))
1553 return PTR_ERR(pctl->domain);
1554 if (!pctl->domain)
1555 dev_warn(dev, "pinctrl without interrupt support\n");
1556
1557 /* hwspinlock is optional */
1558 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1559 if (hwlock_id < 0) {
1560 if (hwlock_id == -EPROBE_DEFER)
1561 return hwlock_id;
1562 } else {
1563 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1564 }
1565
1566 spin_lock_init(&pctl->irqmux_lock);
1567
1568 pctl->dev = dev;
1569 pctl->match_data = match_data;
1570
1571 /* get optional package information */
1572 if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1573 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1574
1575 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1576 sizeof(*pctl->pins), GFP_KERNEL);
1577 if (!pctl->pins)
1578 return -ENOMEM;
1579
1580 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1581 if (ret)
1582 return ret;
1583
1584 ret = stm32_pctrl_build_state(pdev);
1585 if (ret) {
1586 dev_err(dev, "build state failed: %d\n", ret);
1587 return -EINVAL;
1588 }
1589
1590 if (pctl->domain) {
1591 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1592 if (ret)
1593 return ret;
1594 }
1595
1596 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1597 GFP_KERNEL);
1598 if (!pins)
1599 return -ENOMEM;
1600
1601 for (i = 0; i < pctl->npins; i++)
1602 pins[i] = pctl->pins[i].pin;
1603
1604 pctl->pctl_desc.name = dev_name(&pdev->dev);
1605 pctl->pctl_desc.owner = THIS_MODULE;
1606 pctl->pctl_desc.pins = pins;
1607 pctl->pctl_desc.npins = pctl->npins;
1608 pctl->pctl_desc.link_consumers = true;
1609 pctl->pctl_desc.confops = &stm32_pconf_ops;
1610 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1611 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1612 pctl->dev = &pdev->dev;
1613
1614 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1615 pctl);
1616
1617 if (IS_ERR(pctl->pctl_dev)) {
1618 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1619 return PTR_ERR(pctl->pctl_dev);
1620 }
1621
1622 banks = gpiochip_node_count(dev);
1623 if (!banks) {
1624 dev_err(dev, "at least one GPIO bank is required\n");
1625 return -EINVAL;
1626 }
1627 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1628 GFP_KERNEL);
1629 if (!pctl->banks)
1630 return -ENOMEM;
1631
1632 i = 0;
1633 for_each_gpiochip_node(dev, child) {
1634 struct stm32_gpio_bank *bank = &pctl->banks[i];
1635 struct device_node *np = to_of_node(child);
1636
1637 bank->rstc = of_reset_control_get_exclusive(np, NULL);
1638 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1639 fwnode_handle_put(child);
1640 return -EPROBE_DEFER;
1641 }
1642
1643 bank->clk = of_clk_get_by_name(np, NULL);
1644 if (IS_ERR(bank->clk)) {
1645 fwnode_handle_put(child);
1646 return dev_err_probe(dev, PTR_ERR(bank->clk),
1647 "failed to get clk\n");
1648 }
1649 i++;
1650 }
1651
1652 for_each_gpiochip_node(dev, child) {
1653 ret = stm32_gpiolib_register_bank(pctl, child);
1654 if (ret) {
1655 fwnode_handle_put(child);
1656
1657 for (i = 0; i < pctl->nbanks; i++)
1658 clk_disable_unprepare(pctl->banks[i].clk);
1659
1660 return ret;
1661 }
1662
1663 pctl->nbanks++;
1664 }
1665
1666 dev_info(dev, "Pinctrl STM32 initialized\n");
1667
1668 return 0;
1669 }
1670
stm32_pinctrl_restore_gpio_regs(struct stm32_pinctrl * pctl,u32 pin)1671 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1672 struct stm32_pinctrl *pctl, u32 pin)
1673 {
1674 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1675 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1676 struct pinctrl_gpio_range *range;
1677 struct stm32_gpio_bank *bank;
1678 bool pin_is_irq;
1679 int ret;
1680
1681 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1682 if (!range)
1683 return 0;
1684
1685 if (!gpiochip_line_is_valid(range->gc, offset))
1686 return 0;
1687
1688 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1689
1690 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1691 return 0;
1692
1693 bank = gpiochip_get_data(range->gc);
1694
1695 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1696 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1697 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1698 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1699
1700 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1701 if (ret)
1702 return ret;
1703
1704 if (mode == 1) {
1705 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1706 val = val >> STM32_GPIO_BKP_VAL;
1707 __stm32_gpio_set(bank, offset, val);
1708 }
1709
1710 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1711 val >>= STM32_GPIO_BKP_TYPE;
1712 ret = stm32_pconf_set_driving(bank, offset, val);
1713 if (ret)
1714 return ret;
1715
1716 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1717 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1718 ret = stm32_pconf_set_speed(bank, offset, val);
1719 if (ret)
1720 return ret;
1721
1722 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1723 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1724 ret = stm32_pconf_set_bias(bank, offset, val);
1725 if (ret)
1726 return ret;
1727
1728 if (pin_is_irq)
1729 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1730
1731 return 0;
1732 }
1733
stm32_pinctrl_suspend(struct device * dev)1734 int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1735 {
1736 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1737 int i;
1738
1739 for (i = 0; i < pctl->nbanks; i++)
1740 clk_disable(pctl->banks[i].clk);
1741
1742 return 0;
1743 }
1744
stm32_pinctrl_resume(struct device * dev)1745 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1746 {
1747 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1748 struct stm32_pinctrl_group *g = pctl->groups;
1749 int i;
1750
1751 for (i = 0; i < pctl->nbanks; i++)
1752 clk_enable(pctl->banks[i].clk);
1753
1754 for (i = 0; i < pctl->ngroups; i++, g++)
1755 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1756
1757 return 0;
1758 }
1759