1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * srmmu.c:  SRMMU specific routines for memory management.
4  *
5  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
6  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
8  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
10  */
11 
12 #include <linux/seq_file.h>
13 #include <linux/spinlock.h>
14 #include <linux/memblock.h>
15 #include <linux/pagemap.h>
16 #include <linux/vmalloc.h>
17 #include <linux/kdebug.h>
18 #include <linux/export.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
23 #include <linux/fs.h>
24 #include <linux/mm.h>
25 
26 #include <asm/mmu_context.h>
27 #include <asm/cacheflush.h>
28 #include <asm/tlbflush.h>
29 #include <asm/io-unit.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/bitext.h>
33 #include <asm/vaddrs.h>
34 #include <asm/cache.h>
35 #include <asm/traps.h>
36 #include <asm/oplib.h>
37 #include <asm/mbus.h>
38 #include <asm/page.h>
39 #include <asm/asi.h>
40 #include <asm/smp.h>
41 #include <asm/io.h>
42 
43 /* Now the cpu specific definitions. */
44 #include <asm/turbosparc.h>
45 #include <asm/tsunami.h>
46 #include <asm/viking.h>
47 #include <asm/swift.h>
48 #include <asm/leon.h>
49 #include <asm/mxcc.h>
50 #include <asm/ross.h>
51 
52 #include "mm_32.h"
53 
54 enum mbus_module srmmu_modtype;
55 static unsigned int hwbug_bitmask;
56 int vac_cache_size;
57 EXPORT_SYMBOL(vac_cache_size);
58 int vac_line_size;
59 
60 extern struct resource sparc_iomap;
61 
62 extern unsigned long last_valid_pfn;
63 
64 static pgd_t *srmmu_swapper_pg_dir;
65 
66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67 EXPORT_SYMBOL(sparc32_cachetlb_ops);
68 
69 #ifdef CONFIG_SMP
70 const struct sparc32_cachetlb_ops *local_ops;
71 
72 #define FLUSH_BEGIN(mm)
73 #define FLUSH_END
74 #else
75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76 #define FLUSH_END	}
77 #endif
78 
79 int flush_page_for_dma_global = 1;
80 
81 char *srmmu_name;
82 
83 ctxd_t *srmmu_ctx_table_phys;
84 static ctxd_t *srmmu_context_table;
85 
86 int viking_mxcc_present;
87 static DEFINE_SPINLOCK(srmmu_context_spinlock);
88 
89 static int is_hypersparc;
90 
91 static int srmmu_cache_pagetables;
92 
93 /* these will be initialized in srmmu_nocache_calcsize() */
94 static unsigned long srmmu_nocache_size;
95 static unsigned long srmmu_nocache_end;
96 
97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
99 
100 /* The context table is a nocache user with the biggest alignment needs. */
101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
102 
103 void *srmmu_nocache_pool;
104 static struct bit_map srmmu_nocache_map;
105 
srmmu_pmd_none(pmd_t pmd)106 static inline int srmmu_pmd_none(pmd_t pmd)
107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
108 
109 /* XXX should we hyper_flush_whole_icache here - Anton */
srmmu_ctxd_set(ctxd_t * ctxp,pgd_t * pgdp)110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
111 {
112 	pte_t pte;
113 
114 	pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
115 	set_pte((pte_t *)ctxp, pte);
116 }
117 
118 /*
119  * Locations of MSI Registers.
120  */
121 #define MSI_MBUS_ARBEN	0xe0001008	/* MBus Arbiter Enable register */
122 
123 /*
124  * Useful bits in the MSI Registers.
125  */
126 #define MSI_ASYNC_MODE  0x80000000	/* Operate the MSI asynchronously */
127 
msi_set_sync(void)128 static void msi_set_sync(void)
129 {
130 	__asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
131 			      "andn %%g3, %2, %%g3\n\t"
132 			      "sta %%g3, [%0] %1\n\t" : :
133 			      "r" (MSI_MBUS_ARBEN),
134 			      "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
135 }
136 
pmd_set(pmd_t * pmdp,pte_t * ptep)137 void pmd_set(pmd_t *pmdp, pte_t *ptep)
138 {
139 	unsigned long ptp = __nocache_pa(ptep) >> 4;
140 	set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp));
141 }
142 
143 /*
144  * size: bytes to allocate in the nocache area.
145  * align: bytes, number to align at.
146  * Returns the virtual address of the allocated area.
147  */
__srmmu_get_nocache(int size,int align)148 static void *__srmmu_get_nocache(int size, int align)
149 {
150 	int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT;
151 	unsigned long addr;
152 
153 	if (size < minsz) {
154 		printk(KERN_ERR "Size 0x%x too small for nocache request\n",
155 		       size);
156 		size = minsz;
157 	}
158 	if (size & (minsz - 1)) {
159 		printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",
160 		       size);
161 		size += minsz - 1;
162 	}
163 	BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
164 
165 	offset = bit_map_string_get(&srmmu_nocache_map,
166 				    size >> SRMMU_NOCACHE_BITMAP_SHIFT,
167 				    align >> SRMMU_NOCACHE_BITMAP_SHIFT);
168 	if (offset == -1) {
169 		printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
170 		       size, (int) srmmu_nocache_size,
171 		       srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
172 		return NULL;
173 	}
174 
175 	addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
176 	return (void *)addr;
177 }
178 
srmmu_get_nocache(int size,int align)179 void *srmmu_get_nocache(int size, int align)
180 {
181 	void *tmp;
182 
183 	tmp = __srmmu_get_nocache(size, align);
184 
185 	if (tmp)
186 		memset(tmp, 0, size);
187 
188 	return tmp;
189 }
190 
srmmu_free_nocache(void * addr,int size)191 void srmmu_free_nocache(void *addr, int size)
192 {
193 	unsigned long vaddr;
194 	int offset;
195 
196 	vaddr = (unsigned long)addr;
197 	if (vaddr < SRMMU_NOCACHE_VADDR) {
198 		printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
199 		    vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
200 		BUG();
201 	}
202 	if (vaddr + size > srmmu_nocache_end) {
203 		printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
204 		    vaddr, srmmu_nocache_end);
205 		BUG();
206 	}
207 	if (!is_power_of_2(size)) {
208 		printk("Size 0x%x is not a power of 2\n", size);
209 		BUG();
210 	}
211 	if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
212 		printk("Size 0x%x is too small\n", size);
213 		BUG();
214 	}
215 	if (vaddr & (size - 1)) {
216 		printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
217 		BUG();
218 	}
219 
220 	offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
221 	size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
222 
223 	bit_map_clear(&srmmu_nocache_map, offset, size);
224 }
225 
226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
227 						 unsigned long end);
228 
229 /* Return how much physical memory we have.  */
probe_memory(void)230 static unsigned long __init probe_memory(void)
231 {
232 	unsigned long total = 0;
233 	int i;
234 
235 	for (i = 0; sp_banks[i].num_bytes; i++)
236 		total += sp_banks[i].num_bytes;
237 
238 	return total;
239 }
240 
241 /*
242  * Reserve nocache dynamically proportionally to the amount of
243  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
244  */
srmmu_nocache_calcsize(void)245 static void __init srmmu_nocache_calcsize(void)
246 {
247 	unsigned long sysmemavail = probe_memory() / 1024;
248 	int srmmu_nocache_npages;
249 
250 	srmmu_nocache_npages =
251 		sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
252 
253  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
254 	// if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
255 	if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
256 		srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
257 
258 	/* anything above 1280 blows up */
259 	if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
260 		srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
261 
262 	srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
263 	srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
264 }
265 
srmmu_nocache_init(void)266 static void __init srmmu_nocache_init(void)
267 {
268 	void *srmmu_nocache_bitmap;
269 	unsigned int bitmap_bits;
270 	pgd_t *pgd;
271 	p4d_t *p4d;
272 	pud_t *pud;
273 	pmd_t *pmd;
274 	pte_t *pte;
275 	unsigned long paddr, vaddr;
276 	unsigned long pteval;
277 
278 	bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
279 
280 	srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size,
281 					    SRMMU_NOCACHE_ALIGN_MAX);
282 	if (!srmmu_nocache_pool)
283 		panic("%s: Failed to allocate %lu bytes align=0x%x\n",
284 		      __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX);
285 	memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
286 
287 	srmmu_nocache_bitmap =
288 		memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
289 			       SMP_CACHE_BYTES);
290 	if (!srmmu_nocache_bitmap)
291 		panic("%s: Failed to allocate %zu bytes\n", __func__,
292 		      BITS_TO_LONGS(bitmap_bits) * sizeof(long));
293 	bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
294 
295 	srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
296 	memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
297 	init_mm.pgd = srmmu_swapper_pg_dir;
298 
299 	srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
300 
301 	paddr = __pa((unsigned long)srmmu_nocache_pool);
302 	vaddr = SRMMU_NOCACHE_VADDR;
303 
304 	while (vaddr < srmmu_nocache_end) {
305 		pgd = pgd_offset_k(vaddr);
306 		p4d = p4d_offset(pgd, vaddr);
307 		pud = pud_offset(p4d, vaddr);
308 		pmd = pmd_offset(__nocache_fix(pud), vaddr);
309 		pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
310 
311 		pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
312 
313 		if (srmmu_cache_pagetables)
314 			pteval |= SRMMU_CACHE;
315 
316 		set_pte(__nocache_fix(pte), __pte(pteval));
317 
318 		vaddr += PAGE_SIZE;
319 		paddr += PAGE_SIZE;
320 	}
321 
322 	flush_cache_all();
323 	flush_tlb_all();
324 }
325 
get_pgd_fast(void)326 pgd_t *get_pgd_fast(void)
327 {
328 	pgd_t *pgd = NULL;
329 
330 	pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
331 	if (pgd) {
332 		pgd_t *init = pgd_offset_k(0);
333 		memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
334 		memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
335 						(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
336 	}
337 
338 	return pgd;
339 }
340 
341 /*
342  * Hardware needs alignment to 256 only, but we align to whole page size
343  * to reduce fragmentation problems due to the buddy principle.
344  * XXX Provide actual fragmentation statistics in /proc.
345  *
346  * Alignments up to the page size are the same for physical and virtual
347  * addresses of the nocache area.
348  */
pte_alloc_one(struct mm_struct * mm)349 pgtable_t pte_alloc_one(struct mm_struct *mm)
350 {
351 	pte_t *ptep;
352 	struct page *page;
353 
354 	if (!(ptep = pte_alloc_one_kernel(mm)))
355 		return NULL;
356 	page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
357 	spin_lock(&mm->page_table_lock);
358 	if (page_ref_inc_return(page) == 2 && !pgtable_pte_page_ctor(page)) {
359 		page_ref_dec(page);
360 		ptep = NULL;
361 	}
362 	spin_unlock(&mm->page_table_lock);
363 
364 	return ptep;
365 }
366 
pte_free(struct mm_struct * mm,pgtable_t ptep)367 void pte_free(struct mm_struct *mm, pgtable_t ptep)
368 {
369 	struct page *page;
370 
371 	page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
372 	spin_lock(&mm->page_table_lock);
373 	if (page_ref_dec_return(page) == 1)
374 		pgtable_pte_page_dtor(page);
375 	spin_unlock(&mm->page_table_lock);
376 
377 	srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE);
378 }
379 
380 /* context handling - a dynamically sized pool is used */
381 #define NO_CONTEXT	-1
382 
383 struct ctx_list {
384 	struct ctx_list *next;
385 	struct ctx_list *prev;
386 	unsigned int ctx_number;
387 	struct mm_struct *ctx_mm;
388 };
389 
390 static struct ctx_list *ctx_list_pool;
391 static struct ctx_list ctx_free;
392 static struct ctx_list ctx_used;
393 
394 /* At boot time we determine the number of contexts */
395 static int num_contexts;
396 
remove_from_ctx_list(struct ctx_list * entry)397 static inline void remove_from_ctx_list(struct ctx_list *entry)
398 {
399 	entry->next->prev = entry->prev;
400 	entry->prev->next = entry->next;
401 }
402 
add_to_ctx_list(struct ctx_list * head,struct ctx_list * entry)403 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
404 {
405 	entry->next = head;
406 	(entry->prev = head->prev)->next = entry;
407 	head->prev = entry;
408 }
409 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
410 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
411 
412 
alloc_context(struct mm_struct * old_mm,struct mm_struct * mm)413 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
414 {
415 	struct ctx_list *ctxp;
416 
417 	ctxp = ctx_free.next;
418 	if (ctxp != &ctx_free) {
419 		remove_from_ctx_list(ctxp);
420 		add_to_used_ctxlist(ctxp);
421 		mm->context = ctxp->ctx_number;
422 		ctxp->ctx_mm = mm;
423 		return;
424 	}
425 	ctxp = ctx_used.next;
426 	if (ctxp->ctx_mm == old_mm)
427 		ctxp = ctxp->next;
428 	if (ctxp == &ctx_used)
429 		panic("out of mmu contexts");
430 	flush_cache_mm(ctxp->ctx_mm);
431 	flush_tlb_mm(ctxp->ctx_mm);
432 	remove_from_ctx_list(ctxp);
433 	add_to_used_ctxlist(ctxp);
434 	ctxp->ctx_mm->context = NO_CONTEXT;
435 	ctxp->ctx_mm = mm;
436 	mm->context = ctxp->ctx_number;
437 }
438 
free_context(int context)439 static inline void free_context(int context)
440 {
441 	struct ctx_list *ctx_old;
442 
443 	ctx_old = ctx_list_pool + context;
444 	remove_from_ctx_list(ctx_old);
445 	add_to_free_ctxlist(ctx_old);
446 }
447 
sparc_context_init(int numctx)448 static void __init sparc_context_init(int numctx)
449 {
450 	int ctx;
451 	unsigned long size;
452 
453 	size = numctx * sizeof(struct ctx_list);
454 	ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES);
455 	if (!ctx_list_pool)
456 		panic("%s: Failed to allocate %lu bytes\n", __func__, size);
457 
458 	for (ctx = 0; ctx < numctx; ctx++) {
459 		struct ctx_list *clist;
460 
461 		clist = (ctx_list_pool + ctx);
462 		clist->ctx_number = ctx;
463 		clist->ctx_mm = NULL;
464 	}
465 	ctx_free.next = ctx_free.prev = &ctx_free;
466 	ctx_used.next = ctx_used.prev = &ctx_used;
467 	for (ctx = 0; ctx < numctx; ctx++)
468 		add_to_free_ctxlist(ctx_list_pool + ctx);
469 }
470 
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)471 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
472 	       struct task_struct *tsk)
473 {
474 	unsigned long flags;
475 
476 	if (mm->context == NO_CONTEXT) {
477 		spin_lock_irqsave(&srmmu_context_spinlock, flags);
478 		alloc_context(old_mm, mm);
479 		spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
480 		srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
481 	}
482 
483 	if (sparc_cpu_model == sparc_leon)
484 		leon_switch_mm();
485 
486 	if (is_hypersparc)
487 		hyper_flush_whole_icache();
488 
489 	srmmu_set_context(mm->context);
490 }
491 
492 /* Low level IO area allocation on the SRMMU. */
srmmu_mapioaddr(unsigned long physaddr,unsigned long virt_addr,int bus_type)493 static inline void srmmu_mapioaddr(unsigned long physaddr,
494 				   unsigned long virt_addr, int bus_type)
495 {
496 	pgd_t *pgdp;
497 	p4d_t *p4dp;
498 	pud_t *pudp;
499 	pmd_t *pmdp;
500 	pte_t *ptep;
501 	unsigned long tmp;
502 
503 	physaddr &= PAGE_MASK;
504 	pgdp = pgd_offset_k(virt_addr);
505 	p4dp = p4d_offset(pgdp, virt_addr);
506 	pudp = pud_offset(p4dp, virt_addr);
507 	pmdp = pmd_offset(pudp, virt_addr);
508 	ptep = pte_offset_kernel(pmdp, virt_addr);
509 	tmp = (physaddr >> 4) | SRMMU_ET_PTE;
510 
511 	/* I need to test whether this is consistent over all
512 	 * sun4m's.  The bus_type represents the upper 4 bits of
513 	 * 36-bit physical address on the I/O space lines...
514 	 */
515 	tmp |= (bus_type << 28);
516 	tmp |= SRMMU_PRIV;
517 	__flush_page_to_ram(virt_addr);
518 	set_pte(ptep, __pte(tmp));
519 }
520 
srmmu_mapiorange(unsigned int bus,unsigned long xpa,unsigned long xva,unsigned int len)521 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
522 		      unsigned long xva, unsigned int len)
523 {
524 	while (len != 0) {
525 		len -= PAGE_SIZE;
526 		srmmu_mapioaddr(xpa, xva, bus);
527 		xva += PAGE_SIZE;
528 		xpa += PAGE_SIZE;
529 	}
530 	flush_tlb_all();
531 }
532 
srmmu_unmapioaddr(unsigned long virt_addr)533 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
534 {
535 	pgd_t *pgdp;
536 	p4d_t *p4dp;
537 	pud_t *pudp;
538 	pmd_t *pmdp;
539 	pte_t *ptep;
540 
541 
542 	pgdp = pgd_offset_k(virt_addr);
543 	p4dp = p4d_offset(pgdp, virt_addr);
544 	pudp = pud_offset(p4dp, virt_addr);
545 	pmdp = pmd_offset(pudp, virt_addr);
546 	ptep = pte_offset_kernel(pmdp, virt_addr);
547 
548 	/* No need to flush uncacheable page. */
549 	__pte_clear(ptep);
550 }
551 
srmmu_unmapiorange(unsigned long virt_addr,unsigned int len)552 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
553 {
554 	while (len != 0) {
555 		len -= PAGE_SIZE;
556 		srmmu_unmapioaddr(virt_addr);
557 		virt_addr += PAGE_SIZE;
558 	}
559 	flush_tlb_all();
560 }
561 
562 /* tsunami.S */
563 extern void tsunami_flush_cache_all(void);
564 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
565 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
566 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
567 extern void tsunami_flush_page_to_ram(unsigned long page);
568 extern void tsunami_flush_page_for_dma(unsigned long page);
569 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
570 extern void tsunami_flush_tlb_all(void);
571 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
572 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
573 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
574 extern void tsunami_setup_blockops(void);
575 
576 /* swift.S */
577 extern void swift_flush_cache_all(void);
578 extern void swift_flush_cache_mm(struct mm_struct *mm);
579 extern void swift_flush_cache_range(struct vm_area_struct *vma,
580 				    unsigned long start, unsigned long end);
581 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
582 extern void swift_flush_page_to_ram(unsigned long page);
583 extern void swift_flush_page_for_dma(unsigned long page);
584 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
585 extern void swift_flush_tlb_all(void);
586 extern void swift_flush_tlb_mm(struct mm_struct *mm);
587 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
588 				  unsigned long start, unsigned long end);
589 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
590 
591 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
592 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
593 {
594 	int cctx, ctx1;
595 
596 	page &= PAGE_MASK;
597 	if ((ctx1 = vma->vm_mm->context) != -1) {
598 		cctx = srmmu_get_context();
599 /* Is context # ever different from current context? P3 */
600 		if (cctx != ctx1) {
601 			printk("flush ctx %02x curr %02x\n", ctx1, cctx);
602 			srmmu_set_context(ctx1);
603 			swift_flush_page(page);
604 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
605 					"r" (page), "i" (ASI_M_FLUSH_PROBE));
606 			srmmu_set_context(cctx);
607 		} else {
608 			 /* Rm. prot. bits from virt. c. */
609 			/* swift_flush_cache_all(); */
610 			/* swift_flush_cache_page(vma, page); */
611 			swift_flush_page(page);
612 
613 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
614 				"r" (page), "i" (ASI_M_FLUSH_PROBE));
615 			/* same as above: srmmu_flush_tlb_page() */
616 		}
617 	}
618 }
619 #endif
620 
621 /*
622  * The following are all MBUS based SRMMU modules, and therefore could
623  * be found in a multiprocessor configuration.  On the whole, these
624  * chips seems to be much more touchy about DVMA and page tables
625  * with respect to cache coherency.
626  */
627 
628 /* viking.S */
629 extern void viking_flush_cache_all(void);
630 extern void viking_flush_cache_mm(struct mm_struct *mm);
631 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
632 				     unsigned long end);
633 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
634 extern void viking_flush_page_to_ram(unsigned long page);
635 extern void viking_flush_page_for_dma(unsigned long page);
636 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
637 extern void viking_flush_page(unsigned long page);
638 extern void viking_mxcc_flush_page(unsigned long page);
639 extern void viking_flush_tlb_all(void);
640 extern void viking_flush_tlb_mm(struct mm_struct *mm);
641 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
642 				   unsigned long end);
643 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
644 				  unsigned long page);
645 extern void sun4dsmp_flush_tlb_all(void);
646 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
647 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
648 				   unsigned long end);
649 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
650 				  unsigned long page);
651 
652 /* hypersparc.S */
653 extern void hypersparc_flush_cache_all(void);
654 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
655 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
656 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
657 extern void hypersparc_flush_page_to_ram(unsigned long page);
658 extern void hypersparc_flush_page_for_dma(unsigned long page);
659 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
660 extern void hypersparc_flush_tlb_all(void);
661 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
662 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
663 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
664 extern void hypersparc_setup_blockops(void);
665 
666 /*
667  * NOTE: All of this startup code assumes the low 16mb (approx.) of
668  *       kernel mappings are done with one single contiguous chunk of
669  *       ram.  On small ram machines (classics mainly) we only get
670  *       around 8mb mapped for us.
671  */
672 
early_pgtable_allocfail(char * type)673 static void __init early_pgtable_allocfail(char *type)
674 {
675 	prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
676 	prom_halt();
677 }
678 
srmmu_early_allocate_ptable_skeleton(unsigned long start,unsigned long end)679 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
680 							unsigned long end)
681 {
682 	pgd_t *pgdp;
683 	p4d_t *p4dp;
684 	pud_t *pudp;
685 	pmd_t *pmdp;
686 	pte_t *ptep;
687 
688 	while (start < end) {
689 		pgdp = pgd_offset_k(start);
690 		p4dp = p4d_offset(pgdp, start);
691 		pudp = pud_offset(p4dp, start);
692 		if (pud_none(*__nocache_fix(pudp))) {
693 			pmdp = __srmmu_get_nocache(
694 			    SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
695 			if (pmdp == NULL)
696 				early_pgtable_allocfail("pmd");
697 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
698 			pud_set(__nocache_fix(pudp), pmdp);
699 		}
700 		pmdp = pmd_offset(__nocache_fix(pudp), start);
701 		if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
702 			ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
703 			if (ptep == NULL)
704 				early_pgtable_allocfail("pte");
705 			memset(__nocache_fix(ptep), 0, PTE_SIZE);
706 			pmd_set(__nocache_fix(pmdp), ptep);
707 		}
708 		if (start > (0xffffffffUL - PMD_SIZE))
709 			break;
710 		start = (start + PMD_SIZE) & PMD_MASK;
711 	}
712 }
713 
srmmu_allocate_ptable_skeleton(unsigned long start,unsigned long end)714 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
715 						  unsigned long end)
716 {
717 	pgd_t *pgdp;
718 	p4d_t *p4dp;
719 	pud_t *pudp;
720 	pmd_t *pmdp;
721 	pte_t *ptep;
722 
723 	while (start < end) {
724 		pgdp = pgd_offset_k(start);
725 		p4dp = p4d_offset(pgdp, start);
726 		pudp = pud_offset(p4dp, start);
727 		if (pud_none(*pudp)) {
728 			pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
729 			if (pmdp == NULL)
730 				early_pgtable_allocfail("pmd");
731 			memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
732 			pud_set((pud_t *)pgdp, pmdp);
733 		}
734 		pmdp = pmd_offset(pudp, start);
735 		if (srmmu_pmd_none(*pmdp)) {
736 			ptep = __srmmu_get_nocache(PTE_SIZE,
737 							     PTE_SIZE);
738 			if (ptep == NULL)
739 				early_pgtable_allocfail("pte");
740 			memset(ptep, 0, PTE_SIZE);
741 			pmd_set(pmdp, ptep);
742 		}
743 		if (start > (0xffffffffUL - PMD_SIZE))
744 			break;
745 		start = (start + PMD_SIZE) & PMD_MASK;
746 	}
747 }
748 
749 /* These flush types are not available on all chips... */
srmmu_probe(unsigned long vaddr)750 static inline unsigned long srmmu_probe(unsigned long vaddr)
751 {
752 	unsigned long retval;
753 
754 	if (sparc_cpu_model != sparc_leon) {
755 
756 		vaddr &= PAGE_MASK;
757 		__asm__ __volatile__("lda [%1] %2, %0\n\t" :
758 				     "=r" (retval) :
759 				     "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
760 	} else {
761 		retval = leon_swprobe(vaddr, NULL);
762 	}
763 	return retval;
764 }
765 
766 /*
767  * This is much cleaner than poking around physical address space
768  * looking at the prom's page table directly which is what most
769  * other OS's do.  Yuck... this is much better.
770  */
srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)771 static void __init srmmu_inherit_prom_mappings(unsigned long start,
772 					       unsigned long end)
773 {
774 	unsigned long probed;
775 	unsigned long addr;
776 	pgd_t *pgdp;
777 	p4d_t *p4dp;
778 	pud_t *pudp;
779 	pmd_t *pmdp;
780 	pte_t *ptep;
781 	int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
782 
783 	while (start <= end) {
784 		if (start == 0)
785 			break; /* probably wrap around */
786 		if (start == 0xfef00000)
787 			start = KADB_DEBUGGER_BEGVM;
788 		probed = srmmu_probe(start);
789 		if (!probed) {
790 			/* continue probing until we find an entry */
791 			start += PAGE_SIZE;
792 			continue;
793 		}
794 
795 		/* A red snapper, see what it really is. */
796 		what = 0;
797 		addr = start - PAGE_SIZE;
798 
799 		if (!(start & ~(PMD_MASK))) {
800 			if (srmmu_probe(addr + PMD_SIZE) == probed)
801 				what = 1;
802 		}
803 
804 		if (!(start & ~(PGDIR_MASK))) {
805 			if (srmmu_probe(addr + PGDIR_SIZE) == probed)
806 				what = 2;
807 		}
808 
809 		pgdp = pgd_offset_k(start);
810 		p4dp = p4d_offset(pgdp, start);
811 		pudp = pud_offset(p4dp, start);
812 		if (what == 2) {
813 			*__nocache_fix(pgdp) = __pgd(probed);
814 			start += PGDIR_SIZE;
815 			continue;
816 		}
817 		if (pud_none(*__nocache_fix(pudp))) {
818 			pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
819 						   SRMMU_PMD_TABLE_SIZE);
820 			if (pmdp == NULL)
821 				early_pgtable_allocfail("pmd");
822 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
823 			pud_set(__nocache_fix(pudp), pmdp);
824 		}
825 		pmdp = pmd_offset(__nocache_fix(pudp), start);
826 		if (what == 1) {
827 			*(pmd_t *)__nocache_fix(pmdp) = __pmd(probed);
828 			start += PMD_SIZE;
829 			continue;
830 		}
831 		if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
832 			ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
833 			if (ptep == NULL)
834 				early_pgtable_allocfail("pte");
835 			memset(__nocache_fix(ptep), 0, PTE_SIZE);
836 			pmd_set(__nocache_fix(pmdp), ptep);
837 		}
838 		ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
839 		*__nocache_fix(ptep) = __pte(probed);
840 		start += PAGE_SIZE;
841 	}
842 }
843 
844 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
845 
846 /* Create a third-level SRMMU 16MB page mapping. */
do_large_mapping(unsigned long vaddr,unsigned long phys_base)847 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
848 {
849 	pgd_t *pgdp = pgd_offset_k(vaddr);
850 	unsigned long big_pte;
851 
852 	big_pte = KERNEL_PTE(phys_base >> 4);
853 	*__nocache_fix(pgdp) = __pgd(big_pte);
854 }
855 
856 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
map_spbank(unsigned long vbase,int sp_entry)857 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
858 {
859 	unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK);
860 	unsigned long vstart = (vbase & PGDIR_MASK);
861 	unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
862 	/* Map "low" memory only */
863 	const unsigned long min_vaddr = PAGE_OFFSET;
864 	const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
865 
866 	if (vstart < min_vaddr || vstart >= max_vaddr)
867 		return vstart;
868 
869 	if (vend > max_vaddr || vend < min_vaddr)
870 		vend = max_vaddr;
871 
872 	while (vstart < vend) {
873 		do_large_mapping(vstart, pstart);
874 		vstart += PGDIR_SIZE; pstart += PGDIR_SIZE;
875 	}
876 	return vstart;
877 }
878 
map_kernel(void)879 static void __init map_kernel(void)
880 {
881 	int i;
882 
883 	if (phys_base > 0) {
884 		do_large_mapping(PAGE_OFFSET, phys_base);
885 	}
886 
887 	for (i = 0; sp_banks[i].num_bytes != 0; i++) {
888 		map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
889 	}
890 }
891 
892 void (*poke_srmmu)(void) = NULL;
893 
srmmu_paging_init(void)894 void __init srmmu_paging_init(void)
895 {
896 	int i;
897 	phandle cpunode;
898 	char node_str[128];
899 	pgd_t *pgd;
900 	p4d_t *p4d;
901 	pud_t *pud;
902 	pmd_t *pmd;
903 	pte_t *pte;
904 	unsigned long pages_avail;
905 
906 	init_mm.context = (unsigned long) NO_CONTEXT;
907 	sparc_iomap.start = SUN4M_IOBASE_VADDR;	/* 16MB of IOSPACE on all sun4m's. */
908 
909 	if (sparc_cpu_model == sun4d)
910 		num_contexts = 65536; /* We know it is Viking */
911 	else {
912 		/* Find the number of contexts on the srmmu. */
913 		cpunode = prom_getchild(prom_root_node);
914 		num_contexts = 0;
915 		while (cpunode != 0) {
916 			prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
917 			if (!strcmp(node_str, "cpu")) {
918 				num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
919 				break;
920 			}
921 			cpunode = prom_getsibling(cpunode);
922 		}
923 	}
924 
925 	if (!num_contexts) {
926 		prom_printf("Something wrong, can't find cpu node in paging_init.\n");
927 		prom_halt();
928 	}
929 
930 	pages_avail = 0;
931 	last_valid_pfn = bootmem_init(&pages_avail);
932 
933 	srmmu_nocache_calcsize();
934 	srmmu_nocache_init();
935 	srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
936 	map_kernel();
937 
938 	/* ctx table has to be physically aligned to its size */
939 	srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
940 	srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
941 
942 	for (i = 0; i < num_contexts; i++)
943 		srmmu_ctxd_set(__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
944 
945 	flush_cache_all();
946 	srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
947 #ifdef CONFIG_SMP
948 	/* Stop from hanging here... */
949 	local_ops->tlb_all();
950 #else
951 	flush_tlb_all();
952 #endif
953 	poke_srmmu();
954 
955 	srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
956 	srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
957 
958 	srmmu_allocate_ptable_skeleton(
959 		__fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
960 	srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
961 
962 	pgd = pgd_offset_k(PKMAP_BASE);
963 	p4d = p4d_offset(pgd, PKMAP_BASE);
964 	pud = pud_offset(p4d, PKMAP_BASE);
965 	pmd = pmd_offset(pud, PKMAP_BASE);
966 	pte = pte_offset_kernel(pmd, PKMAP_BASE);
967 	pkmap_page_table = pte;
968 
969 	flush_cache_all();
970 	flush_tlb_all();
971 
972 	sparc_context_init(num_contexts);
973 
974 	{
975 		unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
976 
977 		max_zone_pfn[ZONE_DMA] = max_low_pfn;
978 		max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
979 		max_zone_pfn[ZONE_HIGHMEM] = highend_pfn;
980 
981 		free_area_init(max_zone_pfn);
982 	}
983 }
984 
mmu_info(struct seq_file * m)985 void mmu_info(struct seq_file *m)
986 {
987 	seq_printf(m,
988 		   "MMU type\t: %s\n"
989 		   "contexts\t: %d\n"
990 		   "nocache total\t: %ld\n"
991 		   "nocache used\t: %d\n",
992 		   srmmu_name,
993 		   num_contexts,
994 		   srmmu_nocache_size,
995 		   srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
996 }
997 
init_new_context(struct task_struct * tsk,struct mm_struct * mm)998 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
999 {
1000 	mm->context = NO_CONTEXT;
1001 	return 0;
1002 }
1003 
destroy_context(struct mm_struct * mm)1004 void destroy_context(struct mm_struct *mm)
1005 {
1006 	unsigned long flags;
1007 
1008 	if (mm->context != NO_CONTEXT) {
1009 		flush_cache_mm(mm);
1010 		srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1011 		flush_tlb_mm(mm);
1012 		spin_lock_irqsave(&srmmu_context_spinlock, flags);
1013 		free_context(mm->context);
1014 		spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1015 		mm->context = NO_CONTEXT;
1016 	}
1017 }
1018 
1019 /* Init various srmmu chip types. */
srmmu_is_bad(void)1020 static void __init srmmu_is_bad(void)
1021 {
1022 	prom_printf("Could not determine SRMMU chip type.\n");
1023 	prom_halt();
1024 }
1025 
init_vac_layout(void)1026 static void __init init_vac_layout(void)
1027 {
1028 	phandle nd;
1029 	int cache_lines;
1030 	char node_str[128];
1031 #ifdef CONFIG_SMP
1032 	int cpu = 0;
1033 	unsigned long max_size = 0;
1034 	unsigned long min_line_size = 0x10000000;
1035 #endif
1036 
1037 	nd = prom_getchild(prom_root_node);
1038 	while ((nd = prom_getsibling(nd)) != 0) {
1039 		prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1040 		if (!strcmp(node_str, "cpu")) {
1041 			vac_line_size = prom_getint(nd, "cache-line-size");
1042 			if (vac_line_size == -1) {
1043 				prom_printf("can't determine cache-line-size, halting.\n");
1044 				prom_halt();
1045 			}
1046 			cache_lines = prom_getint(nd, "cache-nlines");
1047 			if (cache_lines == -1) {
1048 				prom_printf("can't determine cache-nlines, halting.\n");
1049 				prom_halt();
1050 			}
1051 
1052 			vac_cache_size = cache_lines * vac_line_size;
1053 #ifdef CONFIG_SMP
1054 			if (vac_cache_size > max_size)
1055 				max_size = vac_cache_size;
1056 			if (vac_line_size < min_line_size)
1057 				min_line_size = vac_line_size;
1058 			//FIXME: cpus not contiguous!!
1059 			cpu++;
1060 			if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1061 				break;
1062 #else
1063 			break;
1064 #endif
1065 		}
1066 	}
1067 	if (nd == 0) {
1068 		prom_printf("No CPU nodes found, halting.\n");
1069 		prom_halt();
1070 	}
1071 #ifdef CONFIG_SMP
1072 	vac_cache_size = max_size;
1073 	vac_line_size = min_line_size;
1074 #endif
1075 	printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1076 	       (int)vac_cache_size, (int)vac_line_size);
1077 }
1078 
poke_hypersparc(void)1079 static void poke_hypersparc(void)
1080 {
1081 	volatile unsigned long clear;
1082 	unsigned long mreg = srmmu_get_mmureg();
1083 
1084 	hyper_flush_unconditional_combined();
1085 
1086 	mreg &= ~(HYPERSPARC_CWENABLE);
1087 	mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1088 	mreg |= (HYPERSPARC_CMODE);
1089 
1090 	srmmu_set_mmureg(mreg);
1091 
1092 #if 0 /* XXX I think this is bad news... -DaveM */
1093 	hyper_clear_all_tags();
1094 #endif
1095 
1096 	put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1097 	hyper_flush_whole_icache();
1098 	clear = srmmu_get_faddr();
1099 	clear = srmmu_get_fstatus();
1100 }
1101 
1102 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1103 	.cache_all	= hypersparc_flush_cache_all,
1104 	.cache_mm	= hypersparc_flush_cache_mm,
1105 	.cache_page	= hypersparc_flush_cache_page,
1106 	.cache_range	= hypersparc_flush_cache_range,
1107 	.tlb_all	= hypersparc_flush_tlb_all,
1108 	.tlb_mm		= hypersparc_flush_tlb_mm,
1109 	.tlb_page	= hypersparc_flush_tlb_page,
1110 	.tlb_range	= hypersparc_flush_tlb_range,
1111 	.page_to_ram	= hypersparc_flush_page_to_ram,
1112 	.sig_insns	= hypersparc_flush_sig_insns,
1113 	.page_for_dma	= hypersparc_flush_page_for_dma,
1114 };
1115 
init_hypersparc(void)1116 static void __init init_hypersparc(void)
1117 {
1118 	srmmu_name = "ROSS HyperSparc";
1119 	srmmu_modtype = HyperSparc;
1120 
1121 	init_vac_layout();
1122 
1123 	is_hypersparc = 1;
1124 	sparc32_cachetlb_ops = &hypersparc_ops;
1125 
1126 	poke_srmmu = poke_hypersparc;
1127 
1128 	hypersparc_setup_blockops();
1129 }
1130 
poke_swift(void)1131 static void poke_swift(void)
1132 {
1133 	unsigned long mreg;
1134 
1135 	/* Clear any crap from the cache or else... */
1136 	swift_flush_cache_all();
1137 
1138 	/* Enable I & D caches */
1139 	mreg = srmmu_get_mmureg();
1140 	mreg |= (SWIFT_IE | SWIFT_DE);
1141 	/*
1142 	 * The Swift branch folding logic is completely broken.  At
1143 	 * trap time, if things are just right, if can mistakenly
1144 	 * think that a trap is coming from kernel mode when in fact
1145 	 * it is coming from user mode (it mis-executes the branch in
1146 	 * the trap code).  So you see things like crashme completely
1147 	 * hosing your machine which is completely unacceptable.  Turn
1148 	 * this shit off... nice job Fujitsu.
1149 	 */
1150 	mreg &= ~(SWIFT_BF);
1151 	srmmu_set_mmureg(mreg);
1152 }
1153 
1154 static const struct sparc32_cachetlb_ops swift_ops = {
1155 	.cache_all	= swift_flush_cache_all,
1156 	.cache_mm	= swift_flush_cache_mm,
1157 	.cache_page	= swift_flush_cache_page,
1158 	.cache_range	= swift_flush_cache_range,
1159 	.tlb_all	= swift_flush_tlb_all,
1160 	.tlb_mm		= swift_flush_tlb_mm,
1161 	.tlb_page	= swift_flush_tlb_page,
1162 	.tlb_range	= swift_flush_tlb_range,
1163 	.page_to_ram	= swift_flush_page_to_ram,
1164 	.sig_insns	= swift_flush_sig_insns,
1165 	.page_for_dma	= swift_flush_page_for_dma,
1166 };
1167 
1168 #define SWIFT_MASKID_ADDR  0x10003018
init_swift(void)1169 static void __init init_swift(void)
1170 {
1171 	unsigned long swift_rev;
1172 
1173 	__asm__ __volatile__("lda [%1] %2, %0\n\t"
1174 			     "srl %0, 0x18, %0\n\t" :
1175 			     "=r" (swift_rev) :
1176 			     "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1177 	srmmu_name = "Fujitsu Swift";
1178 	switch (swift_rev) {
1179 	case 0x11:
1180 	case 0x20:
1181 	case 0x23:
1182 	case 0x30:
1183 		srmmu_modtype = Swift_lots_o_bugs;
1184 		hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1185 		/*
1186 		 * Gee george, I wonder why Sun is so hush hush about
1187 		 * this hardware bug... really braindamage stuff going
1188 		 * on here.  However I think we can find a way to avoid
1189 		 * all of the workaround overhead under Linux.  Basically,
1190 		 * any page fault can cause kernel pages to become user
1191 		 * accessible (the mmu gets confused and clears some of
1192 		 * the ACC bits in kernel ptes).  Aha, sounds pretty
1193 		 * horrible eh?  But wait, after extensive testing it appears
1194 		 * that if you use pgd_t level large kernel pte's (like the
1195 		 * 4MB pages on the Pentium) the bug does not get tripped
1196 		 * at all.  This avoids almost all of the major overhead.
1197 		 * Welcome to a world where your vendor tells you to,
1198 		 * "apply this kernel patch" instead of "sorry for the
1199 		 * broken hardware, send it back and we'll give you
1200 		 * properly functioning parts"
1201 		 */
1202 		break;
1203 	case 0x25:
1204 	case 0x31:
1205 		srmmu_modtype = Swift_bad_c;
1206 		hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1207 		/*
1208 		 * You see Sun allude to this hardware bug but never
1209 		 * admit things directly, they'll say things like,
1210 		 * "the Swift chip cache problems" or similar.
1211 		 */
1212 		break;
1213 	default:
1214 		srmmu_modtype = Swift_ok;
1215 		break;
1216 	}
1217 
1218 	sparc32_cachetlb_ops = &swift_ops;
1219 	flush_page_for_dma_global = 0;
1220 
1221 	/*
1222 	 * Are you now convinced that the Swift is one of the
1223 	 * biggest VLSI abortions of all time?  Bravo Fujitsu!
1224 	 * Fujitsu, the !#?!%$'d up processor people.  I bet if
1225 	 * you examined the microcode of the Swift you'd find
1226 	 * XXX's all over the place.
1227 	 */
1228 	poke_srmmu = poke_swift;
1229 }
1230 
turbosparc_flush_cache_all(void)1231 static void turbosparc_flush_cache_all(void)
1232 {
1233 	flush_user_windows();
1234 	turbosparc_idflash_clear();
1235 }
1236 
turbosparc_flush_cache_mm(struct mm_struct * mm)1237 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1238 {
1239 	FLUSH_BEGIN(mm)
1240 	flush_user_windows();
1241 	turbosparc_idflash_clear();
1242 	FLUSH_END
1243 }
1244 
turbosparc_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1245 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1246 {
1247 	FLUSH_BEGIN(vma->vm_mm)
1248 	flush_user_windows();
1249 	turbosparc_idflash_clear();
1250 	FLUSH_END
1251 }
1252 
turbosparc_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1253 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1254 {
1255 	FLUSH_BEGIN(vma->vm_mm)
1256 	flush_user_windows();
1257 	if (vma->vm_flags & VM_EXEC)
1258 		turbosparc_flush_icache();
1259 	turbosparc_flush_dcache();
1260 	FLUSH_END
1261 }
1262 
1263 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
turbosparc_flush_page_to_ram(unsigned long page)1264 static void turbosparc_flush_page_to_ram(unsigned long page)
1265 {
1266 #ifdef TURBOSPARC_WRITEBACK
1267 	volatile unsigned long clear;
1268 
1269 	if (srmmu_probe(page))
1270 		turbosparc_flush_page_cache(page);
1271 	clear = srmmu_get_fstatus();
1272 #endif
1273 }
1274 
turbosparc_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1275 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1276 {
1277 }
1278 
turbosparc_flush_page_for_dma(unsigned long page)1279 static void turbosparc_flush_page_for_dma(unsigned long page)
1280 {
1281 	turbosparc_flush_dcache();
1282 }
1283 
turbosparc_flush_tlb_all(void)1284 static void turbosparc_flush_tlb_all(void)
1285 {
1286 	srmmu_flush_whole_tlb();
1287 }
1288 
turbosparc_flush_tlb_mm(struct mm_struct * mm)1289 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1290 {
1291 	FLUSH_BEGIN(mm)
1292 	srmmu_flush_whole_tlb();
1293 	FLUSH_END
1294 }
1295 
turbosparc_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1296 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1297 {
1298 	FLUSH_BEGIN(vma->vm_mm)
1299 	srmmu_flush_whole_tlb();
1300 	FLUSH_END
1301 }
1302 
turbosparc_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1303 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1304 {
1305 	FLUSH_BEGIN(vma->vm_mm)
1306 	srmmu_flush_whole_tlb();
1307 	FLUSH_END
1308 }
1309 
1310 
poke_turbosparc(void)1311 static void poke_turbosparc(void)
1312 {
1313 	unsigned long mreg = srmmu_get_mmureg();
1314 	unsigned long ccreg;
1315 
1316 	/* Clear any crap from the cache or else... */
1317 	turbosparc_flush_cache_all();
1318 	/* Temporarily disable I & D caches */
1319 	mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1320 	mreg &= ~(TURBOSPARC_PCENABLE);		/* Don't check parity */
1321 	srmmu_set_mmureg(mreg);
1322 
1323 	ccreg = turbosparc_get_ccreg();
1324 
1325 #ifdef TURBOSPARC_WRITEBACK
1326 	ccreg |= (TURBOSPARC_SNENABLE);		/* Do DVMA snooping in Dcache */
1327 	ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1328 			/* Write-back D-cache, emulate VLSI
1329 			 * abortion number three, not number one */
1330 #else
1331 	/* For now let's play safe, optimize later */
1332 	ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1333 			/* Do DVMA snooping in Dcache, Write-thru D-cache */
1334 	ccreg &= ~(TURBOSPARC_uS2);
1335 			/* Emulate VLSI abortion number three, not number one */
1336 #endif
1337 
1338 	switch (ccreg & 7) {
1339 	case 0: /* No SE cache */
1340 	case 7: /* Test mode */
1341 		break;
1342 	default:
1343 		ccreg |= (TURBOSPARC_SCENABLE);
1344 	}
1345 	turbosparc_set_ccreg(ccreg);
1346 
1347 	mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1348 	mreg |= (TURBOSPARC_ICSNOOP);		/* Icache snooping on */
1349 	srmmu_set_mmureg(mreg);
1350 }
1351 
1352 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1353 	.cache_all	= turbosparc_flush_cache_all,
1354 	.cache_mm	= turbosparc_flush_cache_mm,
1355 	.cache_page	= turbosparc_flush_cache_page,
1356 	.cache_range	= turbosparc_flush_cache_range,
1357 	.tlb_all	= turbosparc_flush_tlb_all,
1358 	.tlb_mm		= turbosparc_flush_tlb_mm,
1359 	.tlb_page	= turbosparc_flush_tlb_page,
1360 	.tlb_range	= turbosparc_flush_tlb_range,
1361 	.page_to_ram	= turbosparc_flush_page_to_ram,
1362 	.sig_insns	= turbosparc_flush_sig_insns,
1363 	.page_for_dma	= turbosparc_flush_page_for_dma,
1364 };
1365 
init_turbosparc(void)1366 static void __init init_turbosparc(void)
1367 {
1368 	srmmu_name = "Fujitsu TurboSparc";
1369 	srmmu_modtype = TurboSparc;
1370 	sparc32_cachetlb_ops = &turbosparc_ops;
1371 	poke_srmmu = poke_turbosparc;
1372 }
1373 
poke_tsunami(void)1374 static void poke_tsunami(void)
1375 {
1376 	unsigned long mreg = srmmu_get_mmureg();
1377 
1378 	tsunami_flush_icache();
1379 	tsunami_flush_dcache();
1380 	mreg &= ~TSUNAMI_ITD;
1381 	mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1382 	srmmu_set_mmureg(mreg);
1383 }
1384 
1385 static const struct sparc32_cachetlb_ops tsunami_ops = {
1386 	.cache_all	= tsunami_flush_cache_all,
1387 	.cache_mm	= tsunami_flush_cache_mm,
1388 	.cache_page	= tsunami_flush_cache_page,
1389 	.cache_range	= tsunami_flush_cache_range,
1390 	.tlb_all	= tsunami_flush_tlb_all,
1391 	.tlb_mm		= tsunami_flush_tlb_mm,
1392 	.tlb_page	= tsunami_flush_tlb_page,
1393 	.tlb_range	= tsunami_flush_tlb_range,
1394 	.page_to_ram	= tsunami_flush_page_to_ram,
1395 	.sig_insns	= tsunami_flush_sig_insns,
1396 	.page_for_dma	= tsunami_flush_page_for_dma,
1397 };
1398 
init_tsunami(void)1399 static void __init init_tsunami(void)
1400 {
1401 	/*
1402 	 * Tsunami's pretty sane, Sun and TI actually got it
1403 	 * somewhat right this time.  Fujitsu should have
1404 	 * taken some lessons from them.
1405 	 */
1406 
1407 	srmmu_name = "TI Tsunami";
1408 	srmmu_modtype = Tsunami;
1409 	sparc32_cachetlb_ops = &tsunami_ops;
1410 	poke_srmmu = poke_tsunami;
1411 
1412 	tsunami_setup_blockops();
1413 }
1414 
poke_viking(void)1415 static void poke_viking(void)
1416 {
1417 	unsigned long mreg = srmmu_get_mmureg();
1418 	static int smp_catch;
1419 
1420 	if (viking_mxcc_present) {
1421 		unsigned long mxcc_control = mxcc_get_creg();
1422 
1423 		mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1424 		mxcc_control &= ~(MXCC_CTL_RRC);
1425 		mxcc_set_creg(mxcc_control);
1426 
1427 		/*
1428 		 * We don't need memory parity checks.
1429 		 * XXX This is a mess, have to dig out later. ecd.
1430 		viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1431 		 */
1432 
1433 		/* We do cache ptables on MXCC. */
1434 		mreg |= VIKING_TCENABLE;
1435 	} else {
1436 		unsigned long bpreg;
1437 
1438 		mreg &= ~(VIKING_TCENABLE);
1439 		if (smp_catch++) {
1440 			/* Must disable mixed-cmd mode here for other cpu's. */
1441 			bpreg = viking_get_bpreg();
1442 			bpreg &= ~(VIKING_ACTION_MIX);
1443 			viking_set_bpreg(bpreg);
1444 
1445 			/* Just in case PROM does something funny. */
1446 			msi_set_sync();
1447 		}
1448 	}
1449 
1450 	mreg |= VIKING_SPENABLE;
1451 	mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1452 	mreg |= VIKING_SBENABLE;
1453 	mreg &= ~(VIKING_ACENABLE);
1454 	srmmu_set_mmureg(mreg);
1455 }
1456 
1457 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1458 	.cache_all	= viking_flush_cache_all,
1459 	.cache_mm	= viking_flush_cache_mm,
1460 	.cache_page	= viking_flush_cache_page,
1461 	.cache_range	= viking_flush_cache_range,
1462 	.tlb_all	= viking_flush_tlb_all,
1463 	.tlb_mm		= viking_flush_tlb_mm,
1464 	.tlb_page	= viking_flush_tlb_page,
1465 	.tlb_range	= viking_flush_tlb_range,
1466 	.page_to_ram	= viking_flush_page_to_ram,
1467 	.sig_insns	= viking_flush_sig_insns,
1468 	.page_for_dma	= viking_flush_page_for_dma,
1469 };
1470 
1471 #ifdef CONFIG_SMP
1472 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1473  * perform the local TLB flush and all the other cpus will see it.
1474  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1475  * that requires that we add some synchronization to these flushes.
1476  *
1477  * The bug is that the fifo which keeps track of all the pending TLB
1478  * broadcasts in the system is an entry or two too small, so if we
1479  * have too many going at once we'll overflow that fifo and lose a TLB
1480  * flush resulting in corruption.
1481  *
1482  * Our workaround is to take a global spinlock around the TLB flushes,
1483  * which guarentees we won't ever have too many pending.  It's a big
1484  * hammer, but a semaphore like system to make sure we only have N TLB
1485  * flushes going at once will require SMP locking anyways so there's
1486  * no real value in trying any harder than this.
1487  */
1488 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1489 	.cache_all	= viking_flush_cache_all,
1490 	.cache_mm	= viking_flush_cache_mm,
1491 	.cache_page	= viking_flush_cache_page,
1492 	.cache_range	= viking_flush_cache_range,
1493 	.tlb_all	= sun4dsmp_flush_tlb_all,
1494 	.tlb_mm		= sun4dsmp_flush_tlb_mm,
1495 	.tlb_page	= sun4dsmp_flush_tlb_page,
1496 	.tlb_range	= sun4dsmp_flush_tlb_range,
1497 	.page_to_ram	= viking_flush_page_to_ram,
1498 	.sig_insns	= viking_flush_sig_insns,
1499 	.page_for_dma	= viking_flush_page_for_dma,
1500 };
1501 #endif
1502 
init_viking(void)1503 static void __init init_viking(void)
1504 {
1505 	unsigned long mreg = srmmu_get_mmureg();
1506 
1507 	/* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1508 	if (mreg & VIKING_MMODE) {
1509 		srmmu_name = "TI Viking";
1510 		viking_mxcc_present = 0;
1511 		msi_set_sync();
1512 
1513 		/*
1514 		 * We need this to make sure old viking takes no hits
1515 		 * on it's cache for dma snoops to workaround the
1516 		 * "load from non-cacheable memory" interrupt bug.
1517 		 * This is only necessary because of the new way in
1518 		 * which we use the IOMMU.
1519 		 */
1520 		viking_ops.page_for_dma = viking_flush_page;
1521 #ifdef CONFIG_SMP
1522 		viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1523 #endif
1524 		flush_page_for_dma_global = 0;
1525 	} else {
1526 		srmmu_name = "TI Viking/MXCC";
1527 		viking_mxcc_present = 1;
1528 		srmmu_cache_pagetables = 1;
1529 	}
1530 
1531 	sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1532 		&viking_ops;
1533 #ifdef CONFIG_SMP
1534 	if (sparc_cpu_model == sun4d)
1535 		sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1536 			&viking_sun4d_smp_ops;
1537 #endif
1538 
1539 	poke_srmmu = poke_viking;
1540 }
1541 
1542 /* Probe for the srmmu chip version. */
get_srmmu_type(void)1543 static void __init get_srmmu_type(void)
1544 {
1545 	unsigned long mreg, psr;
1546 	unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1547 
1548 	srmmu_modtype = SRMMU_INVAL_MOD;
1549 	hwbug_bitmask = 0;
1550 
1551 	mreg = srmmu_get_mmureg(); psr = get_psr();
1552 	mod_typ = (mreg & 0xf0000000) >> 28;
1553 	mod_rev = (mreg & 0x0f000000) >> 24;
1554 	psr_typ = (psr >> 28) & 0xf;
1555 	psr_vers = (psr >> 24) & 0xf;
1556 
1557 	/* First, check for sparc-leon. */
1558 	if (sparc_cpu_model == sparc_leon) {
1559 		init_leon();
1560 		return;
1561 	}
1562 
1563 	/* Second, check for HyperSparc or Cypress. */
1564 	if (mod_typ == 1) {
1565 		switch (mod_rev) {
1566 		case 7:
1567 			/* UP or MP Hypersparc */
1568 			init_hypersparc();
1569 			break;
1570 		case 0:
1571 		case 2:
1572 		case 10:
1573 		case 11:
1574 		case 12:
1575 		case 13:
1576 		case 14:
1577 		case 15:
1578 		default:
1579 			prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1580 			prom_halt();
1581 			break;
1582 		}
1583 		return;
1584 	}
1585 
1586 	/* Now Fujitsu TurboSparc. It might happen that it is
1587 	 * in Swift emulation mode, so we will check later...
1588 	 */
1589 	if (psr_typ == 0 && psr_vers == 5) {
1590 		init_turbosparc();
1591 		return;
1592 	}
1593 
1594 	/* Next check for Fujitsu Swift. */
1595 	if (psr_typ == 0 && psr_vers == 4) {
1596 		phandle cpunode;
1597 		char node_str[128];
1598 
1599 		/* Look if it is not a TurboSparc emulating Swift... */
1600 		cpunode = prom_getchild(prom_root_node);
1601 		while ((cpunode = prom_getsibling(cpunode)) != 0) {
1602 			prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1603 			if (!strcmp(node_str, "cpu")) {
1604 				if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1605 				    prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1606 					init_turbosparc();
1607 					return;
1608 				}
1609 				break;
1610 			}
1611 		}
1612 
1613 		init_swift();
1614 		return;
1615 	}
1616 
1617 	/* Now the Viking family of srmmu. */
1618 	if (psr_typ == 4 &&
1619 	   ((psr_vers == 0) ||
1620 	    ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1621 		init_viking();
1622 		return;
1623 	}
1624 
1625 	/* Finally the Tsunami. */
1626 	if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1627 		init_tsunami();
1628 		return;
1629 	}
1630 
1631 	/* Oh well */
1632 	srmmu_is_bad();
1633 }
1634 
1635 #ifdef CONFIG_SMP
1636 /* Local cross-calls. */
smp_flush_page_for_dma(unsigned long page)1637 static void smp_flush_page_for_dma(unsigned long page)
1638 {
1639 	xc1(local_ops->page_for_dma, page);
1640 	local_ops->page_for_dma(page);
1641 }
1642 
smp_flush_cache_all(void)1643 static void smp_flush_cache_all(void)
1644 {
1645 	xc0(local_ops->cache_all);
1646 	local_ops->cache_all();
1647 }
1648 
smp_flush_tlb_all(void)1649 static void smp_flush_tlb_all(void)
1650 {
1651 	xc0(local_ops->tlb_all);
1652 	local_ops->tlb_all();
1653 }
1654 
smp_flush_cache_mm(struct mm_struct * mm)1655 static void smp_flush_cache_mm(struct mm_struct *mm)
1656 {
1657 	if (mm->context != NO_CONTEXT) {
1658 		cpumask_t cpu_mask;
1659 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1660 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1661 		if (!cpumask_empty(&cpu_mask))
1662 			xc1(local_ops->cache_mm, (unsigned long)mm);
1663 		local_ops->cache_mm(mm);
1664 	}
1665 }
1666 
smp_flush_tlb_mm(struct mm_struct * mm)1667 static void smp_flush_tlb_mm(struct mm_struct *mm)
1668 {
1669 	if (mm->context != NO_CONTEXT) {
1670 		cpumask_t cpu_mask;
1671 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1672 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1673 		if (!cpumask_empty(&cpu_mask)) {
1674 			xc1(local_ops->tlb_mm, (unsigned long)mm);
1675 			if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1676 				cpumask_copy(mm_cpumask(mm),
1677 					     cpumask_of(smp_processor_id()));
1678 		}
1679 		local_ops->tlb_mm(mm);
1680 	}
1681 }
1682 
smp_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1683 static void smp_flush_cache_range(struct vm_area_struct *vma,
1684 				  unsigned long start,
1685 				  unsigned long end)
1686 {
1687 	struct mm_struct *mm = vma->vm_mm;
1688 
1689 	if (mm->context != NO_CONTEXT) {
1690 		cpumask_t cpu_mask;
1691 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1692 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1693 		if (!cpumask_empty(&cpu_mask))
1694 			xc3(local_ops->cache_range, (unsigned long)vma, start,
1695 			    end);
1696 		local_ops->cache_range(vma, start, end);
1697 	}
1698 }
1699 
smp_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1700 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1701 				unsigned long start,
1702 				unsigned long end)
1703 {
1704 	struct mm_struct *mm = vma->vm_mm;
1705 
1706 	if (mm->context != NO_CONTEXT) {
1707 		cpumask_t cpu_mask;
1708 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1709 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1710 		if (!cpumask_empty(&cpu_mask))
1711 			xc3(local_ops->tlb_range, (unsigned long)vma, start,
1712 			    end);
1713 		local_ops->tlb_range(vma, start, end);
1714 	}
1715 }
1716 
smp_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1717 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1718 {
1719 	struct mm_struct *mm = vma->vm_mm;
1720 
1721 	if (mm->context != NO_CONTEXT) {
1722 		cpumask_t cpu_mask;
1723 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1724 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1725 		if (!cpumask_empty(&cpu_mask))
1726 			xc2(local_ops->cache_page, (unsigned long)vma, page);
1727 		local_ops->cache_page(vma, page);
1728 	}
1729 }
1730 
smp_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1731 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1732 {
1733 	struct mm_struct *mm = vma->vm_mm;
1734 
1735 	if (mm->context != NO_CONTEXT) {
1736 		cpumask_t cpu_mask;
1737 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1738 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1739 		if (!cpumask_empty(&cpu_mask))
1740 			xc2(local_ops->tlb_page, (unsigned long)vma, page);
1741 		local_ops->tlb_page(vma, page);
1742 	}
1743 }
1744 
smp_flush_page_to_ram(unsigned long page)1745 static void smp_flush_page_to_ram(unsigned long page)
1746 {
1747 	/* Current theory is that those who call this are the one's
1748 	 * who have just dirtied their cache with the pages contents
1749 	 * in kernel space, therefore we only run this on local cpu.
1750 	 *
1751 	 * XXX This experiment failed, research further... -DaveM
1752 	 */
1753 #if 1
1754 	xc1(local_ops->page_to_ram, page);
1755 #endif
1756 	local_ops->page_to_ram(page);
1757 }
1758 
smp_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1759 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1760 {
1761 	cpumask_t cpu_mask;
1762 	cpumask_copy(&cpu_mask, mm_cpumask(mm));
1763 	cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1764 	if (!cpumask_empty(&cpu_mask))
1765 		xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr);
1766 	local_ops->sig_insns(mm, insn_addr);
1767 }
1768 
1769 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1770 	.cache_all	= smp_flush_cache_all,
1771 	.cache_mm	= smp_flush_cache_mm,
1772 	.cache_page	= smp_flush_cache_page,
1773 	.cache_range	= smp_flush_cache_range,
1774 	.tlb_all	= smp_flush_tlb_all,
1775 	.tlb_mm		= smp_flush_tlb_mm,
1776 	.tlb_page	= smp_flush_tlb_page,
1777 	.tlb_range	= smp_flush_tlb_range,
1778 	.page_to_ram	= smp_flush_page_to_ram,
1779 	.sig_insns	= smp_flush_sig_insns,
1780 	.page_for_dma	= smp_flush_page_for_dma,
1781 };
1782 #endif
1783 
1784 /* Load up routines and constants for sun4m and sun4d mmu */
load_mmu(void)1785 void __init load_mmu(void)
1786 {
1787 	/* Functions */
1788 	get_srmmu_type();
1789 
1790 #ifdef CONFIG_SMP
1791 	/* El switcheroo... */
1792 	local_ops = sparc32_cachetlb_ops;
1793 
1794 	if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1795 		smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1796 		smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1797 		smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1798 		smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1799 	}
1800 
1801 	if (poke_srmmu == poke_viking) {
1802 		/* Avoid unnecessary cross calls. */
1803 		smp_cachetlb_ops.cache_all = local_ops->cache_all;
1804 		smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1805 		smp_cachetlb_ops.cache_range = local_ops->cache_range;
1806 		smp_cachetlb_ops.cache_page = local_ops->cache_page;
1807 
1808 		smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1809 		smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1810 		smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1811 	}
1812 
1813 	/* It really is const after this point. */
1814 	sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1815 		&smp_cachetlb_ops;
1816 #endif
1817 
1818 	if (sparc_cpu_model != sun4d)
1819 		ld_mmu_iommu();
1820 #ifdef CONFIG_SMP
1821 	if (sparc_cpu_model == sun4d)
1822 		sun4d_init_smp();
1823 	else if (sparc_cpu_model == sparc_leon)
1824 		leon_init_smp();
1825 	else
1826 		sun4m_init_smp();
1827 #endif
1828 }
1829