1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2005, Intec Automation Inc.
4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
5  */
6 
7 #include <linux/mtd/spi-nor.h>
8 
9 #include "core.h"
10 
11 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
12 #define USE_CLSR	BIT(0)
13 
14 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
15 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
16 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
17 #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
18 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
19 #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
20 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ		BIT(4) /* Page size. */
21 #define SPINOR_REG_CYPRESS_CFR5V		0x00800006
22 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN	0x3
23 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS	0
24 #define SPINOR_OP_CYPRESS_RD_FAST		0xee
25 
26 /* Cypress SPI NOR flash operations. */
27 #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf)		\
28 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0),		\
29 		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
30 		   SPI_MEM_OP_NO_DUMMY,					\
31 		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
32 
33 #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, buf)			\
34 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0),		\
35 		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
36 		   SPI_MEM_OP_NO_DUMMY,					\
37 		   SPI_MEM_OP_DATA_IN(1, buf, 0))
38 
39 #define SPANSION_CLSR_OP						\
40 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),			\
41 		   SPI_MEM_OP_NO_ADDR,					\
42 		   SPI_MEM_OP_NO_DUMMY,					\
43 		   SPI_MEM_OP_NO_DATA)
44 
cypress_nor_octal_dtr_en(struct spi_nor * nor)45 static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
46 {
47 	struct spi_mem_op op;
48 	u8 *buf = nor->bouncebuf;
49 	int ret;
50 
51 	/* Use 24 dummy cycles for memory array reads. */
52 	*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
53 	op = (struct spi_mem_op)
54 		CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf);
55 
56 	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
57 	if (ret)
58 		return ret;
59 
60 	nor->read_dummy = 24;
61 
62 	/* Set the octal and DTR enable bits. */
63 	buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
64 	op = (struct spi_mem_op)
65 		CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf);
66 
67 	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
68 	if (ret)
69 		return ret;
70 
71 	/* Read flash ID to make sure the switch was successful. */
72 	ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);
73 	if (ret) {
74 		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
75 		return ret;
76 	}
77 
78 	if (memcmp(buf, nor->info->id, nor->info->id_len))
79 		return -EINVAL;
80 
81 	return 0;
82 }
83 
cypress_nor_octal_dtr_dis(struct spi_nor * nor)84 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
85 {
86 	struct spi_mem_op op;
87 	u8 *buf = nor->bouncebuf;
88 	int ret;
89 
90 	/*
91 	 * The register is 1-byte wide, but 1-byte transactions are not allowed
92 	 * in 8D-8D-8D mode. Since there is no register at the next location,
93 	 * just initialize the value to 0 and let the transaction go on.
94 	 */
95 	buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
96 	buf[1] = 0;
97 	op = (struct spi_mem_op)
98 		CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf);
99 	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
100 	if (ret)
101 		return ret;
102 
103 	/* Read flash ID to make sure the switch was successful. */
104 	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
105 	if (ret) {
106 		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
107 		return ret;
108 	}
109 
110 	if (memcmp(buf, nor->info->id, nor->info->id_len))
111 		return -EINVAL;
112 
113 	return 0;
114 }
115 
116 /**
117  * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
118  * @nor:		pointer to a 'struct spi_nor'
119  * @enable:              whether to enable or disable Octal DTR
120  *
121  * This also sets the memory access latency cycles to 24 to allow the flash to
122  * run at up to 200MHz.
123  *
124  * Return: 0 on success, -errno otherwise.
125  */
cypress_nor_octal_dtr_enable(struct spi_nor * nor,bool enable)126 static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
127 {
128 	return enable ? cypress_nor_octal_dtr_en(nor) :
129 			cypress_nor_octal_dtr_dis(nor);
130 }
131 
s28hs512t_default_init(struct spi_nor * nor)132 static void s28hs512t_default_init(struct spi_nor *nor)
133 {
134 	nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable;
135 	nor->params->writesize = 16;
136 }
137 
s28hs512t_post_sfdp_fixup(struct spi_nor * nor)138 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
139 {
140 	/*
141 	 * On older versions of the flash the xSPI Profile 1.0 table has the
142 	 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
143 	 */
144 	if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
145 		nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
146 			SPINOR_OP_CYPRESS_RD_FAST;
147 
148 	/* This flash is also missing the 4-byte Page Program opcode bit. */
149 	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
150 				SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
151 	/*
152 	 * Since xSPI Page Program opcode is backward compatible with
153 	 * Legacy SPI, use Legacy SPI opcode there as well.
154 	 */
155 	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
156 				SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
157 
158 	/*
159 	 * The xSPI Profile 1.0 table advertises the number of additional
160 	 * address bytes needed for Read Status Register command as 0 but the
161 	 * actual value for that is 4.
162 	 */
163 	nor->params->rdsr_addr_nbytes = 4;
164 }
165 
s28hs512t_post_bfpt_fixup(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)166 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
167 				     const struct sfdp_parameter_header *bfpt_header,
168 				     const struct sfdp_bfpt *bfpt)
169 {
170 	/*
171 	 * The BFPT table advertises a 512B page size but the page size is
172 	 * actually configurable (with the default being 256B). Read from
173 	 * CFR3V[4] and set the correct size.
174 	 */
175 	struct spi_mem_op op =
176 		CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V,
177 					  nor->bouncebuf);
178 	int ret;
179 
180 	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
181 
182 	ret = spi_mem_exec_op(nor->spimem, &op);
183 	if (ret)
184 		return ret;
185 
186 	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
187 		nor->params->page_size = 512;
188 	else
189 		nor->params->page_size = 256;
190 
191 	return 0;
192 }
193 
194 static const struct spi_nor_fixups s28hs512t_fixups = {
195 	.default_init = s28hs512t_default_init,
196 	.post_sfdp = s28hs512t_post_sfdp_fixup,
197 	.post_bfpt = s28hs512t_post_bfpt_fixup,
198 };
199 
200 static int
s25fs_s_nor_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)201 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor,
202 			     const struct sfdp_parameter_header *bfpt_header,
203 			     const struct sfdp_bfpt *bfpt)
204 {
205 	/*
206 	 * The S25FS-S chip family reports 512-byte pages in BFPT but
207 	 * in reality the write buffer still wraps at the safe default
208 	 * of 256 bytes.  Overwrite the page size advertised by BFPT
209 	 * to get the writes working.
210 	 */
211 	nor->params->page_size = 256;
212 
213 	return 0;
214 }
215 
216 static const struct spi_nor_fixups s25fs_s_nor_fixups = {
217 	.post_bfpt = s25fs_s_nor_post_bfpt_fixups,
218 };
219 
220 static const struct flash_info spansion_nor_parts[] = {
221 	/* Spansion/Cypress -- single (large) sector size only, at least
222 	 * for the chips listed here (without boot sectors).
223 	 */
224 	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64)
225 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
226 	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128)
227 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
228 	{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
229 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
230 		MFR_FLAGS(USE_CLSR)
231 	},
232 	{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
233 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
234 		MFR_FLAGS(USE_CLSR)
235 	},
236 	{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
237 		NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
238 			      SPI_NOR_QUAD_READ)
239 		MFR_FLAGS(USE_CLSR)
240 	},
241 	{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
242 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
243 		MFR_FLAGS(USE_CLSR)
244 	},
245 	{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
246 		FLAGS(SPI_NOR_HAS_LOCK)
247 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
248 		MFR_FLAGS(USE_CLSR)
249 	},
250 	{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
251 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
252 		MFR_FLAGS(USE_CLSR)
253 		.fixups = &s25fs_s_nor_fixups, },
254 	{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
255 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
256 		MFR_FLAGS(USE_CLSR)
257 	},
258 	{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
259 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
260 		MFR_FLAGS(USE_CLSR)
261 	},
262 	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
263 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
264 		MFR_FLAGS(USE_CLSR)
265 		.fixups = &s25fs_s_nor_fixups, },
266 	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64) },
267 	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256) },
268 	{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64)
269 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
270 		MFR_FLAGS(USE_CLSR)
271 	},
272 	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256)
273 		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
274 		MFR_FLAGS(USE_CLSR)
275 	},
276 	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8) },
277 	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16) },
278 	{ "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32) },
279 	{ "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64) },
280 	{ "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128) },
281 	{ "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8)
282 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
283 			      SPI_NOR_QUAD_READ) },
284 	{ "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16)
285 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
286 			      SPI_NOR_QUAD_READ) },
287 	{ "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32)
288 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
289 			      SPI_NOR_QUAD_READ) },
290 	{ "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128)
291 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
292 			      SPI_NOR_QUAD_READ) },
293 	{ "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32)
294 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
295 			      SPI_NOR_QUAD_READ) },
296 	{ "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64)
297 		NO_SFDP_FLAGS(SECT_4K) },
298 	{ "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128)
299 		NO_SFDP_FLAGS(SECT_4K) },
300 	{ "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8)
301 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
302 	{ "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16)
303 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
304 	{ "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128)
305 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
306 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
307 	{ "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256)
308 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
309 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
310 	{ "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
311 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
312 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
313 	{ "cy15x104q",  INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
314 		FLAGS(SPI_NOR_NO_ERASE) },
315 	{ "s28hs512t",   INFO(0x345b1a,      0, 256 * 1024, 256)
316 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
317 			      SPI_NOR_OCTAL_DTR_PP)
318 		.fixups = &s28hs512t_fixups,
319 	},
320 };
321 
322 /**
323  * spansion_nor_clear_sr() - Clear the Status Register.
324  * @nor:	pointer to 'struct spi_nor'.
325  */
spansion_nor_clear_sr(struct spi_nor * nor)326 static void spansion_nor_clear_sr(struct spi_nor *nor)
327 {
328 	int ret;
329 
330 	if (nor->spimem) {
331 		struct spi_mem_op op = SPANSION_CLSR_OP;
332 
333 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
334 
335 		ret = spi_mem_exec_op(nor->spimem, &op);
336 	} else {
337 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
338 						       NULL, 0);
339 	}
340 
341 	if (ret)
342 		dev_dbg(nor->dev, "error %d clearing SR\n", ret);
343 }
344 
345 /**
346  * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
347  * flash is ready for new commands and clear it if there are any errors.
348  * @nor:	pointer to 'struct spi_nor'.
349  *
350  * Return: 1 if ready, 0 if not ready, -errno on errors.
351  */
spansion_nor_sr_ready_and_clear(struct spi_nor * nor)352 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
353 {
354 	int ret;
355 
356 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
357 	if (ret)
358 		return ret;
359 
360 	if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
361 		if (nor->bouncebuf[0] & SR_E_ERR)
362 			dev_err(nor->dev, "Erase Error occurred\n");
363 		else
364 			dev_err(nor->dev, "Programming Error occurred\n");
365 
366 		spansion_nor_clear_sr(nor);
367 
368 		/*
369 		 * WEL bit remains set to one when an erase or page program
370 		 * error occurs. Issue a Write Disable command to protect
371 		 * against inadvertent writes that can possibly corrupt the
372 		 * contents of the memory.
373 		 */
374 		ret = spi_nor_write_disable(nor);
375 		if (ret)
376 			return ret;
377 
378 		return -EIO;
379 	}
380 
381 	return !(nor->bouncebuf[0] & SR_WIP);
382 }
383 
spansion_nor_late_init(struct spi_nor * nor)384 static void spansion_nor_late_init(struct spi_nor *nor)
385 {
386 	if (nor->params->size > SZ_16M) {
387 		nor->flags |= SNOR_F_4B_OPCODES;
388 		/* No small sector erase for 4-byte command set */
389 		nor->erase_opcode = SPINOR_OP_SE;
390 		nor->mtd.erasesize = nor->info->sector_size;
391 	}
392 
393 	if (nor->info->mfr_flags & USE_CLSR)
394 		nor->params->ready = spansion_nor_sr_ready_and_clear;
395 }
396 
397 static const struct spi_nor_fixups spansion_nor_fixups = {
398 	.late_init = spansion_nor_late_init,
399 };
400 
401 const struct spi_nor_manufacturer spi_nor_spansion = {
402 	.name = "spansion",
403 	.parts = spansion_nor_parts,
404 	.nparts = ARRAY_SIZE(spansion_nor_parts),
405 	.fixups = &spansion_nor_fixups,
406 };
407