1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4  * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5  *
6  * Copyright (C) 2005, Intec Automation Inc.
7  * Copyright (C) 2014, Freescale Semiconductor, Inc.
8  */
9 
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 
19 #include <linux/mtd/mtd.h>
20 #include <linux/of_platform.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
24 
25 #include "core.h"
26 
27 /* Define max times to check status register before we give up. */
28 
29 /*
30  * For everything but full-chip erase; probably could be much smaller, but kept
31  * around for safety for now
32  */
33 #define DEFAULT_READY_WAIT_JIFFIES		(40UL * HZ)
34 
35 /*
36  * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37  * for larger flash
38  */
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES	(40UL * HZ)
40 
41 #define SPI_NOR_MAX_ADDR_WIDTH	4
42 
43 #define SPI_NOR_SRST_SLEEP_MIN 200
44 #define SPI_NOR_SRST_SLEEP_MAX 400
45 
46 /**
47  * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
48  *			   extension type.
49  * @nor:		pointer to a 'struct spi_nor'
50  * @op:			pointer to the 'struct spi_mem_op' whose properties
51  *			need to be initialized.
52  *
53  * Right now, only "repeat" and "invert" are supported.
54  *
55  * Return: The opcode extension.
56  */
spi_nor_get_cmd_ext(const struct spi_nor * nor,const struct spi_mem_op * op)57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
58 			      const struct spi_mem_op *op)
59 {
60 	switch (nor->cmd_ext_type) {
61 	case SPI_NOR_EXT_INVERT:
62 		return ~op->cmd.opcode;
63 
64 	case SPI_NOR_EXT_REPEAT:
65 		return op->cmd.opcode;
66 
67 	default:
68 		dev_err(nor->dev, "Unknown command extension type\n");
69 		return 0;
70 	}
71 }
72 
73 /**
74  * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
75  * @nor:		pointer to a 'struct spi_nor'
76  * @op:			pointer to the 'struct spi_mem_op' whose properties
77  *			need to be initialized.
78  * @proto:		the protocol from which the properties need to be set.
79  */
spi_nor_spimem_setup_op(const struct spi_nor * nor,struct spi_mem_op * op,const enum spi_nor_protocol proto)80 void spi_nor_spimem_setup_op(const struct spi_nor *nor,
81 			     struct spi_mem_op *op,
82 			     const enum spi_nor_protocol proto)
83 {
84 	u8 ext;
85 
86 	op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
87 
88 	if (op->addr.nbytes)
89 		op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
90 
91 	if (op->dummy.nbytes)
92 		op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
93 
94 	if (op->data.nbytes)
95 		op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
96 
97 	if (spi_nor_protocol_is_dtr(proto)) {
98 		/*
99 		 * SPIMEM supports mixed DTR modes, but right now we can only
100 		 * have all phases either DTR or STR. IOW, SPIMEM can have
101 		 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
102 		 * phases to either DTR or STR.
103 		 */
104 		op->cmd.dtr = true;
105 		op->addr.dtr = true;
106 		op->dummy.dtr = true;
107 		op->data.dtr = true;
108 
109 		/* 2 bytes per clock cycle in DTR mode. */
110 		op->dummy.nbytes *= 2;
111 
112 		ext = spi_nor_get_cmd_ext(nor, op);
113 		op->cmd.opcode = (op->cmd.opcode << 8) | ext;
114 		op->cmd.nbytes = 2;
115 	}
116 }
117 
118 /**
119  * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
120  *                           transfer
121  * @nor:        pointer to 'struct spi_nor'
122  * @op:         pointer to 'struct spi_mem_op' template for transfer
123  *
124  * If we have to use the bounce buffer, the data field in @op will be updated.
125  *
126  * Return: true if the bounce buffer is needed, false if not
127  */
spi_nor_spimem_bounce(struct spi_nor * nor,struct spi_mem_op * op)128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
129 {
130 	/* op->data.buf.in occupies the same memory as op->data.buf.out */
131 	if (object_is_on_stack(op->data.buf.in) ||
132 	    !virt_addr_valid(op->data.buf.in)) {
133 		if (op->data.nbytes > nor->bouncebuf_size)
134 			op->data.nbytes = nor->bouncebuf_size;
135 		op->data.buf.in = nor->bouncebuf;
136 		return true;
137 	}
138 
139 	return false;
140 }
141 
142 /**
143  * spi_nor_spimem_exec_op() - execute a memory operation
144  * @nor:        pointer to 'struct spi_nor'
145  * @op:         pointer to 'struct spi_mem_op' template for transfer
146  *
147  * Return: 0 on success, -error otherwise.
148  */
spi_nor_spimem_exec_op(struct spi_nor * nor,struct spi_mem_op * op)149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
150 {
151 	int error;
152 
153 	error = spi_mem_adjust_op_size(nor->spimem, op);
154 	if (error)
155 		return error;
156 
157 	return spi_mem_exec_op(nor->spimem, op);
158 }
159 
spi_nor_controller_ops_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,size_t len)160 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
161 				    u8 *buf, size_t len)
162 {
163 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
164 		return -EOPNOTSUPP;
165 
166 	return nor->controller_ops->read_reg(nor, opcode, buf, len);
167 }
168 
spi_nor_controller_ops_write_reg(struct spi_nor * nor,u8 opcode,const u8 * buf,size_t len)169 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170 				     const u8 *buf, size_t len)
171 {
172 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
173 		return -EOPNOTSUPP;
174 
175 	return nor->controller_ops->write_reg(nor, opcode, buf, len);
176 }
177 
spi_nor_controller_ops_erase(struct spi_nor * nor,loff_t offs)178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
179 {
180 	if (spi_nor_protocol_is_dtr(nor->reg_proto))
181 		return -EOPNOTSUPP;
182 
183 	return nor->controller_ops->erase(nor, offs);
184 }
185 
186 /**
187  * spi_nor_spimem_read_data() - read data from flash's memory region via
188  *                              spi-mem
189  * @nor:        pointer to 'struct spi_nor'
190  * @from:       offset to read from
191  * @len:        number of bytes to read
192  * @buf:        pointer to dst buffer
193  *
194  * Return: number of bytes read successfully, -errno otherwise
195  */
spi_nor_spimem_read_data(struct spi_nor * nor,loff_t from,size_t len,u8 * buf)196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
197 					size_t len, u8 *buf)
198 {
199 	struct spi_mem_op op =
200 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
201 			   SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
202 			   SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
203 			   SPI_MEM_OP_DATA_IN(len, buf, 0));
204 	bool usebouncebuf;
205 	ssize_t nbytes;
206 	int error;
207 
208 	spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
209 
210 	/* convert the dummy cycles to the number of bytes */
211 	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
212 	if (spi_nor_protocol_is_dtr(nor->read_proto))
213 		op.dummy.nbytes *= 2;
214 
215 	usebouncebuf = spi_nor_spimem_bounce(nor, &op);
216 
217 	if (nor->dirmap.rdesc) {
218 		nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
219 					     op.data.nbytes, op.data.buf.in);
220 	} else {
221 		error = spi_nor_spimem_exec_op(nor, &op);
222 		if (error)
223 			return error;
224 		nbytes = op.data.nbytes;
225 	}
226 
227 	if (usebouncebuf && nbytes > 0)
228 		memcpy(buf, op.data.buf.in, nbytes);
229 
230 	return nbytes;
231 }
232 
233 /**
234  * spi_nor_read_data() - read data from flash memory
235  * @nor:        pointer to 'struct spi_nor'
236  * @from:       offset to read from
237  * @len:        number of bytes to read
238  * @buf:        pointer to dst buffer
239  *
240  * Return: number of bytes read successfully, -errno otherwise
241  */
spi_nor_read_data(struct spi_nor * nor,loff_t from,size_t len,u8 * buf)242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
243 {
244 	if (nor->spimem)
245 		return spi_nor_spimem_read_data(nor, from, len, buf);
246 
247 	return nor->controller_ops->read(nor, from, len, buf);
248 }
249 
250 /**
251  * spi_nor_spimem_write_data() - write data to flash memory via
252  *                               spi-mem
253  * @nor:        pointer to 'struct spi_nor'
254  * @to:         offset to write to
255  * @len:        number of bytes to write
256  * @buf:        pointer to src buffer
257  *
258  * Return: number of bytes written successfully, -errno otherwise
259  */
spi_nor_spimem_write_data(struct spi_nor * nor,loff_t to,size_t len,const u8 * buf)260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
261 					 size_t len, const u8 *buf)
262 {
263 	struct spi_mem_op op =
264 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
265 			   SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
266 			   SPI_MEM_OP_NO_DUMMY,
267 			   SPI_MEM_OP_DATA_OUT(len, buf, 0));
268 	ssize_t nbytes;
269 	int error;
270 
271 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
272 		op.addr.nbytes = 0;
273 
274 	spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
275 
276 	if (spi_nor_spimem_bounce(nor, &op))
277 		memcpy(nor->bouncebuf, buf, op.data.nbytes);
278 
279 	if (nor->dirmap.wdesc) {
280 		nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
281 					      op.data.nbytes, op.data.buf.out);
282 	} else {
283 		error = spi_nor_spimem_exec_op(nor, &op);
284 		if (error)
285 			return error;
286 		nbytes = op.data.nbytes;
287 	}
288 
289 	return nbytes;
290 }
291 
292 /**
293  * spi_nor_write_data() - write data to flash memory
294  * @nor:        pointer to 'struct spi_nor'
295  * @to:         offset to write to
296  * @len:        number of bytes to write
297  * @buf:        pointer to src buffer
298  *
299  * Return: number of bytes written successfully, -errno otherwise
300  */
spi_nor_write_data(struct spi_nor * nor,loff_t to,size_t len,const u8 * buf)301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
302 			   const u8 *buf)
303 {
304 	if (nor->spimem)
305 		return spi_nor_spimem_write_data(nor, to, len, buf);
306 
307 	return nor->controller_ops->write(nor, to, len, buf);
308 }
309 
310 /**
311  * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
312  * volatile.
313  * @nor:        pointer to 'struct spi_nor'.
314  * @op:		SPI memory operation. op->data.buf must be DMA-able.
315  * @proto:	SPI protocol to use for the register operation.
316  *
317  * Return: zero on success, -errno otherwise
318  */
spi_nor_read_any_reg(struct spi_nor * nor,struct spi_mem_op * op,enum spi_nor_protocol proto)319 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
320 			 enum spi_nor_protocol proto)
321 {
322 	if (!nor->spimem)
323 		return -EOPNOTSUPP;
324 
325 	spi_nor_spimem_setup_op(nor, op, proto);
326 	return spi_nor_spimem_exec_op(nor, op);
327 }
328 
329 /**
330  * spi_nor_write_any_volatile_reg() - write any volatile register to flash
331  * memory.
332  * @nor:        pointer to 'struct spi_nor'
333  * @op:		SPI memory operation. op->data.buf must be DMA-able.
334  * @proto:	SPI protocol to use for the register operation.
335  *
336  * Writing volatile registers are instant according to some manufacturers
337  * (Cypress, Micron) and do not need any status polling.
338  *
339  * Return: zero on success, -errno otherwise
340  */
spi_nor_write_any_volatile_reg(struct spi_nor * nor,struct spi_mem_op * op,enum spi_nor_protocol proto)341 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
342 				   enum spi_nor_protocol proto)
343 {
344 	int ret;
345 
346 	if (!nor->spimem)
347 		return -EOPNOTSUPP;
348 
349 	ret = spi_nor_write_enable(nor);
350 	if (ret)
351 		return ret;
352 	spi_nor_spimem_setup_op(nor, op, proto);
353 	return spi_nor_spimem_exec_op(nor, op);
354 }
355 
356 /**
357  * spi_nor_write_enable() - Set write enable latch with Write Enable command.
358  * @nor:	pointer to 'struct spi_nor'.
359  *
360  * Return: 0 on success, -errno otherwise.
361  */
spi_nor_write_enable(struct spi_nor * nor)362 int spi_nor_write_enable(struct spi_nor *nor)
363 {
364 	int ret;
365 
366 	if (nor->spimem) {
367 		struct spi_mem_op op = SPI_NOR_WREN_OP;
368 
369 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
370 
371 		ret = spi_mem_exec_op(nor->spimem, &op);
372 	} else {
373 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
374 						       NULL, 0);
375 	}
376 
377 	if (ret)
378 		dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
379 
380 	return ret;
381 }
382 
383 /**
384  * spi_nor_write_disable() - Send Write Disable instruction to the chip.
385  * @nor:	pointer to 'struct spi_nor'.
386  *
387  * Return: 0 on success, -errno otherwise.
388  */
spi_nor_write_disable(struct spi_nor * nor)389 int spi_nor_write_disable(struct spi_nor *nor)
390 {
391 	int ret;
392 
393 	if (nor->spimem) {
394 		struct spi_mem_op op = SPI_NOR_WRDI_OP;
395 
396 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
397 
398 		ret = spi_mem_exec_op(nor->spimem, &op);
399 	} else {
400 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
401 						       NULL, 0);
402 	}
403 
404 	if (ret)
405 		dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
406 
407 	return ret;
408 }
409 
410 /**
411  * spi_nor_read_id() - Read the JEDEC ID.
412  * @nor:	pointer to 'struct spi_nor'.
413  * @naddr:	number of address bytes to send. Can be zero if the operation
414  *		does not need to send an address.
415  * @ndummy:	number of dummy bytes to send after an opcode or address. Can
416  *		be zero if the operation does not require dummy bytes.
417  * @id:		pointer to a DMA-able buffer where the value of the JEDEC ID
418  *		will be written.
419  * @proto:	the SPI protocol for register operation.
420  *
421  * Return: 0 on success, -errno otherwise.
422  */
spi_nor_read_id(struct spi_nor * nor,u8 naddr,u8 ndummy,u8 * id,enum spi_nor_protocol proto)423 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
424 		    enum spi_nor_protocol proto)
425 {
426 	int ret;
427 
428 	if (nor->spimem) {
429 		struct spi_mem_op op =
430 			SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);
431 
432 		spi_nor_spimem_setup_op(nor, &op, proto);
433 		ret = spi_mem_exec_op(nor->spimem, &op);
434 	} else {
435 		ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
436 						    SPI_NOR_MAX_ID_LEN);
437 	}
438 	return ret;
439 }
440 
441 /**
442  * spi_nor_read_sr() - Read the Status Register.
443  * @nor:	pointer to 'struct spi_nor'.
444  * @sr:		pointer to a DMA-able buffer where the value of the
445  *              Status Register will be written. Should be at least 2 bytes.
446  *
447  * Return: 0 on success, -errno otherwise.
448  */
spi_nor_read_sr(struct spi_nor * nor,u8 * sr)449 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
450 {
451 	int ret;
452 
453 	if (nor->spimem) {
454 		struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
455 
456 		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
457 			op.addr.nbytes = nor->params->rdsr_addr_nbytes;
458 			op.dummy.nbytes = nor->params->rdsr_dummy;
459 			/*
460 			 * We don't want to read only one byte in DTR mode. So,
461 			 * read 2 and then discard the second byte.
462 			 */
463 			op.data.nbytes = 2;
464 		}
465 
466 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
467 
468 		ret = spi_mem_exec_op(nor->spimem, &op);
469 	} else {
470 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
471 						      1);
472 	}
473 
474 	if (ret)
475 		dev_dbg(nor->dev, "error %d reading SR\n", ret);
476 
477 	return ret;
478 }
479 
480 /**
481  * spi_nor_read_cr() - Read the Configuration Register using the
482  * SPINOR_OP_RDCR (35h) command.
483  * @nor:	pointer to 'struct spi_nor'
484  * @cr:		pointer to a DMA-able buffer where the value of the
485  *              Configuration Register will be written.
486  *
487  * Return: 0 on success, -errno otherwise.
488  */
spi_nor_read_cr(struct spi_nor * nor,u8 * cr)489 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
490 {
491 	int ret;
492 
493 	if (nor->spimem) {
494 		struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
495 
496 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
497 
498 		ret = spi_mem_exec_op(nor->spimem, &op);
499 	} else {
500 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
501 						      1);
502 	}
503 
504 	if (ret)
505 		dev_dbg(nor->dev, "error %d reading CR\n", ret);
506 
507 	return ret;
508 }
509 
510 /**
511  * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode.
512  * @nor:	pointer to 'struct spi_nor'.
513  * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte
514  *		address mode.
515  *
516  * Return: 0 on success, -errno otherwise.
517  */
spi_nor_set_4byte_addr_mode(struct spi_nor * nor,bool enable)518 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
519 {
520 	int ret;
521 
522 	if (nor->spimem) {
523 		struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);
524 
525 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
526 
527 		ret = spi_mem_exec_op(nor->spimem, &op);
528 	} else {
529 		ret = spi_nor_controller_ops_write_reg(nor,
530 						       enable ? SPINOR_OP_EN4B :
531 								SPINOR_OP_EX4B,
532 						       NULL, 0);
533 	}
534 
535 	if (ret)
536 		dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
537 
538 	return ret;
539 }
540 
541 /**
542  * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
543  * flashes.
544  * @nor:	pointer to 'struct spi_nor'.
545  * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte
546  *		address mode.
547  *
548  * Return: 0 on success, -errno otherwise.
549  */
spansion_set_4byte_addr_mode(struct spi_nor * nor,bool enable)550 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
551 {
552 	int ret;
553 
554 	nor->bouncebuf[0] = enable << 7;
555 
556 	if (nor->spimem) {
557 		struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);
558 
559 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
560 
561 		ret = spi_mem_exec_op(nor->spimem, &op);
562 	} else {
563 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
564 						       nor->bouncebuf, 1);
565 	}
566 
567 	if (ret)
568 		dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
569 
570 	return ret;
571 }
572 
573 /**
574  * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
575  * for new commands.
576  * @nor:	pointer to 'struct spi_nor'.
577  *
578  * Return: 1 if ready, 0 if not ready, -errno on errors.
579  */
spi_nor_sr_ready(struct spi_nor * nor)580 int spi_nor_sr_ready(struct spi_nor *nor)
581 {
582 	int ret;
583 
584 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
585 	if (ret)
586 		return ret;
587 
588 	return !(nor->bouncebuf[0] & SR_WIP);
589 }
590 
591 /**
592  * spi_nor_ready() - Query the flash to see if it is ready for new commands.
593  * @nor:	pointer to 'struct spi_nor'.
594  *
595  * Return: 1 if ready, 0 if not ready, -errno on errors.
596  */
spi_nor_ready(struct spi_nor * nor)597 static int spi_nor_ready(struct spi_nor *nor)
598 {
599 	/* Flashes might override the standard routine. */
600 	if (nor->params->ready)
601 		return nor->params->ready(nor);
602 
603 	return spi_nor_sr_ready(nor);
604 }
605 
606 /**
607  * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
608  * Status Register until ready, or timeout occurs.
609  * @nor:		pointer to "struct spi_nor".
610  * @timeout_jiffies:	jiffies to wait until timeout.
611  *
612  * Return: 0 on success, -errno otherwise.
613  */
spi_nor_wait_till_ready_with_timeout(struct spi_nor * nor,unsigned long timeout_jiffies)614 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
615 						unsigned long timeout_jiffies)
616 {
617 	unsigned long deadline;
618 	int timeout = 0, ret;
619 
620 	deadline = jiffies + timeout_jiffies;
621 
622 	while (!timeout) {
623 		if (time_after_eq(jiffies, deadline))
624 			timeout = 1;
625 
626 		ret = spi_nor_ready(nor);
627 		if (ret < 0)
628 			return ret;
629 		if (ret)
630 			return 0;
631 
632 		cond_resched();
633 	}
634 
635 	dev_dbg(nor->dev, "flash operation timed out\n");
636 
637 	return -ETIMEDOUT;
638 }
639 
640 /**
641  * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
642  * flash to be ready, or timeout occurs.
643  * @nor:	pointer to "struct spi_nor".
644  *
645  * Return: 0 on success, -errno otherwise.
646  */
spi_nor_wait_till_ready(struct spi_nor * nor)647 int spi_nor_wait_till_ready(struct spi_nor *nor)
648 {
649 	return spi_nor_wait_till_ready_with_timeout(nor,
650 						    DEFAULT_READY_WAIT_JIFFIES);
651 }
652 
653 /**
654  * spi_nor_global_block_unlock() - Unlock Global Block Protection.
655  * @nor:	pointer to 'struct spi_nor'.
656  *
657  * Return: 0 on success, -errno otherwise.
658  */
spi_nor_global_block_unlock(struct spi_nor * nor)659 int spi_nor_global_block_unlock(struct spi_nor *nor)
660 {
661 	int ret;
662 
663 	ret = spi_nor_write_enable(nor);
664 	if (ret)
665 		return ret;
666 
667 	if (nor->spimem) {
668 		struct spi_mem_op op = SPI_NOR_GBULK_OP;
669 
670 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
671 
672 		ret = spi_mem_exec_op(nor->spimem, &op);
673 	} else {
674 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
675 						       NULL, 0);
676 	}
677 
678 	if (ret) {
679 		dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
680 		return ret;
681 	}
682 
683 	return spi_nor_wait_till_ready(nor);
684 }
685 
686 /**
687  * spi_nor_write_sr() - Write the Status Register.
688  * @nor:	pointer to 'struct spi_nor'.
689  * @sr:		pointer to DMA-able buffer to write to the Status Register.
690  * @len:	number of bytes to write to the Status Register.
691  *
692  * Return: 0 on success, -errno otherwise.
693  */
spi_nor_write_sr(struct spi_nor * nor,const u8 * sr,size_t len)694 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
695 {
696 	int ret;
697 
698 	ret = spi_nor_write_enable(nor);
699 	if (ret)
700 		return ret;
701 
702 	if (nor->spimem) {
703 		struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
704 
705 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
706 
707 		ret = spi_mem_exec_op(nor->spimem, &op);
708 	} else {
709 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
710 						       len);
711 	}
712 
713 	if (ret) {
714 		dev_dbg(nor->dev, "error %d writing SR\n", ret);
715 		return ret;
716 	}
717 
718 	return spi_nor_wait_till_ready(nor);
719 }
720 
721 /**
722  * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
723  * ensure that the byte written match the received value.
724  * @nor:	pointer to a 'struct spi_nor'.
725  * @sr1:	byte value to be written to the Status Register.
726  *
727  * Return: 0 on success, -errno otherwise.
728  */
spi_nor_write_sr1_and_check(struct spi_nor * nor,u8 sr1)729 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
730 {
731 	int ret;
732 
733 	nor->bouncebuf[0] = sr1;
734 
735 	ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
736 	if (ret)
737 		return ret;
738 
739 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
740 	if (ret)
741 		return ret;
742 
743 	if (nor->bouncebuf[0] != sr1) {
744 		dev_dbg(nor->dev, "SR1: read back test failed\n");
745 		return -EIO;
746 	}
747 
748 	return 0;
749 }
750 
751 /**
752  * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
753  * Status Register 2 in one shot. Ensure that the byte written in the Status
754  * Register 1 match the received value, and that the 16-bit Write did not
755  * affect what was already in the Status Register 2.
756  * @nor:	pointer to a 'struct spi_nor'.
757  * @sr1:	byte value to be written to the Status Register 1.
758  *
759  * Return: 0 on success, -errno otherwise.
760  */
spi_nor_write_16bit_sr_and_check(struct spi_nor * nor,u8 sr1)761 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
762 {
763 	int ret;
764 	u8 *sr_cr = nor->bouncebuf;
765 	u8 cr_written;
766 
767 	/* Make sure we don't overwrite the contents of Status Register 2. */
768 	if (!(nor->flags & SNOR_F_NO_READ_CR)) {
769 		ret = spi_nor_read_cr(nor, &sr_cr[1]);
770 		if (ret)
771 			return ret;
772 	} else if (nor->params->quad_enable) {
773 		/*
774 		 * If the Status Register 2 Read command (35h) is not
775 		 * supported, we should at least be sure we don't
776 		 * change the value of the SR2 Quad Enable bit.
777 		 *
778 		 * We can safely assume that when the Quad Enable method is
779 		 * set, the value of the QE bit is one, as a consequence of the
780 		 * nor->params->quad_enable() call.
781 		 *
782 		 * We can safely assume that the Quad Enable bit is present in
783 		 * the Status Register 2 at BIT(1). According to the JESD216
784 		 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
785 		 * Write Status (01h) command is available just for the cases
786 		 * in which the QE bit is described in SR2 at BIT(1).
787 		 */
788 		sr_cr[1] = SR2_QUAD_EN_BIT1;
789 	} else {
790 		sr_cr[1] = 0;
791 	}
792 
793 	sr_cr[0] = sr1;
794 
795 	ret = spi_nor_write_sr(nor, sr_cr, 2);
796 	if (ret)
797 		return ret;
798 
799 	ret = spi_nor_read_sr(nor, sr_cr);
800 	if (ret)
801 		return ret;
802 
803 	if (sr1 != sr_cr[0]) {
804 		dev_dbg(nor->dev, "SR: Read back test failed\n");
805 		return -EIO;
806 	}
807 
808 	if (nor->flags & SNOR_F_NO_READ_CR)
809 		return 0;
810 
811 	cr_written = sr_cr[1];
812 
813 	ret = spi_nor_read_cr(nor, &sr_cr[1]);
814 	if (ret)
815 		return ret;
816 
817 	if (cr_written != sr_cr[1]) {
818 		dev_dbg(nor->dev, "CR: read back test failed\n");
819 		return -EIO;
820 	}
821 
822 	return 0;
823 }
824 
825 /**
826  * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
827  * Configuration Register in one shot. Ensure that the byte written in the
828  * Configuration Register match the received value, and that the 16-bit Write
829  * did not affect what was already in the Status Register 1.
830  * @nor:	pointer to a 'struct spi_nor'.
831  * @cr:		byte value to be written to the Configuration Register.
832  *
833  * Return: 0 on success, -errno otherwise.
834  */
spi_nor_write_16bit_cr_and_check(struct spi_nor * nor,u8 cr)835 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
836 {
837 	int ret;
838 	u8 *sr_cr = nor->bouncebuf;
839 	u8 sr_written;
840 
841 	/* Keep the current value of the Status Register 1. */
842 	ret = spi_nor_read_sr(nor, sr_cr);
843 	if (ret)
844 		return ret;
845 
846 	sr_cr[1] = cr;
847 
848 	ret = spi_nor_write_sr(nor, sr_cr, 2);
849 	if (ret)
850 		return ret;
851 
852 	sr_written = sr_cr[0];
853 
854 	ret = spi_nor_read_sr(nor, sr_cr);
855 	if (ret)
856 		return ret;
857 
858 	if (sr_written != sr_cr[0]) {
859 		dev_dbg(nor->dev, "SR: Read back test failed\n");
860 		return -EIO;
861 	}
862 
863 	if (nor->flags & SNOR_F_NO_READ_CR)
864 		return 0;
865 
866 	ret = spi_nor_read_cr(nor, &sr_cr[1]);
867 	if (ret)
868 		return ret;
869 
870 	if (cr != sr_cr[1]) {
871 		dev_dbg(nor->dev, "CR: read back test failed\n");
872 		return -EIO;
873 	}
874 
875 	return 0;
876 }
877 
878 /**
879  * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
880  * the byte written match the received value without affecting other bits in the
881  * Status Register 1 and 2.
882  * @nor:	pointer to a 'struct spi_nor'.
883  * @sr1:	byte value to be written to the Status Register.
884  *
885  * Return: 0 on success, -errno otherwise.
886  */
spi_nor_write_sr_and_check(struct spi_nor * nor,u8 sr1)887 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
888 {
889 	if (nor->flags & SNOR_F_HAS_16BIT_SR)
890 		return spi_nor_write_16bit_sr_and_check(nor, sr1);
891 
892 	return spi_nor_write_sr1_and_check(nor, sr1);
893 }
894 
895 /**
896  * spi_nor_write_sr2() - Write the Status Register 2 using the
897  * SPINOR_OP_WRSR2 (3eh) command.
898  * @nor:	pointer to 'struct spi_nor'.
899  * @sr2:	pointer to DMA-able buffer to write to the Status Register 2.
900  *
901  * Return: 0 on success, -errno otherwise.
902  */
spi_nor_write_sr2(struct spi_nor * nor,const u8 * sr2)903 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
904 {
905 	int ret;
906 
907 	ret = spi_nor_write_enable(nor);
908 	if (ret)
909 		return ret;
910 
911 	if (nor->spimem) {
912 		struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
913 
914 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
915 
916 		ret = spi_mem_exec_op(nor->spimem, &op);
917 	} else {
918 		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
919 						       sr2, 1);
920 	}
921 
922 	if (ret) {
923 		dev_dbg(nor->dev, "error %d writing SR2\n", ret);
924 		return ret;
925 	}
926 
927 	return spi_nor_wait_till_ready(nor);
928 }
929 
930 /**
931  * spi_nor_read_sr2() - Read the Status Register 2 using the
932  * SPINOR_OP_RDSR2 (3fh) command.
933  * @nor:	pointer to 'struct spi_nor'.
934  * @sr2:	pointer to DMA-able buffer where the value of the
935  *		Status Register 2 will be written.
936  *
937  * Return: 0 on success, -errno otherwise.
938  */
spi_nor_read_sr2(struct spi_nor * nor,u8 * sr2)939 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
940 {
941 	int ret;
942 
943 	if (nor->spimem) {
944 		struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
945 
946 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
947 
948 		ret = spi_mem_exec_op(nor->spimem, &op);
949 	} else {
950 		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
951 						      1);
952 	}
953 
954 	if (ret)
955 		dev_dbg(nor->dev, "error %d reading SR2\n", ret);
956 
957 	return ret;
958 }
959 
960 /**
961  * spi_nor_erase_chip() - Erase the entire flash memory.
962  * @nor:	pointer to 'struct spi_nor'.
963  *
964  * Return: 0 on success, -errno otherwise.
965  */
spi_nor_erase_chip(struct spi_nor * nor)966 static int spi_nor_erase_chip(struct spi_nor *nor)
967 {
968 	int ret;
969 
970 	dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
971 
972 	if (nor->spimem) {
973 		struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;
974 
975 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
976 
977 		ret = spi_mem_exec_op(nor->spimem, &op);
978 	} else {
979 		ret = spi_nor_controller_ops_write_reg(nor,
980 						       SPINOR_OP_CHIP_ERASE,
981 						       NULL, 0);
982 	}
983 
984 	if (ret)
985 		dev_dbg(nor->dev, "error %d erasing chip\n", ret);
986 
987 	return ret;
988 }
989 
spi_nor_convert_opcode(u8 opcode,const u8 table[][2],size_t size)990 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
991 {
992 	size_t i;
993 
994 	for (i = 0; i < size; i++)
995 		if (table[i][0] == opcode)
996 			return table[i][1];
997 
998 	/* No conversion found, keep input op code. */
999 	return opcode;
1000 }
1001 
spi_nor_convert_3to4_read(u8 opcode)1002 u8 spi_nor_convert_3to4_read(u8 opcode)
1003 {
1004 	static const u8 spi_nor_3to4_read[][2] = {
1005 		{ SPINOR_OP_READ,	SPINOR_OP_READ_4B },
1006 		{ SPINOR_OP_READ_FAST,	SPINOR_OP_READ_FAST_4B },
1007 		{ SPINOR_OP_READ_1_1_2,	SPINOR_OP_READ_1_1_2_4B },
1008 		{ SPINOR_OP_READ_1_2_2,	SPINOR_OP_READ_1_2_2_4B },
1009 		{ SPINOR_OP_READ_1_1_4,	SPINOR_OP_READ_1_1_4_4B },
1010 		{ SPINOR_OP_READ_1_4_4,	SPINOR_OP_READ_1_4_4_4B },
1011 		{ SPINOR_OP_READ_1_1_8,	SPINOR_OP_READ_1_1_8_4B },
1012 		{ SPINOR_OP_READ_1_8_8,	SPINOR_OP_READ_1_8_8_4B },
1013 
1014 		{ SPINOR_OP_READ_1_1_1_DTR,	SPINOR_OP_READ_1_1_1_DTR_4B },
1015 		{ SPINOR_OP_READ_1_2_2_DTR,	SPINOR_OP_READ_1_2_2_DTR_4B },
1016 		{ SPINOR_OP_READ_1_4_4_DTR,	SPINOR_OP_READ_1_4_4_DTR_4B },
1017 	};
1018 
1019 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1020 				      ARRAY_SIZE(spi_nor_3to4_read));
1021 }
1022 
spi_nor_convert_3to4_program(u8 opcode)1023 static u8 spi_nor_convert_3to4_program(u8 opcode)
1024 {
1025 	static const u8 spi_nor_3to4_program[][2] = {
1026 		{ SPINOR_OP_PP,		SPINOR_OP_PP_4B },
1027 		{ SPINOR_OP_PP_1_1_4,	SPINOR_OP_PP_1_1_4_4B },
1028 		{ SPINOR_OP_PP_1_4_4,	SPINOR_OP_PP_1_4_4_4B },
1029 		{ SPINOR_OP_PP_1_1_8,	SPINOR_OP_PP_1_1_8_4B },
1030 		{ SPINOR_OP_PP_1_8_8,	SPINOR_OP_PP_1_8_8_4B },
1031 	};
1032 
1033 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1034 				      ARRAY_SIZE(spi_nor_3to4_program));
1035 }
1036 
spi_nor_convert_3to4_erase(u8 opcode)1037 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1038 {
1039 	static const u8 spi_nor_3to4_erase[][2] = {
1040 		{ SPINOR_OP_BE_4K,	SPINOR_OP_BE_4K_4B },
1041 		{ SPINOR_OP_BE_32K,	SPINOR_OP_BE_32K_4B },
1042 		{ SPINOR_OP_SE,		SPINOR_OP_SE_4B },
1043 	};
1044 
1045 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1046 				      ARRAY_SIZE(spi_nor_3to4_erase));
1047 }
1048 
spi_nor_has_uniform_erase(const struct spi_nor * nor)1049 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1050 {
1051 	return !!nor->params->erase_map.uniform_erase_type;
1052 }
1053 
spi_nor_set_4byte_opcodes(struct spi_nor * nor)1054 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1055 {
1056 	nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1057 	nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1058 	nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1059 
1060 	if (!spi_nor_has_uniform_erase(nor)) {
1061 		struct spi_nor_erase_map *map = &nor->params->erase_map;
1062 		struct spi_nor_erase_type *erase;
1063 		int i;
1064 
1065 		for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1066 			erase = &map->erase_type[i];
1067 			erase->opcode =
1068 				spi_nor_convert_3to4_erase(erase->opcode);
1069 		}
1070 	}
1071 }
1072 
spi_nor_lock_and_prep(struct spi_nor * nor)1073 int spi_nor_lock_and_prep(struct spi_nor *nor)
1074 {
1075 	int ret = 0;
1076 
1077 	mutex_lock(&nor->lock);
1078 
1079 	if (nor->controller_ops &&  nor->controller_ops->prepare) {
1080 		ret = nor->controller_ops->prepare(nor);
1081 		if (ret) {
1082 			mutex_unlock(&nor->lock);
1083 			return ret;
1084 		}
1085 	}
1086 	return ret;
1087 }
1088 
spi_nor_unlock_and_unprep(struct spi_nor * nor)1089 void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1090 {
1091 	if (nor->controller_ops && nor->controller_ops->unprepare)
1092 		nor->controller_ops->unprepare(nor);
1093 	mutex_unlock(&nor->lock);
1094 }
1095 
spi_nor_convert_addr(struct spi_nor * nor,loff_t addr)1096 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1097 {
1098 	if (!nor->params->convert_addr)
1099 		return addr;
1100 
1101 	return nor->params->convert_addr(nor, addr);
1102 }
1103 
1104 /*
1105  * Initiate the erasure of a single sector
1106  */
spi_nor_erase_sector(struct spi_nor * nor,u32 addr)1107 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1108 {
1109 	int i;
1110 
1111 	addr = spi_nor_convert_addr(nor, addr);
1112 
1113 	if (nor->spimem) {
1114 		struct spi_mem_op op =
1115 			SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
1116 						nor->addr_width, addr);
1117 
1118 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1119 
1120 		return spi_mem_exec_op(nor->spimem, &op);
1121 	} else if (nor->controller_ops->erase) {
1122 		return spi_nor_controller_ops_erase(nor, addr);
1123 	}
1124 
1125 	/*
1126 	 * Default implementation, if driver doesn't have a specialized HW
1127 	 * control
1128 	 */
1129 	for (i = nor->addr_width - 1; i >= 0; i--) {
1130 		nor->bouncebuf[i] = addr & 0xff;
1131 		addr >>= 8;
1132 	}
1133 
1134 	return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
1135 						nor->bouncebuf, nor->addr_width);
1136 }
1137 
1138 /**
1139  * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1140  * @erase:	pointer to a structure that describes a SPI NOR erase type
1141  * @dividend:	dividend value
1142  * @remainder:	pointer to u32 remainder (will be updated)
1143  *
1144  * Return: the result of the division
1145  */
spi_nor_div_by_erase_size(const struct spi_nor_erase_type * erase,u64 dividend,u32 * remainder)1146 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1147 				     u64 dividend, u32 *remainder)
1148 {
1149 	/* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1150 	*remainder = (u32)dividend & erase->size_mask;
1151 	return dividend >> erase->size_shift;
1152 }
1153 
1154 /**
1155  * spi_nor_find_best_erase_type() - find the best erase type for the given
1156  *				    offset in the serial flash memory and the
1157  *				    number of bytes to erase. The region in
1158  *				    which the address fits is expected to be
1159  *				    provided.
1160  * @map:	the erase map of the SPI NOR
1161  * @region:	pointer to a structure that describes a SPI NOR erase region
1162  * @addr:	offset in the serial flash memory
1163  * @len:	number of bytes to erase
1164  *
1165  * Return: a pointer to the best fitted erase type, NULL otherwise.
1166  */
1167 static const struct spi_nor_erase_type *
spi_nor_find_best_erase_type(const struct spi_nor_erase_map * map,const struct spi_nor_erase_region * region,u64 addr,u32 len)1168 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1169 			     const struct spi_nor_erase_region *region,
1170 			     u64 addr, u32 len)
1171 {
1172 	const struct spi_nor_erase_type *erase;
1173 	u32 rem;
1174 	int i;
1175 	u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1176 
1177 	/*
1178 	 * Erase types are ordered by size, with the smallest erase type at
1179 	 * index 0.
1180 	 */
1181 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1182 		/* Does the erase region support the tested erase type? */
1183 		if (!(erase_mask & BIT(i)))
1184 			continue;
1185 
1186 		erase = &map->erase_type[i];
1187 
1188 		/* Alignment is not mandatory for overlaid regions */
1189 		if (region->offset & SNOR_OVERLAID_REGION &&
1190 		    region->size <= len)
1191 			return erase;
1192 
1193 		/* Don't erase more than what the user has asked for. */
1194 		if (erase->size > len)
1195 			continue;
1196 
1197 		spi_nor_div_by_erase_size(erase, addr, &rem);
1198 		if (!rem)
1199 			return erase;
1200 	}
1201 
1202 	return NULL;
1203 }
1204 
spi_nor_region_is_last(const struct spi_nor_erase_region * region)1205 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1206 {
1207 	return region->offset & SNOR_LAST_REGION;
1208 }
1209 
spi_nor_region_end(const struct spi_nor_erase_region * region)1210 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1211 {
1212 	return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1213 }
1214 
1215 /**
1216  * spi_nor_region_next() - get the next spi nor region
1217  * @region:	pointer to a structure that describes a SPI NOR erase region
1218  *
1219  * Return: the next spi nor region or NULL if last region.
1220  */
1221 struct spi_nor_erase_region *
spi_nor_region_next(struct spi_nor_erase_region * region)1222 spi_nor_region_next(struct spi_nor_erase_region *region)
1223 {
1224 	if (spi_nor_region_is_last(region))
1225 		return NULL;
1226 	region++;
1227 	return region;
1228 }
1229 
1230 /**
1231  * spi_nor_find_erase_region() - find the region of the serial flash memory in
1232  *				 which the offset fits
1233  * @map:	the erase map of the SPI NOR
1234  * @addr:	offset in the serial flash memory
1235  *
1236  * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1237  *	   otherwise.
1238  */
1239 static struct spi_nor_erase_region *
spi_nor_find_erase_region(const struct spi_nor_erase_map * map,u64 addr)1240 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1241 {
1242 	struct spi_nor_erase_region *region = map->regions;
1243 	u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1244 	u64 region_end = region_start + region->size;
1245 
1246 	while (addr < region_start || addr >= region_end) {
1247 		region = spi_nor_region_next(region);
1248 		if (!region)
1249 			return ERR_PTR(-EINVAL);
1250 
1251 		region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1252 		region_end = region_start + region->size;
1253 	}
1254 
1255 	return region;
1256 }
1257 
1258 /**
1259  * spi_nor_init_erase_cmd() - initialize an erase command
1260  * @region:	pointer to a structure that describes a SPI NOR erase region
1261  * @erase:	pointer to a structure that describes a SPI NOR erase type
1262  *
1263  * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1264  *	   otherwise.
1265  */
1266 static struct spi_nor_erase_command *
spi_nor_init_erase_cmd(const struct spi_nor_erase_region * region,const struct spi_nor_erase_type * erase)1267 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1268 		       const struct spi_nor_erase_type *erase)
1269 {
1270 	struct spi_nor_erase_command *cmd;
1271 
1272 	cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1273 	if (!cmd)
1274 		return ERR_PTR(-ENOMEM);
1275 
1276 	INIT_LIST_HEAD(&cmd->list);
1277 	cmd->opcode = erase->opcode;
1278 	cmd->count = 1;
1279 
1280 	if (region->offset & SNOR_OVERLAID_REGION)
1281 		cmd->size = region->size;
1282 	else
1283 		cmd->size = erase->size;
1284 
1285 	return cmd;
1286 }
1287 
1288 /**
1289  * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1290  * @erase_list:	list of erase commands
1291  */
spi_nor_destroy_erase_cmd_list(struct list_head * erase_list)1292 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1293 {
1294 	struct spi_nor_erase_command *cmd, *next;
1295 
1296 	list_for_each_entry_safe(cmd, next, erase_list, list) {
1297 		list_del(&cmd->list);
1298 		kfree(cmd);
1299 	}
1300 }
1301 
1302 /**
1303  * spi_nor_init_erase_cmd_list() - initialize erase command list
1304  * @nor:	pointer to a 'struct spi_nor'
1305  * @erase_list:	list of erase commands to be executed once we validate that the
1306  *		erase can be performed
1307  * @addr:	offset in the serial flash memory
1308  * @len:	number of bytes to erase
1309  *
1310  * Builds the list of best fitted erase commands and verifies if the erase can
1311  * be performed.
1312  *
1313  * Return: 0 on success, -errno otherwise.
1314  */
spi_nor_init_erase_cmd_list(struct spi_nor * nor,struct list_head * erase_list,u64 addr,u32 len)1315 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1316 				       struct list_head *erase_list,
1317 				       u64 addr, u32 len)
1318 {
1319 	const struct spi_nor_erase_map *map = &nor->params->erase_map;
1320 	const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1321 	struct spi_nor_erase_region *region;
1322 	struct spi_nor_erase_command *cmd = NULL;
1323 	u64 region_end;
1324 	int ret = -EINVAL;
1325 
1326 	region = spi_nor_find_erase_region(map, addr);
1327 	if (IS_ERR(region))
1328 		return PTR_ERR(region);
1329 
1330 	region_end = spi_nor_region_end(region);
1331 
1332 	while (len) {
1333 		erase = spi_nor_find_best_erase_type(map, region, addr, len);
1334 		if (!erase)
1335 			goto destroy_erase_cmd_list;
1336 
1337 		if (prev_erase != erase ||
1338 		    erase->size != cmd->size ||
1339 		    region->offset & SNOR_OVERLAID_REGION) {
1340 			cmd = spi_nor_init_erase_cmd(region, erase);
1341 			if (IS_ERR(cmd)) {
1342 				ret = PTR_ERR(cmd);
1343 				goto destroy_erase_cmd_list;
1344 			}
1345 
1346 			list_add_tail(&cmd->list, erase_list);
1347 		} else {
1348 			cmd->count++;
1349 		}
1350 
1351 		addr += cmd->size;
1352 		len -= cmd->size;
1353 
1354 		if (len && addr >= region_end) {
1355 			region = spi_nor_region_next(region);
1356 			if (!region)
1357 				goto destroy_erase_cmd_list;
1358 			region_end = spi_nor_region_end(region);
1359 		}
1360 
1361 		prev_erase = erase;
1362 	}
1363 
1364 	return 0;
1365 
1366 destroy_erase_cmd_list:
1367 	spi_nor_destroy_erase_cmd_list(erase_list);
1368 	return ret;
1369 }
1370 
1371 /**
1372  * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1373  * @nor:	pointer to a 'struct spi_nor'
1374  * @addr:	offset in the serial flash memory
1375  * @len:	number of bytes to erase
1376  *
1377  * Build a list of best fitted erase commands and execute it once we validate
1378  * that the erase can be performed.
1379  *
1380  * Return: 0 on success, -errno otherwise.
1381  */
spi_nor_erase_multi_sectors(struct spi_nor * nor,u64 addr,u32 len)1382 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1383 {
1384 	LIST_HEAD(erase_list);
1385 	struct spi_nor_erase_command *cmd, *next;
1386 	int ret;
1387 
1388 	ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1389 	if (ret)
1390 		return ret;
1391 
1392 	list_for_each_entry_safe(cmd, next, &erase_list, list) {
1393 		nor->erase_opcode = cmd->opcode;
1394 		while (cmd->count) {
1395 			dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1396 				 cmd->size, cmd->opcode, cmd->count);
1397 
1398 			ret = spi_nor_write_enable(nor);
1399 			if (ret)
1400 				goto destroy_erase_cmd_list;
1401 
1402 			ret = spi_nor_erase_sector(nor, addr);
1403 			if (ret)
1404 				goto destroy_erase_cmd_list;
1405 
1406 			ret = spi_nor_wait_till_ready(nor);
1407 			if (ret)
1408 				goto destroy_erase_cmd_list;
1409 
1410 			addr += cmd->size;
1411 			cmd->count--;
1412 		}
1413 		list_del(&cmd->list);
1414 		kfree(cmd);
1415 	}
1416 
1417 	return 0;
1418 
1419 destroy_erase_cmd_list:
1420 	spi_nor_destroy_erase_cmd_list(&erase_list);
1421 	return ret;
1422 }
1423 
1424 /*
1425  * Erase an address range on the nor chip.  The address range may extend
1426  * one or more erase sectors. Return an error if there is a problem erasing.
1427  */
spi_nor_erase(struct mtd_info * mtd,struct erase_info * instr)1428 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1429 {
1430 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
1431 	u32 addr, len;
1432 	uint32_t rem;
1433 	int ret;
1434 
1435 	dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1436 			(long long)instr->len);
1437 
1438 	if (spi_nor_has_uniform_erase(nor)) {
1439 		div_u64_rem(instr->len, mtd->erasesize, &rem);
1440 		if (rem)
1441 			return -EINVAL;
1442 	}
1443 
1444 	addr = instr->addr;
1445 	len = instr->len;
1446 
1447 	ret = spi_nor_lock_and_prep(nor);
1448 	if (ret)
1449 		return ret;
1450 
1451 	/* whole-chip erase? */
1452 	if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1453 		unsigned long timeout;
1454 
1455 		ret = spi_nor_write_enable(nor);
1456 		if (ret)
1457 			goto erase_err;
1458 
1459 		ret = spi_nor_erase_chip(nor);
1460 		if (ret)
1461 			goto erase_err;
1462 
1463 		/*
1464 		 * Scale the timeout linearly with the size of the flash, with
1465 		 * a minimum calibrated to an old 2MB flash. We could try to
1466 		 * pull these from CFI/SFDP, but these values should be good
1467 		 * enough for now.
1468 		 */
1469 		timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1470 			      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1471 			      (unsigned long)(mtd->size / SZ_2M));
1472 		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1473 		if (ret)
1474 			goto erase_err;
1475 
1476 	/* REVISIT in some cases we could speed up erasing large regions
1477 	 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K.  We may have set up
1478 	 * to use "small sector erase", but that's not always optimal.
1479 	 */
1480 
1481 	/* "sector"-at-a-time erase */
1482 	} else if (spi_nor_has_uniform_erase(nor)) {
1483 		while (len) {
1484 			ret = spi_nor_write_enable(nor);
1485 			if (ret)
1486 				goto erase_err;
1487 
1488 			ret = spi_nor_erase_sector(nor, addr);
1489 			if (ret)
1490 				goto erase_err;
1491 
1492 			ret = spi_nor_wait_till_ready(nor);
1493 			if (ret)
1494 				goto erase_err;
1495 
1496 			addr += mtd->erasesize;
1497 			len -= mtd->erasesize;
1498 		}
1499 
1500 	/* erase multiple sectors */
1501 	} else {
1502 		ret = spi_nor_erase_multi_sectors(nor, addr, len);
1503 		if (ret)
1504 			goto erase_err;
1505 	}
1506 
1507 	ret = spi_nor_write_disable(nor);
1508 
1509 erase_err:
1510 	spi_nor_unlock_and_unprep(nor);
1511 
1512 	return ret;
1513 }
1514 
1515 /**
1516  * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1517  * Register 1.
1518  * @nor:	pointer to a 'struct spi_nor'
1519  *
1520  * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1521  *
1522  * Return: 0 on success, -errno otherwise.
1523  */
spi_nor_sr1_bit6_quad_enable(struct spi_nor * nor)1524 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1525 {
1526 	int ret;
1527 
1528 	ret = spi_nor_read_sr(nor, nor->bouncebuf);
1529 	if (ret)
1530 		return ret;
1531 
1532 	if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1533 		return 0;
1534 
1535 	nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1536 
1537 	return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1538 }
1539 
1540 /**
1541  * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1542  * Register 2.
1543  * @nor:       pointer to a 'struct spi_nor'.
1544  *
1545  * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1546  *
1547  * Return: 0 on success, -errno otherwise.
1548  */
spi_nor_sr2_bit1_quad_enable(struct spi_nor * nor)1549 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1550 {
1551 	int ret;
1552 
1553 	if (nor->flags & SNOR_F_NO_READ_CR)
1554 		return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1555 
1556 	ret = spi_nor_read_cr(nor, nor->bouncebuf);
1557 	if (ret)
1558 		return ret;
1559 
1560 	if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1561 		return 0;
1562 
1563 	nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1564 
1565 	return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1566 }
1567 
1568 /**
1569  * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1570  * @nor:	pointer to a 'struct spi_nor'
1571  *
1572  * Set the Quad Enable (QE) bit in the Status Register 2.
1573  *
1574  * This is one of the procedures to set the QE bit described in the SFDP
1575  * (JESD216 rev B) specification but no manufacturer using this procedure has
1576  * been identified yet, hence the name of the function.
1577  *
1578  * Return: 0 on success, -errno otherwise.
1579  */
spi_nor_sr2_bit7_quad_enable(struct spi_nor * nor)1580 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1581 {
1582 	u8 *sr2 = nor->bouncebuf;
1583 	int ret;
1584 	u8 sr2_written;
1585 
1586 	/* Check current Quad Enable bit value. */
1587 	ret = spi_nor_read_sr2(nor, sr2);
1588 	if (ret)
1589 		return ret;
1590 	if (*sr2 & SR2_QUAD_EN_BIT7)
1591 		return 0;
1592 
1593 	/* Update the Quad Enable bit. */
1594 	*sr2 |= SR2_QUAD_EN_BIT7;
1595 
1596 	ret = spi_nor_write_sr2(nor, sr2);
1597 	if (ret)
1598 		return ret;
1599 
1600 	sr2_written = *sr2;
1601 
1602 	/* Read back and check it. */
1603 	ret = spi_nor_read_sr2(nor, sr2);
1604 	if (ret)
1605 		return ret;
1606 
1607 	if (*sr2 != sr2_written) {
1608 		dev_dbg(nor->dev, "SR2: Read back test failed\n");
1609 		return -EIO;
1610 	}
1611 
1612 	return 0;
1613 }
1614 
1615 static const struct spi_nor_manufacturer *manufacturers[] = {
1616 	&spi_nor_atmel,
1617 	&spi_nor_catalyst,
1618 	&spi_nor_eon,
1619 	&spi_nor_esmt,
1620 	&spi_nor_everspin,
1621 	&spi_nor_fujitsu,
1622 	&spi_nor_gigadevice,
1623 	&spi_nor_intel,
1624 	&spi_nor_issi,
1625 	&spi_nor_macronix,
1626 	&spi_nor_micron,
1627 	&spi_nor_st,
1628 	&spi_nor_spansion,
1629 	&spi_nor_sst,
1630 	&spi_nor_winbond,
1631 	&spi_nor_xilinx,
1632 	&spi_nor_xmc,
1633 };
1634 
spi_nor_match_id(struct spi_nor * nor,const u8 * id)1635 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
1636 						 const u8 *id)
1637 {
1638 	const struct flash_info *part;
1639 	unsigned int i, j;
1640 
1641 	for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
1642 		for (j = 0; j < manufacturers[i]->nparts; j++) {
1643 			part = &manufacturers[i]->parts[j];
1644 			if (part->id_len &&
1645 			    !memcmp(part->id, id, part->id_len)) {
1646 				nor->manufacturer = manufacturers[i];
1647 				return part;
1648 			}
1649 		}
1650 	}
1651 
1652 	return NULL;
1653 }
1654 
spi_nor_detect(struct spi_nor * nor)1655 static const struct flash_info *spi_nor_detect(struct spi_nor *nor)
1656 {
1657 	const struct flash_info *info;
1658 	u8 *id = nor->bouncebuf;
1659 	int ret;
1660 
1661 	ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);
1662 	if (ret) {
1663 		dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
1664 		return ERR_PTR(ret);
1665 	}
1666 
1667 	info = spi_nor_match_id(nor, id);
1668 	if (!info) {
1669 		dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
1670 			SPI_NOR_MAX_ID_LEN, id);
1671 		return ERR_PTR(-ENODEV);
1672 	}
1673 	return info;
1674 }
1675 
spi_nor_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1676 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1677 			size_t *retlen, u_char *buf)
1678 {
1679 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
1680 	ssize_t ret;
1681 
1682 	dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1683 
1684 	ret = spi_nor_lock_and_prep(nor);
1685 	if (ret)
1686 		return ret;
1687 
1688 	while (len) {
1689 		loff_t addr = from;
1690 
1691 		addr = spi_nor_convert_addr(nor, addr);
1692 
1693 		ret = spi_nor_read_data(nor, addr, len, buf);
1694 		if (ret == 0) {
1695 			/* We shouldn't see 0-length reads */
1696 			ret = -EIO;
1697 			goto read_err;
1698 		}
1699 		if (ret < 0)
1700 			goto read_err;
1701 
1702 		WARN_ON(ret > len);
1703 		*retlen += ret;
1704 		buf += ret;
1705 		from += ret;
1706 		len -= ret;
1707 	}
1708 	ret = 0;
1709 
1710 read_err:
1711 	spi_nor_unlock_and_unprep(nor);
1712 	return ret;
1713 }
1714 
1715 /*
1716  * Write an address range to the nor chip.  Data must be written in
1717  * FLASH_PAGESIZE chunks.  The address range may be any size provided
1718  * it is within the physical boundaries.
1719  */
spi_nor_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1720 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1721 	size_t *retlen, const u_char *buf)
1722 {
1723 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
1724 	size_t page_offset, page_remain, i;
1725 	ssize_t ret;
1726 	u32 page_size = nor->params->page_size;
1727 
1728 	dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1729 
1730 	ret = spi_nor_lock_and_prep(nor);
1731 	if (ret)
1732 		return ret;
1733 
1734 	for (i = 0; i < len; ) {
1735 		ssize_t written;
1736 		loff_t addr = to + i;
1737 
1738 		/*
1739 		 * If page_size is a power of two, the offset can be quickly
1740 		 * calculated with an AND operation. On the other cases we
1741 		 * need to do a modulus operation (more expensive).
1742 		 */
1743 		if (is_power_of_2(page_size)) {
1744 			page_offset = addr & (page_size - 1);
1745 		} else {
1746 			uint64_t aux = addr;
1747 
1748 			page_offset = do_div(aux, page_size);
1749 		}
1750 		/* the size of data remaining on the first page */
1751 		page_remain = min_t(size_t, page_size - page_offset, len - i);
1752 
1753 		addr = spi_nor_convert_addr(nor, addr);
1754 
1755 		ret = spi_nor_write_enable(nor);
1756 		if (ret)
1757 			goto write_err;
1758 
1759 		ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
1760 		if (ret < 0)
1761 			goto write_err;
1762 		written = ret;
1763 
1764 		ret = spi_nor_wait_till_ready(nor);
1765 		if (ret)
1766 			goto write_err;
1767 		*retlen += written;
1768 		i += written;
1769 	}
1770 
1771 write_err:
1772 	spi_nor_unlock_and_unprep(nor);
1773 	return ret;
1774 }
1775 
spi_nor_check(struct spi_nor * nor)1776 static int spi_nor_check(struct spi_nor *nor)
1777 {
1778 	if (!nor->dev ||
1779 	    (!nor->spimem && !nor->controller_ops) ||
1780 	    (!nor->spimem && nor->controller_ops &&
1781 	    (!nor->controller_ops->read ||
1782 	     !nor->controller_ops->write ||
1783 	     !nor->controller_ops->read_reg ||
1784 	     !nor->controller_ops->write_reg))) {
1785 		pr_err("spi-nor: please fill all the necessary fields!\n");
1786 		return -EINVAL;
1787 	}
1788 
1789 	if (nor->spimem && nor->controller_ops) {
1790 		dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
1791 		return -EINVAL;
1792 	}
1793 
1794 	return 0;
1795 }
1796 
1797 void
spi_nor_set_read_settings(struct spi_nor_read_command * read,u8 num_mode_clocks,u8 num_wait_states,u8 opcode,enum spi_nor_protocol proto)1798 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1799 			  u8 num_mode_clocks,
1800 			  u8 num_wait_states,
1801 			  u8 opcode,
1802 			  enum spi_nor_protocol proto)
1803 {
1804 	read->num_mode_clocks = num_mode_clocks;
1805 	read->num_wait_states = num_wait_states;
1806 	read->opcode = opcode;
1807 	read->proto = proto;
1808 }
1809 
spi_nor_set_pp_settings(struct spi_nor_pp_command * pp,u8 opcode,enum spi_nor_protocol proto)1810 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
1811 			     enum spi_nor_protocol proto)
1812 {
1813 	pp->opcode = opcode;
1814 	pp->proto = proto;
1815 }
1816 
spi_nor_hwcaps2cmd(u32 hwcaps,const int table[][2],size_t size)1817 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
1818 {
1819 	size_t i;
1820 
1821 	for (i = 0; i < size; i++)
1822 		if (table[i][0] == (int)hwcaps)
1823 			return table[i][1];
1824 
1825 	return -EINVAL;
1826 }
1827 
spi_nor_hwcaps_read2cmd(u32 hwcaps)1828 int spi_nor_hwcaps_read2cmd(u32 hwcaps)
1829 {
1830 	static const int hwcaps_read2cmd[][2] = {
1831 		{ SNOR_HWCAPS_READ,		SNOR_CMD_READ },
1832 		{ SNOR_HWCAPS_READ_FAST,	SNOR_CMD_READ_FAST },
1833 		{ SNOR_HWCAPS_READ_1_1_1_DTR,	SNOR_CMD_READ_1_1_1_DTR },
1834 		{ SNOR_HWCAPS_READ_1_1_2,	SNOR_CMD_READ_1_1_2 },
1835 		{ SNOR_HWCAPS_READ_1_2_2,	SNOR_CMD_READ_1_2_2 },
1836 		{ SNOR_HWCAPS_READ_2_2_2,	SNOR_CMD_READ_2_2_2 },
1837 		{ SNOR_HWCAPS_READ_1_2_2_DTR,	SNOR_CMD_READ_1_2_2_DTR },
1838 		{ SNOR_HWCAPS_READ_1_1_4,	SNOR_CMD_READ_1_1_4 },
1839 		{ SNOR_HWCAPS_READ_1_4_4,	SNOR_CMD_READ_1_4_4 },
1840 		{ SNOR_HWCAPS_READ_4_4_4,	SNOR_CMD_READ_4_4_4 },
1841 		{ SNOR_HWCAPS_READ_1_4_4_DTR,	SNOR_CMD_READ_1_4_4_DTR },
1842 		{ SNOR_HWCAPS_READ_1_1_8,	SNOR_CMD_READ_1_1_8 },
1843 		{ SNOR_HWCAPS_READ_1_8_8,	SNOR_CMD_READ_1_8_8 },
1844 		{ SNOR_HWCAPS_READ_8_8_8,	SNOR_CMD_READ_8_8_8 },
1845 		{ SNOR_HWCAPS_READ_1_8_8_DTR,	SNOR_CMD_READ_1_8_8_DTR },
1846 		{ SNOR_HWCAPS_READ_8_8_8_DTR,	SNOR_CMD_READ_8_8_8_DTR },
1847 	};
1848 
1849 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
1850 				  ARRAY_SIZE(hwcaps_read2cmd));
1851 }
1852 
spi_nor_hwcaps_pp2cmd(u32 hwcaps)1853 int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
1854 {
1855 	static const int hwcaps_pp2cmd[][2] = {
1856 		{ SNOR_HWCAPS_PP,		SNOR_CMD_PP },
1857 		{ SNOR_HWCAPS_PP_1_1_4,		SNOR_CMD_PP_1_1_4 },
1858 		{ SNOR_HWCAPS_PP_1_4_4,		SNOR_CMD_PP_1_4_4 },
1859 		{ SNOR_HWCAPS_PP_4_4_4,		SNOR_CMD_PP_4_4_4 },
1860 		{ SNOR_HWCAPS_PP_1_1_8,		SNOR_CMD_PP_1_1_8 },
1861 		{ SNOR_HWCAPS_PP_1_8_8,		SNOR_CMD_PP_1_8_8 },
1862 		{ SNOR_HWCAPS_PP_8_8_8,		SNOR_CMD_PP_8_8_8 },
1863 		{ SNOR_HWCAPS_PP_8_8_8_DTR,	SNOR_CMD_PP_8_8_8_DTR },
1864 	};
1865 
1866 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
1867 				  ARRAY_SIZE(hwcaps_pp2cmd));
1868 }
1869 
1870 /**
1871  * spi_nor_spimem_check_op - check if the operation is supported
1872  *                           by controller
1873  *@nor:        pointer to a 'struct spi_nor'
1874  *@op:         pointer to op template to be checked
1875  *
1876  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1877  */
spi_nor_spimem_check_op(struct spi_nor * nor,struct spi_mem_op * op)1878 static int spi_nor_spimem_check_op(struct spi_nor *nor,
1879 				   struct spi_mem_op *op)
1880 {
1881 	/*
1882 	 * First test with 4 address bytes. The opcode itself might
1883 	 * be a 3B addressing opcode but we don't care, because
1884 	 * SPI controller implementation should not check the opcode,
1885 	 * but just the sequence.
1886 	 */
1887 	op->addr.nbytes = 4;
1888 	if (!spi_mem_supports_op(nor->spimem, op)) {
1889 		if (nor->params->size > SZ_16M)
1890 			return -EOPNOTSUPP;
1891 
1892 		/* If flash size <= 16MB, 3 address bytes are sufficient */
1893 		op->addr.nbytes = 3;
1894 		if (!spi_mem_supports_op(nor->spimem, op))
1895 			return -EOPNOTSUPP;
1896 	}
1897 
1898 	return 0;
1899 }
1900 
1901 /**
1902  * spi_nor_spimem_check_readop - check if the read op is supported
1903  *                               by controller
1904  *@nor:         pointer to a 'struct spi_nor'
1905  *@read:        pointer to op template to be checked
1906  *
1907  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1908  */
spi_nor_spimem_check_readop(struct spi_nor * nor,const struct spi_nor_read_command * read)1909 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
1910 				       const struct spi_nor_read_command *read)
1911 {
1912 	struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);
1913 
1914 	spi_nor_spimem_setup_op(nor, &op, read->proto);
1915 
1916 	/* convert the dummy cycles to the number of bytes */
1917 	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
1918 	if (spi_nor_protocol_is_dtr(nor->read_proto))
1919 		op.dummy.nbytes *= 2;
1920 
1921 	return spi_nor_spimem_check_op(nor, &op);
1922 }
1923 
1924 /**
1925  * spi_nor_spimem_check_pp - check if the page program op is supported
1926  *                           by controller
1927  *@nor:         pointer to a 'struct spi_nor'
1928  *@pp:          pointer to op template to be checked
1929  *
1930  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
1931  */
spi_nor_spimem_check_pp(struct spi_nor * nor,const struct spi_nor_pp_command * pp)1932 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
1933 				   const struct spi_nor_pp_command *pp)
1934 {
1935 	struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);
1936 
1937 	spi_nor_spimem_setup_op(nor, &op, pp->proto);
1938 
1939 	return spi_nor_spimem_check_op(nor, &op);
1940 }
1941 
1942 /**
1943  * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
1944  *                                based on SPI controller capabilities
1945  * @nor:        pointer to a 'struct spi_nor'
1946  * @hwcaps:     pointer to resulting capabilities after adjusting
1947  *              according to controller and flash's capability
1948  */
1949 static void
spi_nor_spimem_adjust_hwcaps(struct spi_nor * nor,u32 * hwcaps)1950 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
1951 {
1952 	struct spi_nor_flash_parameter *params = nor->params;
1953 	unsigned int cap;
1954 
1955 	/* X-X-X modes are not supported yet, mask them all. */
1956 	*hwcaps &= ~SNOR_HWCAPS_X_X_X;
1957 
1958 	/*
1959 	 * If the reset line is broken, we do not want to enter a stateful
1960 	 * mode.
1961 	 */
1962 	if (nor->flags & SNOR_F_BROKEN_RESET)
1963 		*hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
1964 
1965 	for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
1966 		int rdidx, ppidx;
1967 
1968 		if (!(*hwcaps & BIT(cap)))
1969 			continue;
1970 
1971 		rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
1972 		if (rdidx >= 0 &&
1973 		    spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
1974 			*hwcaps &= ~BIT(cap);
1975 
1976 		ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
1977 		if (ppidx < 0)
1978 			continue;
1979 
1980 		if (spi_nor_spimem_check_pp(nor,
1981 					    &params->page_programs[ppidx]))
1982 			*hwcaps &= ~BIT(cap);
1983 	}
1984 }
1985 
1986 /**
1987  * spi_nor_set_erase_type() - set a SPI NOR erase type
1988  * @erase:	pointer to a structure that describes a SPI NOR erase type
1989  * @size:	the size of the sector/block erased by the erase type
1990  * @opcode:	the SPI command op code to erase the sector/block
1991  */
spi_nor_set_erase_type(struct spi_nor_erase_type * erase,u32 size,u8 opcode)1992 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
1993 			    u8 opcode)
1994 {
1995 	erase->size = size;
1996 	erase->opcode = opcode;
1997 	/* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1998 	erase->size_shift = ffs(erase->size) - 1;
1999 	erase->size_mask = (1 << erase->size_shift) - 1;
2000 }
2001 
2002 /**
2003  * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2004  * @map:		the erase map of the SPI NOR
2005  * @erase_mask:		bitmask encoding erase types that can erase the entire
2006  *			flash memory
2007  * @flash_size:		the spi nor flash memory size
2008  */
spi_nor_init_uniform_erase_map(struct spi_nor_erase_map * map,u8 erase_mask,u64 flash_size)2009 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2010 				    u8 erase_mask, u64 flash_size)
2011 {
2012 	/* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2013 	map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2014 				     SNOR_LAST_REGION;
2015 	map->uniform_region.size = flash_size;
2016 	map->regions = &map->uniform_region;
2017 	map->uniform_erase_type = erase_mask;
2018 }
2019 
spi_nor_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)2020 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2021 			     const struct sfdp_parameter_header *bfpt_header,
2022 			     const struct sfdp_bfpt *bfpt)
2023 {
2024 	int ret;
2025 
2026 	if (nor->manufacturer && nor->manufacturer->fixups &&
2027 	    nor->manufacturer->fixups->post_bfpt) {
2028 		ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2029 							   bfpt);
2030 		if (ret)
2031 			return ret;
2032 	}
2033 
2034 	if (nor->info->fixups && nor->info->fixups->post_bfpt)
2035 		return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2036 
2037 	return 0;
2038 }
2039 
spi_nor_select_read(struct spi_nor * nor,u32 shared_hwcaps)2040 static int spi_nor_select_read(struct spi_nor *nor,
2041 			       u32 shared_hwcaps)
2042 {
2043 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2044 	const struct spi_nor_read_command *read;
2045 
2046 	if (best_match < 0)
2047 		return -EINVAL;
2048 
2049 	cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2050 	if (cmd < 0)
2051 		return -EINVAL;
2052 
2053 	read = &nor->params->reads[cmd];
2054 	nor->read_opcode = read->opcode;
2055 	nor->read_proto = read->proto;
2056 
2057 	/*
2058 	 * In the SPI NOR framework, we don't need to make the difference
2059 	 * between mode clock cycles and wait state clock cycles.
2060 	 * Indeed, the value of the mode clock cycles is used by a QSPI
2061 	 * flash memory to know whether it should enter or leave its 0-4-4
2062 	 * (Continuous Read / XIP) mode.
2063 	 * eXecution In Place is out of the scope of the mtd sub-system.
2064 	 * Hence we choose to merge both mode and wait state clock cycles
2065 	 * into the so called dummy clock cycles.
2066 	 */
2067 	nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2068 	return 0;
2069 }
2070 
spi_nor_select_pp(struct spi_nor * nor,u32 shared_hwcaps)2071 static int spi_nor_select_pp(struct spi_nor *nor,
2072 			     u32 shared_hwcaps)
2073 {
2074 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2075 	const struct spi_nor_pp_command *pp;
2076 
2077 	if (best_match < 0)
2078 		return -EINVAL;
2079 
2080 	cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2081 	if (cmd < 0)
2082 		return -EINVAL;
2083 
2084 	pp = &nor->params->page_programs[cmd];
2085 	nor->program_opcode = pp->opcode;
2086 	nor->write_proto = pp->proto;
2087 	return 0;
2088 }
2089 
2090 /**
2091  * spi_nor_select_uniform_erase() - select optimum uniform erase type
2092  * @map:		the erase map of the SPI NOR
2093  * @wanted_size:	the erase type size to search for. Contains the value of
2094  *			info->sector_size or of the "small sector" size in case
2095  *			CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
2096  *
2097  * Once the optimum uniform sector erase command is found, disable all the
2098  * other.
2099  *
2100  * Return: pointer to erase type on success, NULL otherwise.
2101  */
2102 static const struct spi_nor_erase_type *
spi_nor_select_uniform_erase(struct spi_nor_erase_map * map,const u32 wanted_size)2103 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2104 			     const u32 wanted_size)
2105 {
2106 	const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2107 	int i;
2108 	u8 uniform_erase_type = map->uniform_erase_type;
2109 
2110 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2111 		if (!(uniform_erase_type & BIT(i)))
2112 			continue;
2113 
2114 		tested_erase = &map->erase_type[i];
2115 
2116 		/*
2117 		 * If the current erase size is the one, stop here:
2118 		 * we have found the right uniform Sector Erase command.
2119 		 */
2120 		if (tested_erase->size == wanted_size) {
2121 			erase = tested_erase;
2122 			break;
2123 		}
2124 
2125 		/*
2126 		 * Otherwise, the current erase size is still a valid candidate.
2127 		 * Select the biggest valid candidate.
2128 		 */
2129 		if (!erase && tested_erase->size)
2130 			erase = tested_erase;
2131 			/* keep iterating to find the wanted_size */
2132 	}
2133 
2134 	if (!erase)
2135 		return NULL;
2136 
2137 	/* Disable all other Sector Erase commands. */
2138 	map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2139 	map->uniform_erase_type |= BIT(erase - map->erase_type);
2140 	return erase;
2141 }
2142 
spi_nor_select_erase(struct spi_nor * nor)2143 static int spi_nor_select_erase(struct spi_nor *nor)
2144 {
2145 	struct spi_nor_erase_map *map = &nor->params->erase_map;
2146 	const struct spi_nor_erase_type *erase = NULL;
2147 	struct mtd_info *mtd = &nor->mtd;
2148 	u32 wanted_size = nor->info->sector_size;
2149 	int i;
2150 
2151 	/*
2152 	 * The previous implementation handling Sector Erase commands assumed
2153 	 * that the SPI flash memory has an uniform layout then used only one
2154 	 * of the supported erase sizes for all Sector Erase commands.
2155 	 * So to be backward compatible, the new implementation also tries to
2156 	 * manage the SPI flash memory as uniform with a single erase sector
2157 	 * size, when possible.
2158 	 */
2159 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2160 	/* prefer "small sector" erase if possible */
2161 	wanted_size = 4096u;
2162 #endif
2163 
2164 	if (spi_nor_has_uniform_erase(nor)) {
2165 		erase = spi_nor_select_uniform_erase(map, wanted_size);
2166 		if (!erase)
2167 			return -EINVAL;
2168 		nor->erase_opcode = erase->opcode;
2169 		mtd->erasesize = erase->size;
2170 		return 0;
2171 	}
2172 
2173 	/*
2174 	 * For non-uniform SPI flash memory, set mtd->erasesize to the
2175 	 * maximum erase sector size. No need to set nor->erase_opcode.
2176 	 */
2177 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2178 		if (map->erase_type[i].size) {
2179 			erase = &map->erase_type[i];
2180 			break;
2181 		}
2182 	}
2183 
2184 	if (!erase)
2185 		return -EINVAL;
2186 
2187 	mtd->erasesize = erase->size;
2188 	return 0;
2189 }
2190 
spi_nor_default_setup(struct spi_nor * nor,const struct spi_nor_hwcaps * hwcaps)2191 static int spi_nor_default_setup(struct spi_nor *nor,
2192 				 const struct spi_nor_hwcaps *hwcaps)
2193 {
2194 	struct spi_nor_flash_parameter *params = nor->params;
2195 	u32 ignored_mask, shared_mask;
2196 	int err;
2197 
2198 	/*
2199 	 * Keep only the hardware capabilities supported by both the SPI
2200 	 * controller and the SPI flash memory.
2201 	 */
2202 	shared_mask = hwcaps->mask & params->hwcaps.mask;
2203 
2204 	if (nor->spimem) {
2205 		/*
2206 		 * When called from spi_nor_probe(), all caps are set and we
2207 		 * need to discard some of them based on what the SPI
2208 		 * controller actually supports (using spi_mem_supports_op()).
2209 		 */
2210 		spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2211 	} else {
2212 		/*
2213 		 * SPI n-n-n protocols are not supported when the SPI
2214 		 * controller directly implements the spi_nor interface.
2215 		 * Yet another reason to switch to spi-mem.
2216 		 */
2217 		ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2218 		if (shared_mask & ignored_mask) {
2219 			dev_dbg(nor->dev,
2220 				"SPI n-n-n protocols are not supported.\n");
2221 			shared_mask &= ~ignored_mask;
2222 		}
2223 	}
2224 
2225 	/* Select the (Fast) Read command. */
2226 	err = spi_nor_select_read(nor, shared_mask);
2227 	if (err) {
2228 		dev_dbg(nor->dev,
2229 			"can't select read settings supported by both the SPI controller and memory.\n");
2230 		return err;
2231 	}
2232 
2233 	/* Select the Page Program command. */
2234 	err = spi_nor_select_pp(nor, shared_mask);
2235 	if (err) {
2236 		dev_dbg(nor->dev,
2237 			"can't select write settings supported by both the SPI controller and memory.\n");
2238 		return err;
2239 	}
2240 
2241 	/* Select the Sector Erase command. */
2242 	err = spi_nor_select_erase(nor);
2243 	if (err) {
2244 		dev_dbg(nor->dev,
2245 			"can't select erase settings supported by both the SPI controller and memory.\n");
2246 		return err;
2247 	}
2248 
2249 	return 0;
2250 }
2251 
spi_nor_set_addr_width(struct spi_nor * nor)2252 static int spi_nor_set_addr_width(struct spi_nor *nor)
2253 {
2254 	if (nor->addr_width) {
2255 		/* already configured from SFDP */
2256 	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2257 		/*
2258 		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
2259 		 * in this protocol an odd address width cannot be used because
2260 		 * then the address phase would only span a cycle and a half.
2261 		 * Half a cycle would be left over. We would then have to start
2262 		 * the dummy phase in the middle of a cycle and so too the data
2263 		 * phase, and we will end the transaction with half a cycle left
2264 		 * over.
2265 		 *
2266 		 * Force all 8D-8D-8D flashes to use an address width of 4 to
2267 		 * avoid this situation.
2268 		 */
2269 		nor->addr_width = 4;
2270 	} else if (nor->info->addr_width) {
2271 		nor->addr_width = nor->info->addr_width;
2272 	} else {
2273 		nor->addr_width = 3;
2274 	}
2275 
2276 	if (nor->addr_width == 3 && nor->params->size > 0x1000000) {
2277 		/* enable 4-byte addressing if the device exceeds 16MiB */
2278 		nor->addr_width = 4;
2279 	}
2280 
2281 	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2282 		dev_dbg(nor->dev, "address width is too large: %u\n",
2283 			nor->addr_width);
2284 		return -EINVAL;
2285 	}
2286 
2287 	/* Set 4byte opcodes when possible. */
2288 	if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
2289 	    !(nor->flags & SNOR_F_HAS_4BAIT))
2290 		spi_nor_set_4byte_opcodes(nor);
2291 
2292 	return 0;
2293 }
2294 
spi_nor_setup(struct spi_nor * nor,const struct spi_nor_hwcaps * hwcaps)2295 static int spi_nor_setup(struct spi_nor *nor,
2296 			 const struct spi_nor_hwcaps *hwcaps)
2297 {
2298 	int ret;
2299 
2300 	if (nor->params->setup)
2301 		ret = nor->params->setup(nor, hwcaps);
2302 	else
2303 		ret = spi_nor_default_setup(nor, hwcaps);
2304 	if (ret)
2305 		return ret;
2306 
2307 	return spi_nor_set_addr_width(nor);
2308 }
2309 
2310 /**
2311  * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2312  * settings based on MFR register and ->default_init() hook.
2313  * @nor:	pointer to a 'struct spi_nor'.
2314  */
spi_nor_manufacturer_init_params(struct spi_nor * nor)2315 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2316 {
2317 	if (nor->manufacturer && nor->manufacturer->fixups &&
2318 	    nor->manufacturer->fixups->default_init)
2319 		nor->manufacturer->fixups->default_init(nor);
2320 
2321 	if (nor->info->fixups && nor->info->fixups->default_init)
2322 		nor->info->fixups->default_init(nor);
2323 }
2324 
2325 /**
2326  * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2327  * settings based on nor->info->sfdp_flags. This method should be called only by
2328  * flashes that do not define SFDP tables. If the flash supports SFDP but the
2329  * information is wrong and the settings from this function can not be retrieved
2330  * by parsing SFDP, one should instead use the fixup hooks and update the wrong
2331  * bits.
2332  * @nor:	pointer to a 'struct spi_nor'.
2333  */
spi_nor_no_sfdp_init_params(struct spi_nor * nor)2334 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
2335 {
2336 	struct spi_nor_flash_parameter *params = nor->params;
2337 	struct spi_nor_erase_map *map = &params->erase_map;
2338 	const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
2339 	u8 i, erase_mask;
2340 
2341 	if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
2342 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2343 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2344 					  0, 8, SPINOR_OP_READ_1_1_2,
2345 					  SNOR_PROTO_1_1_2);
2346 	}
2347 
2348 	if (no_sfdp_flags & SPI_NOR_QUAD_READ) {
2349 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2350 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2351 					  0, 8, SPINOR_OP_READ_1_1_4,
2352 					  SNOR_PROTO_1_1_4);
2353 	}
2354 
2355 	if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {
2356 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2357 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
2358 					  0, 8, SPINOR_OP_READ_1_1_8,
2359 					  SNOR_PROTO_1_1_8);
2360 	}
2361 
2362 	if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
2363 		params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2364 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
2365 					  0, 20, SPINOR_OP_READ_FAST,
2366 					  SNOR_PROTO_8_8_8_DTR);
2367 	}
2368 
2369 	if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
2370 		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2371 		/*
2372 		 * Since xSPI Page Program opcode is backward compatible with
2373 		 * Legacy SPI, use Legacy SPI opcode there as well.
2374 		 */
2375 		spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2376 					SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2377 	}
2378 
2379 	/*
2380 	 * Sector Erase settings. Sort Erase Types in ascending order, with the
2381 	 * smallest erase size starting at BIT(0).
2382 	 */
2383 	erase_mask = 0;
2384 	i = 0;
2385 	if (no_sfdp_flags & SECT_4K_PMC) {
2386 		erase_mask |= BIT(i);
2387 		spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2388 				       SPINOR_OP_BE_4K_PMC);
2389 		i++;
2390 	} else if (no_sfdp_flags & SECT_4K) {
2391 		erase_mask |= BIT(i);
2392 		spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2393 				       SPINOR_OP_BE_4K);
2394 		i++;
2395 	}
2396 	erase_mask |= BIT(i);
2397 	spi_nor_set_erase_type(&map->erase_type[i], nor->info->sector_size,
2398 			       SPINOR_OP_SE);
2399 	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2400 }
2401 
2402 /**
2403  * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2404  * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.
2405  * @nor:	pointer to a 'struct spi_nor'
2406  */
spi_nor_init_flags(struct spi_nor * nor)2407 static void spi_nor_init_flags(struct spi_nor *nor)
2408 {
2409 	struct device_node *np = spi_nor_get_flash_node(nor);
2410 	const u16 flags = nor->info->flags;
2411 
2412 	if (of_property_read_bool(np, "broken-flash-reset"))
2413 		nor->flags |= SNOR_F_BROKEN_RESET;
2414 
2415 	if (flags & SPI_NOR_SWP_IS_VOLATILE)
2416 		nor->flags |= SNOR_F_SWP_IS_VOLATILE;
2417 
2418 	if (flags & SPI_NOR_HAS_LOCK)
2419 		nor->flags |= SNOR_F_HAS_LOCK;
2420 
2421 	if (flags & SPI_NOR_HAS_TB) {
2422 		nor->flags |= SNOR_F_HAS_SR_TB;
2423 		if (flags & SPI_NOR_TB_SR_BIT6)
2424 			nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
2425 	}
2426 
2427 	if (flags & SPI_NOR_4BIT_BP) {
2428 		nor->flags |= SNOR_F_HAS_4BIT_BP;
2429 		if (flags & SPI_NOR_BP3_SR_BIT6)
2430 			nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
2431 	}
2432 
2433 	if (flags & NO_CHIP_ERASE)
2434 		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2435 }
2436 
2437 /**
2438  * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2439  * be discovered by SFDP for this particular flash because the SFDP table that
2440  * indicates this support is not defined in the flash. In case the table for
2441  * this support is defined but has wrong values, one should instead use a
2442  * post_sfdp() hook to set the SNOR_F equivalent flag.
2443  * @nor:       pointer to a 'struct spi_nor'
2444  */
spi_nor_init_fixup_flags(struct spi_nor * nor)2445 static void spi_nor_init_fixup_flags(struct spi_nor *nor)
2446 {
2447 	const u8 fixup_flags = nor->info->fixup_flags;
2448 
2449 	if (fixup_flags & SPI_NOR_4B_OPCODES)
2450 		nor->flags |= SNOR_F_4B_OPCODES;
2451 
2452 	if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
2453 		nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
2454 }
2455 
2456 /**
2457  * spi_nor_late_init_params() - Late initialization of default flash parameters.
2458  * @nor:	pointer to a 'struct spi_nor'
2459  *
2460  * Used to initialize flash parameters that are not declared in the JESD216
2461  * SFDP standard, or where SFDP tables are not defined at all.
2462  * Will replace the spi_nor_manufacturer_init_params() method.
2463  */
spi_nor_late_init_params(struct spi_nor * nor)2464 static void spi_nor_late_init_params(struct spi_nor *nor)
2465 {
2466 	if (nor->manufacturer && nor->manufacturer->fixups &&
2467 	    nor->manufacturer->fixups->late_init)
2468 		nor->manufacturer->fixups->late_init(nor);
2469 
2470 	if (nor->info->fixups && nor->info->fixups->late_init)
2471 		nor->info->fixups->late_init(nor);
2472 
2473 	spi_nor_init_flags(nor);
2474 	spi_nor_init_fixup_flags(nor);
2475 
2476 	/*
2477 	 * NOR protection support. When locking_ops are not provided, we pick
2478 	 * the default ones.
2479 	 */
2480 	if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2481 		spi_nor_init_default_locking_ops(nor);
2482 }
2483 
2484 /**
2485  * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2486  * parameters and settings based on JESD216 SFDP standard.
2487  * @nor:	pointer to a 'struct spi_nor'.
2488  *
2489  * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2490  * legacy flash parameters and settings will be restored.
2491  */
spi_nor_sfdp_init_params_deprecated(struct spi_nor * nor)2492 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
2493 {
2494 	struct spi_nor_flash_parameter sfdp_params;
2495 
2496 	memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2497 
2498 	if (spi_nor_parse_sfdp(nor)) {
2499 		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2500 		nor->addr_width = 0;
2501 		nor->flags &= ~SNOR_F_4B_OPCODES;
2502 	}
2503 }
2504 
2505 /**
2506  * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2507  * parameters and settings.
2508  * @nor:	pointer to a 'struct spi_nor'.
2509  *
2510  * The method assumes that flash doesn't support SFDP so it initializes flash
2511  * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten
2512  * when parsing SFDP, if supported.
2513  */
spi_nor_init_params_deprecated(struct spi_nor * nor)2514 static void spi_nor_init_params_deprecated(struct spi_nor *nor)
2515 {
2516 	spi_nor_no_sfdp_init_params(nor);
2517 
2518 	spi_nor_manufacturer_init_params(nor);
2519 
2520 	if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
2521 					SPI_NOR_QUAD_READ |
2522 					SPI_NOR_OCTAL_READ |
2523 					SPI_NOR_OCTAL_DTR_READ))
2524 		spi_nor_sfdp_init_params_deprecated(nor);
2525 }
2526 
2527 /**
2528  * spi_nor_init_default_params() - Default initialization of flash parameters
2529  * and settings. Done for all flashes, regardless is they define SFDP tables
2530  * or not.
2531  * @nor:	pointer to a 'struct spi_nor'.
2532  */
spi_nor_init_default_params(struct spi_nor * nor)2533 static void spi_nor_init_default_params(struct spi_nor *nor)
2534 {
2535 	struct spi_nor_flash_parameter *params = nor->params;
2536 	const struct flash_info *info = nor->info;
2537 	struct device_node *np = spi_nor_get_flash_node(nor);
2538 
2539 	params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2540 	params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2541 	params->otp.org = &info->otp_org;
2542 
2543 	/* Default to 16-bit Write Status (01h) Command */
2544 	nor->flags |= SNOR_F_HAS_16BIT_SR;
2545 
2546 	/* Set SPI NOR sizes. */
2547 	params->writesize = 1;
2548 	params->size = (u64)info->sector_size * info->n_sectors;
2549 	params->page_size = info->page_size;
2550 
2551 	if (!(info->flags & SPI_NOR_NO_FR)) {
2552 		/* Default to Fast Read for DT and non-DT platform devices. */
2553 		params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2554 
2555 		/* Mask out Fast Read if not requested at DT instantiation. */
2556 		if (np && !of_property_read_bool(np, "m25p,fast-read"))
2557 			params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2558 	}
2559 
2560 	/* (Fast) Read settings. */
2561 	params->hwcaps.mask |= SNOR_HWCAPS_READ;
2562 	spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2563 				  0, 0, SPINOR_OP_READ,
2564 				  SNOR_PROTO_1_1_1);
2565 
2566 	if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2567 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2568 					  0, 8, SPINOR_OP_READ_FAST,
2569 					  SNOR_PROTO_1_1_1);
2570 	/* Page Program settings. */
2571 	params->hwcaps.mask |= SNOR_HWCAPS_PP;
2572 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2573 				SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2574 }
2575 
2576 /**
2577  * spi_nor_init_params() - Initialize the flash's parameters and settings.
2578  * @nor:	pointer to a 'struct spi_nor'.
2579  *
2580  * The flash parameters and settings are initialized based on a sequence of
2581  * calls that are ordered by priority:
2582  *
2583  * 1/ Default flash parameters initialization. The initializations are done
2584  *    based on nor->info data:
2585  *		spi_nor_info_init_params()
2586  *
2587  * which can be overwritten by:
2588  * 2/ Manufacturer flash parameters initialization. The initializations are
2589  *    done based on MFR register, or when the decisions can not be done solely
2590  *    based on MFR, by using specific flash_info tweeks, ->default_init():
2591  *		spi_nor_manufacturer_init_params()
2592  *
2593  * which can be overwritten by:
2594  * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2595  *    should be more accurate that the above.
2596  *		spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()
2597  *
2598  *    Please note that there is a ->post_bfpt() fixup hook that can overwrite
2599  *    the flash parameters and settings immediately after parsing the Basic
2600  *    Flash Parameter Table.
2601  *    spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.
2602  *    It is used to tweak various flash parameters when information provided
2603  *    by the SFDP tables are wrong.
2604  *
2605  * which can be overwritten by:
2606  * 4/ Late flash parameters initialization, used to initialize flash
2607  * parameters that are not declared in the JESD216 SFDP standard, or where SFDP
2608  * tables are not defined at all.
2609  *		spi_nor_late_init_params()
2610  *
2611  * Return: 0 on success, -errno otherwise.
2612  */
spi_nor_init_params(struct spi_nor * nor)2613 static int spi_nor_init_params(struct spi_nor *nor)
2614 {
2615 	int ret;
2616 
2617 	nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2618 	if (!nor->params)
2619 		return -ENOMEM;
2620 
2621 	spi_nor_init_default_params(nor);
2622 
2623 	if (nor->info->parse_sfdp) {
2624 		ret = spi_nor_parse_sfdp(nor);
2625 		if (ret) {
2626 			dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");
2627 			return ret;
2628 		}
2629 	} else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {
2630 		spi_nor_no_sfdp_init_params(nor);
2631 	} else {
2632 		spi_nor_init_params_deprecated(nor);
2633 	}
2634 
2635 	spi_nor_late_init_params(nor);
2636 
2637 	return 0;
2638 }
2639 
2640 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
2641  * @nor:                 pointer to a 'struct spi_nor'
2642  * @enable:              whether to enable or disable Octal DTR
2643  *
2644  * Return: 0 on success, -errno otherwise.
2645  */
spi_nor_octal_dtr_enable(struct spi_nor * nor,bool enable)2646 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
2647 {
2648 	int ret;
2649 
2650 	if (!nor->params->octal_dtr_enable)
2651 		return 0;
2652 
2653 	if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
2654 	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
2655 		return 0;
2656 
2657 	if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
2658 		return 0;
2659 
2660 	ret = nor->params->octal_dtr_enable(nor, enable);
2661 	if (ret)
2662 		return ret;
2663 
2664 	if (enable)
2665 		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
2666 	else
2667 		nor->reg_proto = SNOR_PROTO_1_1_1;
2668 
2669 	return 0;
2670 }
2671 
2672 /**
2673  * spi_nor_quad_enable() - enable Quad I/O if needed.
2674  * @nor:                pointer to a 'struct spi_nor'
2675  *
2676  * Return: 0 on success, -errno otherwise.
2677  */
spi_nor_quad_enable(struct spi_nor * nor)2678 static int spi_nor_quad_enable(struct spi_nor *nor)
2679 {
2680 	if (!nor->params->quad_enable)
2681 		return 0;
2682 
2683 	if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2684 	      spi_nor_get_protocol_width(nor->write_proto) == 4))
2685 		return 0;
2686 
2687 	return nor->params->quad_enable(nor);
2688 }
2689 
spi_nor_init(struct spi_nor * nor)2690 static int spi_nor_init(struct spi_nor *nor)
2691 {
2692 	int err;
2693 
2694 	err = spi_nor_octal_dtr_enable(nor, true);
2695 	if (err) {
2696 		dev_dbg(nor->dev, "octal mode not supported\n");
2697 		return err;
2698 	}
2699 
2700 	err = spi_nor_quad_enable(nor);
2701 	if (err) {
2702 		dev_dbg(nor->dev, "quad mode not supported\n");
2703 		return err;
2704 	}
2705 
2706 	/*
2707 	 * Some SPI NOR flashes are write protected by default after a power-on
2708 	 * reset cycle, in order to avoid inadvertent writes during power-up.
2709 	 * Backward compatibility imposes to unlock the entire flash memory
2710 	 * array at power-up by default. Depending on the kernel configuration
2711 	 * (1) do nothing, (2) always unlock the entire flash array or (3)
2712 	 * unlock the entire flash array only when the software write
2713 	 * protection bits are volatile. The latter is indicated by
2714 	 * SNOR_F_SWP_IS_VOLATILE.
2715 	 */
2716 	if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
2717 	    (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
2718 	     nor->flags & SNOR_F_SWP_IS_VOLATILE))
2719 		spi_nor_try_unlock_all(nor);
2720 
2721 	if (nor->addr_width == 4 &&
2722 	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
2723 	    !(nor->flags & SNOR_F_4B_OPCODES)) {
2724 		/*
2725 		 * If the RESET# pin isn't hooked up properly, or the system
2726 		 * otherwise doesn't perform a reset command in the boot
2727 		 * sequence, it's impossible to 100% protect against unexpected
2728 		 * reboots (e.g., crashes). Warn the user (or hopefully, system
2729 		 * designer) that this is bad.
2730 		 */
2731 		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2732 			  "enabling reset hack; may not recover from unexpected reboots\n");
2733 		nor->params->set_4byte_addr_mode(nor, true);
2734 	}
2735 
2736 	return 0;
2737 }
2738 
2739 /**
2740  * spi_nor_soft_reset() - Perform a software reset
2741  * @nor:	pointer to 'struct spi_nor'
2742  *
2743  * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
2744  * the device to its power-on-reset state. This is useful when the software has
2745  * made some changes to device (volatile) registers and needs to reset it before
2746  * shutting down, for example.
2747  *
2748  * Not every flash supports this sequence. The same set of opcodes might be used
2749  * for some other operation on a flash that does not support this. Support for
2750  * this sequence can be discovered via SFDP in the BFPT table.
2751  *
2752  * Return: 0 on success, -errno otherwise.
2753  */
spi_nor_soft_reset(struct spi_nor * nor)2754 static void spi_nor_soft_reset(struct spi_nor *nor)
2755 {
2756 	struct spi_mem_op op;
2757 	int ret;
2758 
2759 	op = (struct spi_mem_op)SPINOR_SRSTEN_OP;
2760 
2761 	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2762 
2763 	ret = spi_mem_exec_op(nor->spimem, &op);
2764 	if (ret) {
2765 		dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2766 		return;
2767 	}
2768 
2769 	op = (struct spi_mem_op)SPINOR_SRST_OP;
2770 
2771 	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2772 
2773 	ret = spi_mem_exec_op(nor->spimem, &op);
2774 	if (ret) {
2775 		dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2776 		return;
2777 	}
2778 
2779 	/*
2780 	 * Software Reset is not instant, and the delay varies from flash to
2781 	 * flash. Looking at a few flashes, most range somewhere below 100
2782 	 * microseconds. So, sleep for a range of 200-400 us.
2783 	 */
2784 	usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
2785 }
2786 
2787 /* mtd suspend handler */
spi_nor_suspend(struct mtd_info * mtd)2788 static int spi_nor_suspend(struct mtd_info *mtd)
2789 {
2790 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
2791 	int ret;
2792 
2793 	/* Disable octal DTR mode if we enabled it. */
2794 	ret = spi_nor_octal_dtr_enable(nor, false);
2795 	if (ret)
2796 		dev_err(nor->dev, "suspend() failed\n");
2797 
2798 	return ret;
2799 }
2800 
2801 /* mtd resume handler */
spi_nor_resume(struct mtd_info * mtd)2802 static void spi_nor_resume(struct mtd_info *mtd)
2803 {
2804 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
2805 	struct device *dev = nor->dev;
2806 	int ret;
2807 
2808 	/* re-initialize the nor chip */
2809 	ret = spi_nor_init(nor);
2810 	if (ret)
2811 		dev_err(dev, "resume() failed\n");
2812 }
2813 
spi_nor_get_device(struct mtd_info * mtd)2814 static int spi_nor_get_device(struct mtd_info *mtd)
2815 {
2816 	struct mtd_info *master = mtd_get_master(mtd);
2817 	struct spi_nor *nor = mtd_to_spi_nor(master);
2818 	struct device *dev;
2819 
2820 	if (nor->spimem)
2821 		dev = nor->spimem->spi->controller->dev.parent;
2822 	else
2823 		dev = nor->dev;
2824 
2825 	if (!try_module_get(dev->driver->owner))
2826 		return -ENODEV;
2827 
2828 	return 0;
2829 }
2830 
spi_nor_put_device(struct mtd_info * mtd)2831 static void spi_nor_put_device(struct mtd_info *mtd)
2832 {
2833 	struct mtd_info *master = mtd_get_master(mtd);
2834 	struct spi_nor *nor = mtd_to_spi_nor(master);
2835 	struct device *dev;
2836 
2837 	if (nor->spimem)
2838 		dev = nor->spimem->spi->controller->dev.parent;
2839 	else
2840 		dev = nor->dev;
2841 
2842 	module_put(dev->driver->owner);
2843 }
2844 
spi_nor_restore(struct spi_nor * nor)2845 void spi_nor_restore(struct spi_nor *nor)
2846 {
2847 	/* restore the addressing mode */
2848 	if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
2849 	    nor->flags & SNOR_F_BROKEN_RESET)
2850 		nor->params->set_4byte_addr_mode(nor, false);
2851 
2852 	if (nor->flags & SNOR_F_SOFT_RESET)
2853 		spi_nor_soft_reset(nor);
2854 }
2855 EXPORT_SYMBOL_GPL(spi_nor_restore);
2856 
spi_nor_match_name(struct spi_nor * nor,const char * name)2857 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,
2858 						   const char *name)
2859 {
2860 	unsigned int i, j;
2861 
2862 	for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2863 		for (j = 0; j < manufacturers[i]->nparts; j++) {
2864 			if (!strcmp(name, manufacturers[i]->parts[j].name)) {
2865 				nor->manufacturer = manufacturers[i];
2866 				return &manufacturers[i]->parts[j];
2867 			}
2868 		}
2869 	}
2870 
2871 	return NULL;
2872 }
2873 
spi_nor_get_flash_info(struct spi_nor * nor,const char * name)2874 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
2875 						       const char *name)
2876 {
2877 	const struct flash_info *info = NULL;
2878 
2879 	if (name)
2880 		info = spi_nor_match_name(nor, name);
2881 	/* Try to auto-detect if chip name wasn't specified or not found */
2882 	if (!info)
2883 		return spi_nor_detect(nor);
2884 
2885 	/*
2886 	 * If caller has specified name of flash model that can normally be
2887 	 * detected using JEDEC, let's verify it.
2888 	 */
2889 	if (name && info->id_len) {
2890 		const struct flash_info *jinfo;
2891 
2892 		jinfo = spi_nor_detect(nor);
2893 		if (IS_ERR(jinfo)) {
2894 			return jinfo;
2895 		} else if (jinfo != info) {
2896 			/*
2897 			 * JEDEC knows better, so overwrite platform ID. We
2898 			 * can't trust partitions any longer, but we'll let
2899 			 * mtd apply them anyway, since some partitions may be
2900 			 * marked read-only, and we don't want to lose that
2901 			 * information, even if it's not 100% accurate.
2902 			 */
2903 			dev_warn(nor->dev, "found %s, expected %s\n",
2904 				 jinfo->name, info->name);
2905 			info = jinfo;
2906 		}
2907 	}
2908 
2909 	return info;
2910 }
2911 
spi_nor_set_mtd_info(struct spi_nor * nor)2912 static void spi_nor_set_mtd_info(struct spi_nor *nor)
2913 {
2914 	struct mtd_info *mtd = &nor->mtd;
2915 	struct device *dev = nor->dev;
2916 
2917 	spi_nor_set_mtd_locking_ops(nor);
2918 	spi_nor_set_mtd_otp_ops(nor);
2919 
2920 	mtd->dev.parent = dev;
2921 	if (!mtd->name)
2922 		mtd->name = dev_name(dev);
2923 	mtd->type = MTD_NORFLASH;
2924 	mtd->flags = MTD_CAP_NORFLASH;
2925 	if (nor->info->flags & SPI_NOR_NO_ERASE)
2926 		mtd->flags |= MTD_NO_ERASE;
2927 	else
2928 		mtd->_erase = spi_nor_erase;
2929 	mtd->writesize = nor->params->writesize;
2930 	mtd->writebufsize = nor->params->page_size;
2931 	mtd->size = nor->params->size;
2932 	mtd->_read = spi_nor_read;
2933 	/* Might be already set by some SST flashes. */
2934 	if (!mtd->_write)
2935 		mtd->_write = spi_nor_write;
2936 	mtd->_suspend = spi_nor_suspend;
2937 	mtd->_resume = spi_nor_resume;
2938 	mtd->_get_device = spi_nor_get_device;
2939 	mtd->_put_device = spi_nor_put_device;
2940 }
2941 
spi_nor_scan(struct spi_nor * nor,const char * name,const struct spi_nor_hwcaps * hwcaps)2942 int spi_nor_scan(struct spi_nor *nor, const char *name,
2943 		 const struct spi_nor_hwcaps *hwcaps)
2944 {
2945 	const struct flash_info *info;
2946 	struct device *dev = nor->dev;
2947 	struct mtd_info *mtd = &nor->mtd;
2948 	int ret;
2949 	int i;
2950 
2951 	ret = spi_nor_check(nor);
2952 	if (ret)
2953 		return ret;
2954 
2955 	/* Reset SPI protocol for all commands. */
2956 	nor->reg_proto = SNOR_PROTO_1_1_1;
2957 	nor->read_proto = SNOR_PROTO_1_1_1;
2958 	nor->write_proto = SNOR_PROTO_1_1_1;
2959 
2960 	/*
2961 	 * We need the bounce buffer early to read/write registers when going
2962 	 * through the spi-mem layer (buffers have to be DMA-able).
2963 	 * For spi-mem drivers, we'll reallocate a new buffer if
2964 	 * nor->params->page_size turns out to be greater than PAGE_SIZE (which
2965 	 * shouldn't happen before long since NOR pages are usually less
2966 	 * than 1KB) after spi_nor_scan() returns.
2967 	 */
2968 	nor->bouncebuf_size = PAGE_SIZE;
2969 	nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
2970 				      GFP_KERNEL);
2971 	if (!nor->bouncebuf)
2972 		return -ENOMEM;
2973 
2974 	info = spi_nor_get_flash_info(nor, name);
2975 	if (IS_ERR(info))
2976 		return PTR_ERR(info);
2977 
2978 	nor->info = info;
2979 
2980 	mutex_init(&nor->lock);
2981 
2982 	/* Init flash parameters based on flash_info struct and SFDP */
2983 	ret = spi_nor_init_params(nor);
2984 	if (ret)
2985 		return ret;
2986 
2987 	/*
2988 	 * Configure the SPI memory:
2989 	 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2990 	 * - set the number of dummy cycles (mode cycles + wait states).
2991 	 * - set the SPI protocols for register and memory accesses.
2992 	 * - set the address width.
2993 	 */
2994 	ret = spi_nor_setup(nor, hwcaps);
2995 	if (ret)
2996 		return ret;
2997 
2998 	/* Send all the required SPI flash commands to initialize device */
2999 	ret = spi_nor_init(nor);
3000 	if (ret)
3001 		return ret;
3002 
3003 	/* No mtd_info fields should be used up to this point. */
3004 	spi_nor_set_mtd_info(nor);
3005 
3006 	dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3007 			(long long)mtd->size >> 10);
3008 
3009 	dev_dbg(dev,
3010 		"mtd .name = %s, .size = 0x%llx (%lldMiB), "
3011 		".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3012 		mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3013 		mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3014 
3015 	if (mtd->numeraseregions)
3016 		for (i = 0; i < mtd->numeraseregions; i++)
3017 			dev_dbg(dev,
3018 				"mtd.eraseregions[%d] = { .offset = 0x%llx, "
3019 				".erasesize = 0x%.8x (%uKiB), "
3020 				".numblocks = %d }\n",
3021 				i, (long long)mtd->eraseregions[i].offset,
3022 				mtd->eraseregions[i].erasesize,
3023 				mtd->eraseregions[i].erasesize / 1024,
3024 				mtd->eraseregions[i].numblocks);
3025 	return 0;
3026 }
3027 EXPORT_SYMBOL_GPL(spi_nor_scan);
3028 
spi_nor_create_read_dirmap(struct spi_nor * nor)3029 static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3030 {
3031 	struct spi_mem_dirmap_info info = {
3032 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
3033 				      SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3034 				      SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3035 				      SPI_MEM_OP_DATA_IN(0, NULL, 0)),
3036 		.offset = 0,
3037 		.length = nor->params->size,
3038 	};
3039 	struct spi_mem_op *op = &info.op_tmpl;
3040 
3041 	spi_nor_spimem_setup_op(nor, op, nor->read_proto);
3042 
3043 	/* convert the dummy cycles to the number of bytes */
3044 	op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3045 	if (spi_nor_protocol_is_dtr(nor->read_proto))
3046 		op->dummy.nbytes *= 2;
3047 
3048 	/*
3049 	 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3050 	 * of data bytes is non-zero, the data buswidth won't be set here. So,
3051 	 * do it explicitly.
3052 	 */
3053 	op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3054 
3055 	nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3056 						       &info);
3057 	return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3058 }
3059 
spi_nor_create_write_dirmap(struct spi_nor * nor)3060 static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3061 {
3062 	struct spi_mem_dirmap_info info = {
3063 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
3064 				      SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3065 				      SPI_MEM_OP_NO_DUMMY,
3066 				      SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
3067 		.offset = 0,
3068 		.length = nor->params->size,
3069 	};
3070 	struct spi_mem_op *op = &info.op_tmpl;
3071 
3072 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3073 		op->addr.nbytes = 0;
3074 
3075 	spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3076 
3077 	/*
3078 	 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3079 	 * of data bytes is non-zero, the data buswidth won't be set here. So,
3080 	 * do it explicitly.
3081 	 */
3082 	op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3083 
3084 	nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3085 						       &info);
3086 	return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3087 }
3088 
spi_nor_probe(struct spi_mem * spimem)3089 static int spi_nor_probe(struct spi_mem *spimem)
3090 {
3091 	struct spi_device *spi = spimem->spi;
3092 	struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3093 	struct spi_nor *nor;
3094 	/*
3095 	 * Enable all caps by default. The core will mask them after
3096 	 * checking what's really supported using spi_mem_supports_op().
3097 	 */
3098 	const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3099 	char *flash_name;
3100 	int ret;
3101 
3102 	nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3103 	if (!nor)
3104 		return -ENOMEM;
3105 
3106 	nor->spimem = spimem;
3107 	nor->dev = &spi->dev;
3108 	spi_nor_set_flash_node(nor, spi->dev.of_node);
3109 
3110 	spi_mem_set_drvdata(spimem, nor);
3111 
3112 	if (data && data->name)
3113 		nor->mtd.name = data->name;
3114 
3115 	if (!nor->mtd.name)
3116 		nor->mtd.name = spi_mem_get_name(spimem);
3117 
3118 	/*
3119 	 * For some (historical?) reason many platforms provide two different
3120 	 * names in flash_platform_data: "name" and "type". Quite often name is
3121 	 * set to "m25p80" and then "type" provides a real chip name.
3122 	 * If that's the case, respect "type" and ignore a "name".
3123 	 */
3124 	if (data && data->type)
3125 		flash_name = data->type;
3126 	else if (!strcmp(spi->modalias, "spi-nor"))
3127 		flash_name = NULL; /* auto-detect */
3128 	else
3129 		flash_name = spi->modalias;
3130 
3131 	ret = spi_nor_scan(nor, flash_name, &hwcaps);
3132 	if (ret)
3133 		return ret;
3134 
3135 	spi_nor_debugfs_register(nor);
3136 
3137 	/*
3138 	 * None of the existing parts have > 512B pages, but let's play safe
3139 	 * and add this logic so that if anyone ever adds support for such
3140 	 * a NOR we don't end up with buffer overflows.
3141 	 */
3142 	if (nor->params->page_size > PAGE_SIZE) {
3143 		nor->bouncebuf_size = nor->params->page_size;
3144 		devm_kfree(nor->dev, nor->bouncebuf);
3145 		nor->bouncebuf = devm_kmalloc(nor->dev,
3146 					      nor->bouncebuf_size,
3147 					      GFP_KERNEL);
3148 		if (!nor->bouncebuf)
3149 			return -ENOMEM;
3150 	}
3151 
3152 	ret = spi_nor_create_read_dirmap(nor);
3153 	if (ret)
3154 		return ret;
3155 
3156 	ret = spi_nor_create_write_dirmap(nor);
3157 	if (ret)
3158 		return ret;
3159 
3160 	return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3161 				   data ? data->nr_parts : 0);
3162 }
3163 
spi_nor_remove(struct spi_mem * spimem)3164 static int spi_nor_remove(struct spi_mem *spimem)
3165 {
3166 	struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3167 
3168 	spi_nor_restore(nor);
3169 
3170 	/* Clean up MTD stuff. */
3171 	return mtd_device_unregister(&nor->mtd);
3172 }
3173 
spi_nor_shutdown(struct spi_mem * spimem)3174 static void spi_nor_shutdown(struct spi_mem *spimem)
3175 {
3176 	struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3177 
3178 	spi_nor_restore(nor);
3179 }
3180 
3181 /*
3182  * Do NOT add to this array without reading the following:
3183  *
3184  * Historically, many flash devices are bound to this driver by their name. But
3185  * since most of these flash are compatible to some extent, and their
3186  * differences can often be differentiated by the JEDEC read-ID command, we
3187  * encourage new users to add support to the spi-nor library, and simply bind
3188  * against a generic string here (e.g., "jedec,spi-nor").
3189  *
3190  * Many flash names are kept here in this list to keep them available
3191  * as module aliases for existing platforms.
3192  */
3193 static const struct spi_device_id spi_nor_dev_ids[] = {
3194 	/*
3195 	 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3196 	 * hack around the fact that the SPI core does not provide uevent
3197 	 * matching for .of_match_table
3198 	 */
3199 	{"spi-nor"},
3200 
3201 	/*
3202 	 * Entries not used in DTs that should be safe to drop after replacing
3203 	 * them with "spi-nor" in platform data.
3204 	 */
3205 	{"s25sl064a"},	{"w25x16"},	{"m25p10"},	{"m25px64"},
3206 
3207 	/*
3208 	 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3209 	 * should be kept for backward compatibility.
3210 	 */
3211 	{"at25df321a"},	{"at25df641"},	{"at26df081a"},
3212 	{"mx25l4005a"},	{"mx25l1606e"},	{"mx25l6405d"},	{"mx25l12805d"},
3213 	{"mx25l25635e"},{"mx66l51235l"},
3214 	{"n25q064"},	{"n25q128a11"},	{"n25q128a13"},	{"n25q512a"},
3215 	{"s25fl256s1"},	{"s25fl512s"},	{"s25sl12801"},	{"s25fl008k"},
3216 	{"s25fl064k"},
3217 	{"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3218 	{"m25p40"},	{"m25p80"},	{"m25p16"},	{"m25p32"},
3219 	{"m25p64"},	{"m25p128"},
3220 	{"w25x80"},	{"w25x32"},	{"w25q32"},	{"w25q32dw"},
3221 	{"w25q80bl"},	{"w25q128"},	{"w25q256"},
3222 
3223 	/* Flashes that can't be detected using JEDEC */
3224 	{"m25p05-nonjedec"},	{"m25p10-nonjedec"},	{"m25p20-nonjedec"},
3225 	{"m25p40-nonjedec"},	{"m25p80-nonjedec"},	{"m25p16-nonjedec"},
3226 	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},
3227 
3228 	/* Everspin MRAMs (non-JEDEC) */
3229 	{ "mr25h128" }, /* 128 Kib, 40 MHz */
3230 	{ "mr25h256" }, /* 256 Kib, 40 MHz */
3231 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
3232 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
3233 
3234 	{ },
3235 };
3236 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3237 
3238 static const struct of_device_id spi_nor_of_table[] = {
3239 	/*
3240 	 * Generic compatibility for SPI NOR that can be identified by the
3241 	 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3242 	 */
3243 	{ .compatible = "jedec,spi-nor" },
3244 	{ /* sentinel */ },
3245 };
3246 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3247 
3248 /*
3249  * REVISIT: many of these chips have deep power-down modes, which
3250  * should clearly be entered on suspend() to minimize power use.
3251  * And also when they're otherwise idle...
3252  */
3253 static struct spi_mem_driver spi_nor_driver = {
3254 	.spidrv = {
3255 		.driver = {
3256 			.name = "spi-nor",
3257 			.of_match_table = spi_nor_of_table,
3258 			.dev_groups = spi_nor_sysfs_groups,
3259 		},
3260 		.id_table = spi_nor_dev_ids,
3261 	},
3262 	.probe = spi_nor_probe,
3263 	.remove = spi_nor_remove,
3264 	.shutdown = spi_nor_shutdown,
3265 };
3266 module_spi_mem_driver(spi_nor_driver);
3267 
3268 MODULE_LICENSE("GPL v2");
3269 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3270 MODULE_AUTHOR("Mike Lavender");
3271 MODULE_DESCRIPTION("framework for SPI NOR");
3272