1 /*
2 * arch/arm/mach-spear3xx/spear3xx.c
3 *
4 * SPEAr3XX machines common source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/types.h>
15 #include <linux/amba/pl061.h>
16 #include <linux/ptrace.h>
17 #include <linux/io.h>
18 #include <asm/hardware/vic.h>
19 #include <asm/irq.h>
20 #include <asm/mach/arch.h>
21 #include <mach/generic.h>
22 #include <mach/hardware.h>
23
24 /* Add spear3xx machines common devices here */
25 /* gpio device registration */
26 static struct pl061_platform_data gpio_plat_data = {
27 .gpio_base = 0,
28 .irq_base = SPEAR3XX_GPIO_INT_BASE,
29 };
30
31 AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
33
34 /* uart device registration */
35 AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
36 {SPEAR3XX_IRQ_UART}, NULL);
37
38 /* Do spear3xx familiy common initialization part here */
spear3xx_init(void)39 void __init spear3xx_init(void)
40 {
41 /* nothing to do for now */
42 }
43
44 /* This will initialize vic */
spear3xx_init_irq(void)45 void __init spear3xx_init_irq(void)
46 {
47 vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48 }
49
50 /* Following will create static virtual/physical mappings */
51 struct map_desc spear3xx_io_desc[] __initdata = {
52 {
53 .virtual = VA_SPEAR3XX_ICM1_UART_BASE,
54 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
55 .length = SZ_4K,
56 .type = MT_DEVICE
57 }, {
58 .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59 .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60 .length = SZ_4K,
61 .type = MT_DEVICE
62 }, {
63 .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
64 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
65 .length = SZ_4K,
66 .type = MT_DEVICE
67 }, {
68 .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
69 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
70 .length = SZ_4K,
71 .type = MT_DEVICE
72 },
73 };
74
75 /* This will create static memory mapping for selected devices */
spear3xx_map_io(void)76 void __init spear3xx_map_io(void)
77 {
78 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
79
80 /* This will initialize clock framework */
81 spear3xx_clk_init();
82 }
83
84 /* pad multiplexing support */
85 /* devices */
86 static struct pmx_dev_mode pmx_firda_modes[] = {
87 {
88 .ids = 0xffffffff,
89 .mask = PMX_FIRDA_MASK,
90 },
91 };
92
93 struct pmx_dev spear3xx_pmx_firda = {
94 .name = "firda",
95 .modes = pmx_firda_modes,
96 .mode_count = ARRAY_SIZE(pmx_firda_modes),
97 .enb_on_reset = 0,
98 };
99
100 static struct pmx_dev_mode pmx_i2c_modes[] = {
101 {
102 .ids = 0xffffffff,
103 .mask = PMX_I2C_MASK,
104 },
105 };
106
107 struct pmx_dev spear3xx_pmx_i2c = {
108 .name = "i2c",
109 .modes = pmx_i2c_modes,
110 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
111 .enb_on_reset = 0,
112 };
113
114 static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
115 {
116 .ids = 0xffffffff,
117 .mask = PMX_SSP_CS_MASK,
118 },
119 };
120
121 struct pmx_dev spear3xx_pmx_ssp_cs = {
122 .name = "ssp_chip_selects",
123 .modes = pmx_ssp_cs_modes,
124 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
125 .enb_on_reset = 0,
126 };
127
128 static struct pmx_dev_mode pmx_ssp_modes[] = {
129 {
130 .ids = 0xffffffff,
131 .mask = PMX_SSP_MASK,
132 },
133 };
134
135 struct pmx_dev spear3xx_pmx_ssp = {
136 .name = "ssp",
137 .modes = pmx_ssp_modes,
138 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
139 .enb_on_reset = 0,
140 };
141
142 static struct pmx_dev_mode pmx_mii_modes[] = {
143 {
144 .ids = 0xffffffff,
145 .mask = PMX_MII_MASK,
146 },
147 };
148
149 struct pmx_dev spear3xx_pmx_mii = {
150 .name = "mii",
151 .modes = pmx_mii_modes,
152 .mode_count = ARRAY_SIZE(pmx_mii_modes),
153 .enb_on_reset = 0,
154 };
155
156 static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
157 {
158 .ids = 0xffffffff,
159 .mask = PMX_GPIO_PIN0_MASK,
160 },
161 };
162
163 struct pmx_dev spear3xx_pmx_gpio_pin0 = {
164 .name = "gpio_pin0",
165 .modes = pmx_gpio_pin0_modes,
166 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
167 .enb_on_reset = 0,
168 };
169
170 static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
171 {
172 .ids = 0xffffffff,
173 .mask = PMX_GPIO_PIN1_MASK,
174 },
175 };
176
177 struct pmx_dev spear3xx_pmx_gpio_pin1 = {
178 .name = "gpio_pin1",
179 .modes = pmx_gpio_pin1_modes,
180 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
181 .enb_on_reset = 0,
182 };
183
184 static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
185 {
186 .ids = 0xffffffff,
187 .mask = PMX_GPIO_PIN2_MASK,
188 },
189 };
190
191 struct pmx_dev spear3xx_pmx_gpio_pin2 = {
192 .name = "gpio_pin2",
193 .modes = pmx_gpio_pin2_modes,
194 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
195 .enb_on_reset = 0,
196 };
197
198 static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
199 {
200 .ids = 0xffffffff,
201 .mask = PMX_GPIO_PIN3_MASK,
202 },
203 };
204
205 struct pmx_dev spear3xx_pmx_gpio_pin3 = {
206 .name = "gpio_pin3",
207 .modes = pmx_gpio_pin3_modes,
208 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
209 .enb_on_reset = 0,
210 };
211
212 static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
213 {
214 .ids = 0xffffffff,
215 .mask = PMX_GPIO_PIN4_MASK,
216 },
217 };
218
219 struct pmx_dev spear3xx_pmx_gpio_pin4 = {
220 .name = "gpio_pin4",
221 .modes = pmx_gpio_pin4_modes,
222 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
223 .enb_on_reset = 0,
224 };
225
226 static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
227 {
228 .ids = 0xffffffff,
229 .mask = PMX_GPIO_PIN5_MASK,
230 },
231 };
232
233 struct pmx_dev spear3xx_pmx_gpio_pin5 = {
234 .name = "gpio_pin5",
235 .modes = pmx_gpio_pin5_modes,
236 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
237 .enb_on_reset = 0,
238 };
239
240 static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
241 {
242 .ids = 0xffffffff,
243 .mask = PMX_UART0_MODEM_MASK,
244 },
245 };
246
247 struct pmx_dev spear3xx_pmx_uart0_modem = {
248 .name = "uart0_modem",
249 .modes = pmx_uart0_modem_modes,
250 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
251 .enb_on_reset = 0,
252 };
253
254 static struct pmx_dev_mode pmx_uart0_modes[] = {
255 {
256 .ids = 0xffffffff,
257 .mask = PMX_UART0_MASK,
258 },
259 };
260
261 struct pmx_dev spear3xx_pmx_uart0 = {
262 .name = "uart0",
263 .modes = pmx_uart0_modes,
264 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
265 .enb_on_reset = 0,
266 };
267
268 static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
269 {
270 .ids = 0xffffffff,
271 .mask = PMX_TIMER_3_4_MASK,
272 },
273 };
274
275 struct pmx_dev spear3xx_pmx_timer_3_4 = {
276 .name = "timer_3_4",
277 .modes = pmx_timer_3_4_modes,
278 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
279 .enb_on_reset = 0,
280 };
281
282 static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
283 {
284 .ids = 0xffffffff,
285 .mask = PMX_TIMER_1_2_MASK,
286 },
287 };
288
289 struct pmx_dev spear3xx_pmx_timer_1_2 = {
290 .name = "timer_1_2",
291 .modes = pmx_timer_1_2_modes,
292 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
293 .enb_on_reset = 0,
294 };
295
296 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
297 /* plgpios devices */
298 static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
299 {
300 .ids = 0x00,
301 .mask = PMX_FIRDA_MASK,
302 },
303 };
304
305 struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
306 .name = "plgpio 0 and 1",
307 .modes = pmx_plgpio_0_1_modes,
308 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
309 .enb_on_reset = 1,
310 };
311
312 static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
313 {
314 .ids = 0x00,
315 .mask = PMX_UART0_MASK,
316 },
317 };
318
319 struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
320 .name = "plgpio 2 and 3",
321 .modes = pmx_plgpio_2_3_modes,
322 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
323 .enb_on_reset = 1,
324 };
325
326 static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
327 {
328 .ids = 0x00,
329 .mask = PMX_I2C_MASK,
330 },
331 };
332
333 struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
334 .name = "plgpio 4 and 5",
335 .modes = pmx_plgpio_4_5_modes,
336 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
337 .enb_on_reset = 1,
338 };
339
340 static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
341 {
342 .ids = 0x00,
343 .mask = PMX_SSP_MASK,
344 },
345 };
346
347 struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
348 .name = "plgpio 6 to 9",
349 .modes = pmx_plgpio_6_9_modes,
350 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
351 .enb_on_reset = 1,
352 };
353
354 static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
355 {
356 .ids = 0x00,
357 .mask = PMX_MII_MASK,
358 },
359 };
360
361 struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
362 .name = "plgpio 10 to 27",
363 .modes = pmx_plgpio_10_27_modes,
364 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
365 .enb_on_reset = 1,
366 };
367
368 static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
369 {
370 .ids = 0x00,
371 .mask = PMX_GPIO_PIN0_MASK,
372 },
373 };
374
375 struct pmx_dev spear3xx_pmx_plgpio_28 = {
376 .name = "plgpio 28",
377 .modes = pmx_plgpio_28_modes,
378 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
379 .enb_on_reset = 1,
380 };
381
382 static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
383 {
384 .ids = 0x00,
385 .mask = PMX_GPIO_PIN1_MASK,
386 },
387 };
388
389 struct pmx_dev spear3xx_pmx_plgpio_29 = {
390 .name = "plgpio 29",
391 .modes = pmx_plgpio_29_modes,
392 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
393 .enb_on_reset = 1,
394 };
395
396 static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
397 {
398 .ids = 0x00,
399 .mask = PMX_GPIO_PIN2_MASK,
400 },
401 };
402
403 struct pmx_dev spear3xx_pmx_plgpio_30 = {
404 .name = "plgpio 30",
405 .modes = pmx_plgpio_30_modes,
406 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
407 .enb_on_reset = 1,
408 };
409
410 static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
411 {
412 .ids = 0x00,
413 .mask = PMX_GPIO_PIN3_MASK,
414 },
415 };
416
417 struct pmx_dev spear3xx_pmx_plgpio_31 = {
418 .name = "plgpio 31",
419 .modes = pmx_plgpio_31_modes,
420 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
421 .enb_on_reset = 1,
422 };
423
424 static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
425 {
426 .ids = 0x00,
427 .mask = PMX_GPIO_PIN4_MASK,
428 },
429 };
430
431 struct pmx_dev spear3xx_pmx_plgpio_32 = {
432 .name = "plgpio 32",
433 .modes = pmx_plgpio_32_modes,
434 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
435 .enb_on_reset = 1,
436 };
437
438 static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
439 {
440 .ids = 0x00,
441 .mask = PMX_GPIO_PIN5_MASK,
442 },
443 };
444
445 struct pmx_dev spear3xx_pmx_plgpio_33 = {
446 .name = "plgpio 33",
447 .modes = pmx_plgpio_33_modes,
448 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
449 .enb_on_reset = 1,
450 };
451
452 static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
453 {
454 .ids = 0x00,
455 .mask = PMX_SSP_CS_MASK,
456 },
457 };
458
459 struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
460 .name = "plgpio 34 to 36",
461 .modes = pmx_plgpio_34_36_modes,
462 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
463 .enb_on_reset = 1,
464 };
465
466 static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
467 {
468 .ids = 0x00,
469 .mask = PMX_UART0_MODEM_MASK,
470 },
471 };
472
473 struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
474 .name = "plgpio 37 to 42",
475 .modes = pmx_plgpio_37_42_modes,
476 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
477 .enb_on_reset = 1,
478 };
479
480 static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
481 {
482 .ids = 0x00,
483 .mask = PMX_TIMER_1_2_MASK,
484 },
485 };
486
487 struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
488 .name = "plgpio 43, 44, 47 and 48",
489 .modes = pmx_plgpio_43_44_47_48_modes,
490 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
491 .enb_on_reset = 1,
492 };
493
494 static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
495 {
496 .ids = 0x00,
497 .mask = PMX_TIMER_3_4_MASK,
498 },
499 };
500
501 struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
502 .name = "plgpio 45, 46, 49 and 50",
503 .modes = pmx_plgpio_45_46_49_50_modes,
504 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
505 .enb_on_reset = 1,
506 };
507 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
508
spear3xx_timer_init(void)509 static void __init spear3xx_timer_init(void)
510 {
511 char pclk_name[] = "pll3_48m_clk";
512 struct clk *gpt_clk, *pclk;
513
514 /* get the system timer clock */
515 gpt_clk = clk_get_sys("gpt0", NULL);
516 if (IS_ERR(gpt_clk)) {
517 pr_err("%s:couldn't get clk for gpt\n", __func__);
518 BUG();
519 }
520
521 /* get the suitable parent clock for timer*/
522 pclk = clk_get(NULL, pclk_name);
523 if (IS_ERR(pclk)) {
524 pr_err("%s:couldn't get %s as parent for gpt\n",
525 __func__, pclk_name);
526 BUG();
527 }
528
529 clk_set_parent(gpt_clk, pclk);
530 clk_put(gpt_clk);
531 clk_put(pclk);
532
533 spear_setup_timer();
534 }
535
536 struct sys_timer spear3xx_timer = {
537 .init = spear3xx_timer_init,
538 };
539