1 /*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <asm/mach-types.h>
18 #include <plat/clock.h>
19 #include <mach/misc_regs.h>
20
21 /* root clks */
22 /* 32 KHz oscillator clock */
23 static struct clk osc_32k_clk = {
24 .flags = ALWAYS_ENABLED,
25 .rate = 32000,
26 };
27
28 /* 24 MHz oscillator clock */
29 static struct clk osc_24m_clk = {
30 .flags = ALWAYS_ENABLED,
31 .rate = 24000000,
32 };
33
34 /* clock derived from 32 KHz osc clk */
35 /* rtc clock */
36 static struct clk rtc_clk = {
37 .pclk = &osc_32k_clk,
38 .en_reg = PERIP1_CLK_ENB,
39 .en_reg_bit = RTC_CLK_ENB,
40 .recalc = &follow_parent,
41 };
42
43 /* clock derived from 24 MHz osc clk */
44 /* pll masks structure */
45 static struct pll_clk_masks pll1_masks = {
46 .mode_mask = PLL_MODE_MASK,
47 .mode_shift = PLL_MODE_SHIFT,
48 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
49 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
50 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
51 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
52 .div_p_mask = PLL_DIV_P_MASK,
53 .div_p_shift = PLL_DIV_P_SHIFT,
54 .div_n_mask = PLL_DIV_N_MASK,
55 .div_n_shift = PLL_DIV_N_SHIFT,
56 };
57
58 /* pll1 configuration structure */
59 static struct pll_clk_config pll1_config = {
60 .mode_reg = PLL1_CTR,
61 .cfg_reg = PLL1_FRQ,
62 .masks = &pll1_masks,
63 };
64
65 /* pll rate configuration table, in ascending order of rates */
66 struct pll_rate_tbl pll_rtbl[] = {
67 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
68 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
69 };
70
71 /* PLL1 clock */
72 static struct clk pll1_clk = {
73 .flags = ENABLED_ON_INIT,
74 .pclk = &osc_24m_clk,
75 .en_reg = PLL1_CTR,
76 .en_reg_bit = PLL_ENABLE,
77 .calc_rate = &pll_calc_rate,
78 .recalc = &pll_clk_recalc,
79 .set_rate = &pll_clk_set_rate,
80 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
81 .private_data = &pll1_config,
82 };
83
84 /* PLL3 48 MHz clock */
85 static struct clk pll3_48m_clk = {
86 .flags = ALWAYS_ENABLED,
87 .pclk = &osc_24m_clk,
88 .rate = 48000000,
89 };
90
91 /* watch dog timer clock */
92 static struct clk wdt_clk = {
93 .flags = ALWAYS_ENABLED,
94 .pclk = &osc_24m_clk,
95 .recalc = &follow_parent,
96 };
97
98 /* clock derived from pll1 clk */
99 /* cpu clock */
100 static struct clk cpu_clk = {
101 .flags = ALWAYS_ENABLED,
102 .pclk = &pll1_clk,
103 .recalc = &follow_parent,
104 };
105
106 /* ahb masks structure */
107 static struct bus_clk_masks ahb_masks = {
108 .mask = PLL_HCLK_RATIO_MASK,
109 .shift = PLL_HCLK_RATIO_SHIFT,
110 };
111
112 /* ahb configuration structure */
113 static struct bus_clk_config ahb_config = {
114 .reg = CORE_CLK_CFG,
115 .masks = &ahb_masks,
116 };
117
118 /* ahb rate configuration table, in ascending order of rates */
119 struct bus_rate_tbl bus_rtbl[] = {
120 {.div = 3}, /* == parent divided by 4 */
121 {.div = 2}, /* == parent divided by 3 */
122 {.div = 1}, /* == parent divided by 2 */
123 {.div = 0}, /* == parent divided by 1 */
124 };
125
126 /* ahb clock */
127 static struct clk ahb_clk = {
128 .flags = ALWAYS_ENABLED,
129 .pclk = &pll1_clk,
130 .calc_rate = &bus_calc_rate,
131 .recalc = &bus_clk_recalc,
132 .set_rate = &bus_clk_set_rate,
133 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
134 .private_data = &ahb_config,
135 };
136
137 /* auxiliary synthesizers masks */
138 static struct aux_clk_masks aux_masks = {
139 .eq_sel_mask = AUX_EQ_SEL_MASK,
140 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
141 .eq1_mask = AUX_EQ1_SEL,
142 .eq2_mask = AUX_EQ2_SEL,
143 .xscale_sel_mask = AUX_XSCALE_MASK,
144 .xscale_sel_shift = AUX_XSCALE_SHIFT,
145 .yscale_sel_mask = AUX_YSCALE_MASK,
146 .yscale_sel_shift = AUX_YSCALE_SHIFT,
147 };
148
149 /* uart synth configurations */
150 static struct aux_clk_config uart_synth_config = {
151 .synth_reg = UART_CLK_SYNT,
152 .masks = &aux_masks,
153 };
154
155 /* aux rate configuration table, in ascending order of rates */
156 struct aux_rate_tbl aux_rtbl[] = {
157 /* For PLL1 = 332 MHz */
158 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
159 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
160 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
161 };
162
163 /* uart synth clock */
164 static struct clk uart_synth_clk = {
165 .en_reg = UART_CLK_SYNT,
166 .en_reg_bit = AUX_SYNT_ENB,
167 .pclk = &pll1_clk,
168 .calc_rate = &aux_calc_rate,
169 .recalc = &aux_clk_recalc,
170 .set_rate = &aux_clk_set_rate,
171 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
172 .private_data = &uart_synth_config,
173 };
174
175 /* uart parents */
176 static struct pclk_info uart_pclk_info[] = {
177 {
178 .pclk = &uart_synth_clk,
179 .pclk_val = AUX_CLK_PLL1_VAL,
180 }, {
181 .pclk = &pll3_48m_clk,
182 .pclk_val = AUX_CLK_PLL3_VAL,
183 },
184 };
185
186 /* uart parent select structure */
187 static struct pclk_sel uart_pclk_sel = {
188 .pclk_info = uart_pclk_info,
189 .pclk_count = ARRAY_SIZE(uart_pclk_info),
190 .pclk_sel_reg = PERIP_CLK_CFG,
191 .pclk_sel_mask = UART_CLK_MASK,
192 };
193
194 /* uart clock */
195 static struct clk uart_clk = {
196 .en_reg = PERIP1_CLK_ENB,
197 .en_reg_bit = UART_CLK_ENB,
198 .pclk_sel = &uart_pclk_sel,
199 .pclk_sel_shift = UART_CLK_SHIFT,
200 .recalc = &follow_parent,
201 };
202
203 /* firda configurations */
204 static struct aux_clk_config firda_synth_config = {
205 .synth_reg = FIRDA_CLK_SYNT,
206 .masks = &aux_masks,
207 };
208
209 /* firda synth clock */
210 static struct clk firda_synth_clk = {
211 .en_reg = FIRDA_CLK_SYNT,
212 .en_reg_bit = AUX_SYNT_ENB,
213 .pclk = &pll1_clk,
214 .calc_rate = &aux_calc_rate,
215 .recalc = &aux_clk_recalc,
216 .set_rate = &aux_clk_set_rate,
217 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
218 .private_data = &firda_synth_config,
219 };
220
221 /* firda parents */
222 static struct pclk_info firda_pclk_info[] = {
223 {
224 .pclk = &firda_synth_clk,
225 .pclk_val = AUX_CLK_PLL1_VAL,
226 }, {
227 .pclk = &pll3_48m_clk,
228 .pclk_val = AUX_CLK_PLL3_VAL,
229 },
230 };
231
232 /* firda parent select structure */
233 static struct pclk_sel firda_pclk_sel = {
234 .pclk_info = firda_pclk_info,
235 .pclk_count = ARRAY_SIZE(firda_pclk_info),
236 .pclk_sel_reg = PERIP_CLK_CFG,
237 .pclk_sel_mask = FIRDA_CLK_MASK,
238 };
239
240 /* firda clock */
241 static struct clk firda_clk = {
242 .en_reg = PERIP1_CLK_ENB,
243 .en_reg_bit = FIRDA_CLK_ENB,
244 .pclk_sel = &firda_pclk_sel,
245 .pclk_sel_shift = FIRDA_CLK_SHIFT,
246 .recalc = &follow_parent,
247 };
248
249 /* gpt synthesizer masks */
250 static struct gpt_clk_masks gpt_masks = {
251 .mscale_sel_mask = GPT_MSCALE_MASK,
252 .mscale_sel_shift = GPT_MSCALE_SHIFT,
253 .nscale_sel_mask = GPT_NSCALE_MASK,
254 .nscale_sel_shift = GPT_NSCALE_SHIFT,
255 };
256
257 /* gpt rate configuration table, in ascending order of rates */
258 struct gpt_rate_tbl gpt_rtbl[] = {
259 /* For pll1 = 332 MHz */
260 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
261 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
262 {.mscale = 1, .nscale = 0}, /* 83 MHz */
263 };
264
265 /* gpt0 synth clk config*/
266 static struct gpt_clk_config gpt0_synth_config = {
267 .synth_reg = PRSC1_CLK_CFG,
268 .masks = &gpt_masks,
269 };
270
271 /* gpt synth clock */
272 static struct clk gpt0_synth_clk = {
273 .flags = ALWAYS_ENABLED,
274 .pclk = &pll1_clk,
275 .calc_rate = &gpt_calc_rate,
276 .recalc = &gpt_clk_recalc,
277 .set_rate = &gpt_clk_set_rate,
278 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
279 .private_data = &gpt0_synth_config,
280 };
281
282 /* gpt parents */
283 static struct pclk_info gpt0_pclk_info[] = {
284 {
285 .pclk = &gpt0_synth_clk,
286 .pclk_val = AUX_CLK_PLL1_VAL,
287 }, {
288 .pclk = &pll3_48m_clk,
289 .pclk_val = AUX_CLK_PLL3_VAL,
290 },
291 };
292
293 /* gpt parent select structure */
294 static struct pclk_sel gpt0_pclk_sel = {
295 .pclk_info = gpt0_pclk_info,
296 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
297 .pclk_sel_reg = PERIP_CLK_CFG,
298 .pclk_sel_mask = GPT_CLK_MASK,
299 };
300
301 /* gpt0 timer clock */
302 static struct clk gpt0_clk = {
303 .flags = ALWAYS_ENABLED,
304 .pclk_sel = &gpt0_pclk_sel,
305 .pclk_sel_shift = GPT0_CLK_SHIFT,
306 .recalc = &follow_parent,
307 };
308
309 /* gpt1 synth clk configurations */
310 static struct gpt_clk_config gpt1_synth_config = {
311 .synth_reg = PRSC2_CLK_CFG,
312 .masks = &gpt_masks,
313 };
314
315 /* gpt1 synth clock */
316 static struct clk gpt1_synth_clk = {
317 .flags = ALWAYS_ENABLED,
318 .pclk = &pll1_clk,
319 .calc_rate = &gpt_calc_rate,
320 .recalc = &gpt_clk_recalc,
321 .set_rate = &gpt_clk_set_rate,
322 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
323 .private_data = &gpt1_synth_config,
324 };
325
326 static struct pclk_info gpt1_pclk_info[] = {
327 {
328 .pclk = &gpt1_synth_clk,
329 .pclk_val = AUX_CLK_PLL1_VAL,
330 }, {
331 .pclk = &pll3_48m_clk,
332 .pclk_val = AUX_CLK_PLL3_VAL,
333 },
334 };
335
336 /* gpt parent select structure */
337 static struct pclk_sel gpt1_pclk_sel = {
338 .pclk_info = gpt1_pclk_info,
339 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
340 .pclk_sel_reg = PERIP_CLK_CFG,
341 .pclk_sel_mask = GPT_CLK_MASK,
342 };
343
344 /* gpt1 timer clock */
345 static struct clk gpt1_clk = {
346 .en_reg = PERIP1_CLK_ENB,
347 .en_reg_bit = GPT1_CLK_ENB,
348 .pclk_sel = &gpt1_pclk_sel,
349 .pclk_sel_shift = GPT1_CLK_SHIFT,
350 .recalc = &follow_parent,
351 };
352
353 /* gpt2 synth clk configurations */
354 static struct gpt_clk_config gpt2_synth_config = {
355 .synth_reg = PRSC3_CLK_CFG,
356 .masks = &gpt_masks,
357 };
358
359 /* gpt1 synth clock */
360 static struct clk gpt2_synth_clk = {
361 .flags = ALWAYS_ENABLED,
362 .pclk = &pll1_clk,
363 .calc_rate = &gpt_calc_rate,
364 .recalc = &gpt_clk_recalc,
365 .set_rate = &gpt_clk_set_rate,
366 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
367 .private_data = &gpt2_synth_config,
368 };
369
370 static struct pclk_info gpt2_pclk_info[] = {
371 {
372 .pclk = &gpt2_synth_clk,
373 .pclk_val = AUX_CLK_PLL1_VAL,
374 }, {
375 .pclk = &pll3_48m_clk,
376 .pclk_val = AUX_CLK_PLL3_VAL,
377 },
378 };
379
380 /* gpt parent select structure */
381 static struct pclk_sel gpt2_pclk_sel = {
382 .pclk_info = gpt2_pclk_info,
383 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
384 .pclk_sel_reg = PERIP_CLK_CFG,
385 .pclk_sel_mask = GPT_CLK_MASK,
386 };
387
388 /* gpt2 timer clock */
389 static struct clk gpt2_clk = {
390 .en_reg = PERIP1_CLK_ENB,
391 .en_reg_bit = GPT2_CLK_ENB,
392 .pclk_sel = &gpt2_pclk_sel,
393 .pclk_sel_shift = GPT2_CLK_SHIFT,
394 .recalc = &follow_parent,
395 };
396
397 /* clock derived from pll3 clk */
398 /* usbh clock */
399 static struct clk usbh_clk = {
400 .pclk = &pll3_48m_clk,
401 .en_reg = PERIP1_CLK_ENB,
402 .en_reg_bit = USBH_CLK_ENB,
403 .recalc = &follow_parent,
404 };
405
406 /* usbd clock */
407 static struct clk usbd_clk = {
408 .pclk = &pll3_48m_clk,
409 .en_reg = PERIP1_CLK_ENB,
410 .en_reg_bit = USBD_CLK_ENB,
411 .recalc = &follow_parent,
412 };
413
414 /* clock derived from ahb clk */
415 /* apb masks structure */
416 static struct bus_clk_masks apb_masks = {
417 .mask = HCLK_PCLK_RATIO_MASK,
418 .shift = HCLK_PCLK_RATIO_SHIFT,
419 };
420
421 /* apb configuration structure */
422 static struct bus_clk_config apb_config = {
423 .reg = CORE_CLK_CFG,
424 .masks = &apb_masks,
425 };
426
427 /* apb clock */
428 static struct clk apb_clk = {
429 .flags = ALWAYS_ENABLED,
430 .pclk = &ahb_clk,
431 .calc_rate = &bus_calc_rate,
432 .recalc = &bus_clk_recalc,
433 .set_rate = &bus_clk_set_rate,
434 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
435 .private_data = &apb_config,
436 };
437
438 /* i2c clock */
439 static struct clk i2c_clk = {
440 .pclk = &ahb_clk,
441 .en_reg = PERIP1_CLK_ENB,
442 .en_reg_bit = I2C_CLK_ENB,
443 .recalc = &follow_parent,
444 };
445
446 /* dma clock */
447 static struct clk dma_clk = {
448 .pclk = &ahb_clk,
449 .en_reg = PERIP1_CLK_ENB,
450 .en_reg_bit = DMA_CLK_ENB,
451 .recalc = &follow_parent,
452 };
453
454 /* jpeg clock */
455 static struct clk jpeg_clk = {
456 .pclk = &ahb_clk,
457 .en_reg = PERIP1_CLK_ENB,
458 .en_reg_bit = JPEG_CLK_ENB,
459 .recalc = &follow_parent,
460 };
461
462 /* gmac clock */
463 static struct clk gmac_clk = {
464 .pclk = &ahb_clk,
465 .en_reg = PERIP1_CLK_ENB,
466 .en_reg_bit = GMAC_CLK_ENB,
467 .recalc = &follow_parent,
468 };
469
470 /* smi clock */
471 static struct clk smi_clk = {
472 .pclk = &ahb_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = SMI_CLK_ENB,
475 .recalc = &follow_parent,
476 };
477
478 /* c3 clock */
479 static struct clk c3_clk = {
480 .pclk = &ahb_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = C3_CLK_ENB,
483 .recalc = &follow_parent,
484 };
485
486 /* clock derived from apb clk */
487 /* adc clock */
488 static struct clk adc_clk = {
489 .pclk = &apb_clk,
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = ADC_CLK_ENB,
492 .recalc = &follow_parent,
493 };
494
495 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
496 /* emi clock */
497 static struct clk emi_clk = {
498 .flags = ALWAYS_ENABLED,
499 .pclk = &ahb_clk,
500 .recalc = &follow_parent,
501 };
502 #endif
503
504 /* ssp clock */
505 static struct clk ssp0_clk = {
506 .pclk = &apb_clk,
507 .en_reg = PERIP1_CLK_ENB,
508 .en_reg_bit = SSP_CLK_ENB,
509 .recalc = &follow_parent,
510 };
511
512 /* gpio clock */
513 static struct clk gpio_clk = {
514 .pclk = &apb_clk,
515 .en_reg = PERIP1_CLK_ENB,
516 .en_reg_bit = GPIO_CLK_ENB,
517 .recalc = &follow_parent,
518 };
519
520 static struct clk dummy_apb_pclk;
521
522 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
523 defined(CONFIG_MACH_SPEAR320)
524 /* fsmc clock */
525 static struct clk fsmc_clk = {
526 .flags = ALWAYS_ENABLED,
527 .pclk = &ahb_clk,
528 .recalc = &follow_parent,
529 };
530 #endif
531
532 /* common clocks to spear310 and spear320 */
533 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
534 /* uart1 clock */
535 static struct clk uart1_clk = {
536 .flags = ALWAYS_ENABLED,
537 .pclk = &apb_clk,
538 .recalc = &follow_parent,
539 };
540
541 /* uart2 clock */
542 static struct clk uart2_clk = {
543 .flags = ALWAYS_ENABLED,
544 .pclk = &apb_clk,
545 .recalc = &follow_parent,
546 };
547 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
548
549 /* common clocks to spear300 and spear320 */
550 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
551 /* clcd clock */
552 static struct clk clcd_clk = {
553 .flags = ALWAYS_ENABLED,
554 .pclk = &pll3_48m_clk,
555 .recalc = &follow_parent,
556 };
557
558 /* sdhci clock */
559 static struct clk sdhci_clk = {
560 .flags = ALWAYS_ENABLED,
561 .pclk = &ahb_clk,
562 .recalc = &follow_parent,
563 };
564 #endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
565
566 /* spear300 machine specific clock structures */
567 #ifdef CONFIG_MACH_SPEAR300
568 /* gpio1 clock */
569 static struct clk gpio1_clk = {
570 .flags = ALWAYS_ENABLED,
571 .pclk = &apb_clk,
572 .recalc = &follow_parent,
573 };
574
575 /* keyboard clock */
576 static struct clk kbd_clk = {
577 .flags = ALWAYS_ENABLED,
578 .pclk = &apb_clk,
579 .recalc = &follow_parent,
580 };
581
582 #endif
583
584 /* spear310 machine specific clock structures */
585 #ifdef CONFIG_MACH_SPEAR310
586 /* uart3 clock */
587 static struct clk uart3_clk = {
588 .flags = ALWAYS_ENABLED,
589 .pclk = &apb_clk,
590 .recalc = &follow_parent,
591 };
592
593 /* uart4 clock */
594 static struct clk uart4_clk = {
595 .flags = ALWAYS_ENABLED,
596 .pclk = &apb_clk,
597 .recalc = &follow_parent,
598 };
599
600 /* uart5 clock */
601 static struct clk uart5_clk = {
602 .flags = ALWAYS_ENABLED,
603 .pclk = &apb_clk,
604 .recalc = &follow_parent,
605 };
606 #endif
607
608 /* spear320 machine specific clock structures */
609 #ifdef CONFIG_MACH_SPEAR320
610 /* can0 clock */
611 static struct clk can0_clk = {
612 .flags = ALWAYS_ENABLED,
613 .pclk = &apb_clk,
614 .recalc = &follow_parent,
615 };
616
617 /* can1 clock */
618 static struct clk can1_clk = {
619 .flags = ALWAYS_ENABLED,
620 .pclk = &apb_clk,
621 .recalc = &follow_parent,
622 };
623
624 /* i2c1 clock */
625 static struct clk i2c1_clk = {
626 .flags = ALWAYS_ENABLED,
627 .pclk = &ahb_clk,
628 .recalc = &follow_parent,
629 };
630
631 /* ssp1 clock */
632 static struct clk ssp1_clk = {
633 .flags = ALWAYS_ENABLED,
634 .pclk = &apb_clk,
635 .recalc = &follow_parent,
636 };
637
638 /* ssp2 clock */
639 static struct clk ssp2_clk = {
640 .flags = ALWAYS_ENABLED,
641 .pclk = &apb_clk,
642 .recalc = &follow_parent,
643 };
644
645 /* pwm clock */
646 static struct clk pwm_clk = {
647 .flags = ALWAYS_ENABLED,
648 .pclk = &apb_clk,
649 .recalc = &follow_parent,
650 };
651 #endif
652
653 /* array of all spear 3xx clock lookups */
654 static struct clk_lookup spear_clk_lookups[] = {
655 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
656 /* root clks */
657 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
658 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
659 /* clock derived from 32 KHz osc clk */
660 { .dev_id = "rtc-spear", .clk = &rtc_clk},
661 /* clock derived from 24 MHz osc clk */
662 { .con_id = "pll1_clk", .clk = &pll1_clk},
663 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
664 { .dev_id = "wdt", .clk = &wdt_clk},
665 /* clock derived from pll1 clk */
666 { .con_id = "cpu_clk", .clk = &cpu_clk},
667 { .con_id = "ahb_clk", .clk = &ahb_clk},
668 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
669 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
670 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
671 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
672 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
673 { .dev_id = "uart", .clk = &uart_clk},
674 { .dev_id = "firda", .clk = &firda_clk},
675 { .dev_id = "gpt0", .clk = &gpt0_clk},
676 { .dev_id = "gpt1", .clk = &gpt1_clk},
677 { .dev_id = "gpt2", .clk = &gpt2_clk},
678 /* clock derived from pll3 clk */
679 { .dev_id = "designware_udc", .clk = &usbd_clk},
680 { .con_id = "usbh_clk", .clk = &usbh_clk},
681 /* clock derived from ahb clk */
682 { .con_id = "apb_clk", .clk = &apb_clk},
683 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
684 { .dev_id = "dma", .clk = &dma_clk},
685 { .dev_id = "jpeg", .clk = &jpeg_clk},
686 { .dev_id = "gmac", .clk = &gmac_clk},
687 { .dev_id = "smi", .clk = &smi_clk},
688 { .dev_id = "c3", .clk = &c3_clk},
689 /* clock derived from apb clk */
690 { .dev_id = "adc", .clk = &adc_clk},
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
692 { .dev_id = "gpio", .clk = &gpio_clk},
693 };
694
695 /* array of all spear 300 clock lookups */
696 #ifdef CONFIG_MACH_SPEAR300
697 static struct clk_lookup spear300_clk_lookups[] = {
698 { .dev_id = "clcd", .clk = &clcd_clk},
699 { .con_id = "fsmc", .clk = &fsmc_clk},
700 { .dev_id = "gpio1", .clk = &gpio1_clk},
701 { .dev_id = "keyboard", .clk = &kbd_clk},
702 { .dev_id = "sdhci", .clk = &sdhci_clk},
703 };
704 #endif
705
706 /* array of all spear 310 clock lookups */
707 #ifdef CONFIG_MACH_SPEAR310
708 static struct clk_lookup spear310_clk_lookups[] = {
709 { .con_id = "fsmc", .clk = &fsmc_clk},
710 { .con_id = "emi", .clk = &emi_clk},
711 { .dev_id = "uart1", .clk = &uart1_clk},
712 { .dev_id = "uart2", .clk = &uart2_clk},
713 { .dev_id = "uart3", .clk = &uart3_clk},
714 { .dev_id = "uart4", .clk = &uart4_clk},
715 { .dev_id = "uart5", .clk = &uart5_clk},
716 };
717 #endif
718
719 /* array of all spear 320 clock lookups */
720 #ifdef CONFIG_MACH_SPEAR320
721 static struct clk_lookup spear320_clk_lookups[] = {
722 { .dev_id = "clcd", .clk = &clcd_clk},
723 { .con_id = "fsmc", .clk = &fsmc_clk},
724 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
725 { .con_id = "emi", .clk = &emi_clk},
726 { .dev_id = "pwm", .clk = &pwm_clk},
727 { .dev_id = "sdhci", .clk = &sdhci_clk},
728 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
729 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
730 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
731 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
732 { .dev_id = "uart1", .clk = &uart1_clk},
733 { .dev_id = "uart2", .clk = &uart2_clk},
734 };
735 #endif
736
spear3xx_clk_init(void)737 void __init spear3xx_clk_init(void)
738 {
739 int i, cnt;
740 struct clk_lookup *lookups;
741
742 if (machine_is_spear300()) {
743 cnt = ARRAY_SIZE(spear300_clk_lookups);
744 lookups = spear300_clk_lookups;
745 } else if (machine_is_spear310()) {
746 cnt = ARRAY_SIZE(spear310_clk_lookups);
747 lookups = spear310_clk_lookups;
748 } else {
749 cnt = ARRAY_SIZE(spear320_clk_lookups);
750 lookups = spear320_clk_lookups;
751 }
752
753 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
754 clk_register(&spear_clk_lookups[i]);
755
756 for (i = 0; i < cnt; i++)
757 clk_register(&lookups[i]);
758
759 clk_init();
760 }
761