1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
36 #include "atom.h"
37 #include "amd_pcie.h"
38
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15_common.h"
45 #include "soc21.h"
46
47 static const struct amd_ip_funcs soc21_common_ip_funcs;
48
49 /* SOC21 */
50 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =
51 {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
54 };
55
56 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode =
57 {
58 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array),
59 .codec_array = vcn_4_0_0_video_codecs_encode_array,
60 };
61
62 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] =
63 {
64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
66 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
67 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
68 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
69 };
70
71 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode =
72 {
73 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array),
74 .codec_array = vcn_4_0_0_video_codecs_decode_array,
75 };
76
soc21_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)77 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
78 const struct amdgpu_video_codecs **codecs)
79 {
80 switch (adev->ip_versions[UVD_HWIP][0]) {
81
82 case IP_VERSION(4, 0, 0):
83 case IP_VERSION(4, 0, 2):
84 if (encode)
85 *codecs = &vcn_4_0_0_video_codecs_encode;
86 else
87 *codecs = &vcn_4_0_0_video_codecs_decode;
88 return 0;
89 default:
90 return -EINVAL;
91 }
92 }
93 /*
94 * Indirect registers accessor
95 */
soc21_pcie_rreg(struct amdgpu_device * adev,u32 reg)96 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)
97 {
98 unsigned long address, data;
99 address = adev->nbio.funcs->get_pcie_index_offset(adev);
100 data = adev->nbio.funcs->get_pcie_data_offset(adev);
101
102 return amdgpu_device_indirect_rreg(adev, address, data, reg);
103 }
104
soc21_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)105 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
106 {
107 unsigned long address, data;
108
109 address = adev->nbio.funcs->get_pcie_index_offset(adev);
110 data = adev->nbio.funcs->get_pcie_data_offset(adev);
111
112 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
113 }
114
soc21_pcie_rreg64(struct amdgpu_device * adev,u32 reg)115 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
116 {
117 unsigned long address, data;
118 address = adev->nbio.funcs->get_pcie_index_offset(adev);
119 data = adev->nbio.funcs->get_pcie_data_offset(adev);
120
121 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
122 }
123
soc21_pcie_wreg64(struct amdgpu_device * adev,u32 reg,u64 v)124 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
125 {
126 unsigned long address, data;
127
128 address = adev->nbio.funcs->get_pcie_index_offset(adev);
129 data = adev->nbio.funcs->get_pcie_data_offset(adev);
130
131 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
132 }
133
soc21_didt_rreg(struct amdgpu_device * adev,u32 reg)134 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
135 {
136 unsigned long flags, address, data;
137 u32 r;
138
139 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
140 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
141
142 spin_lock_irqsave(&adev->didt_idx_lock, flags);
143 WREG32(address, (reg));
144 r = RREG32(data);
145 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
146 return r;
147 }
148
soc21_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)149 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
150 {
151 unsigned long flags, address, data;
152
153 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
154 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
155
156 spin_lock_irqsave(&adev->didt_idx_lock, flags);
157 WREG32(address, (reg));
158 WREG32(data, (v));
159 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
160 }
161
soc21_get_config_memsize(struct amdgpu_device * adev)162 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
163 {
164 return adev->nbio.funcs->get_memsize(adev);
165 }
166
soc21_get_xclk(struct amdgpu_device * adev)167 static u32 soc21_get_xclk(struct amdgpu_device *adev)
168 {
169 return adev->clock.spll.reference_freq;
170 }
171
172
soc21_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)173 void soc21_grbm_select(struct amdgpu_device *adev,
174 u32 me, u32 pipe, u32 queue, u32 vmid)
175 {
176 u32 grbm_gfx_cntl = 0;
177 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
178 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
179 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
180 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
181
182 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
183 }
184
soc21_vga_set_state(struct amdgpu_device * adev,bool state)185 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
186 {
187 /* todo */
188 }
189
soc21_read_disabled_bios(struct amdgpu_device * adev)190 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
191 {
192 /* todo */
193 return false;
194 }
195
196 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
197 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
198 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
199 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
200 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
201 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
202 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
203 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
204 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
205 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
206 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
207 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
208 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
209 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
210 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
211 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
212 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
213 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
214 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
215 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
216 };
217
soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)218 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
219 u32 sh_num, u32 reg_offset)
220 {
221 uint32_t val;
222
223 mutex_lock(&adev->grbm_idx_mutex);
224 if (se_num != 0xffffffff || sh_num != 0xffffffff)
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
226
227 val = RREG32(reg_offset);
228
229 if (se_num != 0xffffffff || sh_num != 0xffffffff)
230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
231 mutex_unlock(&adev->grbm_idx_mutex);
232 return val;
233 }
234
soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)235 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
236 bool indexed, u32 se_num,
237 u32 sh_num, u32 reg_offset)
238 {
239 if (indexed) {
240 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
241 } else {
242 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
243 return adev->gfx.config.gb_addr_config;
244 return RREG32(reg_offset);
245 }
246 }
247
soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)248 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
249 u32 sh_num, u32 reg_offset, u32 *value)
250 {
251 uint32_t i;
252 struct soc15_allowed_register_entry *en;
253
254 *value = 0;
255 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
256 en = &soc21_allowed_read_registers[i];
257 if (adev->reg_offset[en->hwip][en->inst] &&
258 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
259 + en->reg_offset))
260 continue;
261
262 *value = soc21_get_register_value(adev,
263 soc21_allowed_read_registers[i].grbm_indexed,
264 se_num, sh_num, reg_offset);
265 return 0;
266 }
267 return -EINVAL;
268 }
269
270 #if 0
271 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
272 {
273 u32 i;
274 int ret = 0;
275
276 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
277
278 /* disable BM */
279 pci_clear_master(adev->pdev);
280
281 amdgpu_device_cache_pci_state(adev->pdev);
282
283 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
284 dev_info(adev->dev, "GPU smu mode1 reset\n");
285 ret = amdgpu_dpm_mode1_reset(adev);
286 } else {
287 dev_info(adev->dev, "GPU psp mode1 reset\n");
288 ret = psp_gpu_reset(adev);
289 }
290
291 if (ret)
292 dev_err(adev->dev, "GPU mode1 reset failed\n");
293 amdgpu_device_load_pci_state(adev->pdev);
294
295 /* wait for asic to come out of reset */
296 for (i = 0; i < adev->usec_timeout; i++) {
297 u32 memsize = adev->nbio.funcs->get_memsize(adev);
298
299 if (memsize != 0xffffffff)
300 break;
301 udelay(1);
302 }
303
304 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
305
306 return ret;
307 }
308 #endif
309
310 static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device * adev)311 soc21_asic_reset_method(struct amdgpu_device *adev)
312 {
313 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
314 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
315 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
316 return amdgpu_reset_method;
317
318 if (amdgpu_reset_method != -1)
319 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
320 amdgpu_reset_method);
321
322 switch (adev->ip_versions[MP1_HWIP][0]) {
323 case IP_VERSION(13, 0, 0):
324 case IP_VERSION(13, 0, 7):
325 case IP_VERSION(13, 0, 10):
326 return AMD_RESET_METHOD_MODE1;
327 case IP_VERSION(13, 0, 4):
328 case IP_VERSION(13, 0, 11):
329 return AMD_RESET_METHOD_MODE2;
330 default:
331 if (amdgpu_dpm_is_baco_supported(adev))
332 return AMD_RESET_METHOD_BACO;
333 else
334 return AMD_RESET_METHOD_MODE1;
335 }
336 }
337
soc21_asic_reset(struct amdgpu_device * adev)338 static int soc21_asic_reset(struct amdgpu_device *adev)
339 {
340 int ret = 0;
341
342 switch (soc21_asic_reset_method(adev)) {
343 case AMD_RESET_METHOD_PCI:
344 dev_info(adev->dev, "PCI reset\n");
345 ret = amdgpu_device_pci_reset(adev);
346 break;
347 case AMD_RESET_METHOD_BACO:
348 dev_info(adev->dev, "BACO reset\n");
349 ret = amdgpu_dpm_baco_reset(adev);
350 break;
351 case AMD_RESET_METHOD_MODE2:
352 dev_info(adev->dev, "MODE2 reset\n");
353 ret = amdgpu_dpm_mode2_reset(adev);
354 break;
355 default:
356 dev_info(adev->dev, "MODE1 reset\n");
357 ret = amdgpu_device_mode1_reset(adev);
358 break;
359 }
360
361 return ret;
362 }
363
soc21_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)364 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
365 {
366 /* todo */
367 return 0;
368 }
369
soc21_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)370 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
371 {
372 /* todo */
373 return 0;
374 }
375
soc21_pcie_gen3_enable(struct amdgpu_device * adev)376 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
377 {
378 if (pci_is_root_bus(adev->pdev->bus))
379 return;
380
381 if (amdgpu_pcie_gen2 == 0)
382 return;
383
384 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
385 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
386 return;
387
388 /* todo */
389 }
390
soc21_program_aspm(struct amdgpu_device * adev)391 static void soc21_program_aspm(struct amdgpu_device *adev)
392 {
393 if (!amdgpu_device_should_use_aspm(adev))
394 return;
395
396 if (!(adev->flags & AMD_IS_APU) &&
397 (adev->nbio.funcs->program_aspm))
398 adev->nbio.funcs->program_aspm(adev);
399 }
400
soc21_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)401 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
402 bool enable)
403 {
404 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
405 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
406 }
407
408 const struct amdgpu_ip_block_version soc21_common_ip_block =
409 {
410 .type = AMD_IP_BLOCK_TYPE_COMMON,
411 .major = 1,
412 .minor = 0,
413 .rev = 0,
414 .funcs = &soc21_common_ip_funcs,
415 };
416
soc21_get_rev_id(struct amdgpu_device * adev)417 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)
418 {
419 return adev->nbio.funcs->get_rev_id(adev);
420 }
421
soc21_need_full_reset(struct amdgpu_device * adev)422 static bool soc21_need_full_reset(struct amdgpu_device *adev)
423 {
424 switch (adev->ip_versions[GC_HWIP][0]) {
425 case IP_VERSION(11, 0, 0):
426 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
427 case IP_VERSION(11, 0, 2):
428 case IP_VERSION(11, 0, 3):
429 return false;
430 default:
431 return true;
432 }
433 }
434
soc21_need_reset_on_init(struct amdgpu_device * adev)435 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
436 {
437 u32 sol_reg;
438
439 if (adev->flags & AMD_IS_APU)
440 return false;
441
442 /* Check sOS sign of life register to confirm sys driver and sOS
443 * are already been loaded.
444 */
445 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
446 if (sol_reg)
447 return true;
448
449 return false;
450 }
451
soc21_get_pcie_replay_count(struct amdgpu_device * adev)452 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
453 {
454
455 /* TODO
456 * dummy implement for pcie_replay_count sysfs interface
457 * */
458
459 return 0;
460 }
461
soc21_init_doorbell_index(struct amdgpu_device * adev)462 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
463 {
464 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
465 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
466 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
467 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
468 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
469 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
470 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
471 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
472 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
473 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
474 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
475 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
476 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
477 adev->doorbell_index.gfx_userqueue_start =
478 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
479 adev->doorbell_index.gfx_userqueue_end =
480 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
481 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
482 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
483 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
484 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
485 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
486 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
487 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
488 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
489 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
490 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
491 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
492
493 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
494 adev->doorbell_index.sdma_doorbell_range = 20;
495 }
496
soc21_pre_asic_init(struct amdgpu_device * adev)497 static void soc21_pre_asic_init(struct amdgpu_device *adev)
498 {
499 }
500
soc21_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)501 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
502 bool enter)
503 {
504 if (enter)
505 amdgpu_gfx_rlc_enter_safe_mode(adev);
506 else
507 amdgpu_gfx_rlc_exit_safe_mode(adev);
508
509 if (adev->gfx.funcs->update_perfmon_mgcg)
510 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
511
512 return 0;
513 }
514
515 static const struct amdgpu_asic_funcs soc21_asic_funcs =
516 {
517 .read_disabled_bios = &soc21_read_disabled_bios,
518 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
519 .read_register = &soc21_read_register,
520 .reset = &soc21_asic_reset,
521 .reset_method = &soc21_asic_reset_method,
522 .set_vga_state = &soc21_vga_set_state,
523 .get_xclk = &soc21_get_xclk,
524 .set_uvd_clocks = &soc21_set_uvd_clocks,
525 .set_vce_clocks = &soc21_set_vce_clocks,
526 .get_config_memsize = &soc21_get_config_memsize,
527 .init_doorbell_index = &soc21_init_doorbell_index,
528 .need_full_reset = &soc21_need_full_reset,
529 .need_reset_on_init = &soc21_need_reset_on_init,
530 .get_pcie_replay_count = &soc21_get_pcie_replay_count,
531 .supports_baco = &amdgpu_dpm_is_baco_supported,
532 .pre_asic_init = &soc21_pre_asic_init,
533 .query_video_codecs = &soc21_query_video_codecs,
534 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
535 };
536
soc21_common_early_init(void * handle)537 static int soc21_common_early_init(void *handle)
538 {
539 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
540 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
541
542 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
543 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
544 adev->smc_rreg = NULL;
545 adev->smc_wreg = NULL;
546 adev->pcie_rreg = &soc21_pcie_rreg;
547 adev->pcie_wreg = &soc21_pcie_wreg;
548 adev->pcie_rreg64 = &soc21_pcie_rreg64;
549 adev->pcie_wreg64 = &soc21_pcie_wreg64;
550 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
551 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
552
553 /* TODO: will add them during VCN v2 implementation */
554 adev->uvd_ctx_rreg = NULL;
555 adev->uvd_ctx_wreg = NULL;
556
557 adev->didt_rreg = &soc21_didt_rreg;
558 adev->didt_wreg = &soc21_didt_wreg;
559
560 adev->asic_funcs = &soc21_asic_funcs;
561
562 adev->rev_id = soc21_get_rev_id(adev);
563 adev->external_rev_id = 0xff;
564 switch (adev->ip_versions[GC_HWIP][0]) {
565 case IP_VERSION(11, 0, 0):
566 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
567 AMD_CG_SUPPORT_GFX_CGLS |
568 #if 0
569 AMD_CG_SUPPORT_GFX_3D_CGCG |
570 AMD_CG_SUPPORT_GFX_3D_CGLS |
571 #endif
572 AMD_CG_SUPPORT_GFX_MGCG |
573 AMD_CG_SUPPORT_REPEATER_FGCG |
574 AMD_CG_SUPPORT_GFX_FGCG |
575 AMD_CG_SUPPORT_GFX_PERF_CLK |
576 AMD_CG_SUPPORT_VCN_MGCG |
577 AMD_CG_SUPPORT_JPEG_MGCG |
578 AMD_CG_SUPPORT_ATHUB_MGCG |
579 AMD_CG_SUPPORT_ATHUB_LS |
580 AMD_CG_SUPPORT_MC_MGCG |
581 AMD_CG_SUPPORT_MC_LS |
582 AMD_CG_SUPPORT_IH_CG |
583 AMD_CG_SUPPORT_HDP_SD;
584 adev->pg_flags = AMD_PG_SUPPORT_VCN |
585 AMD_PG_SUPPORT_VCN_DPG |
586 AMD_PG_SUPPORT_JPEG |
587 AMD_PG_SUPPORT_ATHUB |
588 AMD_PG_SUPPORT_MMHUB;
589 if (amdgpu_sriov_vf(adev)) {
590 adev->cg_flags = 0;
591 adev->pg_flags = 0;
592 }
593 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
594 break;
595 case IP_VERSION(11, 0, 2):
596 adev->cg_flags =
597 AMD_CG_SUPPORT_GFX_CGCG |
598 AMD_CG_SUPPORT_GFX_CGLS |
599 AMD_CG_SUPPORT_REPEATER_FGCG |
600 AMD_CG_SUPPORT_VCN_MGCG |
601 AMD_CG_SUPPORT_JPEG_MGCG |
602 AMD_CG_SUPPORT_ATHUB_MGCG |
603 AMD_CG_SUPPORT_ATHUB_LS |
604 AMD_CG_SUPPORT_IH_CG |
605 AMD_CG_SUPPORT_HDP_SD;
606 adev->pg_flags =
607 AMD_PG_SUPPORT_VCN |
608 AMD_PG_SUPPORT_VCN_DPG |
609 AMD_PG_SUPPORT_JPEG |
610 AMD_PG_SUPPORT_ATHUB |
611 AMD_PG_SUPPORT_MMHUB;
612 adev->external_rev_id = adev->rev_id + 0x10;
613 break;
614 case IP_VERSION(11, 0, 1):
615 adev->cg_flags =
616 AMD_CG_SUPPORT_GFX_CGCG |
617 AMD_CG_SUPPORT_GFX_CGLS |
618 AMD_CG_SUPPORT_GFX_MGCG |
619 AMD_CG_SUPPORT_GFX_FGCG |
620 AMD_CG_SUPPORT_REPEATER_FGCG |
621 AMD_CG_SUPPORT_GFX_PERF_CLK |
622 AMD_CG_SUPPORT_MC_MGCG |
623 AMD_CG_SUPPORT_MC_LS |
624 AMD_CG_SUPPORT_HDP_MGCG |
625 AMD_CG_SUPPORT_HDP_LS |
626 AMD_CG_SUPPORT_ATHUB_MGCG |
627 AMD_CG_SUPPORT_ATHUB_LS |
628 AMD_CG_SUPPORT_IH_CG |
629 AMD_CG_SUPPORT_BIF_MGCG |
630 AMD_CG_SUPPORT_BIF_LS |
631 AMD_CG_SUPPORT_VCN_MGCG |
632 AMD_CG_SUPPORT_JPEG_MGCG;
633 adev->pg_flags =
634 AMD_PG_SUPPORT_GFX_PG |
635 AMD_PG_SUPPORT_VCN |
636 AMD_PG_SUPPORT_VCN_DPG |
637 AMD_PG_SUPPORT_JPEG;
638 adev->external_rev_id = adev->rev_id + 0x1;
639 break;
640 case IP_VERSION(11, 0, 3):
641 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
642 AMD_CG_SUPPORT_JPEG_MGCG |
643 AMD_CG_SUPPORT_GFX_CGCG |
644 AMD_CG_SUPPORT_GFX_CGLS |
645 AMD_CG_SUPPORT_REPEATER_FGCG |
646 AMD_CG_SUPPORT_GFX_MGCG;
647 adev->pg_flags = AMD_PG_SUPPORT_VCN |
648 AMD_PG_SUPPORT_VCN_DPG |
649 AMD_PG_SUPPORT_JPEG;
650 if (amdgpu_sriov_vf(adev)) {
651 /* hypervisor control CG and PG enablement */
652 adev->cg_flags = 0;
653 adev->pg_flags = 0;
654 }
655 adev->external_rev_id = adev->rev_id + 0x20;
656 break;
657 case IP_VERSION(11, 0, 4):
658 adev->cg_flags =
659 AMD_CG_SUPPORT_GFX_CGCG |
660 AMD_CG_SUPPORT_GFX_CGLS |
661 AMD_CG_SUPPORT_GFX_MGCG |
662 AMD_CG_SUPPORT_GFX_FGCG |
663 AMD_CG_SUPPORT_REPEATER_FGCG |
664 AMD_CG_SUPPORT_GFX_PERF_CLK |
665 AMD_CG_SUPPORT_MC_MGCG |
666 AMD_CG_SUPPORT_MC_LS |
667 AMD_CG_SUPPORT_HDP_MGCG |
668 AMD_CG_SUPPORT_HDP_LS |
669 AMD_CG_SUPPORT_ATHUB_MGCG |
670 AMD_CG_SUPPORT_ATHUB_LS |
671 AMD_CG_SUPPORT_IH_CG |
672 AMD_CG_SUPPORT_BIF_MGCG |
673 AMD_CG_SUPPORT_BIF_LS |
674 AMD_CG_SUPPORT_VCN_MGCG |
675 AMD_CG_SUPPORT_JPEG_MGCG;
676 adev->pg_flags = AMD_PG_SUPPORT_VCN |
677 AMD_PG_SUPPORT_VCN_DPG |
678 AMD_PG_SUPPORT_GFX_PG |
679 AMD_PG_SUPPORT_JPEG;
680 adev->external_rev_id = adev->rev_id + 0x1;
681 break;
682
683 default:
684 /* FIXME: not supported yet */
685 return -EINVAL;
686 }
687
688 return 0;
689 }
690
soc21_common_late_init(void * handle)691 static int soc21_common_late_init(void *handle)
692 {
693 return 0;
694 }
695
soc21_common_sw_init(void * handle)696 static int soc21_common_sw_init(void *handle)
697 {
698 return 0;
699 }
700
soc21_common_sw_fini(void * handle)701 static int soc21_common_sw_fini(void *handle)
702 {
703 return 0;
704 }
705
soc21_common_hw_init(void * handle)706 static int soc21_common_hw_init(void *handle)
707 {
708 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
709
710 /* enable pcie gen2/3 link */
711 soc21_pcie_gen3_enable(adev);
712 /* enable aspm */
713 soc21_program_aspm(adev);
714 /* setup nbio registers */
715 adev->nbio.funcs->init_registers(adev);
716 /* remap HDP registers to a hole in mmio space,
717 * for the purpose of expose those registers
718 * to process space
719 */
720 if (adev->nbio.funcs->remap_hdp_registers)
721 adev->nbio.funcs->remap_hdp_registers(adev);
722 /* enable the doorbell aperture */
723 soc21_enable_doorbell_aperture(adev, true);
724
725 return 0;
726 }
727
soc21_common_hw_fini(void * handle)728 static int soc21_common_hw_fini(void *handle)
729 {
730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
731
732 /* disable the doorbell aperture */
733 soc21_enable_doorbell_aperture(adev, false);
734
735 return 0;
736 }
737
soc21_common_suspend(void * handle)738 static int soc21_common_suspend(void *handle)
739 {
740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
741
742 return soc21_common_hw_fini(adev);
743 }
744
soc21_common_resume(void * handle)745 static int soc21_common_resume(void *handle)
746 {
747 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
748
749 return soc21_common_hw_init(adev);
750 }
751
soc21_common_is_idle(void * handle)752 static bool soc21_common_is_idle(void *handle)
753 {
754 return true;
755 }
756
soc21_common_wait_for_idle(void * handle)757 static int soc21_common_wait_for_idle(void *handle)
758 {
759 return 0;
760 }
761
soc21_common_soft_reset(void * handle)762 static int soc21_common_soft_reset(void *handle)
763 {
764 return 0;
765 }
766
soc21_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)767 static int soc21_common_set_clockgating_state(void *handle,
768 enum amd_clockgating_state state)
769 {
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 switch (adev->ip_versions[NBIO_HWIP][0]) {
773 case IP_VERSION(4, 3, 0):
774 case IP_VERSION(4, 3, 1):
775 case IP_VERSION(7, 7, 0):
776 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
777 state == AMD_CG_STATE_GATE);
778 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
779 state == AMD_CG_STATE_GATE);
780 adev->hdp.funcs->update_clock_gating(adev,
781 state == AMD_CG_STATE_GATE);
782 break;
783 default:
784 break;
785 }
786 return 0;
787 }
788
soc21_common_set_powergating_state(void * handle,enum amd_powergating_state state)789 static int soc21_common_set_powergating_state(void *handle,
790 enum amd_powergating_state state)
791 {
792 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
793
794 switch (adev->ip_versions[LSDMA_HWIP][0]) {
795 case IP_VERSION(6, 0, 0):
796 case IP_VERSION(6, 0, 2):
797 adev->lsdma.funcs->update_memory_power_gating(adev,
798 state == AMD_PG_STATE_GATE);
799 break;
800 default:
801 break;
802 }
803
804 return 0;
805 }
806
soc21_common_get_clockgating_state(void * handle,u64 * flags)807 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
808 {
809 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
810
811 adev->nbio.funcs->get_clockgating_state(adev, flags);
812
813 adev->hdp.funcs->get_clock_gating_state(adev, flags);
814
815 return;
816 }
817
818 static const struct amd_ip_funcs soc21_common_ip_funcs = {
819 .name = "soc21_common",
820 .early_init = soc21_common_early_init,
821 .late_init = soc21_common_late_init,
822 .sw_init = soc21_common_sw_init,
823 .sw_fini = soc21_common_sw_fini,
824 .hw_init = soc21_common_hw_init,
825 .hw_fini = soc21_common_hw_fini,
826 .suspend = soc21_common_suspend,
827 .resume = soc21_common_resume,
828 .is_idle = soc21_common_is_idle,
829 .wait_for_idle = soc21_common_wait_for_idle,
830 .soft_reset = soc21_common_soft_reset,
831 .set_clockgating_state = soc21_common_set_clockgating_state,
832 .set_powergating_state = soc21_common_set_powergating_state,
833 .get_clockgating_state = soc21_common_get_clockgating_state,
834 };
835