1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * HD-audio core stuff
4  */
5 
6 #ifndef __SOUND_HDAUDIO_H
7 #define __SOUND_HDAUDIO_H
8 
9 #include <linux/device.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include <linux/iopoll.h>
14 #include <linux/pci.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/timecounter.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/memalloc.h>
20 #include <sound/hda_verbs.h>
21 #include <drm/i915_component.h>
22 
23 /* codec node id */
24 typedef u16 hda_nid_t;
25 
26 struct hdac_bus;
27 struct hdac_stream;
28 struct hdac_device;
29 struct hdac_driver;
30 struct hdac_widget_tree;
31 struct hda_device_id;
32 
33 /*
34  * exported bus type
35  */
36 extern struct bus_type snd_hda_bus_type;
37 
38 /*
39  * generic arrays
40  */
41 struct snd_array {
42 	unsigned int used;
43 	unsigned int alloced;
44 	unsigned int elem_size;
45 	unsigned int alloc_align;
46 	void *list;
47 };
48 
49 /*
50  * HD-audio codec base device
51  */
52 struct hdac_device {
53 	struct device dev;
54 	int type;
55 	struct hdac_bus *bus;
56 	unsigned int addr;		/* codec address */
57 	struct list_head list;		/* list point for bus codec_list */
58 
59 	hda_nid_t afg;			/* AFG node id */
60 	hda_nid_t mfg;			/* MFG node id */
61 
62 	/* ids */
63 	unsigned int vendor_id;
64 	unsigned int subsystem_id;
65 	unsigned int revision_id;
66 	unsigned int afg_function_id;
67 	unsigned int mfg_function_id;
68 	unsigned int afg_unsol:1;
69 	unsigned int mfg_unsol:1;
70 
71 	unsigned int power_caps;	/* FG power caps */
72 
73 	const char *vendor_name;	/* codec vendor name */
74 	const char *chip_name;		/* codec chip name */
75 
76 	/* verb exec op override */
77 	int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
78 			 unsigned int flags, unsigned int *res);
79 
80 	/* widgets */
81 	unsigned int num_nodes;
82 	hda_nid_t start_nid, end_nid;
83 
84 	/* misc flags */
85 	atomic_t in_pm;		/* suspend/resume being performed */
86 
87 	/* sysfs */
88 	struct mutex widget_lock;
89 	struct hdac_widget_tree *widgets;
90 
91 	/* regmap */
92 	struct regmap *regmap;
93 	struct mutex regmap_lock;
94 	struct snd_array vendor_verbs;
95 	bool lazy_cache:1;	/* don't wake up for writes */
96 	bool caps_overwriting:1; /* caps overwrite being in process */
97 	bool cache_coef:1;	/* cache COEF read/write too */
98 	unsigned int registered:1; /* codec was registered */
99 };
100 
101 /* device/driver type used for matching */
102 enum {
103 	HDA_DEV_CORE,
104 	HDA_DEV_LEGACY,
105 	HDA_DEV_ASOC,
106 };
107 
108 enum {
109 	SND_SKL_PCI_BIND_AUTO,	/* automatic selection based on pci class */
110 	SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
111 	SND_SKL_PCI_BIND_ASOC	/* bind only with ASoC driver */
112 };
113 
114 /* direction */
115 enum {
116 	HDA_INPUT, HDA_OUTPUT
117 };
118 
119 #define dev_to_hdac_dev(_dev)	container_of(_dev, struct hdac_device, dev)
120 
121 int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
122 			 const char *name, unsigned int addr);
123 void snd_hdac_device_exit(struct hdac_device *dev);
124 int snd_hdac_device_register(struct hdac_device *codec);
125 void snd_hdac_device_unregister(struct hdac_device *codec);
126 int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
127 int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
128 
129 int snd_hdac_refresh_widgets(struct hdac_device *codec);
130 
131 int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
132 		  unsigned int verb, unsigned int parm, unsigned int *res);
133 int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
134 			unsigned int *res);
135 int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
136 				int parm);
137 int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
138 			   unsigned int parm, unsigned int val);
139 int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
140 			     hda_nid_t *conn_list, int max_conns);
141 int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
142 			   hda_nid_t *start_id);
143 unsigned int snd_hdac_calc_stream_format(unsigned int rate,
144 					 unsigned int channels,
145 					 snd_pcm_format_t format,
146 					 unsigned int maxbps,
147 					 unsigned short spdif_ctls);
148 int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
149 				u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
150 bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
151 				  unsigned int format);
152 
153 int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
154 			int flags, unsigned int verb, unsigned int parm);
155 int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
156 			int flags, unsigned int verb, unsigned int parm);
157 bool snd_hdac_check_power_state(struct hdac_device *hdac,
158 		hda_nid_t nid, unsigned int target_state);
159 unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
160 		      hda_nid_t nid, unsigned int target_state);
161 /**
162  * snd_hdac_read_parm - read a codec parameter
163  * @codec: the codec object
164  * @nid: NID to read a parameter
165  * @parm: parameter to read
166  *
167  * Returns -1 for error.  If you need to distinguish the error more
168  * strictly, use _snd_hdac_read_parm() directly.
169  */
snd_hdac_read_parm(struct hdac_device * codec,hda_nid_t nid,int parm)170 static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
171 				     int parm)
172 {
173 	unsigned int val;
174 
175 	return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
176 }
177 
178 #ifdef CONFIG_PM
179 int snd_hdac_power_up(struct hdac_device *codec);
180 int snd_hdac_power_down(struct hdac_device *codec);
181 int snd_hdac_power_up_pm(struct hdac_device *codec);
182 int snd_hdac_power_down_pm(struct hdac_device *codec);
183 int snd_hdac_keep_power_up(struct hdac_device *codec);
184 
185 /* call this at entering into suspend/resume callbacks in codec driver */
snd_hdac_enter_pm(struct hdac_device * codec)186 static inline void snd_hdac_enter_pm(struct hdac_device *codec)
187 {
188 	atomic_inc(&codec->in_pm);
189 }
190 
191 /* call this at leaving from suspend/resume callbacks in codec driver */
snd_hdac_leave_pm(struct hdac_device * codec)192 static inline void snd_hdac_leave_pm(struct hdac_device *codec)
193 {
194 	atomic_dec(&codec->in_pm);
195 }
196 
snd_hdac_is_in_pm(struct hdac_device * codec)197 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
198 {
199 	return atomic_read(&codec->in_pm);
200 }
201 
snd_hdac_is_power_on(struct hdac_device * codec)202 static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
203 {
204 	return !pm_runtime_suspended(&codec->dev);
205 }
206 #else
snd_hdac_power_up(struct hdac_device * codec)207 static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
snd_hdac_power_down(struct hdac_device * codec)208 static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
snd_hdac_power_up_pm(struct hdac_device * codec)209 static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
snd_hdac_power_down_pm(struct hdac_device * codec)210 static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
snd_hdac_keep_power_up(struct hdac_device * codec)211 static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
snd_hdac_enter_pm(struct hdac_device * codec)212 static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
snd_hdac_leave_pm(struct hdac_device * codec)213 static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
snd_hdac_is_in_pm(struct hdac_device * codec)214 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
snd_hdac_is_power_on(struct hdac_device * codec)215 static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
216 #endif
217 
218 /*
219  * HD-audio codec base driver
220  */
221 struct hdac_driver {
222 	struct device_driver driver;
223 	int type;
224 	const struct hda_device_id *id_table;
225 	int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
226 	void (*unsol_event)(struct hdac_device *dev, unsigned int event);
227 
228 	/* fields used by ext bus APIs */
229 	int (*probe)(struct hdac_device *dev);
230 	int (*remove)(struct hdac_device *dev);
231 	void (*shutdown)(struct hdac_device *dev);
232 };
233 
234 #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
235 
236 const struct hda_device_id *
237 hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
238 
239 /*
240  * Bus verb operators
241  */
242 struct hdac_bus_ops {
243 	/* send a single command */
244 	int (*command)(struct hdac_bus *bus, unsigned int cmd);
245 	/* get a response from the last command */
246 	int (*get_response)(struct hdac_bus *bus, unsigned int addr,
247 			    unsigned int *res);
248 	/* notify of codec link power-up/down */
249 	void (*link_power)(struct hdac_device *hdev, bool enable);
250 };
251 
252 /*
253  * ops used for ASoC HDA codec drivers
254  */
255 struct hdac_ext_bus_ops {
256 	int (*hdev_attach)(struct hdac_device *hdev);
257 	int (*hdev_detach)(struct hdac_device *hdev);
258 };
259 
260 #define HDA_UNSOL_QUEUE_SIZE	64
261 #define HDA_MAX_CODECS		8	/* limit by controller side */
262 
263 /*
264  * CORB/RIRB
265  *
266  * Each CORB entry is 4byte, RIRB is 8byte
267  */
268 struct hdac_rb {
269 	__le32 *buf;		/* virtual address of CORB/RIRB buffer */
270 	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */
271 	unsigned short rp, wp;	/* RIRB read/write pointers */
272 	int cmds[HDA_MAX_CODECS];	/* number of pending requests */
273 	u32 res[HDA_MAX_CODECS];	/* last read value */
274 };
275 
276 /*
277  * HD-audio bus base driver
278  *
279  * @ppcap: pp capabilities pointer
280  * @spbcap: SPIB capabilities pointer
281  * @mlcap: MultiLink capabilities pointer
282  * @gtscap: gts capabilities pointer
283  * @drsmcap: dma resume capabilities pointer
284  * @num_streams: streams supported
285  * @idx: HDA link index
286  * @hlink_list: link list of HDA links
287  * @lock: lock for link and display power mgmt
288  * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
289  */
290 struct hdac_bus {
291 	struct device *dev;
292 	const struct hdac_bus_ops *ops;
293 	const struct hdac_ext_bus_ops *ext_ops;
294 
295 	/* h/w resources */
296 	unsigned long addr;
297 	void __iomem *remap_addr;
298 	int irq;
299 
300 	void __iomem *ppcap;
301 	void __iomem *spbcap;
302 	void __iomem *mlcap;
303 	void __iomem *gtscap;
304 	void __iomem *drsmcap;
305 
306 	/* codec linked list */
307 	struct list_head codec_list;
308 	unsigned int num_codecs;
309 
310 	/* link caddr -> codec */
311 	struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
312 
313 	/* unsolicited event queue */
314 	u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
315 	unsigned int unsol_rp, unsol_wp;
316 	struct work_struct unsol_work;
317 
318 	/* bit flags of detected codecs */
319 	unsigned long codec_mask;
320 
321 	/* bit flags of powered codecs */
322 	unsigned long codec_powered;
323 
324 	/* CORB/RIRB */
325 	struct hdac_rb corb;
326 	struct hdac_rb rirb;
327 	unsigned int last_cmd[HDA_MAX_CODECS];	/* last sent command */
328 	wait_queue_head_t rirb_wq;
329 
330 	/* CORB/RIRB and position buffers */
331 	struct snd_dma_buffer rb;
332 	struct snd_dma_buffer posbuf;
333 	int dma_type;			/* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
334 
335 	/* hdac_stream linked list */
336 	struct list_head stream_list;
337 
338 	/* operation state */
339 	bool chip_init:1;		/* h/w initialized */
340 
341 	/* behavior flags */
342 	bool aligned_mmio:1;		/* aligned MMIO access */
343 	bool sync_write:1;		/* sync after verb write */
344 	bool use_posbuf:1;		/* use position buffer */
345 	bool snoop:1;			/* enable snooping */
346 	bool align_bdle_4k:1;		/* BDLE align 4K boundary */
347 	bool reverse_assign:1;		/* assign devices in reverse order */
348 	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */
349 	bool polling_mode:1;
350 	bool needs_damn_long_delay:1;
351 	bool not_use_interrupts:1;	/* prohibiting the RIRB IRQ */
352 	bool access_sdnctl_in_dword:1;	/* accessing the sdnctl register by dword */
353 
354 	int poll_count;
355 
356 	int bdl_pos_adj;		/* BDL position adjustment */
357 
358 	/* delay time in us for dma stop */
359 	unsigned int dma_stop_delay;
360 
361 	/* locks */
362 	spinlock_t reg_lock;
363 	struct mutex cmd_mutex;
364 	struct mutex lock;
365 
366 	/* DRM component interface */
367 	struct drm_audio_component *audio_component;
368 	long display_power_status;
369 	unsigned long display_power_active;
370 
371 	/* parameters required for enhanced capabilities */
372 	int num_streams;
373 	int idx;
374 
375 	/* link management */
376 	struct list_head hlink_list;
377 	bool cmd_dma_state;
378 
379 	/* factor used to derive STRIPE control value */
380 	unsigned int sdo_limit;
381 };
382 
383 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
384 		      const struct hdac_bus_ops *ops);
385 void snd_hdac_bus_exit(struct hdac_bus *bus);
386 int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
387 				    unsigned int cmd, unsigned int *res);
388 
389 void snd_hdac_codec_link_up(struct hdac_device *codec);
390 void snd_hdac_codec_link_down(struct hdac_device *codec);
391 
392 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
393 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
394 			      unsigned int *res);
395 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
396 
397 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
398 void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
399 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
400 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
401 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
402 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
403 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
404 void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
405 
406 void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
407 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
408 				    void (*ack)(struct hdac_bus *,
409 						struct hdac_stream *));
410 
411 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
412 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
413 
414 #ifdef CONFIG_SND_HDA_ALIGNED_MMIO
415 unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
416 void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
417 			    unsigned int mask);
418 #define snd_hdac_aligned_mmio(bus)	(bus)->aligned_mmio
419 #else
420 #define snd_hdac_aligned_mmio(bus)	false
421 #define snd_hdac_aligned_read(addr, mask)	0
422 #define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
423 #endif
424 
snd_hdac_reg_writeb(struct hdac_bus * bus,void __iomem * addr,u8 val)425 static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
426 				       u8 val)
427 {
428 	if (snd_hdac_aligned_mmio(bus))
429 		snd_hdac_aligned_write(val, addr, 0xff);
430 	else
431 		writeb(val, addr);
432 }
433 
snd_hdac_reg_writew(struct hdac_bus * bus,void __iomem * addr,u16 val)434 static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
435 				       u16 val)
436 {
437 	if (snd_hdac_aligned_mmio(bus))
438 		snd_hdac_aligned_write(val, addr, 0xffff);
439 	else
440 		writew(val, addr);
441 }
442 
snd_hdac_reg_readb(struct hdac_bus * bus,void __iomem * addr)443 static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
444 {
445 	return snd_hdac_aligned_mmio(bus) ?
446 		snd_hdac_aligned_read(addr, 0xff) : readb(addr);
447 }
448 
snd_hdac_reg_readw(struct hdac_bus * bus,void __iomem * addr)449 static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
450 {
451 	return snd_hdac_aligned_mmio(bus) ?
452 		snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
453 }
454 
455 #define snd_hdac_reg_writel(bus, addr, val)	writel(val, addr)
456 #define snd_hdac_reg_readl(bus, addr)	readl(addr)
457 #define snd_hdac_reg_writeq(bus, addr, val)	writeq(val, addr)
458 #define snd_hdac_reg_readq(bus, addr)		readq(addr)
459 
460 /*
461  * macros for easy use
462  */
463 #define _snd_hdac_chip_writeb(chip, reg, value) \
464 	snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
465 #define _snd_hdac_chip_readb(chip, reg) \
466 	snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
467 #define _snd_hdac_chip_writew(chip, reg, value) \
468 	snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
469 #define _snd_hdac_chip_readw(chip, reg) \
470 	snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
471 #define _snd_hdac_chip_writel(chip, reg, value) \
472 	snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
473 #define _snd_hdac_chip_readl(chip, reg) \
474 	snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
475 
476 /* read/write a register, pass without AZX_REG_ prefix */
477 #define snd_hdac_chip_writel(chip, reg, value) \
478 	_snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
479 #define snd_hdac_chip_writew(chip, reg, value) \
480 	_snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
481 #define snd_hdac_chip_writeb(chip, reg, value) \
482 	_snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
483 #define snd_hdac_chip_readl(chip, reg) \
484 	_snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
485 #define snd_hdac_chip_readw(chip, reg) \
486 	_snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
487 #define snd_hdac_chip_readb(chip, reg) \
488 	_snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
489 
490 /* update a register, pass without AZX_REG_ prefix */
491 #define snd_hdac_chip_updatel(chip, reg, mask, val) \
492 	snd_hdac_chip_writel(chip, reg, \
493 			     (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
494 #define snd_hdac_chip_updatew(chip, reg, mask, val) \
495 	snd_hdac_chip_writew(chip, reg, \
496 			     (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
497 #define snd_hdac_chip_updateb(chip, reg, mask, val) \
498 	snd_hdac_chip_writeb(chip, reg, \
499 			     (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
500 
501 /* update register macro */
502 #define snd_hdac_updatel(addr, reg, mask, val)		\
503 	writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
504 
505 #define snd_hdac_updatew(addr, reg, mask, val)		\
506 	writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
507 
508 /*
509  * HD-audio stream
510  */
511 struct hdac_stream {
512 	struct hdac_bus *bus;
513 	struct snd_dma_buffer bdl; /* BDL buffer */
514 	__le32 *posbuf;		/* position buffer pointer */
515 	int direction;		/* playback / capture (SNDRV_PCM_STREAM_*) */
516 
517 	unsigned int bufsize;	/* size of the play buffer in bytes */
518 	unsigned int period_bytes; /* size of the period in bytes */
519 	unsigned int frags;	/* number for period in the play buffer */
520 	unsigned int fifo_size;	/* FIFO size */
521 
522 	void __iomem *sd_addr;	/* stream descriptor pointer */
523 
524 	void __iomem *spib_addr; /* software position in buffers stream pointer */
525 	void __iomem *fifo_addr; /* software position Max fifos stream pointer */
526 
527 	void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
528 	u32 dpib;		/* DMA position in buffer */
529 	u32 lpib;		/* Linear position in buffer */
530 
531 	u32 sd_int_sta_mask;	/* stream int status mask */
532 
533 	/* pcm support */
534 	struct snd_pcm_substream *substream;	/* assigned substream,
535 						 * set in PCM open
536 						 */
537 	struct snd_compr_stream *cstream;
538 	unsigned int format_val;	/* format value to be set in the
539 					 * controller and the codec
540 					 */
541 	unsigned char stream_tag;	/* assigned stream */
542 	unsigned char index;		/* stream index */
543 	int assigned_key;		/* last device# key assigned to */
544 
545 	bool opened:1;
546 	bool running:1;
547 	bool prepared:1;
548 	bool no_period_wakeup:1;
549 	bool locked:1;
550 	bool stripe:1;			/* apply stripe control */
551 
552 	u64 curr_pos;
553 	/* timestamp */
554 	unsigned long start_wallclk;	/* start + minimum wallclk */
555 	unsigned long period_wallclk;	/* wallclk for period */
556 	struct timecounter  tc;
557 	struct cyclecounter cc;
558 	int delay_negative_threshold;
559 
560 	struct list_head list;
561 #ifdef CONFIG_SND_HDA_DSP_LOADER
562 	/* DSP access mutex */
563 	struct mutex dsp_mutex;
564 #endif
565 };
566 
567 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
568 			  int idx, int direction, int tag);
569 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
570 					   struct snd_pcm_substream *substream);
571 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
572 void snd_hdac_stream_release(struct hdac_stream *azx_dev);
573 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
574 					int dir, int stream_tag);
575 
576 int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
577 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
578 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
579 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
580 				unsigned int format_val);
581 void snd_hdac_stream_start(struct hdac_stream *azx_dev);
582 void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
583 void snd_hdac_stop_streams(struct hdac_bus *bus);
584 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
585 void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
586 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
587 				  unsigned int streams, unsigned int reg);
588 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
589 			  unsigned int streams);
590 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
591 				      unsigned int streams);
592 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
593 				struct snd_pcm_substream *substream);
594 
595 void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
596 				   bool enable, int index);
597 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
598 			     struct hdac_stream *azx_dev, u32 value);
599 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
600 				   struct hdac_stream *azx_dev);
601 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
602 				 bool enable, int index);
603 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
604 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
605 			      struct hdac_stream *azx_dev, u32 value);
606 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
607 
608 /*
609  * macros for easy use
610  */
611 /* read/write a register, pass without AZX_REG_ prefix */
612 #define snd_hdac_stream_writel(dev, reg, value) \
613 	snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
614 #define snd_hdac_stream_writew(dev, reg, value) \
615 	snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
616 #define snd_hdac_stream_writeb(dev, reg, value) \
617 	snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
618 #define snd_hdac_stream_readl(dev, reg) \
619 	snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
620 #define snd_hdac_stream_readw(dev, reg) \
621 	snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
622 #define snd_hdac_stream_readb(dev, reg) \
623 	snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
624 #define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
625 	read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
626 				 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
627 #define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
628 	read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
629 				 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
630 
631 /* update a register, pass without AZX_REG_ prefix */
632 #define snd_hdac_stream_updatel(dev, reg, mask, val) \
633 	snd_hdac_stream_writel(dev, reg, \
634 			       (snd_hdac_stream_readl(dev, reg) & \
635 				~(mask)) | (val))
636 #define snd_hdac_stream_updatew(dev, reg, mask, val) \
637 	snd_hdac_stream_writew(dev, reg, \
638 			       (snd_hdac_stream_readw(dev, reg) & \
639 				~(mask)) | (val))
640 #define snd_hdac_stream_updateb(dev, reg, mask, val) \
641 	snd_hdac_stream_writeb(dev, reg, \
642 			       (snd_hdac_stream_readb(dev, reg) & \
643 				~(mask)) | (val))
644 
645 #ifdef CONFIG_SND_HDA_DSP_LOADER
646 /* DSP lock helpers */
647 #define snd_hdac_dsp_lock_init(dev)	mutex_init(&(dev)->dsp_mutex)
648 #define snd_hdac_dsp_lock(dev)		mutex_lock(&(dev)->dsp_mutex)
649 #define snd_hdac_dsp_unlock(dev)	mutex_unlock(&(dev)->dsp_mutex)
650 #define snd_hdac_stream_is_locked(dev)	((dev)->locked)
651 /* DSP loader helpers */
652 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
653 			 unsigned int byte_size, struct snd_dma_buffer *bufp);
654 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
655 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
656 			  struct snd_dma_buffer *dmab);
657 #else /* CONFIG_SND_HDA_DSP_LOADER */
658 #define snd_hdac_dsp_lock_init(dev)	do {} while (0)
659 #define snd_hdac_dsp_lock(dev)		do {} while (0)
660 #define snd_hdac_dsp_unlock(dev)	do {} while (0)
661 #define snd_hdac_stream_is_locked(dev)	0
662 
663 static inline int
snd_hdac_dsp_prepare(struct hdac_stream * azx_dev,unsigned int format,unsigned int byte_size,struct snd_dma_buffer * bufp)664 snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
665 		     unsigned int byte_size, struct snd_dma_buffer *bufp)
666 {
667 	return 0;
668 }
669 
snd_hdac_dsp_trigger(struct hdac_stream * azx_dev,bool start)670 static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
671 {
672 }
673 
snd_hdac_dsp_cleanup(struct hdac_stream * azx_dev,struct snd_dma_buffer * dmab)674 static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
675 					struct snd_dma_buffer *dmab)
676 {
677 }
678 #endif /* CONFIG_SND_HDA_DSP_LOADER */
679 
680 
681 /*
682  * generic array helpers
683  */
684 void *snd_array_new(struct snd_array *array);
685 void snd_array_free(struct snd_array *array);
snd_array_init(struct snd_array * array,unsigned int size,unsigned int align)686 static inline void snd_array_init(struct snd_array *array, unsigned int size,
687 				  unsigned int align)
688 {
689 	array->elem_size = size;
690 	array->alloc_align = align;
691 }
692 
snd_array_elem(struct snd_array * array,unsigned int idx)693 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
694 {
695 	return array->list + idx * array->elem_size;
696 }
697 
snd_array_index(struct snd_array * array,void * ptr)698 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
699 {
700 	return (unsigned long)(ptr - array->list) / array->elem_size;
701 }
702 
703 /* a helper macro to iterate for each snd_array element */
704 #define snd_array_for_each(array, idx, ptr) \
705 	for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
706 	     (ptr) = snd_array_elem(array, ++(idx)))
707 
708 /*
709  * Device matching
710  */
711 
712 #define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
713 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
714 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \
715 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \
716 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \
717 			{ } \
718 		}, pci))
719 
720 #define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \
721 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \
722 			{ } \
723 		}, pci))
724 
725 #define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \
726 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \
727 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \
728 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \
729 			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \
730 			{ } \
731 		}, pci) || HDA_CONTROLLER_IS_HSW(pci))
732 
733 #endif /* __SOUND_HDAUDIO_H */
734