1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HD-audio controller helpers
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
12 #include "local.h"
13
14 /* clear CORB read pointer properly */
azx_clear_corbrp(struct hdac_bus * bus)15 static void azx_clear_corbrp(struct hdac_bus *bus)
16 {
17 int timeout;
18
19 for (timeout = 1000; timeout > 0; timeout--) {
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
21 break;
22 udelay(1);
23 }
24 if (timeout <= 0)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
27
28 snd_hdac_chip_writew(bus, CORBRP, 0);
29 for (timeout = 1000; timeout > 0; timeout--) {
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
31 break;
32 udelay(1);
33 }
34 if (timeout <= 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
37 }
38
39 /**
40 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
41 * @bus: HD-audio core bus
42 */
snd_hdac_bus_init_cmd_io(struct hdac_bus * bus)43 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
44 {
45 WARN_ON_ONCE(!bus->rb.area);
46
47 spin_lock_irq(&bus->reg_lock);
48 /* CORB set up */
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
53
54 /* set the corb size to 256 entries (ULI requires explicitly) */
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
56 /* set the corb write pointer to 0 */
57 snd_hdac_chip_writew(bus, CORBWP, 0);
58
59 /* reset the corb hw read pointer */
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
63
64 /* enable corb dma */
65 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
66
67 /* RIRB set up */
68 bus->rirb.addr = bus->rb.addr + 2048;
69 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
70 bus->rirb.wp = bus->rirb.rp = 0;
71 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
72 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
73 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
74
75 /* set the rirb size to 256 entries (ULI requires explicitly) */
76 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
77 /* reset the rirb hw write pointer */
78 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
79 /* set N=1, get RIRB response interrupt for new entry */
80 snd_hdac_chip_writew(bus, RINTCNT, 1);
81 /* enable rirb dma and response irq */
82 if (bus->not_use_interrupts)
83 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
84 else
85 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
86 /* Accept unsolicited responses */
87 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
88 spin_unlock_irq(&bus->reg_lock);
89 }
90 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
91
92 /* wait for cmd dmas till they are stopped */
hdac_wait_for_cmd_dmas(struct hdac_bus * bus)93 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
94 {
95 unsigned long timeout;
96
97 timeout = jiffies + msecs_to_jiffies(100);
98 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
99 && time_before(jiffies, timeout))
100 udelay(10);
101
102 timeout = jiffies + msecs_to_jiffies(100);
103 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
104 && time_before(jiffies, timeout))
105 udelay(10);
106 }
107
108 /**
109 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
110 * @bus: HD-audio core bus
111 */
snd_hdac_bus_stop_cmd_io(struct hdac_bus * bus)112 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
113 {
114 spin_lock_irq(&bus->reg_lock);
115 /* disable ringbuffer DMAs */
116 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
117 snd_hdac_chip_writeb(bus, CORBCTL, 0);
118 spin_unlock_irq(&bus->reg_lock);
119
120 hdac_wait_for_cmd_dmas(bus);
121
122 spin_lock_irq(&bus->reg_lock);
123 /* disable unsolicited responses */
124 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
125 spin_unlock_irq(&bus->reg_lock);
126 }
127 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
128
azx_command_addr(u32 cmd)129 static unsigned int azx_command_addr(u32 cmd)
130 {
131 unsigned int addr = cmd >> 28;
132
133 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
134 addr = 0;
135 return addr;
136 }
137
138 /**
139 * snd_hdac_bus_send_cmd - send a command verb via CORB
140 * @bus: HD-audio core bus
141 * @val: encoded verb value to send
142 *
143 * Returns zero for success or a negative error code.
144 */
snd_hdac_bus_send_cmd(struct hdac_bus * bus,unsigned int val)145 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
146 {
147 unsigned int addr = azx_command_addr(val);
148 unsigned int wp, rp;
149
150 spin_lock_irq(&bus->reg_lock);
151
152 bus->last_cmd[azx_command_addr(val)] = val;
153
154 /* add command to corb */
155 wp = snd_hdac_chip_readw(bus, CORBWP);
156 if (wp == 0xffff) {
157 /* something wrong, controller likely turned to D3 */
158 spin_unlock_irq(&bus->reg_lock);
159 return -EIO;
160 }
161 wp++;
162 wp %= AZX_MAX_CORB_ENTRIES;
163
164 rp = snd_hdac_chip_readw(bus, CORBRP);
165 if (wp == rp) {
166 /* oops, it's full */
167 spin_unlock_irq(&bus->reg_lock);
168 return -EAGAIN;
169 }
170
171 bus->rirb.cmds[addr]++;
172 bus->corb.buf[wp] = cpu_to_le32(val);
173 snd_hdac_chip_writew(bus, CORBWP, wp);
174
175 spin_unlock_irq(&bus->reg_lock);
176
177 return 0;
178 }
179 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
180
181 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
182
183 /**
184 * snd_hdac_bus_update_rirb - retrieve RIRB entries
185 * @bus: HD-audio core bus
186 *
187 * Usually called from interrupt handler.
188 * The caller needs bus->reg_lock spinlock before calling this.
189 */
snd_hdac_bus_update_rirb(struct hdac_bus * bus)190 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
191 {
192 unsigned int rp, wp;
193 unsigned int addr;
194 u32 res, res_ex;
195
196 wp = snd_hdac_chip_readw(bus, RIRBWP);
197 if (wp == 0xffff) {
198 /* something wrong, controller likely turned to D3 */
199 return;
200 }
201
202 if (wp == bus->rirb.wp)
203 return;
204 bus->rirb.wp = wp;
205
206 while (bus->rirb.rp != wp) {
207 bus->rirb.rp++;
208 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
209
210 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
211 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
212 res = le32_to_cpu(bus->rirb.buf[rp]);
213 addr = res_ex & 0xf;
214 if (addr >= HDA_MAX_CODECS) {
215 dev_err(bus->dev,
216 "spurious response %#x:%#x, rp = %d, wp = %d",
217 res, res_ex, bus->rirb.rp, wp);
218 snd_BUG();
219 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
220 snd_hdac_bus_queue_event(bus, res, res_ex);
221 else if (bus->rirb.cmds[addr]) {
222 bus->rirb.res[addr] = res;
223 bus->rirb.cmds[addr]--;
224 if (!bus->rirb.cmds[addr] &&
225 waitqueue_active(&bus->rirb_wq))
226 wake_up(&bus->rirb_wq);
227 } else {
228 dev_err_ratelimited(bus->dev,
229 "spurious response %#x:%#x, last cmd=%#08x\n",
230 res, res_ex, bus->last_cmd[addr]);
231 }
232 }
233 }
234 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
235
236 /**
237 * snd_hdac_bus_get_response - receive a response via RIRB
238 * @bus: HD-audio core bus
239 * @addr: codec address
240 * @res: pointer to store the value, NULL when not needed
241 *
242 * Returns zero if a value is read, or a negative error code.
243 */
snd_hdac_bus_get_response(struct hdac_bus * bus,unsigned int addr,unsigned int * res)244 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
245 unsigned int *res)
246 {
247 unsigned long timeout;
248 unsigned long loopcounter;
249 wait_queue_entry_t wait;
250 bool warned = false;
251
252 init_wait_entry(&wait, 0);
253 timeout = jiffies + msecs_to_jiffies(1000);
254
255 for (loopcounter = 0;; loopcounter++) {
256 spin_lock_irq(&bus->reg_lock);
257 if (!bus->polling_mode)
258 prepare_to_wait(&bus->rirb_wq, &wait,
259 TASK_UNINTERRUPTIBLE);
260 if (bus->polling_mode)
261 snd_hdac_bus_update_rirb(bus);
262 if (!bus->rirb.cmds[addr]) {
263 if (res)
264 *res = bus->rirb.res[addr]; /* the last value */
265 if (!bus->polling_mode)
266 finish_wait(&bus->rirb_wq, &wait);
267 spin_unlock_irq(&bus->reg_lock);
268 return 0;
269 }
270 spin_unlock_irq(&bus->reg_lock);
271 if (time_after(jiffies, timeout))
272 break;
273 #define LOOP_COUNT_MAX 3000
274 if (!bus->polling_mode) {
275 schedule_timeout(msecs_to_jiffies(2));
276 } else if (bus->needs_damn_long_delay ||
277 loopcounter > LOOP_COUNT_MAX) {
278 if (loopcounter > LOOP_COUNT_MAX && !warned) {
279 dev_dbg_ratelimited(bus->dev,
280 "too slow response, last cmd=%#08x\n",
281 bus->last_cmd[addr]);
282 warned = true;
283 }
284 msleep(2); /* temporary workaround */
285 } else {
286 udelay(10);
287 cond_resched();
288 }
289 }
290
291 if (!bus->polling_mode)
292 finish_wait(&bus->rirb_wq, &wait);
293
294 return -EIO;
295 }
296 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
297
298 #define HDAC_MAX_CAPS 10
299 /**
300 * snd_hdac_bus_parse_capabilities - parse capability structure
301 * @bus: the pointer to bus object
302 *
303 * Returns 0 if successful, or a negative error code.
304 */
snd_hdac_bus_parse_capabilities(struct hdac_bus * bus)305 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
306 {
307 unsigned int cur_cap;
308 unsigned int offset;
309 unsigned int counter = 0;
310
311 offset = snd_hdac_chip_readw(bus, LLCH);
312
313 /* Lets walk the linked capabilities list */
314 do {
315 cur_cap = _snd_hdac_chip_readl(bus, offset);
316
317 dev_dbg(bus->dev, "Capability version: 0x%x\n",
318 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
319
320 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
321 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
322
323 if (cur_cap == -1) {
324 dev_dbg(bus->dev, "Invalid capability reg read\n");
325 break;
326 }
327
328 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
329 case AZX_ML_CAP_ID:
330 dev_dbg(bus->dev, "Found ML capability\n");
331 bus->mlcap = bus->remap_addr + offset;
332 break;
333
334 case AZX_GTS_CAP_ID:
335 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
336 bus->gtscap = bus->remap_addr + offset;
337 break;
338
339 case AZX_PP_CAP_ID:
340 /* PP capability found, the Audio DSP is present */
341 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
342 bus->ppcap = bus->remap_addr + offset;
343 break;
344
345 case AZX_SPB_CAP_ID:
346 /* SPIB capability found, handler function */
347 dev_dbg(bus->dev, "Found SPB capability\n");
348 bus->spbcap = bus->remap_addr + offset;
349 break;
350
351 case AZX_DRSM_CAP_ID:
352 /* DMA resume capability found, handler function */
353 dev_dbg(bus->dev, "Found DRSM capability\n");
354 bus->drsmcap = bus->remap_addr + offset;
355 break;
356
357 default:
358 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
359 cur_cap = 0;
360 break;
361 }
362
363 counter++;
364
365 if (counter > HDAC_MAX_CAPS) {
366 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
367 break;
368 }
369
370 /* read the offset of next capability */
371 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
372
373 } while (offset);
374
375 return 0;
376 }
377 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
378
379 /*
380 * Lowlevel interface
381 */
382
383 /**
384 * snd_hdac_bus_enter_link_reset - enter link reset
385 * @bus: HD-audio core bus
386 *
387 * Enter to the link reset state.
388 */
snd_hdac_bus_enter_link_reset(struct hdac_bus * bus)389 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
390 {
391 unsigned long timeout;
392
393 /* reset controller */
394 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
395
396 timeout = jiffies + msecs_to_jiffies(100);
397 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
398 time_before(jiffies, timeout))
399 usleep_range(500, 1000);
400 }
401 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
402
403 /**
404 * snd_hdac_bus_exit_link_reset - exit link reset
405 * @bus: HD-audio core bus
406 *
407 * Exit from the link reset state.
408 */
snd_hdac_bus_exit_link_reset(struct hdac_bus * bus)409 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
410 {
411 unsigned long timeout;
412
413 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
414
415 timeout = jiffies + msecs_to_jiffies(100);
416 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
417 usleep_range(500, 1000);
418 }
419 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
420
421 /* reset codec link */
snd_hdac_bus_reset_link(struct hdac_bus * bus,bool full_reset)422 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
423 {
424 if (!full_reset)
425 goto skip_reset;
426
427 /* clear STATESTS if not in reset */
428 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
429 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
430
431 /* reset controller */
432 snd_hdac_bus_enter_link_reset(bus);
433
434 /* delay for >= 100us for codec PLL to settle per spec
435 * Rev 0.9 section 5.5.1
436 */
437 usleep_range(500, 1000);
438
439 /* Bring controller out of reset */
440 snd_hdac_bus_exit_link_reset(bus);
441
442 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
443 usleep_range(1000, 1200);
444
445 skip_reset:
446 /* check to see if controller is ready */
447 if (!snd_hdac_chip_readb(bus, GCTL)) {
448 dev_dbg(bus->dev, "controller not ready!\n");
449 return -EBUSY;
450 }
451
452 /* detect codecs */
453 if (!bus->codec_mask) {
454 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
455 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
456 }
457
458 return 0;
459 }
460 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
461
462 /* enable interrupts */
azx_int_enable(struct hdac_bus * bus)463 static void azx_int_enable(struct hdac_bus *bus)
464 {
465 /* enable controller CIE and GIE */
466 snd_hdac_chip_updatel(bus, INTCTL,
467 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
468 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
469 }
470
471 /* disable interrupts */
azx_int_disable(struct hdac_bus * bus)472 static void azx_int_disable(struct hdac_bus *bus)
473 {
474 struct hdac_stream *azx_dev;
475
476 /* disable interrupts in stream descriptor */
477 list_for_each_entry(azx_dev, &bus->stream_list, list)
478 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
479
480 /* disable SIE for all streams & disable controller CIE and GIE */
481 snd_hdac_chip_writel(bus, INTCTL, 0);
482 }
483
484 /* clear interrupts */
azx_int_clear(struct hdac_bus * bus)485 static void azx_int_clear(struct hdac_bus *bus)
486 {
487 struct hdac_stream *azx_dev;
488
489 /* clear stream status */
490 list_for_each_entry(azx_dev, &bus->stream_list, list)
491 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
492
493 /* clear STATESTS */
494 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
495
496 /* clear rirb status */
497 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
498
499 /* clear int status */
500 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
501 }
502
503 /**
504 * snd_hdac_bus_init_chip - reset and start the controller registers
505 * @bus: HD-audio core bus
506 * @full_reset: Do full reset
507 */
snd_hdac_bus_init_chip(struct hdac_bus * bus,bool full_reset)508 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
509 {
510 if (bus->chip_init)
511 return false;
512
513 /* reset controller */
514 snd_hdac_bus_reset_link(bus, full_reset);
515
516 /* clear interrupts */
517 azx_int_clear(bus);
518
519 /* initialize the codec command I/O */
520 snd_hdac_bus_init_cmd_io(bus);
521
522 /* enable interrupts after CORB/RIRB buffers are initialized above */
523 azx_int_enable(bus);
524
525 /* program the position buffer */
526 if (bus->use_posbuf && bus->posbuf.addr) {
527 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
528 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
529 }
530
531 bus->chip_init = true;
532
533 return true;
534 }
535 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
536
537 /**
538 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
539 * @bus: HD-audio core bus
540 */
snd_hdac_bus_stop_chip(struct hdac_bus * bus)541 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
542 {
543 if (!bus->chip_init)
544 return;
545
546 /* disable interrupts */
547 azx_int_disable(bus);
548 azx_int_clear(bus);
549
550 /* disable CORB/RIRB */
551 snd_hdac_bus_stop_cmd_io(bus);
552
553 /* disable position buffer */
554 if (bus->posbuf.addr) {
555 snd_hdac_chip_writel(bus, DPLBASE, 0);
556 snd_hdac_chip_writel(bus, DPUBASE, 0);
557 }
558
559 bus->chip_init = false;
560 }
561 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
562
563 /**
564 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
565 * @bus: HD-audio core bus
566 * @status: INTSTS register value
567 * @ack: callback to be called for woken streams
568 *
569 * Returns the bits of handled streams, or zero if no stream is handled.
570 */
snd_hdac_bus_handle_stream_irq(struct hdac_bus * bus,unsigned int status,void (* ack)(struct hdac_bus *,struct hdac_stream *))571 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
572 void (*ack)(struct hdac_bus *,
573 struct hdac_stream *))
574 {
575 struct hdac_stream *azx_dev;
576 u8 sd_status;
577 int handled = 0;
578
579 list_for_each_entry(azx_dev, &bus->stream_list, list) {
580 if (status & azx_dev->sd_int_sta_mask) {
581 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
582 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
583 handled |= 1 << azx_dev->index;
584 if ((!azx_dev->substream && !azx_dev->cstream) ||
585 !azx_dev->running || !(sd_status & SD_INT_COMPLETE))
586 continue;
587 if (ack)
588 ack(bus, azx_dev);
589 }
590 }
591 return handled;
592 }
593 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
594
595 /**
596 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
597 * @bus: HD-audio core bus
598 *
599 * Call this after assigning the all streams.
600 * Returns zero for success, or a negative error code.
601 */
snd_hdac_bus_alloc_stream_pages(struct hdac_bus * bus)602 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
603 {
604 struct hdac_stream *s;
605 int num_streams = 0;
606 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
607 int err;
608
609 list_for_each_entry(s, &bus->stream_list, list) {
610 /* allocate memory for the BDL for each stream */
611 err = snd_dma_alloc_pages(dma_type, bus->dev,
612 BDL_SIZE, &s->bdl);
613 num_streams++;
614 if (err < 0)
615 return -ENOMEM;
616 }
617
618 if (WARN_ON(!num_streams))
619 return -EINVAL;
620 /* allocate memory for the position buffer */
621 err = snd_dma_alloc_pages(dma_type, bus->dev,
622 num_streams * 8, &bus->posbuf);
623 if (err < 0)
624 return -ENOMEM;
625 list_for_each_entry(s, &bus->stream_list, list)
626 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
627
628 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
629 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
630 }
631 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
632
633 /**
634 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
635 * @bus: HD-audio core bus
636 */
snd_hdac_bus_free_stream_pages(struct hdac_bus * bus)637 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
638 {
639 struct hdac_stream *s;
640
641 list_for_each_entry(s, &bus->stream_list, list) {
642 if (s->bdl.area)
643 snd_dma_free_pages(&s->bdl);
644 }
645
646 if (bus->rb.area)
647 snd_dma_free_pages(&bus->rb);
648 if (bus->posbuf.area)
649 snd_dma_free_pages(&bus->posbuf);
650 }
651 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);
652
653 /**
654 * snd_hdac_bus_link_power - power up/down codec link
655 * @codec: HD-audio device
656 * @enable: whether to power-up the link
657 */
snd_hdac_bus_link_power(struct hdac_device * codec,bool enable)658 void snd_hdac_bus_link_power(struct hdac_device *codec, bool enable)
659 {
660 if (enable)
661 set_bit(codec->addr, &codec->bus->codec_powered);
662 else
663 clear_bit(codec->addr, &codec->bus->codec_powered);
664 }
665 EXPORT_SYMBOL_GPL(snd_hdac_bus_link_power);
666