1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62
63 #define SMU13_VOLTAGE_SCALE 4
64
65 #define LINK_WIDTH_MAX 6
66 #define LINK_SPEED_MAX 3
67
68 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
71 #define smnPCIE_LC_SPEED_CNTL 0x11140290
72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
74
75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
76 static const int link_speed[] = {25, 50, 80, 160};
77
78 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
79 uint32_t pptable_id);
80
smu_v13_0_init_microcode(struct smu_context * smu)81 int smu_v13_0_init_microcode(struct smu_context *smu)
82 {
83 struct amdgpu_device *adev = smu->adev;
84 const char *chip_name;
85 char fw_name[30];
86 char ucode_prefix[30];
87 int err = 0;
88 const struct smc_firmware_header_v1_0 *hdr;
89 const struct common_firmware_header *header;
90 struct amdgpu_firmware_info *ucode = NULL;
91
92 /* doesn't need to load smu firmware in IOV mode */
93 if (amdgpu_sriov_vf(adev))
94 return 0;
95
96 switch (adev->ip_versions[MP1_HWIP][0]) {
97 case IP_VERSION(13, 0, 2):
98 chip_name = "aldebaran_smc";
99 break;
100 default:
101 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
102 chip_name = ucode_prefix;
103 }
104
105 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
106
107 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
108 if (err)
109 goto out;
110 err = amdgpu_ucode_validate(adev->pm.fw);
111 if (err)
112 goto out;
113
114 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
115 amdgpu_ucode_print_smc_hdr(&hdr->header);
116 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
117
118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
119 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
120 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
121 ucode->fw = adev->pm.fw;
122 header = (const struct common_firmware_header *)ucode->fw->data;
123 adev->firmware.fw_size +=
124 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
125 }
126
127 out:
128 if (err) {
129 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
130 fw_name);
131 release_firmware(adev->pm.fw);
132 adev->pm.fw = NULL;
133 }
134 return err;
135 }
136
smu_v13_0_fini_microcode(struct smu_context * smu)137 void smu_v13_0_fini_microcode(struct smu_context *smu)
138 {
139 struct amdgpu_device *adev = smu->adev;
140
141 release_firmware(adev->pm.fw);
142 adev->pm.fw = NULL;
143 adev->pm.fw_version = 0;
144 }
145
smu_v13_0_load_microcode(struct smu_context * smu)146 int smu_v13_0_load_microcode(struct smu_context *smu)
147 {
148 #if 0
149 struct amdgpu_device *adev = smu->adev;
150 const uint32_t *src;
151 const struct smc_firmware_header_v1_0 *hdr;
152 uint32_t addr_start = MP1_SRAM;
153 uint32_t i;
154 uint32_t smc_fw_size;
155 uint32_t mp1_fw_flags;
156
157 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
158 src = (const uint32_t *)(adev->pm.fw->data +
159 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
160 smc_fw_size = hdr->header.ucode_size_bytes;
161
162 for (i = 1; i < smc_fw_size/4 - 1; i++) {
163 WREG32_PCIE(addr_start, src[i]);
164 addr_start += 4;
165 }
166
167 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
168 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
169 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
170 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
171
172 for (i = 0; i < adev->usec_timeout; i++) {
173 mp1_fw_flags = RREG32_PCIE(MP1_Public |
174 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
175 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
176 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
177 break;
178 udelay(1);
179 }
180
181 if (i == adev->usec_timeout)
182 return -ETIME;
183 #endif
184
185 return 0;
186 }
187
smu_v13_0_init_pptable_microcode(struct smu_context * smu)188 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
189 {
190 struct amdgpu_device *adev = smu->adev;
191 struct amdgpu_firmware_info *ucode = NULL;
192 uint32_t size = 0, pptable_id = 0;
193 int ret = 0;
194 void *table;
195
196 /* doesn't need to load smu firmware in IOV mode */
197 if (amdgpu_sriov_vf(adev))
198 return 0;
199
200 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
201 return 0;
202
203 if (!adev->scpm_enabled)
204 return 0;
205
206 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
207 return 0;
208
209 /* override pptable_id from driver parameter */
210 if (amdgpu_smu_pptable_id >= 0) {
211 pptable_id = amdgpu_smu_pptable_id;
212 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
213 } else {
214 pptable_id = smu->smu_table.boot_values.pp_table_id;
215
216 /*
217 * Temporary solution for SMU V13.0.0 with SCPM enabled:
218 * - use 36831 signed pptable when pp_table_id is 3683
219 * - use 36641 signed pptable when pp_table_id is 3664 or 0
220 * TODO: drop these when the pptable carried in vbios is ready.
221 */
222 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
223 switch (pptable_id) {
224 case 0:
225 case 3664:
226 pptable_id = 36641;
227 break;
228 case 3683:
229 pptable_id = 36831;
230 break;
231 default:
232 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
233 return -EINVAL;
234 }
235 }
236 }
237
238 /* "pptable_id == 0" means vbios carries the pptable. */
239 if (!pptable_id)
240 return 0;
241
242 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
243 if (ret)
244 return ret;
245
246 smu->pptable_firmware.data = table;
247 smu->pptable_firmware.size = size;
248
249 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
250 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
251 ucode->fw = &smu->pptable_firmware;
252 adev->firmware.fw_size +=
253 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
254
255 return 0;
256 }
257
smu_v13_0_check_fw_status(struct smu_context * smu)258 int smu_v13_0_check_fw_status(struct smu_context *smu)
259 {
260 struct amdgpu_device *adev = smu->adev;
261 uint32_t mp1_fw_flags;
262
263 mp1_fw_flags = RREG32_PCIE(MP1_Public |
264 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
265
266 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
267 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
268 return 0;
269
270 return -EIO;
271 }
272
smu_v13_0_check_fw_version(struct smu_context * smu)273 int smu_v13_0_check_fw_version(struct smu_context *smu)
274 {
275 struct amdgpu_device *adev = smu->adev;
276 uint32_t if_version = 0xff, smu_version = 0xff;
277 uint8_t smu_program, smu_major, smu_minor, smu_debug;
278 int ret = 0;
279
280 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
281 if (ret)
282 return ret;
283
284 smu_program = (smu_version >> 24) & 0xff;
285 smu_major = (smu_version >> 16) & 0xff;
286 smu_minor = (smu_version >> 8) & 0xff;
287 smu_debug = (smu_version >> 0) & 0xff;
288 if (smu->is_apu)
289 adev->pm.fw_version = smu_version;
290
291 switch (adev->ip_versions[MP1_HWIP][0]) {
292 case IP_VERSION(13, 0, 2):
293 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
294 break;
295 case IP_VERSION(13, 0, 0):
296 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
297 break;
298 case IP_VERSION(13, 0, 7):
299 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
300 break;
301 case IP_VERSION(13, 0, 1):
302 case IP_VERSION(13, 0, 3):
303 case IP_VERSION(13, 0, 8):
304 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
305 break;
306 case IP_VERSION(13, 0, 4):
307 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
308 break;
309 case IP_VERSION(13, 0, 5):
310 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
311 break;
312 default:
313 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
314 adev->ip_versions[MP1_HWIP][0]);
315 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
316 break;
317 }
318
319 /* only for dGPU w/ SMU13*/
320 if (adev->pm.fw)
321 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
322 smu_program, smu_version, smu_major, smu_minor, smu_debug);
323
324 /*
325 * 1. if_version mismatch is not critical as our fw is designed
326 * to be backward compatible.
327 * 2. New fw usually brings some optimizations. But that's visible
328 * only on the paired driver.
329 * Considering above, we just leave user a warning message instead
330 * of halt driver loading.
331 */
332 if (if_version != smu->smc_driver_if_version) {
333 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
334 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
335 smu->smc_driver_if_version, if_version,
336 smu_program, smu_version, smu_major, smu_minor, smu_debug);
337 dev_warn(adev->dev, "SMU driver if version not matched\n");
338 }
339
340 return ret;
341 }
342
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)343 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
344 {
345 struct amdgpu_device *adev = smu->adev;
346 uint32_t ppt_offset_bytes;
347 const struct smc_firmware_header_v2_0 *v2;
348
349 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
350
351 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
352 *size = le32_to_cpu(v2->ppt_size_bytes);
353 *table = (uint8_t *)v2 + ppt_offset_bytes;
354
355 return 0;
356 }
357
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)358 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
359 uint32_t *size, uint32_t pptable_id)
360 {
361 struct amdgpu_device *adev = smu->adev;
362 const struct smc_firmware_header_v2_1 *v2_1;
363 struct smc_soft_pptable_entry *entries;
364 uint32_t pptable_count = 0;
365 int i = 0;
366
367 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
368 entries = (struct smc_soft_pptable_entry *)
369 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
370 pptable_count = le32_to_cpu(v2_1->pptable_count);
371 for (i = 0; i < pptable_count; i++) {
372 if (le32_to_cpu(entries[i].id) == pptable_id) {
373 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
374 *size = le32_to_cpu(entries[i].ppt_size_bytes);
375 break;
376 }
377 }
378
379 if (i == pptable_count)
380 return -EINVAL;
381
382 return 0;
383 }
384
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)385 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
386 {
387 struct amdgpu_device *adev = smu->adev;
388 uint16_t atom_table_size;
389 uint8_t frev, crev;
390 int ret, index;
391
392 dev_info(adev->dev, "use vbios provided pptable\n");
393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
394 powerplayinfo);
395
396 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
397 (uint8_t **)table);
398 if (ret)
399 return ret;
400
401 if (size)
402 *size = atom_table_size;
403
404 return 0;
405 }
406
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)407 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
408 uint32_t pptable_id)
409 {
410 const struct smc_firmware_header_v1_0 *hdr;
411 struct amdgpu_device *adev = smu->adev;
412 uint16_t version_major, version_minor;
413 int ret;
414
415 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
416 if (!hdr)
417 return -EINVAL;
418
419 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
420
421 version_major = le16_to_cpu(hdr->header.header_version_major);
422 version_minor = le16_to_cpu(hdr->header.header_version_minor);
423 if (version_major != 2) {
424 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
425 version_major, version_minor);
426 return -EINVAL;
427 }
428
429 switch (version_minor) {
430 case 0:
431 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
432 break;
433 case 1:
434 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
435 break;
436 default:
437 ret = -EINVAL;
438 break;
439 }
440
441 return ret;
442 }
443
smu_v13_0_setup_pptable(struct smu_context * smu)444 int smu_v13_0_setup_pptable(struct smu_context *smu)
445 {
446 struct amdgpu_device *adev = smu->adev;
447 uint32_t size = 0, pptable_id = 0;
448 void *table;
449 int ret = 0;
450
451 /* override pptable_id from driver parameter */
452 if (amdgpu_smu_pptable_id >= 0) {
453 pptable_id = amdgpu_smu_pptable_id;
454 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
455 } else {
456 pptable_id = smu->smu_table.boot_values.pp_table_id;
457
458 /*
459 * Temporary solution for SMU V13.0.0 with SCPM disabled:
460 * - use 3664 or 3683 on request
461 * - use 3664 when pptable_id is 0
462 * TODO: drop these when the pptable carried in vbios is ready.
463 */
464 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
465 switch (pptable_id) {
466 case 0:
467 pptable_id = 3664;
468 break;
469 case 3664:
470 case 3683:
471 break;
472 default:
473 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
474 return -EINVAL;
475 }
476 }
477 }
478
479 /* force using vbios pptable in sriov mode */
480 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
481 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
482 else
483 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
484
485 if (ret)
486 return ret;
487
488 if (!smu->smu_table.power_play_table)
489 smu->smu_table.power_play_table = table;
490 if (!smu->smu_table.power_play_table_size)
491 smu->smu_table.power_play_table_size = size;
492
493 return 0;
494 }
495
smu_v13_0_init_smc_tables(struct smu_context * smu)496 int smu_v13_0_init_smc_tables(struct smu_context *smu)
497 {
498 struct smu_table_context *smu_table = &smu->smu_table;
499 struct smu_table *tables = smu_table->tables;
500 int ret = 0;
501
502 smu_table->driver_pptable =
503 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
504 if (!smu_table->driver_pptable) {
505 ret = -ENOMEM;
506 goto err0_out;
507 }
508
509 smu_table->max_sustainable_clocks =
510 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
511 if (!smu_table->max_sustainable_clocks) {
512 ret = -ENOMEM;
513 goto err1_out;
514 }
515
516 /* Aldebaran does not support OVERDRIVE */
517 if (tables[SMU_TABLE_OVERDRIVE].size) {
518 smu_table->overdrive_table =
519 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
520 if (!smu_table->overdrive_table) {
521 ret = -ENOMEM;
522 goto err2_out;
523 }
524
525 smu_table->boot_overdrive_table =
526 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
527 if (!smu_table->boot_overdrive_table) {
528 ret = -ENOMEM;
529 goto err3_out;
530 }
531 }
532
533 smu_table->combo_pptable =
534 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
535 if (!smu_table->combo_pptable) {
536 ret = -ENOMEM;
537 goto err4_out;
538 }
539
540 return 0;
541
542 err4_out:
543 kfree(smu_table->boot_overdrive_table);
544 err3_out:
545 kfree(smu_table->overdrive_table);
546 err2_out:
547 kfree(smu_table->max_sustainable_clocks);
548 err1_out:
549 kfree(smu_table->driver_pptable);
550 err0_out:
551 return ret;
552 }
553
smu_v13_0_fini_smc_tables(struct smu_context * smu)554 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
555 {
556 struct smu_table_context *smu_table = &smu->smu_table;
557 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
558
559 kfree(smu_table->gpu_metrics_table);
560 kfree(smu_table->combo_pptable);
561 kfree(smu_table->boot_overdrive_table);
562 kfree(smu_table->overdrive_table);
563 kfree(smu_table->max_sustainable_clocks);
564 kfree(smu_table->driver_pptable);
565 smu_table->gpu_metrics_table = NULL;
566 smu_table->combo_pptable = NULL;
567 smu_table->boot_overdrive_table = NULL;
568 smu_table->overdrive_table = NULL;
569 smu_table->max_sustainable_clocks = NULL;
570 smu_table->driver_pptable = NULL;
571 kfree(smu_table->hardcode_pptable);
572 smu_table->hardcode_pptable = NULL;
573
574 kfree(smu_table->ecc_table);
575 kfree(smu_table->metrics_table);
576 kfree(smu_table->watermarks_table);
577 smu_table->ecc_table = NULL;
578 smu_table->metrics_table = NULL;
579 smu_table->watermarks_table = NULL;
580 smu_table->metrics_time = 0;
581
582 kfree(smu_dpm->dpm_context);
583 kfree(smu_dpm->golden_dpm_context);
584 kfree(smu_dpm->dpm_current_power_state);
585 kfree(smu_dpm->dpm_request_power_state);
586 smu_dpm->dpm_context = NULL;
587 smu_dpm->golden_dpm_context = NULL;
588 smu_dpm->dpm_context_size = 0;
589 smu_dpm->dpm_current_power_state = NULL;
590 smu_dpm->dpm_request_power_state = NULL;
591
592 return 0;
593 }
594
smu_v13_0_init_power(struct smu_context * smu)595 int smu_v13_0_init_power(struct smu_context *smu)
596 {
597 struct smu_power_context *smu_power = &smu->smu_power;
598
599 if (smu_power->power_context || smu_power->power_context_size != 0)
600 return -EINVAL;
601
602 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
603 GFP_KERNEL);
604 if (!smu_power->power_context)
605 return -ENOMEM;
606 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
607
608 return 0;
609 }
610
smu_v13_0_fini_power(struct smu_context * smu)611 int smu_v13_0_fini_power(struct smu_context *smu)
612 {
613 struct smu_power_context *smu_power = &smu->smu_power;
614
615 if (!smu_power->power_context || smu_power->power_context_size == 0)
616 return -EINVAL;
617
618 kfree(smu_power->power_context);
619 smu_power->power_context = NULL;
620 smu_power->power_context_size = 0;
621
622 return 0;
623 }
624
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)625 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
626 {
627 int ret, index;
628 uint16_t size;
629 uint8_t frev, crev;
630 struct atom_common_table_header *header;
631 struct atom_firmware_info_v3_4 *v_3_4;
632 struct atom_firmware_info_v3_3 *v_3_3;
633 struct atom_firmware_info_v3_1 *v_3_1;
634 struct atom_smu_info_v3_6 *smu_info_v3_6;
635 struct atom_smu_info_v4_0 *smu_info_v4_0;
636
637 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
638 firmwareinfo);
639
640 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
641 (uint8_t **)&header);
642 if (ret)
643 return ret;
644
645 if (header->format_revision != 3) {
646 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
647 return -EINVAL;
648 }
649
650 switch (header->content_revision) {
651 case 0:
652 case 1:
653 case 2:
654 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
655 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
656 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
657 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
658 smu->smu_table.boot_values.socclk = 0;
659 smu->smu_table.boot_values.dcefclk = 0;
660 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
661 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
662 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
663 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
664 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
665 smu->smu_table.boot_values.pp_table_id = 0;
666 break;
667 case 3:
668 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
669 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
670 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
671 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
672 smu->smu_table.boot_values.socclk = 0;
673 smu->smu_table.boot_values.dcefclk = 0;
674 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
675 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
676 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
677 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
678 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
679 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
680 break;
681 case 4:
682 default:
683 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
684 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
685 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
686 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
687 smu->smu_table.boot_values.socclk = 0;
688 smu->smu_table.boot_values.dcefclk = 0;
689 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
690 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
691 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
692 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
693 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
694 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
695 break;
696 }
697
698 smu->smu_table.boot_values.format_revision = header->format_revision;
699 smu->smu_table.boot_values.content_revision = header->content_revision;
700
701 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
702 smu_info);
703 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
704 (uint8_t **)&header)) {
705
706 if ((frev == 3) && (crev == 6)) {
707 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
708
709 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
710 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
711 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
712 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
713 } else if ((frev == 3) && (crev == 1)) {
714 return 0;
715 } else if ((frev == 4) && (crev == 0)) {
716 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
717
718 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
719 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
720 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
721 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
722 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
723 } else {
724 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
725 (uint32_t)frev, (uint32_t)crev);
726 }
727 }
728
729 return 0;
730 }
731
732
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)733 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
734 {
735 struct smu_table_context *smu_table = &smu->smu_table;
736 struct smu_table *memory_pool = &smu_table->memory_pool;
737 int ret = 0;
738 uint64_t address;
739 uint32_t address_low, address_high;
740
741 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
742 return ret;
743
744 address = memory_pool->mc_address;
745 address_high = (uint32_t)upper_32_bits(address);
746 address_low = (uint32_t)lower_32_bits(address);
747
748 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
749 address_high, NULL);
750 if (ret)
751 return ret;
752 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
753 address_low, NULL);
754 if (ret)
755 return ret;
756 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
757 (uint32_t)memory_pool->size, NULL);
758 if (ret)
759 return ret;
760
761 return ret;
762 }
763
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)764 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
765 {
766 int ret;
767
768 ret = smu_cmn_send_smc_msg_with_param(smu,
769 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
770 if (ret)
771 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
772
773 return ret;
774 }
775
smu_v13_0_set_driver_table_location(struct smu_context * smu)776 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
777 {
778 struct smu_table *driver_table = &smu->smu_table.driver_table;
779 int ret = 0;
780
781 if (driver_table->mc_address) {
782 ret = smu_cmn_send_smc_msg_with_param(smu,
783 SMU_MSG_SetDriverDramAddrHigh,
784 upper_32_bits(driver_table->mc_address),
785 NULL);
786 if (!ret)
787 ret = smu_cmn_send_smc_msg_with_param(smu,
788 SMU_MSG_SetDriverDramAddrLow,
789 lower_32_bits(driver_table->mc_address),
790 NULL);
791 }
792
793 return ret;
794 }
795
smu_v13_0_set_tool_table_location(struct smu_context * smu)796 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
797 {
798 int ret = 0;
799 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
800
801 if (tool_table->mc_address) {
802 ret = smu_cmn_send_smc_msg_with_param(smu,
803 SMU_MSG_SetToolsDramAddrHigh,
804 upper_32_bits(tool_table->mc_address),
805 NULL);
806 if (!ret)
807 ret = smu_cmn_send_smc_msg_with_param(smu,
808 SMU_MSG_SetToolsDramAddrLow,
809 lower_32_bits(tool_table->mc_address),
810 NULL);
811 }
812
813 return ret;
814 }
815
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)816 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
817 {
818 int ret = 0;
819
820 if (!smu->pm_enabled)
821 return ret;
822
823 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
824
825 return ret;
826 }
827
smu_v13_0_set_allowed_mask(struct smu_context * smu)828 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
829 {
830 struct smu_feature *feature = &smu->smu_feature;
831 int ret = 0;
832 uint32_t feature_mask[2];
833
834 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
835 feature->feature_num < 64)
836 return -EINVAL;
837
838 bitmap_to_arr32(feature_mask, feature->allowed, 64);
839
840 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
841 feature_mask[1], NULL);
842 if (ret)
843 return ret;
844
845 return smu_cmn_send_smc_msg_with_param(smu,
846 SMU_MSG_SetAllowedFeaturesMaskLow,
847 feature_mask[0],
848 NULL);
849 }
850
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)851 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
852 {
853 int ret = 0;
854 struct amdgpu_device *adev = smu->adev;
855
856 switch (adev->ip_versions[MP1_HWIP][0]) {
857 case IP_VERSION(13, 0, 0):
858 case IP_VERSION(13, 0, 1):
859 case IP_VERSION(13, 0, 3):
860 case IP_VERSION(13, 0, 4):
861 case IP_VERSION(13, 0, 5):
862 case IP_VERSION(13, 0, 7):
863 case IP_VERSION(13, 0, 8):
864 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
865 return 0;
866 if (enable)
867 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
868 else
869 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
870 break;
871 default:
872 break;
873 }
874
875 return ret;
876 }
877
smu_v13_0_system_features_control(struct smu_context * smu,bool en)878 int smu_v13_0_system_features_control(struct smu_context *smu,
879 bool en)
880 {
881 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
882 SMU_MSG_DisableAllSmuFeatures), NULL);
883 }
884
smu_v13_0_notify_display_change(struct smu_context * smu)885 int smu_v13_0_notify_display_change(struct smu_context *smu)
886 {
887 int ret = 0;
888
889 if (!smu->pm_enabled)
890 return ret;
891
892 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
893 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
894 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
895
896 return ret;
897 }
898
899 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)900 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
901 enum smu_clk_type clock_select)
902 {
903 int ret = 0;
904 int clk_id;
905
906 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
907 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
908 return 0;
909
910 clk_id = smu_cmn_to_asic_specific_index(smu,
911 CMN2ASIC_MAPPING_CLK,
912 clock_select);
913 if (clk_id < 0)
914 return -EINVAL;
915
916 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
917 clk_id << 16, clock);
918 if (ret) {
919 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
920 return ret;
921 }
922
923 if (*clock != 0)
924 return 0;
925
926 /* if DC limit is zero, return AC limit */
927 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
928 clk_id << 16, clock);
929 if (ret) {
930 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
931 return ret;
932 }
933
934 return 0;
935 }
936
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)937 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
938 {
939 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
940 smu->smu_table.max_sustainable_clocks;
941 int ret = 0;
942
943 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
944 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
945 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
946 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
947 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
948 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
949
950 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
951 ret = smu_v13_0_get_max_sustainable_clock(smu,
952 &(max_sustainable_clocks->uclock),
953 SMU_UCLK);
954 if (ret) {
955 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
956 __func__);
957 return ret;
958 }
959 }
960
961 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
962 ret = smu_v13_0_get_max_sustainable_clock(smu,
963 &(max_sustainable_clocks->soc_clock),
964 SMU_SOCCLK);
965 if (ret) {
966 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
967 __func__);
968 return ret;
969 }
970 }
971
972 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
973 ret = smu_v13_0_get_max_sustainable_clock(smu,
974 &(max_sustainable_clocks->dcef_clock),
975 SMU_DCEFCLK);
976 if (ret) {
977 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
978 __func__);
979 return ret;
980 }
981
982 ret = smu_v13_0_get_max_sustainable_clock(smu,
983 &(max_sustainable_clocks->display_clock),
984 SMU_DISPCLK);
985 if (ret) {
986 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
987 __func__);
988 return ret;
989 }
990 ret = smu_v13_0_get_max_sustainable_clock(smu,
991 &(max_sustainable_clocks->phy_clock),
992 SMU_PHYCLK);
993 if (ret) {
994 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
995 __func__);
996 return ret;
997 }
998 ret = smu_v13_0_get_max_sustainable_clock(smu,
999 &(max_sustainable_clocks->pixel_clock),
1000 SMU_PIXCLK);
1001 if (ret) {
1002 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1003 __func__);
1004 return ret;
1005 }
1006 }
1007
1008 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1009 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1010
1011 return 0;
1012 }
1013
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)1014 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1015 uint32_t *power_limit)
1016 {
1017 int power_src;
1018 int ret = 0;
1019
1020 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1021 return -EINVAL;
1022
1023 power_src = smu_cmn_to_asic_specific_index(smu,
1024 CMN2ASIC_MAPPING_PWR,
1025 smu->adev->pm.ac_power ?
1026 SMU_POWER_SOURCE_AC :
1027 SMU_POWER_SOURCE_DC);
1028 if (power_src < 0)
1029 return -EINVAL;
1030
1031 ret = smu_cmn_send_smc_msg_with_param(smu,
1032 SMU_MSG_GetPptLimit,
1033 power_src << 16,
1034 power_limit);
1035 if (ret)
1036 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1037
1038 return ret;
1039 }
1040
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1041 int smu_v13_0_set_power_limit(struct smu_context *smu,
1042 enum smu_ppt_limit_type limit_type,
1043 uint32_t limit)
1044 {
1045 int ret = 0;
1046
1047 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1048 return -EINVAL;
1049
1050 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1051 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1052 return -EOPNOTSUPP;
1053 }
1054
1055 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1056 if (ret) {
1057 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1058 return ret;
1059 }
1060
1061 smu->current_power_limit = limit;
1062
1063 return 0;
1064 }
1065
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1066 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1067 {
1068 if (smu->smu_table.thermal_controller_type)
1069 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1070
1071 return 0;
1072 }
1073
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1074 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1075 {
1076 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1077 }
1078
convert_to_vddc(uint8_t vid)1079 static uint16_t convert_to_vddc(uint8_t vid)
1080 {
1081 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1082 }
1083
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1084 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1085 {
1086 struct amdgpu_device *adev = smu->adev;
1087 uint32_t vdd = 0, val_vid = 0;
1088
1089 if (!value)
1090 return -EINVAL;
1091 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1092 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1093 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1094
1095 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1096
1097 *value = vdd;
1098
1099 return 0;
1100
1101 }
1102
1103 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1104 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1105 struct pp_display_clock_request
1106 *clock_req)
1107 {
1108 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1109 int ret = 0;
1110 enum smu_clk_type clk_select = 0;
1111 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1112
1113 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1114 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1115 switch (clk_type) {
1116 case amd_pp_dcef_clock:
1117 clk_select = SMU_DCEFCLK;
1118 break;
1119 case amd_pp_disp_clock:
1120 clk_select = SMU_DISPCLK;
1121 break;
1122 case amd_pp_pixel_clock:
1123 clk_select = SMU_PIXCLK;
1124 break;
1125 case amd_pp_phy_clock:
1126 clk_select = SMU_PHYCLK;
1127 break;
1128 case amd_pp_mem_clock:
1129 clk_select = SMU_UCLK;
1130 break;
1131 default:
1132 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1133 ret = -EINVAL;
1134 break;
1135 }
1136
1137 if (ret)
1138 goto failed;
1139
1140 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1141 return 0;
1142
1143 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1144
1145 if(clk_select == SMU_UCLK)
1146 smu->hard_min_uclk_req_from_dal = clk_freq;
1147 }
1148
1149 failed:
1150 return ret;
1151 }
1152
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1153 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1154 {
1155 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1156 return AMD_FAN_CTRL_MANUAL;
1157 else
1158 return AMD_FAN_CTRL_AUTO;
1159 }
1160
1161 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1162 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1163 {
1164 int ret = 0;
1165
1166 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1167 return 0;
1168
1169 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1170 if (ret)
1171 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1172 __func__, (auto_fan_control ? "Start" : "Stop"));
1173
1174 return ret;
1175 }
1176
1177 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1178 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1179 {
1180 struct amdgpu_device *adev = smu->adev;
1181
1182 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1183 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1184 CG_FDO_CTRL2, TMIN, 0));
1185 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1186 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1187 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1188
1189 return 0;
1190 }
1191
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1192 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1193 uint32_t speed)
1194 {
1195 struct amdgpu_device *adev = smu->adev;
1196 uint32_t duty100, duty;
1197 uint64_t tmp64;
1198
1199 speed = MIN(speed, 255);
1200
1201 if (smu_v13_0_auto_fan_control(smu, 0))
1202 return -EINVAL;
1203
1204 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1205 CG_FDO_CTRL1, FMAX_DUTY100);
1206 if (!duty100)
1207 return -EINVAL;
1208
1209 tmp64 = (uint64_t)speed * duty100;
1210 do_div(tmp64, 255);
1211 duty = (uint32_t)tmp64;
1212
1213 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1214 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1215 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1216
1217 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1218 }
1219
1220 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1221 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1222 uint32_t mode)
1223 {
1224 int ret = 0;
1225
1226 switch (mode) {
1227 case AMD_FAN_CTRL_NONE:
1228 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1229 break;
1230 case AMD_FAN_CTRL_MANUAL:
1231 ret = smu_v13_0_auto_fan_control(smu, 0);
1232 break;
1233 case AMD_FAN_CTRL_AUTO:
1234 ret = smu_v13_0_auto_fan_control(smu, 1);
1235 break;
1236 default:
1237 break;
1238 }
1239
1240 if (ret) {
1241 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1242 return -EINVAL;
1243 }
1244
1245 return ret;
1246 }
1247
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1248 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1249 uint32_t speed)
1250 {
1251 struct amdgpu_device *adev = smu->adev;
1252 uint32_t tach_period, crystal_clock_freq;
1253 int ret;
1254
1255 if (!speed)
1256 return -EINVAL;
1257
1258 ret = smu_v13_0_auto_fan_control(smu, 0);
1259 if (ret)
1260 return ret;
1261
1262 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1263 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1264 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1265 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1266 CG_TACH_CTRL, TARGET_PERIOD,
1267 tach_period));
1268
1269 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1270 }
1271
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1272 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1273 uint32_t pstate)
1274 {
1275 int ret = 0;
1276 ret = smu_cmn_send_smc_msg_with_param(smu,
1277 SMU_MSG_SetXgmiMode,
1278 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1279 NULL);
1280 return ret;
1281 }
1282
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1283 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1284 struct amdgpu_irq_src *source,
1285 unsigned tyep,
1286 enum amdgpu_interrupt_state state)
1287 {
1288 struct smu_context *smu = adev->powerplay.pp_handle;
1289 uint32_t low, high;
1290 uint32_t val = 0;
1291
1292 switch (state) {
1293 case AMDGPU_IRQ_STATE_DISABLE:
1294 /* For THM irqs */
1295 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1296 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1297 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1298 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1299
1300 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1301
1302 /* For MP1 SW irqs */
1303 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1304 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1305 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1306
1307 break;
1308 case AMDGPU_IRQ_STATE_ENABLE:
1309 /* For THM irqs */
1310 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1311 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1312 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1313 smu->thermal_range.software_shutdown_temp);
1314
1315 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1316 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1317 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1318 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1319 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1320 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1321 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1322 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1323 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1324
1325 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1326 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1327 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1328 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1329
1330 /* For MP1 SW irqs */
1331 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1332 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1333 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1334 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1335
1336 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1337 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1338 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1339
1340 break;
1341 default:
1342 break;
1343 }
1344
1345 return 0;
1346 }
1347
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1348 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1349 {
1350 return smu_cmn_send_smc_msg(smu,
1351 SMU_MSG_ReenableAcDcInterrupt,
1352 NULL);
1353 }
1354
1355 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1356 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1357 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1358
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1359 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1360 struct amdgpu_irq_src *source,
1361 struct amdgpu_iv_entry *entry)
1362 {
1363 struct smu_context *smu = adev->powerplay.pp_handle;
1364 uint32_t client_id = entry->client_id;
1365 uint32_t src_id = entry->src_id;
1366 /*
1367 * ctxid is used to distinguish different
1368 * events for SMCToHost interrupt.
1369 */
1370 uint32_t ctxid = entry->src_data[0];
1371 uint32_t data;
1372
1373 if (client_id == SOC15_IH_CLIENTID_THM) {
1374 switch (src_id) {
1375 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1376 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1377 /*
1378 * SW CTF just occurred.
1379 * Try to do a graceful shutdown to prevent further damage.
1380 */
1381 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1382 orderly_poweroff(true);
1383 break;
1384 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1385 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1386 break;
1387 default:
1388 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1389 src_id);
1390 break;
1391 }
1392 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1393 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1394 /*
1395 * HW CTF just occurred. Shutdown to prevent further damage.
1396 */
1397 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1398 orderly_poweroff(true);
1399 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1400 if (src_id == 0xfe) {
1401 /* ACK SMUToHost interrupt */
1402 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1403 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1404 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1405
1406 switch (ctxid) {
1407 case 0x3:
1408 dev_dbg(adev->dev, "Switched to AC mode!\n");
1409 smu_v13_0_ack_ac_dc_interrupt(smu);
1410 break;
1411 case 0x4:
1412 dev_dbg(adev->dev, "Switched to DC mode!\n");
1413 smu_v13_0_ack_ac_dc_interrupt(smu);
1414 break;
1415 case 0x7:
1416 /*
1417 * Increment the throttle interrupt counter
1418 */
1419 atomic64_inc(&smu->throttle_int_counter);
1420
1421 if (!atomic_read(&adev->throttling_logging_enabled))
1422 return 0;
1423
1424 if (__ratelimit(&adev->throttling_logging_rs))
1425 schedule_work(&smu->throttling_logging_work);
1426
1427 break;
1428 }
1429 }
1430 }
1431
1432 return 0;
1433 }
1434
1435 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1436 {
1437 .set = smu_v13_0_set_irq_state,
1438 .process = smu_v13_0_irq_process,
1439 };
1440
smu_v13_0_register_irq_handler(struct smu_context * smu)1441 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1442 {
1443 struct amdgpu_device *adev = smu->adev;
1444 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1445 int ret = 0;
1446
1447 irq_src->num_types = 1;
1448 irq_src->funcs = &smu_v13_0_irq_funcs;
1449
1450 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1451 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1452 irq_src);
1453 if (ret)
1454 return ret;
1455
1456 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1457 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1458 irq_src);
1459 if (ret)
1460 return ret;
1461
1462 /* Register CTF(GPIO_19) interrupt */
1463 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1464 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1465 irq_src);
1466 if (ret)
1467 return ret;
1468
1469 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1470 0xfe,
1471 irq_src);
1472 if (ret)
1473 return ret;
1474
1475 return ret;
1476 }
1477
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1478 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1479 struct pp_smu_nv_clock_table *max_clocks)
1480 {
1481 struct smu_table_context *table_context = &smu->smu_table;
1482 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1483
1484 if (!max_clocks || !table_context->max_sustainable_clocks)
1485 return -EINVAL;
1486
1487 sustainable_clocks = table_context->max_sustainable_clocks;
1488
1489 max_clocks->dcfClockInKhz =
1490 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1491 max_clocks->displayClockInKhz =
1492 (unsigned int) sustainable_clocks->display_clock * 1000;
1493 max_clocks->phyClockInKhz =
1494 (unsigned int) sustainable_clocks->phy_clock * 1000;
1495 max_clocks->pixelClockInKhz =
1496 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1497 max_clocks->uClockInKhz =
1498 (unsigned int) sustainable_clocks->uclock * 1000;
1499 max_clocks->socClockInKhz =
1500 (unsigned int) sustainable_clocks->soc_clock * 1000;
1501 max_clocks->dscClockInKhz = 0;
1502 max_clocks->dppClockInKhz = 0;
1503 max_clocks->fabricClockInKhz = 0;
1504
1505 return 0;
1506 }
1507
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1508 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1509 {
1510 int ret = 0;
1511
1512 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1513
1514 return ret;
1515 }
1516
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1517 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1518 uint64_t event_arg)
1519 {
1520 int ret = 0;
1521
1522 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1523 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1524
1525 return ret;
1526 }
1527
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1528 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1529 uint64_t event_arg)
1530 {
1531 int ret = -EINVAL;
1532
1533 switch (event) {
1534 case SMU_EVENT_RESET_COMPLETE:
1535 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1536 break;
1537 default:
1538 break;
1539 }
1540
1541 return ret;
1542 }
1543
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1544 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1545 uint32_t *min, uint32_t *max)
1546 {
1547 int ret = 0, clk_id = 0;
1548 uint32_t param = 0;
1549 uint32_t clock_limit;
1550
1551 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1552 switch (clk_type) {
1553 case SMU_MCLK:
1554 case SMU_UCLK:
1555 clock_limit = smu->smu_table.boot_values.uclk;
1556 break;
1557 case SMU_GFXCLK:
1558 case SMU_SCLK:
1559 clock_limit = smu->smu_table.boot_values.gfxclk;
1560 break;
1561 case SMU_SOCCLK:
1562 clock_limit = smu->smu_table.boot_values.socclk;
1563 break;
1564 default:
1565 clock_limit = 0;
1566 break;
1567 }
1568
1569 /* clock in Mhz unit */
1570 if (min)
1571 *min = clock_limit / 100;
1572 if (max)
1573 *max = clock_limit / 100;
1574
1575 return 0;
1576 }
1577
1578 clk_id = smu_cmn_to_asic_specific_index(smu,
1579 CMN2ASIC_MAPPING_CLK,
1580 clk_type);
1581 if (clk_id < 0) {
1582 ret = -EINVAL;
1583 goto failed;
1584 }
1585 param = (clk_id & 0xffff) << 16;
1586
1587 if (max) {
1588 if (smu->adev->pm.ac_power)
1589 ret = smu_cmn_send_smc_msg_with_param(smu,
1590 SMU_MSG_GetMaxDpmFreq,
1591 param,
1592 max);
1593 else
1594 ret = smu_cmn_send_smc_msg_with_param(smu,
1595 SMU_MSG_GetDcModeMaxDpmFreq,
1596 param,
1597 max);
1598 if (ret)
1599 goto failed;
1600 }
1601
1602 if (min) {
1603 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1604 if (ret)
1605 goto failed;
1606 }
1607
1608 failed:
1609 return ret;
1610 }
1611
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1612 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1613 enum smu_clk_type clk_type,
1614 uint32_t min,
1615 uint32_t max)
1616 {
1617 int ret = 0, clk_id = 0;
1618 uint32_t param;
1619
1620 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1621 return 0;
1622
1623 clk_id = smu_cmn_to_asic_specific_index(smu,
1624 CMN2ASIC_MAPPING_CLK,
1625 clk_type);
1626 if (clk_id < 0)
1627 return clk_id;
1628
1629 if (max > 0) {
1630 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1631 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1632 param, NULL);
1633 if (ret)
1634 goto out;
1635 }
1636
1637 if (min > 0) {
1638 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1639 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1640 param, NULL);
1641 if (ret)
1642 goto out;
1643 }
1644
1645 out:
1646 return ret;
1647 }
1648
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1649 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1650 enum smu_clk_type clk_type,
1651 uint32_t min,
1652 uint32_t max)
1653 {
1654 int ret = 0, clk_id = 0;
1655 uint32_t param;
1656
1657 if (min <= 0 && max <= 0)
1658 return -EINVAL;
1659
1660 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1661 return 0;
1662
1663 clk_id = smu_cmn_to_asic_specific_index(smu,
1664 CMN2ASIC_MAPPING_CLK,
1665 clk_type);
1666 if (clk_id < 0)
1667 return clk_id;
1668
1669 if (max > 0) {
1670 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1671 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1672 param, NULL);
1673 if (ret)
1674 return ret;
1675 }
1676
1677 if (min > 0) {
1678 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1679 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1680 param, NULL);
1681 if (ret)
1682 return ret;
1683 }
1684
1685 return ret;
1686 }
1687
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1688 int smu_v13_0_set_performance_level(struct smu_context *smu,
1689 enum amd_dpm_forced_level level)
1690 {
1691 struct smu_13_0_dpm_context *dpm_context =
1692 smu->smu_dpm.dpm_context;
1693 struct smu_13_0_dpm_table *gfx_table =
1694 &dpm_context->dpm_tables.gfx_table;
1695 struct smu_13_0_dpm_table *mem_table =
1696 &dpm_context->dpm_tables.uclk_table;
1697 struct smu_13_0_dpm_table *soc_table =
1698 &dpm_context->dpm_tables.soc_table;
1699 struct smu_13_0_dpm_table *vclk_table =
1700 &dpm_context->dpm_tables.vclk_table;
1701 struct smu_13_0_dpm_table *dclk_table =
1702 &dpm_context->dpm_tables.dclk_table;
1703 struct smu_13_0_dpm_table *fclk_table =
1704 &dpm_context->dpm_tables.fclk_table;
1705 struct smu_umd_pstate_table *pstate_table =
1706 &smu->pstate_table;
1707 struct amdgpu_device *adev = smu->adev;
1708 uint32_t sclk_min = 0, sclk_max = 0;
1709 uint32_t mclk_min = 0, mclk_max = 0;
1710 uint32_t socclk_min = 0, socclk_max = 0;
1711 uint32_t vclk_min = 0, vclk_max = 0;
1712 uint32_t dclk_min = 0, dclk_max = 0;
1713 uint32_t fclk_min = 0, fclk_max = 0;
1714 int ret = 0, i;
1715
1716 switch (level) {
1717 case AMD_DPM_FORCED_LEVEL_HIGH:
1718 sclk_min = sclk_max = gfx_table->max;
1719 mclk_min = mclk_max = mem_table->max;
1720 socclk_min = socclk_max = soc_table->max;
1721 vclk_min = vclk_max = vclk_table->max;
1722 dclk_min = dclk_max = dclk_table->max;
1723 fclk_min = fclk_max = fclk_table->max;
1724 break;
1725 case AMD_DPM_FORCED_LEVEL_LOW:
1726 sclk_min = sclk_max = gfx_table->min;
1727 mclk_min = mclk_max = mem_table->min;
1728 socclk_min = socclk_max = soc_table->min;
1729 vclk_min = vclk_max = vclk_table->min;
1730 dclk_min = dclk_max = dclk_table->min;
1731 fclk_min = fclk_max = fclk_table->min;
1732 break;
1733 case AMD_DPM_FORCED_LEVEL_AUTO:
1734 sclk_min = gfx_table->min;
1735 sclk_max = gfx_table->max;
1736 mclk_min = mem_table->min;
1737 mclk_max = mem_table->max;
1738 socclk_min = soc_table->min;
1739 socclk_max = soc_table->max;
1740 vclk_min = vclk_table->min;
1741 vclk_max = vclk_table->max;
1742 dclk_min = dclk_table->min;
1743 dclk_max = dclk_table->max;
1744 fclk_min = fclk_table->min;
1745 fclk_max = fclk_table->max;
1746 break;
1747 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1748 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1749 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1750 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1751 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1752 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1753 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1754 break;
1755 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1756 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1757 break;
1758 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1759 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1760 break;
1761 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1762 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1763 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1764 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1765 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1766 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1767 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1768 break;
1769 case AMD_DPM_FORCED_LEVEL_MANUAL:
1770 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1771 return 0;
1772 default:
1773 dev_err(adev->dev, "Invalid performance level %d\n", level);
1774 return -EINVAL;
1775 }
1776
1777 /*
1778 * Unset those settings for SMU 13.0.2. As soft limits settings
1779 * for those clock domains are not supported.
1780 */
1781 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1782 mclk_min = mclk_max = 0;
1783 socclk_min = socclk_max = 0;
1784 vclk_min = vclk_max = 0;
1785 dclk_min = dclk_max = 0;
1786 fclk_min = fclk_max = 0;
1787 }
1788
1789 if (sclk_min && sclk_max) {
1790 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1791 SMU_GFXCLK,
1792 sclk_min,
1793 sclk_max);
1794 if (ret)
1795 return ret;
1796
1797 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1798 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1799 }
1800
1801 if (mclk_min && mclk_max) {
1802 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1803 SMU_MCLK,
1804 mclk_min,
1805 mclk_max);
1806 if (ret)
1807 return ret;
1808
1809 pstate_table->uclk_pstate.curr.min = mclk_min;
1810 pstate_table->uclk_pstate.curr.max = mclk_max;
1811 }
1812
1813 if (socclk_min && socclk_max) {
1814 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1815 SMU_SOCCLK,
1816 socclk_min,
1817 socclk_max);
1818 if (ret)
1819 return ret;
1820
1821 pstate_table->socclk_pstate.curr.min = socclk_min;
1822 pstate_table->socclk_pstate.curr.max = socclk_max;
1823 }
1824
1825 if (vclk_min && vclk_max) {
1826 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1827 if (adev->vcn.harvest_config & (1 << i))
1828 continue;
1829 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1830 i ? SMU_VCLK1 : SMU_VCLK,
1831 vclk_min,
1832 vclk_max);
1833 if (ret)
1834 return ret;
1835 }
1836 pstate_table->vclk_pstate.curr.min = vclk_min;
1837 pstate_table->vclk_pstate.curr.max = vclk_max;
1838 }
1839
1840 if (dclk_min && dclk_max) {
1841 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1842 if (adev->vcn.harvest_config & (1 << i))
1843 continue;
1844 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1845 i ? SMU_DCLK1 : SMU_DCLK,
1846 dclk_min,
1847 dclk_max);
1848 if (ret)
1849 return ret;
1850 }
1851 pstate_table->dclk_pstate.curr.min = dclk_min;
1852 pstate_table->dclk_pstate.curr.max = dclk_max;
1853 }
1854
1855 if (fclk_min && fclk_max) {
1856 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1857 SMU_FCLK,
1858 fclk_min,
1859 fclk_max);
1860 if (ret)
1861 return ret;
1862
1863 pstate_table->fclk_pstate.curr.min = fclk_min;
1864 pstate_table->fclk_pstate.curr.max = fclk_max;
1865 }
1866
1867 return ret;
1868 }
1869
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1870 int smu_v13_0_set_power_source(struct smu_context *smu,
1871 enum smu_power_src_type power_src)
1872 {
1873 int pwr_source;
1874
1875 pwr_source = smu_cmn_to_asic_specific_index(smu,
1876 CMN2ASIC_MAPPING_PWR,
1877 (uint32_t)power_src);
1878 if (pwr_source < 0)
1879 return -EINVAL;
1880
1881 return smu_cmn_send_smc_msg_with_param(smu,
1882 SMU_MSG_NotifyPowerSource,
1883 pwr_source,
1884 NULL);
1885 }
1886
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1887 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1888 enum smu_clk_type clk_type,
1889 uint16_t level,
1890 uint32_t *value)
1891 {
1892 int ret = 0, clk_id = 0;
1893 uint32_t param;
1894
1895 if (!value)
1896 return -EINVAL;
1897
1898 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1899 return 0;
1900
1901 clk_id = smu_cmn_to_asic_specific_index(smu,
1902 CMN2ASIC_MAPPING_CLK,
1903 clk_type);
1904 if (clk_id < 0)
1905 return clk_id;
1906
1907 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1908
1909 ret = smu_cmn_send_smc_msg_with_param(smu,
1910 SMU_MSG_GetDpmFreqByIndex,
1911 param,
1912 value);
1913 if (ret)
1914 return ret;
1915
1916 *value = *value & 0x7fffffff;
1917
1918 return ret;
1919 }
1920
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1921 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1922 enum smu_clk_type clk_type,
1923 uint32_t *value)
1924 {
1925 int ret;
1926
1927 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1928 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1929 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1930 ++(*value);
1931
1932 return ret;
1933 }
1934
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1935 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1936 enum smu_clk_type clk_type,
1937 bool *is_fine_grained_dpm)
1938 {
1939 int ret = 0, clk_id = 0;
1940 uint32_t param;
1941 uint32_t value;
1942
1943 if (!is_fine_grained_dpm)
1944 return -EINVAL;
1945
1946 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1947 return 0;
1948
1949 clk_id = smu_cmn_to_asic_specific_index(smu,
1950 CMN2ASIC_MAPPING_CLK,
1951 clk_type);
1952 if (clk_id < 0)
1953 return clk_id;
1954
1955 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1956
1957 ret = smu_cmn_send_smc_msg_with_param(smu,
1958 SMU_MSG_GetDpmFreqByIndex,
1959 param,
1960 &value);
1961 if (ret)
1962 return ret;
1963
1964 /*
1965 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1966 * now, we un-support it
1967 */
1968 *is_fine_grained_dpm = value & 0x80000000;
1969
1970 return 0;
1971 }
1972
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)1973 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1974 enum smu_clk_type clk_type,
1975 struct smu_13_0_dpm_table *single_dpm_table)
1976 {
1977 int ret = 0;
1978 uint32_t clk;
1979 int i;
1980
1981 ret = smu_v13_0_get_dpm_level_count(smu,
1982 clk_type,
1983 &single_dpm_table->count);
1984 if (ret) {
1985 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1986 return ret;
1987 }
1988
1989 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1990 ret = smu_v13_0_get_fine_grained_status(smu,
1991 clk_type,
1992 &single_dpm_table->is_fine_grained);
1993 if (ret) {
1994 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1995 return ret;
1996 }
1997 }
1998
1999 for (i = 0; i < single_dpm_table->count; i++) {
2000 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2001 clk_type,
2002 i,
2003 &clk);
2004 if (ret) {
2005 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2006 return ret;
2007 }
2008
2009 single_dpm_table->dpm_levels[i].value = clk;
2010 single_dpm_table->dpm_levels[i].enabled = true;
2011
2012 if (i == 0)
2013 single_dpm_table->min = clk;
2014 else if (i == single_dpm_table->count - 1)
2015 single_dpm_table->max = clk;
2016 }
2017
2018 return 0;
2019 }
2020
smu_v13_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)2021 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2022 enum smu_clk_type clk_type,
2023 uint32_t *min_value,
2024 uint32_t *max_value)
2025 {
2026 uint32_t level_count = 0;
2027 int ret = 0;
2028
2029 if (!min_value && !max_value)
2030 return -EINVAL;
2031
2032 if (min_value) {
2033 /* by default, level 0 clock value as min value */
2034 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2035 clk_type,
2036 0,
2037 min_value);
2038 if (ret)
2039 return ret;
2040 }
2041
2042 if (max_value) {
2043 ret = smu_v13_0_get_dpm_level_count(smu,
2044 clk_type,
2045 &level_count);
2046 if (ret)
2047 return ret;
2048
2049 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2050 clk_type,
2051 level_count - 1,
2052 max_value);
2053 if (ret)
2054 return ret;
2055 }
2056
2057 return ret;
2058 }
2059
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2060 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2061 {
2062 struct amdgpu_device *adev = smu->adev;
2063
2064 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2065 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2066 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2067 }
2068
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2069 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2070 {
2071 uint32_t width_level;
2072
2073 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2074 if (width_level > LINK_WIDTH_MAX)
2075 width_level = 0;
2076
2077 return link_width[width_level];
2078 }
2079
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2080 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2081 {
2082 struct amdgpu_device *adev = smu->adev;
2083
2084 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2085 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2086 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2087 }
2088
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2089 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2090 {
2091 uint32_t speed_level;
2092
2093 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2094 if (speed_level > LINK_SPEED_MAX)
2095 speed_level = 0;
2096
2097 return link_speed[speed_level];
2098 }
2099
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2100 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2101 bool enable)
2102 {
2103 struct amdgpu_device *adev = smu->adev;
2104 int i, ret = 0;
2105
2106 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2107 if (adev->vcn.harvest_config & (1 << i))
2108 continue;
2109
2110 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2111 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2112 i << 16U, NULL);
2113 if (ret)
2114 return ret;
2115 }
2116
2117 return ret;
2118 }
2119
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2120 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2121 bool enable)
2122 {
2123 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2124 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2125 0, NULL);
2126 }
2127
smu_v13_0_run_btc(struct smu_context * smu)2128 int smu_v13_0_run_btc(struct smu_context *smu)
2129 {
2130 int res;
2131
2132 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2133 if (res)
2134 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2135
2136 return res;
2137 }
2138
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2139 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2140 bool enablement)
2141 {
2142 struct amdgpu_device *adev = smu->adev;
2143 int ret = 0;
2144
2145 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2146 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2147 if (ret) {
2148 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2149 return ret;
2150 }
2151 }
2152
2153 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2154 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2155 if (ret) {
2156 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2157 return ret;
2158 }
2159 }
2160
2161 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2162 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2163 if (ret) {
2164 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2165 return ret;
2166 }
2167 }
2168
2169 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2170 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2171 if (ret) {
2172 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2173 return ret;
2174 }
2175 }
2176
2177 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2178 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2179 if (ret) {
2180 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2181 return ret;
2182 }
2183 }
2184
2185 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2186 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2187 if (ret) {
2188 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2189 return ret;
2190 }
2191 }
2192
2193 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2194 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2195 if (ret) {
2196 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2197 return ret;
2198 }
2199 }
2200
2201 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2202 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2203 if (ret) {
2204 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2205 return ret;
2206 }
2207 }
2208
2209 return ret;
2210 }
2211
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2212 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2213 bool enablement)
2214 {
2215 int ret = 0;
2216
2217 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2218 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2219
2220 return ret;
2221 }
2222
smu_v13_0_baco_is_support(struct smu_context * smu)2223 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2224 {
2225 struct smu_baco_context *smu_baco = &smu->smu_baco;
2226
2227 if (amdgpu_sriov_vf(smu->adev) ||
2228 !smu_baco->platform_support)
2229 return false;
2230
2231 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2232 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2233 return false;
2234
2235 return true;
2236 }
2237
smu_v13_0_baco_get_state(struct smu_context * smu)2238 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2239 {
2240 struct smu_baco_context *smu_baco = &smu->smu_baco;
2241
2242 return smu_baco->state;
2243 }
2244
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2245 int smu_v13_0_baco_set_state(struct smu_context *smu,
2246 enum smu_baco_state state)
2247 {
2248 struct smu_baco_context *smu_baco = &smu->smu_baco;
2249 struct amdgpu_device *adev = smu->adev;
2250 int ret = 0;
2251
2252 if (smu_v13_0_baco_get_state(smu) == state)
2253 return 0;
2254
2255 if (state == SMU_BACO_STATE_ENTER) {
2256 ret = smu_cmn_send_smc_msg_with_param(smu,
2257 SMU_MSG_EnterBaco,
2258 0,
2259 NULL);
2260 } else {
2261 ret = smu_cmn_send_smc_msg(smu,
2262 SMU_MSG_ExitBaco,
2263 NULL);
2264 if (ret)
2265 return ret;
2266
2267 /* clear vbios scratch 6 and 7 for coming asic reinit */
2268 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2269 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2270 }
2271
2272 if (!ret)
2273 smu_baco->state = state;
2274
2275 return ret;
2276 }
2277
smu_v13_0_baco_enter(struct smu_context * smu)2278 int smu_v13_0_baco_enter(struct smu_context *smu)
2279 {
2280 int ret = 0;
2281
2282 ret = smu_v13_0_baco_set_state(smu,
2283 SMU_BACO_STATE_ENTER);
2284 if (ret)
2285 return ret;
2286
2287 msleep(10);
2288
2289 return ret;
2290 }
2291
smu_v13_0_baco_exit(struct smu_context * smu)2292 int smu_v13_0_baco_exit(struct smu_context *smu)
2293 {
2294 return smu_v13_0_baco_set_state(smu,
2295 SMU_BACO_STATE_EXIT);
2296 }
2297
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2298 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2299 enum PP_OD_DPM_TABLE_COMMAND type,
2300 long input[], uint32_t size)
2301 {
2302 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2303 int ret = 0;
2304
2305 /* Only allowed in manual mode */
2306 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2307 return -EINVAL;
2308
2309 switch (type) {
2310 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2311 if (size != 2) {
2312 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2313 return -EINVAL;
2314 }
2315
2316 if (input[0] == 0) {
2317 if (input[1] < smu->gfx_default_hard_min_freq) {
2318 dev_warn(smu->adev->dev,
2319 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2320 input[1], smu->gfx_default_hard_min_freq);
2321 return -EINVAL;
2322 }
2323 smu->gfx_actual_hard_min_freq = input[1];
2324 } else if (input[0] == 1) {
2325 if (input[1] > smu->gfx_default_soft_max_freq) {
2326 dev_warn(smu->adev->dev,
2327 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2328 input[1], smu->gfx_default_soft_max_freq);
2329 return -EINVAL;
2330 }
2331 smu->gfx_actual_soft_max_freq = input[1];
2332 } else {
2333 return -EINVAL;
2334 }
2335 break;
2336 case PP_OD_RESTORE_DEFAULT_TABLE:
2337 if (size != 0) {
2338 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2339 return -EINVAL;
2340 }
2341 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2342 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2343 break;
2344 case PP_OD_COMMIT_DPM_TABLE:
2345 if (size != 0) {
2346 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2347 return -EINVAL;
2348 }
2349 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2350 dev_err(smu->adev->dev,
2351 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2352 smu->gfx_actual_hard_min_freq,
2353 smu->gfx_actual_soft_max_freq);
2354 return -EINVAL;
2355 }
2356
2357 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2358 smu->gfx_actual_hard_min_freq,
2359 NULL);
2360 if (ret) {
2361 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2362 return ret;
2363 }
2364
2365 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2366 smu->gfx_actual_soft_max_freq,
2367 NULL);
2368 if (ret) {
2369 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2370 return ret;
2371 }
2372 break;
2373 default:
2374 return -ENOSYS;
2375 }
2376
2377 return ret;
2378 }
2379
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2380 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2381 {
2382 struct smu_table_context *smu_table = &smu->smu_table;
2383
2384 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2385 smu_table->clocks_table, false);
2386 }
2387