1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "smu_types.h"
25 #define SWSMU_CODE_LAYER_L2
26 
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "smu_v13_0.h"
30 #include "smu13_driver_if_v13_0_4.h"
31 #include "smu_v13_0_4_ppt.h"
32 #include "smu_v13_0_4_ppsmc.h"
33 #include "smu_v13_0_4_pmfw.h"
34 #include "smu_cmn.h"
35 
36 /*
37  * DO NOT use these for err/warn/info/debug messages.
38  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
39  * They are more MGPU friendly.
40  */
41 #undef pr_err
42 #undef pr_warn
43 #undef pr_info
44 #undef pr_debug
45 
46 #define mmMP1_SMN_C2PMSG_66			0x0282
47 #define mmMP1_SMN_C2PMSG_66_BASE_IDX            1
48 
49 #define mmMP1_SMN_C2PMSG_82			0x0292
50 #define mmMP1_SMN_C2PMSG_82_BASE_IDX            1
51 
52 #define mmMP1_SMN_C2PMSG_90			0x029a
53 #define mmMP1_SMN_C2PMSG_90_BASE_IDX		1
54 
55 #define FEATURE_MASK(feature) (1ULL << feature)
56 
57 #define SMC_DPM_FEATURE ( \
58 	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
59 	FEATURE_MASK(FEATURE_VCN_DPM_BIT)	 | \
60 	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	 | \
61 	FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)	 | \
62 	FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)	 | \
63 	FEATURE_MASK(FEATURE_LCLK_DPM_BIT)	 | \
64 	FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)	 | \
65 	FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)	 | \
66 	FEATURE_MASK(FEATURE_ISP_DPM_BIT)	 | \
67 	FEATURE_MASK(FEATURE_IPU_DPM_BIT)	 | \
68 	FEATURE_MASK(FEATURE_GFX_DPM_BIT))
69 
70 static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = {
71 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			1),
72 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetPmfwVersion,		1),
73 	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,		1),
74 	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,			1),
75 	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,		1),
76 	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,			1),
77 	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,			1),
78 	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,		1),
79 	MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,		1),
80 	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,	1),
81 	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,		1),
82 	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,	1),
83 	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,	1),
84 	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,		1),
85 	MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,	1),
86 	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,	1),
87 	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,		1),
88 	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,		1),
89 	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,		1),
90 	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,		1),
91 	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,		1),
92 	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,	1),
93 	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,		1),
94 	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,		1),
95 	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,	1),
96 	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,		1),
97 	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,			1),
98 	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,		1),
99 	MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,	1),
100 	MSG_MAP(EnableGfxImu,                   PPSMC_MSG_EnableGfxImu,			1),
101 	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,		1),
102 	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,		1),
103 };
104 
105 static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = {
106 	FEA_MAP(CCLK_DPM),
107 	FEA_MAP(FAN_CONTROLLER),
108 	FEA_MAP(PPT),
109 	FEA_MAP(TDC),
110 	FEA_MAP(THERMAL),
111 	FEA_MAP(VCN_DPM),
112 	FEA_MAP_REVERSE(FCLK),
113 	FEA_MAP_REVERSE(SOCCLK),
114 	FEA_MAP(LCLK_DPM),
115 	FEA_MAP(SHUBCLK_DPM),
116 	FEA_MAP(DCFCLK_DPM),
117 	FEA_MAP_HALF_REVERSE(GFX),
118 	FEA_MAP(DS_GFXCLK),
119 	FEA_MAP(DS_SOCCLK),
120 	FEA_MAP(DS_LCLK),
121 	FEA_MAP(DS_DCFCLK),
122 	FEA_MAP(DS_FCLK),
123 	FEA_MAP(DS_MP1CLK),
124 	FEA_MAP(DS_MP0CLK),
125 	FEA_MAP(GFX_DEM),
126 	FEA_MAP(PSI),
127 	FEA_MAP(PROCHOT),
128 	FEA_MAP(CPUOFF),
129 	FEA_MAP(STAPM),
130 	FEA_MAP(S0I3),
131 	FEA_MAP(PERF_LIMIT),
132 	FEA_MAP(CORE_DLDO),
133 	FEA_MAP(DS_VCN),
134 	FEA_MAP(CPPC),
135 	FEA_MAP(DF_CSTATES),
136 	FEA_MAP(ATHUB_PG),
137 };
138 
139 static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = {
140 	TAB_MAP_VALID(WATERMARKS),
141 	TAB_MAP_VALID(SMU_METRICS),
142 	TAB_MAP_VALID(CUSTOM_DPM),
143 	TAB_MAP_VALID(DPMCLOCKS),
144 };
145 
smu_v13_0_4_init_smc_tables(struct smu_context * smu)146 static int smu_v13_0_4_init_smc_tables(struct smu_context *smu)
147 {
148 	struct smu_table_context *smu_table = &smu->smu_table;
149 	struct smu_table *tables = smu_table->tables;
150 
151 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
152 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
153 	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
154 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
155 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
156 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
157 
158 	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
159 	if (!smu_table->clocks_table)
160 		goto err0_out;
161 
162 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
163 	if (!smu_table->metrics_table)
164 		goto err1_out;
165 	smu_table->metrics_time = 0;
166 
167 	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
168 	if (!smu_table->watermarks_table)
169 		goto err2_out;
170 
171 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
172 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
173 	if (!smu_table->gpu_metrics_table)
174 		goto err3_out;
175 
176 	return 0;
177 
178 err3_out:
179 	kfree(smu_table->watermarks_table);
180 err2_out:
181 	kfree(smu_table->metrics_table);
182 err1_out:
183 	kfree(smu_table->clocks_table);
184 err0_out:
185 	return -ENOMEM;
186 }
187 
smu_v13_0_4_fini_smc_tables(struct smu_context * smu)188 static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
189 {
190 	struct smu_table_context *smu_table = &smu->smu_table;
191 
192 	kfree(smu_table->clocks_table);
193 	smu_table->clocks_table = NULL;
194 
195 	kfree(smu_table->metrics_table);
196 	smu_table->metrics_table = NULL;
197 
198 	kfree(smu_table->watermarks_table);
199 	smu_table->watermarks_table = NULL;
200 
201 	kfree(smu_table->gpu_metrics_table);
202 	smu_table->gpu_metrics_table = NULL;
203 
204 	return 0;
205 }
206 
smu_v13_0_4_is_dpm_running(struct smu_context * smu)207 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
208 {
209 	int ret = 0;
210 	uint64_t feature_enabled;
211 
212 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
213 
214 	if (ret)
215 		return false;
216 
217 	return !!(feature_enabled & SMC_DPM_FEATURE);
218 }
219 
smu_v13_0_4_system_features_control(struct smu_context * smu,bool en)220 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
221 {
222 	struct amdgpu_device *adev = smu->adev;
223 	int ret = 0;
224 
225 	if (!en && !adev->in_s0ix)
226 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
227 
228 	return ret;
229 }
230 
smu_v13_0_4_get_gpu_metrics(struct smu_context * smu,void ** table)231 static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu,
232 					   void **table)
233 {
234 	struct smu_table_context *smu_table = &smu->smu_table;
235 	struct gpu_metrics_v2_1 *gpu_metrics =
236 		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
237 	SmuMetrics_t metrics;
238 	int ret = 0;
239 
240 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
241 	if (ret)
242 		return ret;
243 
244 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
245 
246 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
247 	gpu_metrics->temperature_soc = metrics.SocTemperature;
248 	memcpy(&gpu_metrics->temperature_core[0],
249 		&metrics.CoreTemperature[0],
250 		sizeof(uint16_t) * 8);
251 	gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
252 
253 	gpu_metrics->average_gfx_activity = metrics.GfxActivity;
254 	gpu_metrics->average_mm_activity = metrics.UvdActivity;
255 
256 	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
257 	gpu_metrics->average_gfx_power = metrics.Power[0];
258 	gpu_metrics->average_soc_power = metrics.Power[1];
259 	memcpy(&gpu_metrics->average_core_power[0],
260 		&metrics.CorePower[0],
261 		sizeof(uint16_t) * 8);
262 
263 	gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
264 	gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
265 	gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
266 	gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
267 	gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
268 	gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
269 
270 	memcpy(&gpu_metrics->current_coreclk[0],
271 		&metrics.CoreFrequency[0],
272 		sizeof(uint16_t) * 8);
273 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
274 
275 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
276 
277 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
278 
279 	*table = (void *)gpu_metrics;
280 
281 	return sizeof(struct gpu_metrics_v2_1);
282 }
283 
smu_v13_0_4_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)284 static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu,
285 					    MetricsMember_t member,
286 					    uint32_t *value)
287 {
288 	struct smu_table_context *smu_table = &smu->smu_table;
289 
290 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
291 	int ret = 0;
292 
293 	ret = smu_cmn_get_metrics_table(smu, NULL, false);
294 	if (ret)
295 		return ret;
296 
297 	switch (member) {
298 	case METRICS_AVERAGE_GFXCLK:
299 		*value = metrics->GfxclkFrequency;
300 		break;
301 	case METRICS_AVERAGE_SOCCLK:
302 		*value = metrics->SocclkFrequency;
303 		break;
304 	case METRICS_AVERAGE_VCLK:
305 		*value = metrics->VclkFrequency;
306 		break;
307 	case METRICS_AVERAGE_DCLK:
308 		*value = metrics->DclkFrequency;
309 		break;
310 	case METRICS_AVERAGE_UCLK:
311 		*value = metrics->MemclkFrequency;
312 		break;
313 	case METRICS_AVERAGE_GFXACTIVITY:
314 		*value = metrics->GfxActivity / 100;
315 		break;
316 	case METRICS_AVERAGE_VCNACTIVITY:
317 		*value = metrics->UvdActivity;
318 		break;
319 	case METRICS_AVERAGE_SOCKETPOWER:
320 		*value = (metrics->CurrentSocketPower << 8) / 1000;
321 		break;
322 	case METRICS_TEMPERATURE_EDGE:
323 		*value = metrics->GfxTemperature / 100 *
324 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
325 		break;
326 	case METRICS_TEMPERATURE_HOTSPOT:
327 		*value = metrics->SocTemperature / 100 *
328 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
329 		break;
330 	case METRICS_THROTTLER_STATUS:
331 		*value = metrics->ThrottlerStatus;
332 		break;
333 	case METRICS_VOLTAGE_VDDGFX:
334 		*value = metrics->Voltage[0];
335 		break;
336 	case METRICS_VOLTAGE_VDDSOC:
337 		*value = metrics->Voltage[1];
338 		break;
339 	case METRICS_SS_APU_SHARE:
340 		/* return the percentage of APU power with respect to APU's power limit.
341 		 * percentage is reported, this isn't boost value. Smartshift power
342 		 * boost/shift is only when the percentage is more than 100.
343 		 */
344 		if (metrics->StapmOpnLimit > 0)
345 			*value =  (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
346 		else
347 			*value = 0;
348 		break;
349 	case METRICS_SS_DGPU_SHARE:
350 		/* return the percentage of dGPU power with respect to dGPU's power limit.
351 		 * percentage is reported, this isn't boost value. Smartshift power
352 		 * boost/shift is only when the percentage is more than 100.
353 		 */
354 		if ((metrics->dGpuPower > 0) &&
355 		    (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
356 			*value = (metrics->dGpuPower * 100) /
357 				 (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
358 		else
359 			*value = 0;
360 		break;
361 	default:
362 		*value = UINT_MAX;
363 		break;
364 	}
365 
366 	return ret;
367 }
368 
smu_v13_0_4_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)369 static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu,
370 					    enum smu_clk_type clk_type,
371 					    uint32_t *value)
372 {
373 	MetricsMember_t member_type;
374 
375 	switch (clk_type) {
376 	case SMU_SOCCLK:
377 		member_type = METRICS_AVERAGE_SOCCLK;
378 		break;
379 	case SMU_VCLK:
380 		member_type = METRICS_AVERAGE_VCLK;
381 		break;
382 	case SMU_DCLK:
383 		member_type = METRICS_AVERAGE_DCLK;
384 		break;
385 	case SMU_MCLK:
386 		member_type = METRICS_AVERAGE_UCLK;
387 		break;
388 	case SMU_FCLK:
389 		return smu_cmn_send_smc_msg_with_param(smu,
390 						       SMU_MSG_GetFclkFrequency,
391 						       0, value);
392 	case SMU_GFXCLK:
393 	case SMU_SCLK:
394 		return smu_cmn_send_smc_msg_with_param(smu,
395 						       SMU_MSG_GetGfxclkFrequency,
396 						       0, value);
397 		break;
398 	default:
399 		return -EINVAL;
400 	}
401 
402 	return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value);
403 }
404 
smu_v13_0_4_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)405 static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu,
406 					     enum smu_clk_type clk_type,
407 					     uint32_t dpm_level,
408 					     uint32_t *freq)
409 {
410 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
411 
412 	if (!clk_table || clk_type >= SMU_CLK_COUNT)
413 		return -EINVAL;
414 
415 	switch (clk_type) {
416 	case SMU_SOCCLK:
417 		if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
418 			return -EINVAL;
419 		*freq = clk_table->SocClocks[dpm_level];
420 		break;
421 	case SMU_VCLK:
422 		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
423 			return -EINVAL;
424 		*freq = clk_table->VClocks[dpm_level];
425 		break;
426 	case SMU_DCLK:
427 		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
428 			return -EINVAL;
429 		*freq = clk_table->DClocks[dpm_level];
430 		break;
431 	case SMU_UCLK:
432 	case SMU_MCLK:
433 		if (dpm_level >= clk_table->NumDfPstatesEnabled)
434 			return -EINVAL;
435 		*freq = clk_table->DfPstateTable[dpm_level].MemClk;
436 		break;
437 	case SMU_FCLK:
438 		if (dpm_level >= clk_table->NumDfPstatesEnabled)
439 			return -EINVAL;
440 		*freq = clk_table->DfPstateTable[dpm_level].FClk;
441 		break;
442 	default:
443 		return -EINVAL;
444 	}
445 
446 	return 0;
447 }
448 
smu_v13_0_4_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)449 static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
450 					   enum smu_clk_type clk_type,
451 					   uint32_t *count)
452 {
453 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
454 
455 	switch (clk_type) {
456 	case SMU_SOCCLK:
457 		*count = clk_table->NumSocClkLevelsEnabled;
458 		break;
459 	case SMU_VCLK:
460 		*count = clk_table->VcnClkLevelsEnabled;
461 		break;
462 	case SMU_DCLK:
463 		*count = clk_table->VcnClkLevelsEnabled;
464 		break;
465 	case SMU_MCLK:
466 		*count = clk_table->NumDfPstatesEnabled;
467 		break;
468 	case SMU_FCLK:
469 		*count = clk_table->NumDfPstatesEnabled;
470 		break;
471 	default:
472 		break;
473 	}
474 
475 	return 0;
476 }
477 
smu_v13_0_4_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)478 static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
479 					enum smu_clk_type clk_type, char *buf)
480 {
481 	int i, size = 0, ret = 0;
482 	uint32_t cur_value = 0, value = 0, count = 0;
483 	uint32_t min, max;
484 
485 	smu_cmn_get_sysfs_buf(&buf, &size);
486 
487 	switch (clk_type) {
488 	case SMU_OD_SCLK:
489 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
490 		size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
491 		(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
492 		size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
493 		(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
494 		break;
495 	case SMU_OD_RANGE:
496 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
497 		size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
498 				      smu->gfx_default_hard_min_freq,
499 				      smu->gfx_default_soft_max_freq);
500 		break;
501 	case SMU_SOCCLK:
502 	case SMU_VCLK:
503 	case SMU_DCLK:
504 	case SMU_MCLK:
505 	case SMU_FCLK:
506 		ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
507 		if (ret)
508 			break;
509 
510 		ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);
511 		if (ret)
512 			break;
513 
514 		for (i = 0; i < count; i++) {
515 			ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, i, &value);
516 			if (ret)
517 				break;
518 
519 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
520 					      cur_value == value ? "*" : "");
521 		}
522 		break;
523 	case SMU_GFXCLK:
524 	case SMU_SCLK:
525 		ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
526 		if (ret)
527 			break;
528 		min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
529 		max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
530 		if (cur_value  == max)
531 			i = 2;
532 		else if (cur_value == min)
533 			i = 0;
534 		else
535 			i = 1;
536 		size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
537 				      i == 0 ? "*" : "");
538 		size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
539 				      i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
540 				      i == 1 ? "*" : "");
541 		size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
542 				      i == 2 ? "*" : "");
543 		break;
544 	default:
545 		break;
546 	}
547 
548 	return size;
549 }
550 
smu_v13_0_4_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)551 static int smu_v13_0_4_read_sensor(struct smu_context *smu,
552 				   enum amd_pp_sensors sensor,
553 				   void *data, uint32_t *size)
554 {
555 	int ret = 0;
556 
557 	if (!data || !size)
558 		return -EINVAL;
559 
560 	switch (sensor) {
561 	case AMDGPU_PP_SENSOR_GPU_LOAD:
562 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
563 						       METRICS_AVERAGE_GFXACTIVITY,
564 						       (uint32_t *)data);
565 		*size = 4;
566 		break;
567 	case AMDGPU_PP_SENSOR_GPU_POWER:
568 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
569 						       METRICS_AVERAGE_SOCKETPOWER,
570 						       (uint32_t *)data);
571 		*size = 4;
572 		break;
573 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
574 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
575 						       METRICS_TEMPERATURE_EDGE,
576 						       (uint32_t *)data);
577 		*size = 4;
578 		break;
579 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
580 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
581 						       METRICS_TEMPERATURE_HOTSPOT,
582 						       (uint32_t *)data);
583 		*size = 4;
584 		break;
585 	case AMDGPU_PP_SENSOR_GFX_MCLK:
586 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
587 						       METRICS_AVERAGE_UCLK,
588 						       (uint32_t *)data);
589 		*(uint32_t *)data *= 100;
590 		*size = 4;
591 		break;
592 	case AMDGPU_PP_SENSOR_GFX_SCLK:
593 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
594 						       METRICS_AVERAGE_GFXCLK,
595 						       (uint32_t *)data);
596 		*(uint32_t *)data *= 100;
597 		*size = 4;
598 		break;
599 	case AMDGPU_PP_SENSOR_VDDGFX:
600 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
601 						       METRICS_VOLTAGE_VDDGFX,
602 						       (uint32_t *)data);
603 		*size = 4;
604 		break;
605 	case AMDGPU_PP_SENSOR_VDDNB:
606 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
607 						       METRICS_VOLTAGE_VDDSOC,
608 						       (uint32_t *)data);
609 		*size = 4;
610 		break;
611 	case AMDGPU_PP_SENSOR_SS_APU_SHARE:
612 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
613 						       METRICS_SS_APU_SHARE,
614 						       (uint32_t *)data);
615 		*size = 4;
616 		break;
617 	case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
618 		ret = smu_v13_0_4_get_smu_metrics_data(smu,
619 						       METRICS_SS_DGPU_SHARE,
620 						       (uint32_t *)data);
621 		*size = 4;
622 		break;
623 	default:
624 		ret = -EOPNOTSUPP;
625 		break;
626 	}
627 
628 	return ret;
629 }
630 
smu_v13_0_4_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)631 static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu,
632 					    struct pp_smu_wm_range_sets *clock_ranges)
633 {
634 	int i;
635 	int ret = 0;
636 	Watermarks_t *table = smu->smu_table.watermarks_table;
637 
638 	if (!table || !clock_ranges)
639 		return -EINVAL;
640 
641 	if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
642 		clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
643 		return -EINVAL;
644 
645 	for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
646 		table->WatermarkRow[WM_DCFCLK][i].MinClock =
647 			clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
648 		table->WatermarkRow[WM_DCFCLK][i].MaxClock =
649 			clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
650 		table->WatermarkRow[WM_DCFCLK][i].MinMclk =
651 			clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
652 		table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
653 			clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
654 
655 		table->WatermarkRow[WM_DCFCLK][i].WmSetting =
656 			clock_ranges->reader_wm_sets[i].wm_inst;
657 	}
658 
659 	for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
660 		table->WatermarkRow[WM_SOCCLK][i].MinClock =
661 			clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
662 		table->WatermarkRow[WM_SOCCLK][i].MaxClock =
663 			clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
664 		table->WatermarkRow[WM_SOCCLK][i].MinMclk =
665 			clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
666 		table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
667 			clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
668 
669 		table->WatermarkRow[WM_SOCCLK][i].WmSetting =
670 			clock_ranges->writer_wm_sets[i].wm_inst;
671 	}
672 
673 	smu->watermarks_bitmap |= WATERMARKS_EXIST;
674 
675 	/* pass data to smu controller */
676 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
677 	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
678 		ret = smu_cmn_write_watermarks_table(smu);
679 		if (ret) {
680 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
681 			return ret;
682 		}
683 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
684 	}
685 
686 	return 0;
687 }
688 
smu_v13_0_4_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)689 static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
690 					   enum smu_clk_type clk_type)
691 {
692 	enum smu_feature_mask feature_id = 0;
693 
694 	switch (clk_type) {
695 	case SMU_MCLK:
696 	case SMU_UCLK:
697 	case SMU_FCLK:
698 		feature_id = SMU_FEATURE_DPM_FCLK_BIT;
699 		break;
700 	case SMU_GFXCLK:
701 	case SMU_SCLK:
702 		feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
703 		break;
704 	case SMU_SOCCLK:
705 		feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
706 		break;
707 	case SMU_VCLK:
708 	case SMU_DCLK:
709 		feature_id = SMU_FEATURE_VCN_DPM_BIT;
710 		break;
711 	default:
712 		return true;
713 	}
714 
715 	return smu_cmn_feature_is_enabled(smu, feature_id);
716 }
717 
smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)718 static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
719 					     enum smu_clk_type clk_type,
720 					     uint32_t *min,
721 					     uint32_t *max)
722 {
723 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
724 	uint32_t clock_limit;
725 	uint32_t max_dpm_level, min_dpm_level;
726 	int ret = 0;
727 
728 	if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
729 		switch (clk_type) {
730 		case SMU_MCLK:
731 		case SMU_UCLK:
732 			clock_limit = smu->smu_table.boot_values.uclk;
733 			break;
734 		case SMU_FCLK:
735 			clock_limit = smu->smu_table.boot_values.fclk;
736 			break;
737 		case SMU_GFXCLK:
738 		case SMU_SCLK:
739 			clock_limit = smu->smu_table.boot_values.gfxclk;
740 			break;
741 		case SMU_SOCCLK:
742 			clock_limit = smu->smu_table.boot_values.socclk;
743 			break;
744 		case SMU_VCLK:
745 			clock_limit = smu->smu_table.boot_values.vclk;
746 			break;
747 		case SMU_DCLK:
748 			clock_limit = smu->smu_table.boot_values.dclk;
749 			break;
750 		default:
751 			clock_limit = 0;
752 			break;
753 		}
754 
755 		/* clock in Mhz unit */
756 		if (min)
757 			*min = clock_limit / 100;
758 		if (max)
759 			*max = clock_limit / 100;
760 
761 		return 0;
762 	}
763 
764 	if (max) {
765 		switch (clk_type) {
766 		case SMU_GFXCLK:
767 		case SMU_SCLK:
768 			*max = clk_table->MaxGfxClk;
769 			break;
770 		case SMU_MCLK:
771 		case SMU_UCLK:
772 		case SMU_FCLK:
773 			max_dpm_level = 0;
774 			break;
775 		case SMU_SOCCLK:
776 			max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
777 			break;
778 		case SMU_VCLK:
779 		case SMU_DCLK:
780 			max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
781 			break;
782 		default:
783 			return -EINVAL;
784 		}
785 
786 		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
787 			ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
788 								max_dpm_level,
789 								max);
790 			if (ret)
791 				return ret;
792 		}
793 	}
794 
795 	if (min) {
796 		switch (clk_type) {
797 		case SMU_GFXCLK:
798 		case SMU_SCLK:
799 			*min = clk_table->MinGfxClk;
800 			break;
801 		case SMU_MCLK:
802 		case SMU_UCLK:
803 		case SMU_FCLK:
804 			min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
805 			break;
806 		case SMU_SOCCLK:
807 			min_dpm_level = 0;
808 			break;
809 		case SMU_VCLK:
810 		case SMU_DCLK:
811 			min_dpm_level = 0;
812 			break;
813 		default:
814 			return -EINVAL;
815 		}
816 
817 		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
818 			ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
819 								min_dpm_level,
820 								min);
821 		}
822 	}
823 
824 	return ret;
825 }
826 
smu_v13_0_4_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)827 static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
828 						   enum smu_clk_type clk_type,
829 						   uint32_t min,
830 						   uint32_t max)
831 {
832 	enum smu_message_type msg_set_min, msg_set_max;
833 	int ret = 0;
834 
835 	if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
836 		return -EINVAL;
837 
838 	switch (clk_type) {
839 	case SMU_GFXCLK:
840 	case SMU_SCLK:
841 		msg_set_min = SMU_MSG_SetHardMinGfxClk;
842 		msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
843 		break;
844 	case SMU_FCLK:
845 		msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
846 		msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
847 		break;
848 	case SMU_SOCCLK:
849 		msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
850 		msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
851 		break;
852 	case SMU_VCLK:
853 	case SMU_DCLK:
854 		msg_set_min = SMU_MSG_SetHardMinVcn;
855 		msg_set_max = SMU_MSG_SetSoftMaxVcn;
856 		break;
857 	default:
858 		return -EINVAL;
859 	}
860 
861 	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
862 	if (ret)
863 		return ret;
864 
865 	return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
866 					       max, NULL);
867 }
868 
smu_v13_0_4_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)869 static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
870 					enum smu_clk_type clk_type,
871 					uint32_t mask)
872 {
873 	uint32_t soft_min_level = 0, soft_max_level = 0;
874 	uint32_t min_freq = 0, max_freq = 0;
875 	int ret = 0;
876 
877 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
878 	soft_max_level = mask ? (fls(mask) - 1) : 0;
879 
880 	switch (clk_type) {
881 	case SMU_SOCCLK:
882 	case SMU_FCLK:
883 	case SMU_VCLK:
884 	case SMU_DCLK:
885 		ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
886 		if (ret)
887 			break;
888 
889 		ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
890 		if (ret)
891 			break;
892 
893 		ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
894 		break;
895 	default:
896 		ret = -EINVAL;
897 		break;
898 	}
899 
900 	return ret;
901 }
902 
smu_v13_0_4_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)903 static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
904 					     enum amd_dpm_forced_level level)
905 {
906 	struct amdgpu_device *adev = smu->adev;
907 	uint32_t sclk_min = 0, sclk_max = 0;
908 	uint32_t fclk_min = 0, fclk_max = 0;
909 	uint32_t socclk_min = 0, socclk_max = 0;
910 	int ret = 0;
911 
912 	switch (level) {
913 	case AMD_DPM_FORCED_LEVEL_HIGH:
914 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
915 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
916 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
917 		sclk_min = sclk_max;
918 		fclk_min = fclk_max;
919 		socclk_min = socclk_max;
920 		break;
921 	case AMD_DPM_FORCED_LEVEL_LOW:
922 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
923 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
924 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
925 		sclk_max = sclk_min;
926 		fclk_max = fclk_min;
927 		socclk_max = socclk_min;
928 		break;
929 	case AMD_DPM_FORCED_LEVEL_AUTO:
930 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
931 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
932 		smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
933 		break;
934 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
935 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
936 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
937 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
938 		/* Temporarily do nothing since the optimal clocks haven't been provided yet */
939 		break;
940 	case AMD_DPM_FORCED_LEVEL_MANUAL:
941 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
942 		return 0;
943 	default:
944 		dev_err(adev->dev, "Invalid performance level %d\n", level);
945 		return -EINVAL;
946 	}
947 
948 	if (sclk_min && sclk_max) {
949 		ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
950 							      SMU_SCLK,
951 							      sclk_min,
952 							      sclk_max);
953 		if (ret)
954 			return ret;
955 
956 		smu->gfx_actual_hard_min_freq = sclk_min;
957 		smu->gfx_actual_soft_max_freq = sclk_max;
958 	}
959 
960 	if (fclk_min && fclk_max) {
961 		ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
962 							      SMU_FCLK,
963 							      fclk_min,
964 							      fclk_max);
965 		if (ret)
966 			return ret;
967 	}
968 
969 	if (socclk_min && socclk_max) {
970 		ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
971 							      SMU_SOCCLK,
972 							      socclk_min,
973 							      socclk_max);
974 		if (ret)
975 			return ret;
976 	}
977 
978 	return ret;
979 }
980 
smu_v13_0_4_mode2_reset(struct smu_context * smu)981 static int smu_v13_0_4_mode2_reset(struct smu_context *smu)
982 {
983 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
984 					       SMU_RESET_MODE_2, NULL);
985 }
986 
smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)987 static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
988 {
989 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
990 
991 	smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
992 	smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
993 	smu->gfx_actual_hard_min_freq = 0;
994 	smu->gfx_actual_soft_max_freq = 0;
995 
996 	return 0;
997 }
998 
999 static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
1000 	.check_fw_status = smu_v13_0_check_fw_status,
1001 	.check_fw_version = smu_v13_0_check_fw_version,
1002 	.init_smc_tables = smu_v13_0_4_init_smc_tables,
1003 	.fini_smc_tables = smu_v13_0_4_fini_smc_tables,
1004 	.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1005 	.system_features_control = smu_v13_0_4_system_features_control,
1006 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1007 	.send_smc_msg = smu_cmn_send_smc_msg,
1008 	.dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1009 	.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1010 	.set_default_dpm_table = smu_v13_0_set_default_dpm_tables,
1011 	.read_sensor = smu_v13_0_4_read_sensor,
1012 	.is_dpm_running = smu_v13_0_4_is_dpm_running,
1013 	.set_watermarks_table = smu_v13_0_4_set_watermarks_table,
1014 	.get_gpu_metrics = smu_v13_0_4_get_gpu_metrics,
1015 	.get_enabled_mask = smu_cmn_get_enabled_mask,
1016 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1017 	.set_driver_table_location = smu_v13_0_set_driver_table_location,
1018 	.gfx_off_control = smu_v13_0_gfx_off_control,
1019 	.mode2_reset = smu_v13_0_4_mode2_reset,
1020 	.get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq,
1021 	.od_edit_dpm_table = smu_v13_0_od_edit_dpm_table,
1022 	.print_clk_levels = smu_v13_0_4_print_clk_levels,
1023 	.force_clk_levels = smu_v13_0_4_force_clk_levels,
1024 	.set_performance_level = smu_v13_0_4_set_performance_level,
1025 	.set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters,
1026 	.set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
1027 };
1028 
smu_v13_0_4_set_smu_mailbox_registers(struct smu_context * smu)1029 static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
1030 {
1031 	struct amdgpu_device *adev = smu->adev;
1032 
1033 	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1034 	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1035 	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1036 }
1037 
smu_v13_0_4_set_ppt_funcs(struct smu_context * smu)1038 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
1039 {
1040 	struct amdgpu_device *adev = smu->adev;
1041 
1042 	smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
1043 	smu->message_map = smu_v13_0_4_message_map;
1044 	smu->feature_map = smu_v13_0_4_feature_mask_map;
1045 	smu->table_map = smu_v13_0_4_table_map;
1046 	smu->is_apu = true;
1047 
1048 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
1049 		smu_v13_0_4_set_smu_mailbox_registers(smu);
1050 	else
1051 		smu_v13_0_set_smu_mailbox_registers(smu);
1052 }
1053