1 /*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2004 Mips Technologies, Inc
17 * Copyright (C) 2008 Kevin D. Kissell
18 */
19
20 #include <linux/clockchips.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/cpumask.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/module.h>
28 #include <linux/ftrace.h>
29 #include <linux/slab.h>
30
31 #include <asm/cpu.h>
32 #include <asm/processor.h>
33 #include <linux/atomic.h>
34 #include <asm/hardirq.h>
35 #include <asm/hazards.h>
36 #include <asm/irq.h>
37 #include <asm/mmu_context.h>
38 #include <asm/mipsregs.h>
39 #include <asm/cacheflush.h>
40 #include <asm/time.h>
41 #include <asm/addrspace.h>
42 #include <asm/smtc.h>
43 #include <asm/smtc_proc.h>
44
45 /*
46 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
47 * in do_IRQ. These are passed in setup_irq_smtc() and stored
48 * in this table.
49 */
50 unsigned long irq_hwmask[NR_IRQS];
51
52 #define LOCK_MT_PRA() \
53 local_irq_save(flags); \
54 mtflags = dmt()
55
56 #define UNLOCK_MT_PRA() \
57 emt(mtflags); \
58 local_irq_restore(flags)
59
60 #define LOCK_CORE_PRA() \
61 local_irq_save(flags); \
62 mtflags = dvpe()
63
64 #define UNLOCK_CORE_PRA() \
65 evpe(mtflags); \
66 local_irq_restore(flags)
67
68 /*
69 * Data structures purely associated with SMTC parallelism
70 */
71
72
73 /*
74 * Table for tracking ASIDs whose lifetime is prolonged.
75 */
76
77 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
78
79 /*
80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
81 */
82
83 #define IPIBUF_PER_CPU 4
84
85 struct smtc_ipi_q IPIQ[NR_CPUS];
86 static struct smtc_ipi_q freeIPIq;
87
88
89 /* Forward declarations */
90
91 void ipi_decode(struct smtc_ipi *);
92 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
93 static void setup_cross_vpe_interrupts(unsigned int nvpe);
94 void init_smtc_stats(void);
95
96 /* Global SMTC Status */
97
98 unsigned int smtc_status;
99
100 /* Boot command line configuration overrides */
101
102 static int vpe0limit;
103 static int ipibuffers;
104 static int nostlb;
105 static int asidmask;
106 unsigned long smtc_asid_mask = 0xff;
107
vpe0tcs(char * str)108 static int __init vpe0tcs(char *str)
109 {
110 get_option(&str, &vpe0limit);
111
112 return 1;
113 }
114
ipibufs(char * str)115 static int __init ipibufs(char *str)
116 {
117 get_option(&str, &ipibuffers);
118 return 1;
119 }
120
stlb_disable(char * s)121 static int __init stlb_disable(char *s)
122 {
123 nostlb = 1;
124 return 1;
125 }
126
asidmask_set(char * str)127 static int __init asidmask_set(char *str)
128 {
129 get_option(&str, &asidmask);
130 switch (asidmask) {
131 case 0x1:
132 case 0x3:
133 case 0x7:
134 case 0xf:
135 case 0x1f:
136 case 0x3f:
137 case 0x7f:
138 case 0xff:
139 smtc_asid_mask = (unsigned long)asidmask;
140 break;
141 default:
142 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
143 }
144 return 1;
145 }
146
147 __setup("vpe0tcs=", vpe0tcs);
148 __setup("ipibufs=", ipibufs);
149 __setup("nostlb", stlb_disable);
150 __setup("asidmask=", asidmask_set);
151
152 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
153
154 static int hang_trig;
155
hangtrig_enable(char * s)156 static int __init hangtrig_enable(char *s)
157 {
158 hang_trig = 1;
159 return 1;
160 }
161
162
163 __setup("hangtrig", hangtrig_enable);
164
165 #define DEFAULT_BLOCKED_IPI_LIMIT 32
166
167 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
168
tintq(char * str)169 static int __init tintq(char *str)
170 {
171 get_option(&str, &timerq_limit);
172 return 1;
173 }
174
175 __setup("tintq=", tintq);
176
177 static int imstuckcount[2][8];
178 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
179 static int vpemask[2][8] = {
180 {0, 0, 1, 0, 0, 0, 0, 1},
181 {0, 0, 0, 0, 0, 0, 0, 1}
182 };
183 int tcnoprog[NR_CPUS];
184 static atomic_t idle_hook_initialized = ATOMIC_INIT(0);
185 static int clock_hang_reported[NR_CPUS];
186
187 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
188
189 /*
190 * Configure shared TLB - VPC configuration bit must be set by caller
191 */
192
smtc_configure_tlb(void)193 static void smtc_configure_tlb(void)
194 {
195 int i, tlbsiz, vpes;
196 unsigned long mvpconf0;
197 unsigned long config1val;
198
199 /* Set up ASID preservation table */
200 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
201 for(i = 0; i < MAX_SMTC_ASIDS; i++) {
202 smtc_live_asid[vpes][i] = 0;
203 }
204 }
205 mvpconf0 = read_c0_mvpconf0();
206
207 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
208 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
209 /* If we have multiple VPEs, try to share the TLB */
210 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
211 /*
212 * If TLB sizing is programmable, shared TLB
213 * size is the total available complement.
214 * Otherwise, we have to take the sum of all
215 * static VPE TLB entries.
216 */
217 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
218 >> MVPCONF0_PTLBE_SHIFT)) == 0) {
219 /*
220 * If there's more than one VPE, there had better
221 * be more than one TC, because we need one to bind
222 * to each VPE in turn to be able to read
223 * its configuration state!
224 */
225 settc(1);
226 /* Stop the TC from doing anything foolish */
227 write_tc_c0_tchalt(TCHALT_H);
228 mips_ihb();
229 /* No need to un-Halt - that happens later anyway */
230 for (i=0; i < vpes; i++) {
231 write_tc_c0_tcbind(i);
232 /*
233 * To be 100% sure we're really getting the right
234 * information, we exit the configuration state
235 * and do an IHB after each rebinding.
236 */
237 write_c0_mvpcontrol(
238 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
239 mips_ihb();
240 /*
241 * Only count if the MMU Type indicated is TLB
242 */
243 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
244 config1val = read_vpe_c0_config1();
245 tlbsiz += ((config1val >> 25) & 0x3f) + 1;
246 }
247
248 /* Put core back in configuration state */
249 write_c0_mvpcontrol(
250 read_c0_mvpcontrol() | MVPCONTROL_VPC );
251 mips_ihb();
252 }
253 }
254 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
255 ehb();
256
257 /*
258 * Setup kernel data structures to use software total,
259 * rather than read the per-VPE Config1 value. The values
260 * for "CPU 0" gets copied to all the other CPUs as part
261 * of their initialization in smtc_cpu_setup().
262 */
263
264 /* MIPS32 limits TLB indices to 64 */
265 if (tlbsiz > 64)
266 tlbsiz = 64;
267 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
268 smtc_status |= SMTC_TLB_SHARED;
269 local_flush_tlb_all();
270
271 printk("TLB of %d entry pairs shared by %d VPEs\n",
272 tlbsiz, vpes);
273 } else {
274 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
275 }
276 }
277 }
278
279
280 /*
281 * Incrementally build the CPU map out of constituent MIPS MT cores,
282 * using the specified available VPEs and TCs. Plaform code needs
283 * to ensure that each MIPS MT core invokes this routine on reset,
284 * one at a time(!).
285 *
286 * This version of the build_cpu_map and prepare_cpus routines assumes
287 * that *all* TCs of a MIPS MT core will be used for Linux, and that
288 * they will be spread across *all* available VPEs (to minimise the
289 * loss of efficiency due to exception service serialization).
290 * An improved version would pick up configuration information and
291 * possibly leave some TCs/VPEs as "slave" processors.
292 *
293 * Use c0_MVPConf0 to find out how many TCs are available, setting up
294 * cpu_possible_mask and the logical/physical mappings.
295 */
296
smtc_build_cpu_map(int start_cpu_slot)297 int __init smtc_build_cpu_map(int start_cpu_slot)
298 {
299 int i, ntcs;
300
301 /*
302 * The CPU map isn't actually used for anything at this point,
303 * so it's not clear what else we should do apart from set
304 * everything up so that "logical" = "physical".
305 */
306 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
307 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
308 set_cpu_possible(i, true);
309 __cpu_number_map[i] = i;
310 __cpu_logical_map[i] = i;
311 }
312 #ifdef CONFIG_MIPS_MT_FPAFF
313 /* Initialize map of CPUs with FPUs */
314 cpus_clear(mt_fpu_cpumask);
315 #endif
316
317 /* One of those TC's is the one booting, and not a secondary... */
318 printk("%i available secondary CPU TC(s)\n", i - 1);
319
320 return i;
321 }
322
323 /*
324 * Common setup before any secondaries are started
325 * Make sure all CPU's are in a sensible state before we boot any of the
326 * secondaries.
327 *
328 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
329 * as possible across the available VPEs.
330 */
331
smtc_tc_setup(int vpe,int tc,int cpu)332 static void smtc_tc_setup(int vpe, int tc, int cpu)
333 {
334 settc(tc);
335 write_tc_c0_tchalt(TCHALT_H);
336 mips_ihb();
337 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
338 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
339 | TCSTATUS_A);
340 /*
341 * TCContext gets an offset from the base of the IPIQ array
342 * to be used in low-level code to detect the presence of
343 * an active IPI queue
344 */
345 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
346 /* Bind tc to vpe */
347 write_tc_c0_tcbind(vpe);
348 /* In general, all TCs should have the same cpu_data indications */
349 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
350 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
351 if (cpu_data[0].cputype == CPU_34K ||
352 cpu_data[0].cputype == CPU_1004K)
353 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
354 cpu_data[cpu].vpe_id = vpe;
355 cpu_data[cpu].tc_id = tc;
356 /* Multi-core SMTC hasn't been tested, but be prepared */
357 cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
358 }
359
360 /*
361 * Tweak to get Count registes in as close a sync as possible.
362 * Value seems good for 34K-class cores.
363 */
364
365 #define CP0_SKEW 8
366
smtc_prepare_cpus(int cpus)367 void smtc_prepare_cpus(int cpus)
368 {
369 int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
370 unsigned long flags;
371 unsigned long val;
372 int nipi;
373 struct smtc_ipi *pipi;
374
375 /* disable interrupts so we can disable MT */
376 local_irq_save(flags);
377 /* disable MT so we can configure */
378 dvpe();
379 dmt();
380
381 spin_lock_init(&freeIPIq.lock);
382
383 /*
384 * We probably don't have as many VPEs as we do SMP "CPUs",
385 * but it's possible - and in any case we'll never use more!
386 */
387 for (i=0; i<NR_CPUS; i++) {
388 IPIQ[i].head = IPIQ[i].tail = NULL;
389 spin_lock_init(&IPIQ[i].lock);
390 IPIQ[i].depth = 0;
391 IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
392 }
393
394 /* cpu_data index starts at zero */
395 cpu = 0;
396 cpu_data[cpu].vpe_id = 0;
397 cpu_data[cpu].tc_id = 0;
398 cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
399 cpu++;
400
401 /* Report on boot-time options */
402 mips_mt_set_cpuoptions();
403 if (vpelimit > 0)
404 printk("Limit of %d VPEs set\n", vpelimit);
405 if (tclimit > 0)
406 printk("Limit of %d TCs set\n", tclimit);
407 if (nostlb) {
408 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
409 }
410 if (asidmask)
411 printk("ASID mask value override to 0x%x\n", asidmask);
412
413 /* Temporary */
414 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
415 if (hang_trig)
416 printk("Logic Analyser Trigger on suspected TC hang\n");
417 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
418
419 /* Put MVPE's into 'configuration state' */
420 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
421
422 val = read_c0_mvpconf0();
423 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
424 if (vpelimit > 0 && nvpe > vpelimit)
425 nvpe = vpelimit;
426 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
427 if (ntc > NR_CPUS)
428 ntc = NR_CPUS;
429 if (tclimit > 0 && ntc > tclimit)
430 ntc = tclimit;
431 slop = ntc % nvpe;
432 for (i = 0; i < nvpe; i++) {
433 tcpervpe[i] = ntc / nvpe;
434 if (slop) {
435 if((slop - i) > 0) tcpervpe[i]++;
436 }
437 }
438 /* Handle command line override for VPE0 */
439 if (vpe0limit > ntc) vpe0limit = ntc;
440 if (vpe0limit > 0) {
441 int slopslop;
442 if (vpe0limit < tcpervpe[0]) {
443 /* Reducing TC count - distribute to others */
444 slop = tcpervpe[0] - vpe0limit;
445 slopslop = slop % (nvpe - 1);
446 tcpervpe[0] = vpe0limit;
447 for (i = 1; i < nvpe; i++) {
448 tcpervpe[i] += slop / (nvpe - 1);
449 if(slopslop && ((slopslop - (i - 1) > 0)))
450 tcpervpe[i]++;
451 }
452 } else if (vpe0limit > tcpervpe[0]) {
453 /* Increasing TC count - steal from others */
454 slop = vpe0limit - tcpervpe[0];
455 slopslop = slop % (nvpe - 1);
456 tcpervpe[0] = vpe0limit;
457 for (i = 1; i < nvpe; i++) {
458 tcpervpe[i] -= slop / (nvpe - 1);
459 if(slopslop && ((slopslop - (i - 1) > 0)))
460 tcpervpe[i]--;
461 }
462 }
463 }
464
465 /* Set up shared TLB */
466 smtc_configure_tlb();
467
468 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
469 if (tcpervpe[vpe] == 0)
470 continue;
471 if (vpe != 0)
472 printk(", ");
473 printk("VPE %d: TC", vpe);
474 for (i = 0; i < tcpervpe[vpe]; i++) {
475 /*
476 * TC 0 is bound to VPE 0 at reset,
477 * and is presumably executing this
478 * code. Leave it alone!
479 */
480 if (tc != 0) {
481 smtc_tc_setup(vpe, tc, cpu);
482 cpu++;
483 }
484 printk(" %d", tc);
485 tc++;
486 }
487 if (vpe != 0) {
488 /*
489 * Allow this VPE to control others.
490 */
491 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
492 VPECONF0_MVP);
493
494 /*
495 * Clear any stale software interrupts from VPE's Cause
496 */
497 write_vpe_c0_cause(0);
498
499 /*
500 * Clear ERL/EXL of VPEs other than 0
501 * and set restricted interrupt enable/mask.
502 */
503 write_vpe_c0_status((read_vpe_c0_status()
504 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
505 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
506 | ST0_IE));
507 /*
508 * set config to be the same as vpe0,
509 * particularly kseg0 coherency alg
510 */
511 write_vpe_c0_config(read_c0_config());
512 /* Clear any pending timer interrupt */
513 write_vpe_c0_compare(0);
514 /* Propagate Config7 */
515 write_vpe_c0_config7(read_c0_config7());
516 write_vpe_c0_count(read_c0_count() + CP0_SKEW);
517 ehb();
518 }
519 /* enable multi-threading within VPE */
520 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
521 /* enable the VPE */
522 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
523 }
524
525 /*
526 * Pull any physically present but unused TCs out of circulation.
527 */
528 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
529 set_cpu_possible(tc, false);
530 set_cpu_present(tc, false);
531 tc++;
532 }
533
534 /* release config state */
535 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
536
537 printk("\n");
538
539 /* Set up coprocessor affinity CPU mask(s) */
540
541 #ifdef CONFIG_MIPS_MT_FPAFF
542 for (tc = 0; tc < ntc; tc++) {
543 if (cpu_data[tc].options & MIPS_CPU_FPU)
544 cpu_set(tc, mt_fpu_cpumask);
545 }
546 #endif
547
548 /* set up ipi interrupts... */
549
550 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
551
552 setup_cross_vpe_interrupts(nvpe);
553
554 /* Set up queue of free IPI "messages". */
555 nipi = NR_CPUS * IPIBUF_PER_CPU;
556 if (ipibuffers > 0)
557 nipi = ipibuffers;
558
559 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
560 if (pipi == NULL)
561 panic("kmalloc of IPI message buffers failed");
562 else
563 printk("IPI buffer pool of %d buffers\n", nipi);
564 for (i = 0; i < nipi; i++) {
565 smtc_ipi_nq(&freeIPIq, pipi);
566 pipi++;
567 }
568
569 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
570 emt(EMT_ENABLE);
571 evpe(EVPE_ENABLE);
572 local_irq_restore(flags);
573 /* Initialize SMTC /proc statistics/diagnostics */
574 init_smtc_stats();
575 }
576
577
578 /*
579 * Setup the PC, SP, and GP of a secondary processor and start it
580 * running!
581 * smp_bootstrap is the place to resume from
582 * __KSTK_TOS(idle) is apparently the stack pointer
583 * (unsigned long)idle->thread_info the gp
584 *
585 */
smtc_boot_secondary(int cpu,struct task_struct * idle)586 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
587 {
588 extern u32 kernelsp[NR_CPUS];
589 unsigned long flags;
590 int mtflags;
591
592 LOCK_MT_PRA();
593 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
594 dvpe();
595 }
596 settc(cpu_data[cpu].tc_id);
597
598 /* pc */
599 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
600
601 /* stack pointer */
602 kernelsp[cpu] = __KSTK_TOS(idle);
603 write_tc_gpr_sp(__KSTK_TOS(idle));
604
605 /* global pointer */
606 write_tc_gpr_gp((unsigned long)task_thread_info(idle));
607
608 smtc_status |= SMTC_MTC_ACTIVE;
609 write_tc_c0_tchalt(0);
610 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
611 evpe(EVPE_ENABLE);
612 }
613 UNLOCK_MT_PRA();
614 }
615
smtc_init_secondary(void)616 void smtc_init_secondary(void)
617 {
618 local_irq_enable();
619 }
620
smtc_smp_finish(void)621 void smtc_smp_finish(void)
622 {
623 int cpu = smp_processor_id();
624
625 /*
626 * Lowest-numbered CPU per VPE starts a clock tick.
627 * Like per_cpu_trap_init() hack, this assumes that
628 * SMTC init code assigns TCs consdecutively and
629 * in ascending order across available VPEs.
630 */
631 if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
632 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
633
634 printk("TC %d going on-line as CPU %d\n",
635 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
636 }
637
smtc_cpus_done(void)638 void smtc_cpus_done(void)
639 {
640 }
641
642 /*
643 * Support for SMTC-optimized driver IRQ registration
644 */
645
646 /*
647 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
648 * in do_IRQ. These are passed in setup_irq_smtc() and stored
649 * in this table.
650 */
651
setup_irq_smtc(unsigned int irq,struct irqaction * new,unsigned long hwmask)652 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
653 unsigned long hwmask)
654 {
655 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
656 unsigned int vpe = current_cpu_data.vpe_id;
657
658 vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
659 #endif
660 irq_hwmask[irq] = hwmask;
661
662 return setup_irq(irq, new);
663 }
664
665 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
666 /*
667 * Support for IRQ affinity to TCs
668 */
669
smtc_set_irq_affinity(unsigned int irq,cpumask_t affinity)670 void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
671 {
672 /*
673 * If a "fast path" cache of quickly decodable affinity state
674 * is maintained, this is where it gets done, on a call up
675 * from the platform affinity code.
676 */
677 }
678
smtc_forward_irq(struct irq_data * d)679 void smtc_forward_irq(struct irq_data *d)
680 {
681 unsigned int irq = d->irq;
682 int target;
683
684 /*
685 * OK wise guy, now figure out how to get the IRQ
686 * to be serviced on an authorized "CPU".
687 *
688 * Ideally, to handle the situation where an IRQ has multiple
689 * eligible CPUS, we would maintain state per IRQ that would
690 * allow a fair distribution of service requests. Since the
691 * expected use model is any-or-only-one, for simplicity
692 * and efficiency, we just pick the easiest one to find.
693 */
694
695 target = cpumask_first(d->affinity);
696
697 /*
698 * We depend on the platform code to have correctly processed
699 * IRQ affinity change requests to ensure that the IRQ affinity
700 * mask has been purged of bits corresponding to nonexistent and
701 * offline "CPUs", and to TCs bound to VPEs other than the VPE
702 * connected to the physical interrupt input for the interrupt
703 * in question. Otherwise we have a nasty problem with interrupt
704 * mask management. This is best handled in non-performance-critical
705 * platform IRQ affinity setting code, to minimize interrupt-time
706 * checks.
707 */
708
709 /* If no one is eligible, service locally */
710 if (target >= NR_CPUS)
711 do_IRQ_no_affinity(irq);
712 else
713 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
714 }
715
716 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
717
718 /*
719 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
720 * Within a VPE one TC can interrupt another by different approaches.
721 * The easiest to get right would probably be to make all TCs except
722 * the target IXMT and set a software interrupt, but an IXMT-based
723 * scheme requires that a handler must run before a new IPI could
724 * be sent, which would break the "broadcast" loops in MIPS MT.
725 * A more gonzo approach within a VPE is to halt the TC, extract
726 * its Restart, Status, and a couple of GPRs, and program the Restart
727 * address to emulate an interrupt.
728 *
729 * Within a VPE, one can be confident that the target TC isn't in
730 * a critical EXL state when halted, since the write to the Halt
731 * register could not have issued on the writing thread if the
732 * halting thread had EXL set. So k0 and k1 of the target TC
733 * can be used by the injection code. Across VPEs, one can't
734 * be certain that the target TC isn't in a critical exception
735 * state. So we try a two-step process of sending a software
736 * interrupt to the target VPE, which either handles the event
737 * itself (if it was the target) or injects the event within
738 * the VPE.
739 */
740
smtc_ipi_qdump(void)741 static void smtc_ipi_qdump(void)
742 {
743 int i;
744 struct smtc_ipi *temp;
745
746 for (i = 0; i < NR_CPUS ;i++) {
747 pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
748 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
749 IPIQ[i].depth);
750 temp = IPIQ[i].head;
751
752 while (temp != IPIQ[i].tail) {
753 pr_debug("%d %d %d: ", temp->type, temp->dest,
754 (int)temp->arg);
755 #ifdef SMTC_IPI_DEBUG
756 pr_debug("%u %lu\n", temp->sender, temp->stamp);
757 #else
758 pr_debug("\n");
759 #endif
760 temp = temp->flink;
761 }
762 }
763 }
764
765 /*
766 * The standard atomic.h primitives don't quite do what we want
767 * here: We need an atomic add-and-return-previous-value (which
768 * could be done with atomic_add_return and a decrement) and an
769 * atomic set/zero-and-return-previous-value (which can't really
770 * be done with the atomic.h primitives). And since this is
771 * MIPS MT, we can assume that we have LL/SC.
772 */
atomic_postincrement(atomic_t * v)773 static inline int atomic_postincrement(atomic_t *v)
774 {
775 unsigned long result;
776
777 unsigned long temp;
778
779 __asm__ __volatile__(
780 "1: ll %0, %2 \n"
781 " addu %1, %0, 1 \n"
782 " sc %1, %2 \n"
783 " beqz %1, 1b \n"
784 __WEAK_LLSC_MB
785 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
786 : "m" (v->counter)
787 : "memory");
788
789 return result;
790 }
791
smtc_send_ipi(int cpu,int type,unsigned int action)792 void smtc_send_ipi(int cpu, int type, unsigned int action)
793 {
794 int tcstatus;
795 struct smtc_ipi *pipi;
796 unsigned long flags;
797 int mtflags;
798 unsigned long tcrestart;
799 extern void r4k_wait_irqoff(void), __pastwait(void);
800 int set_resched_flag = (type == LINUX_SMP_IPI &&
801 action == SMP_RESCHEDULE_YOURSELF);
802
803 if (cpu == smp_processor_id()) {
804 printk("Cannot Send IPI to self!\n");
805 return;
806 }
807 if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
808 return; /* There is a reschedule queued already */
809
810 /* Set up a descriptor, to be delivered either promptly or queued */
811 pipi = smtc_ipi_dq(&freeIPIq);
812 if (pipi == NULL) {
813 bust_spinlocks(1);
814 mips_mt_regdump(dvpe());
815 panic("IPI Msg. Buffers Depleted");
816 }
817 pipi->type = type;
818 pipi->arg = (void *)action;
819 pipi->dest = cpu;
820 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
821 /* If not on same VPE, enqueue and send cross-VPE interrupt */
822 IPIQ[cpu].resched_flag |= set_resched_flag;
823 smtc_ipi_nq(&IPIQ[cpu], pipi);
824 LOCK_CORE_PRA();
825 settc(cpu_data[cpu].tc_id);
826 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
827 UNLOCK_CORE_PRA();
828 } else {
829 /*
830 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
831 * since ASID shootdown on the other VPE may
832 * collide with this operation.
833 */
834 LOCK_CORE_PRA();
835 settc(cpu_data[cpu].tc_id);
836 /* Halt the targeted TC */
837 write_tc_c0_tchalt(TCHALT_H);
838 mips_ihb();
839
840 /*
841 * Inspect TCStatus - if IXMT is set, we have to queue
842 * a message. Otherwise, we set up the "interrupt"
843 * of the other TC
844 */
845 tcstatus = read_tc_c0_tcstatus();
846
847 if ((tcstatus & TCSTATUS_IXMT) != 0) {
848 /*
849 * If we're in the the irq-off version of the wait
850 * loop, we need to force exit from the wait and
851 * do a direct post of the IPI.
852 */
853 if (cpu_wait == r4k_wait_irqoff) {
854 tcrestart = read_tc_c0_tcrestart();
855 if (tcrestart >= (unsigned long)r4k_wait_irqoff
856 && tcrestart < (unsigned long)__pastwait) {
857 write_tc_c0_tcrestart(__pastwait);
858 tcstatus &= ~TCSTATUS_IXMT;
859 write_tc_c0_tcstatus(tcstatus);
860 goto postdirect;
861 }
862 }
863 /*
864 * Otherwise we queue the message for the target TC
865 * to pick up when he does a local_irq_restore()
866 */
867 write_tc_c0_tchalt(0);
868 UNLOCK_CORE_PRA();
869 IPIQ[cpu].resched_flag |= set_resched_flag;
870 smtc_ipi_nq(&IPIQ[cpu], pipi);
871 } else {
872 postdirect:
873 post_direct_ipi(cpu, pipi);
874 write_tc_c0_tchalt(0);
875 UNLOCK_CORE_PRA();
876 }
877 }
878 }
879
880 /*
881 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
882 */
post_direct_ipi(int cpu,struct smtc_ipi * pipi)883 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
884 {
885 struct pt_regs *kstack;
886 unsigned long tcstatus;
887 unsigned long tcrestart;
888 extern u32 kernelsp[NR_CPUS];
889 extern void __smtc_ipi_vector(void);
890 //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
891
892 /* Extract Status, EPC from halted TC */
893 tcstatus = read_tc_c0_tcstatus();
894 tcrestart = read_tc_c0_tcrestart();
895 /* If TCRestart indicates a WAIT instruction, advance the PC */
896 if ((tcrestart & 0x80000000)
897 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
898 tcrestart += 4;
899 }
900 /*
901 * Save on TC's future kernel stack
902 *
903 * CU bit of Status is indicator that TC was
904 * already running on a kernel stack...
905 */
906 if (tcstatus & ST0_CU0) {
907 /* Note that this "- 1" is pointer arithmetic */
908 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
909 } else {
910 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
911 }
912
913 kstack->cp0_epc = (long)tcrestart;
914 /* Save TCStatus */
915 kstack->cp0_tcstatus = tcstatus;
916 /* Pass token of operation to be performed kernel stack pad area */
917 kstack->pad0[4] = (unsigned long)pipi;
918 /* Pass address of function to be called likewise */
919 kstack->pad0[5] = (unsigned long)&ipi_decode;
920 /* Set interrupt exempt and kernel mode */
921 tcstatus |= TCSTATUS_IXMT;
922 tcstatus &= ~TCSTATUS_TKSU;
923 write_tc_c0_tcstatus(tcstatus);
924 ehb();
925 /* Set TC Restart address to be SMTC IPI vector */
926 write_tc_c0_tcrestart(__smtc_ipi_vector);
927 }
928
ipi_resched_interrupt(void)929 static void ipi_resched_interrupt(void)
930 {
931 scheduler_ipi();
932 }
933
ipi_call_interrupt(void)934 static void ipi_call_interrupt(void)
935 {
936 /* Invoke generic function invocation code in smp.c */
937 smp_call_function_interrupt();
938 }
939
940 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
941
smtc_clock_tick_interrupt(void)942 static void __irq_entry smtc_clock_tick_interrupt(void)
943 {
944 unsigned int cpu = smp_processor_id();
945 struct clock_event_device *cd;
946 int irq = MIPS_CPU_IRQ_BASE + 1;
947
948 irq_enter();
949 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
950 cd = &per_cpu(mips_clockevent_device, cpu);
951 cd->event_handler(cd);
952 irq_exit();
953 }
954
ipi_decode(struct smtc_ipi * pipi)955 void ipi_decode(struct smtc_ipi *pipi)
956 {
957 void *arg_copy = pipi->arg;
958 int type_copy = pipi->type;
959
960 smtc_ipi_nq(&freeIPIq, pipi);
961
962 switch (type_copy) {
963 case SMTC_CLOCK_TICK:
964 smtc_clock_tick_interrupt();
965 break;
966
967 case LINUX_SMP_IPI:
968 switch ((int)arg_copy) {
969 case SMP_RESCHEDULE_YOURSELF:
970 ipi_resched_interrupt();
971 break;
972 case SMP_CALL_FUNCTION:
973 ipi_call_interrupt();
974 break;
975 default:
976 printk("Impossible SMTC IPI Argument %p\n", arg_copy);
977 break;
978 }
979 break;
980 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
981 case IRQ_AFFINITY_IPI:
982 /*
983 * Accept a "forwarded" interrupt that was initially
984 * taken by a TC who doesn't have affinity for the IRQ.
985 */
986 do_IRQ_no_affinity((int)arg_copy);
987 break;
988 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
989 default:
990 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
991 break;
992 }
993 }
994
995 /*
996 * Similar to smtc_ipi_replay(), but invoked from context restore,
997 * so it reuses the current exception frame rather than set up a
998 * new one with self_ipi.
999 */
1000
deferred_smtc_ipi(void)1001 void deferred_smtc_ipi(void)
1002 {
1003 int cpu = smp_processor_id();
1004
1005 /*
1006 * Test is not atomic, but much faster than a dequeue,
1007 * and the vast majority of invocations will have a null queue.
1008 * If irq_disabled when this was called, then any IPIs queued
1009 * after we test last will be taken on the next irq_enable/restore.
1010 * If interrupts were enabled, then any IPIs added after the
1011 * last test will be taken directly.
1012 */
1013
1014 while (IPIQ[cpu].head != NULL) {
1015 struct smtc_ipi_q *q = &IPIQ[cpu];
1016 struct smtc_ipi *pipi;
1017 unsigned long flags;
1018
1019 /*
1020 * It may be possible we'll come in with interrupts
1021 * already enabled.
1022 */
1023 local_irq_save(flags);
1024 spin_lock(&q->lock);
1025 pipi = __smtc_ipi_dq(q);
1026 spin_unlock(&q->lock);
1027 if (pipi != NULL) {
1028 if (pipi->type == LINUX_SMP_IPI &&
1029 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1030 IPIQ[cpu].resched_flag = 0;
1031 ipi_decode(pipi);
1032 }
1033 /*
1034 * The use of the __raw_local restore isn't
1035 * as obviously necessary here as in smtc_ipi_replay(),
1036 * but it's more efficient, given that we're already
1037 * running down the IPI queue.
1038 */
1039 __arch_local_irq_restore(flags);
1040 }
1041 }
1042
1043 /*
1044 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
1045 * set via cross-VPE MTTR manipulation of the Cause register. It would be
1046 * in some regards preferable to have external logic for "doorbell" hardware
1047 * interrupts.
1048 */
1049
1050 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
1051
ipi_interrupt(int irq,void * dev_idm)1052 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1053 {
1054 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
1055 int my_tc = cpu_data[smp_processor_id()].tc_id;
1056 int cpu;
1057 struct smtc_ipi *pipi;
1058 unsigned long tcstatus;
1059 int sent;
1060 unsigned long flags;
1061 unsigned int mtflags;
1062 unsigned int vpflags;
1063
1064 /*
1065 * So long as cross-VPE interrupts are done via
1066 * MFTR/MTTR read-modify-writes of Cause, we need
1067 * to stop other VPEs whenever the local VPE does
1068 * anything similar.
1069 */
1070 local_irq_save(flags);
1071 vpflags = dvpe();
1072 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
1073 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
1074 irq_enable_hazard();
1075 evpe(vpflags);
1076 local_irq_restore(flags);
1077
1078 /*
1079 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
1080 * queued for TCs on this VPE other than the current one.
1081 * Return-from-interrupt should cause us to drain the queue
1082 * for the current TC, so we ought not to have to do it explicitly here.
1083 */
1084
1085 for_each_online_cpu(cpu) {
1086 if (cpu_data[cpu].vpe_id != my_vpe)
1087 continue;
1088
1089 pipi = smtc_ipi_dq(&IPIQ[cpu]);
1090 if (pipi != NULL) {
1091 if (cpu_data[cpu].tc_id != my_tc) {
1092 sent = 0;
1093 LOCK_MT_PRA();
1094 settc(cpu_data[cpu].tc_id);
1095 write_tc_c0_tchalt(TCHALT_H);
1096 mips_ihb();
1097 tcstatus = read_tc_c0_tcstatus();
1098 if ((tcstatus & TCSTATUS_IXMT) == 0) {
1099 post_direct_ipi(cpu, pipi);
1100 sent = 1;
1101 }
1102 write_tc_c0_tchalt(0);
1103 UNLOCK_MT_PRA();
1104 if (!sent) {
1105 smtc_ipi_req(&IPIQ[cpu], pipi);
1106 }
1107 } else {
1108 /*
1109 * ipi_decode() should be called
1110 * with interrupts off
1111 */
1112 local_irq_save(flags);
1113 if (pipi->type == LINUX_SMP_IPI &&
1114 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1115 IPIQ[cpu].resched_flag = 0;
1116 ipi_decode(pipi);
1117 local_irq_restore(flags);
1118 }
1119 }
1120 }
1121
1122 return IRQ_HANDLED;
1123 }
1124
ipi_irq_dispatch(void)1125 static void ipi_irq_dispatch(void)
1126 {
1127 do_IRQ(cpu_ipi_irq);
1128 }
1129
1130 static struct irqaction irq_ipi = {
1131 .handler = ipi_interrupt,
1132 .flags = IRQF_PERCPU,
1133 .name = "SMTC_IPI"
1134 };
1135
setup_cross_vpe_interrupts(unsigned int nvpe)1136 static void setup_cross_vpe_interrupts(unsigned int nvpe)
1137 {
1138 if (nvpe < 1)
1139 return;
1140
1141 if (!cpu_has_vint)
1142 panic("SMTC Kernel requires Vectored Interrupt support");
1143
1144 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
1145
1146 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1147
1148 irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
1149 }
1150
1151 /*
1152 * SMTC-specific hacks invoked from elsewhere in the kernel.
1153 */
1154
1155 /*
1156 * smtc_ipi_replay is called from raw_local_irq_restore
1157 */
1158
smtc_ipi_replay(void)1159 void smtc_ipi_replay(void)
1160 {
1161 unsigned int cpu = smp_processor_id();
1162
1163 /*
1164 * To the extent that we've ever turned interrupts off,
1165 * we may have accumulated deferred IPIs. This is subtle.
1166 * we should be OK: If we pick up something and dispatch
1167 * it here, that's great. If we see nothing, but concurrent
1168 * with this operation, another TC sends us an IPI, IXMT
1169 * is clear, and we'll handle it as a real pseudo-interrupt
1170 * and not a pseudo-pseudo interrupt. The important thing
1171 * is to do the last check for queued message *after* the
1172 * re-enabling of interrupts.
1173 */
1174 while (IPIQ[cpu].head != NULL) {
1175 struct smtc_ipi_q *q = &IPIQ[cpu];
1176 struct smtc_ipi *pipi;
1177 unsigned long flags;
1178
1179 /*
1180 * It's just possible we'll come in with interrupts
1181 * already enabled.
1182 */
1183 local_irq_save(flags);
1184
1185 spin_lock(&q->lock);
1186 pipi = __smtc_ipi_dq(q);
1187 spin_unlock(&q->lock);
1188 /*
1189 ** But use a raw restore here to avoid recursion.
1190 */
1191 __arch_local_irq_restore(flags);
1192
1193 if (pipi) {
1194 self_ipi(pipi);
1195 smtc_cpu_stats[cpu].selfipis++;
1196 }
1197 }
1198 }
1199
1200 EXPORT_SYMBOL(smtc_ipi_replay);
1201
smtc_idle_loop_hook(void)1202 void smtc_idle_loop_hook(void)
1203 {
1204 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1205 int im;
1206 int flags;
1207 int mtflags;
1208 int bit;
1209 int vpe;
1210 int tc;
1211 int hook_ntcs;
1212 /*
1213 * printk within DMT-protected regions can deadlock,
1214 * so buffer diagnostic messages for later output.
1215 */
1216 char *pdb_msg;
1217 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1218
1219 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1220 if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1221 int mvpconf0;
1222 /* Tedious stuff to just do once */
1223 mvpconf0 = read_c0_mvpconf0();
1224 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1225 if (hook_ntcs > NR_CPUS)
1226 hook_ntcs = NR_CPUS;
1227 for (tc = 0; tc < hook_ntcs; tc++) {
1228 tcnoprog[tc] = 0;
1229 clock_hang_reported[tc] = 0;
1230 }
1231 for (vpe = 0; vpe < 2; vpe++)
1232 for (im = 0; im < 8; im++)
1233 imstuckcount[vpe][im] = 0;
1234 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1235 atomic_set(&idle_hook_initialized, 1000);
1236 } else {
1237 /* Someone else is initializing in parallel - let 'em finish */
1238 while (atomic_read(&idle_hook_initialized) < 1000)
1239 ;
1240 }
1241 }
1242
1243 /* Have we stupidly left IXMT set somewhere? */
1244 if (read_c0_tcstatus() & 0x400) {
1245 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1246 ehb();
1247 printk("Dangling IXMT in cpu_idle()\n");
1248 }
1249
1250 /* Have we stupidly left an IM bit turned off? */
1251 #define IM_LIMIT 2000
1252 local_irq_save(flags);
1253 mtflags = dmt();
1254 pdb_msg = &id_ho_db_msg[0];
1255 im = read_c0_status();
1256 vpe = current_cpu_data.vpe_id;
1257 for (bit = 0; bit < 8; bit++) {
1258 /*
1259 * In current prototype, I/O interrupts
1260 * are masked for VPE > 0
1261 */
1262 if (vpemask[vpe][bit]) {
1263 if (!(im & (0x100 << bit)))
1264 imstuckcount[vpe][bit]++;
1265 else
1266 imstuckcount[vpe][bit] = 0;
1267 if (imstuckcount[vpe][bit] > IM_LIMIT) {
1268 set_c0_status(0x100 << bit);
1269 ehb();
1270 imstuckcount[vpe][bit] = 0;
1271 pdb_msg += sprintf(pdb_msg,
1272 "Dangling IM %d fixed for VPE %d\n", bit,
1273 vpe);
1274 }
1275 }
1276 }
1277
1278 emt(mtflags);
1279 local_irq_restore(flags);
1280 if (pdb_msg != &id_ho_db_msg[0])
1281 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1282 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1283
1284 smtc_ipi_replay();
1285 }
1286
smtc_soft_dump(void)1287 void smtc_soft_dump(void)
1288 {
1289 int i;
1290
1291 printk("Counter Interrupts taken per CPU (TC)\n");
1292 for (i=0; i < NR_CPUS; i++) {
1293 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1294 }
1295 printk("Self-IPI invocations:\n");
1296 for (i=0; i < NR_CPUS; i++) {
1297 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1298 }
1299 smtc_ipi_qdump();
1300 printk("%d Recoveries of \"stolen\" FPU\n",
1301 atomic_read(&smtc_fpu_recoveries));
1302 }
1303
1304
1305 /*
1306 * TLB management routines special to SMTC
1307 */
1308
smtc_get_new_mmu_context(struct mm_struct * mm,unsigned long cpu)1309 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1310 {
1311 unsigned long flags, mtflags, tcstat, prevhalt, asid;
1312 int tlb, i;
1313
1314 /*
1315 * It would be nice to be able to use a spinlock here,
1316 * but this is invoked from within TLB flush routines
1317 * that protect themselves with DVPE, so if a lock is
1318 * held by another TC, it'll never be freed.
1319 *
1320 * DVPE/DMT must not be done with interrupts enabled,
1321 * so even so most callers will already have disabled
1322 * them, let's be really careful...
1323 */
1324
1325 local_irq_save(flags);
1326 if (smtc_status & SMTC_TLB_SHARED) {
1327 mtflags = dvpe();
1328 tlb = 0;
1329 } else {
1330 mtflags = dmt();
1331 tlb = cpu_data[cpu].vpe_id;
1332 }
1333 asid = asid_cache(cpu);
1334
1335 do {
1336 if (!((asid += ASID_INC) & ASID_MASK) ) {
1337 if (cpu_has_vtag_icache)
1338 flush_icache_all();
1339 /* Traverse all online CPUs (hack requires contiguous range) */
1340 for_each_online_cpu(i) {
1341 /*
1342 * We don't need to worry about our own CPU, nor those of
1343 * CPUs who don't share our TLB.
1344 */
1345 if ((i != smp_processor_id()) &&
1346 ((smtc_status & SMTC_TLB_SHARED) ||
1347 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1348 settc(cpu_data[i].tc_id);
1349 prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1350 if (!prevhalt) {
1351 write_tc_c0_tchalt(TCHALT_H);
1352 mips_ihb();
1353 }
1354 tcstat = read_tc_c0_tcstatus();
1355 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1356 if (!prevhalt)
1357 write_tc_c0_tchalt(0);
1358 }
1359 }
1360 if (!asid) /* fix version if needed */
1361 asid = ASID_FIRST_VERSION;
1362 local_flush_tlb_all(); /* start new asid cycle */
1363 }
1364 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1365
1366 /*
1367 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1368 */
1369 for_each_online_cpu(i) {
1370 if ((smtc_status & SMTC_TLB_SHARED) ||
1371 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1372 cpu_context(i, mm) = asid_cache(i) = asid;
1373 }
1374
1375 if (smtc_status & SMTC_TLB_SHARED)
1376 evpe(mtflags);
1377 else
1378 emt(mtflags);
1379 local_irq_restore(flags);
1380 }
1381
1382 /*
1383 * Invoked from macros defined in mmu_context.h
1384 * which must already have disabled interrupts
1385 * and done a DVPE or DMT as appropriate.
1386 */
1387
smtc_flush_tlb_asid(unsigned long asid)1388 void smtc_flush_tlb_asid(unsigned long asid)
1389 {
1390 int entry;
1391 unsigned long ehi;
1392
1393 entry = read_c0_wired();
1394
1395 /* Traverse all non-wired entries */
1396 while (entry < current_cpu_data.tlbsize) {
1397 write_c0_index(entry);
1398 ehb();
1399 tlb_read();
1400 ehb();
1401 ehi = read_c0_entryhi();
1402 if ((ehi & ASID_MASK) == asid) {
1403 /*
1404 * Invalidate only entries with specified ASID,
1405 * makiing sure all entries differ.
1406 */
1407 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1408 write_c0_entrylo0(0);
1409 write_c0_entrylo1(0);
1410 mtc0_tlbw_hazard();
1411 tlb_write_indexed();
1412 }
1413 entry++;
1414 }
1415 write_c0_index(PARKED_INDEX);
1416 tlbw_use_hazard();
1417 }
1418
1419 /*
1420 * Support for single-threading cache flush operations.
1421 */
1422
1423 static int halt_state_save[NR_CPUS];
1424
1425 /*
1426 * To really, really be sure that nothing is being done
1427 * by other TCs, halt them all. This code assumes that
1428 * a DVPE has already been done, so while their Halted
1429 * state is theoretically architecturally unstable, in
1430 * practice, it's not going to change while we're looking
1431 * at it.
1432 */
1433
smtc_cflush_lockdown(void)1434 void smtc_cflush_lockdown(void)
1435 {
1436 int cpu;
1437
1438 for_each_online_cpu(cpu) {
1439 if (cpu != smp_processor_id()) {
1440 settc(cpu_data[cpu].tc_id);
1441 halt_state_save[cpu] = read_tc_c0_tchalt();
1442 write_tc_c0_tchalt(TCHALT_H);
1443 }
1444 }
1445 mips_ihb();
1446 }
1447
1448 /* It would be cheating to change the cpu_online states during a flush! */
1449
smtc_cflush_release(void)1450 void smtc_cflush_release(void)
1451 {
1452 int cpu;
1453
1454 /*
1455 * Start with a hazard barrier to ensure
1456 * that all CACHE ops have played through.
1457 */
1458 mips_ihb();
1459
1460 for_each_online_cpu(cpu) {
1461 if (cpu != smp_processor_id()) {
1462 settc(cpu_data[cpu].tc_id);
1463 write_tc_c0_tchalt(halt_state_save[cpu]);
1464 }
1465 }
1466 mips_ihb();
1467 }
1468