1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5 #include "intel_de.h"
6 #include "intel_display_types.h"
7 #include "intel_fb.h"
8 #include "skl_scaler.h"
9 #include "skl_universal_plane.h"
10
11 /*
12 * The hardware phase 0.0 refers to the center of the pixel.
13 * We want to start from the top/left edge which is phase
14 * -0.5. That matches how the hardware calculates the scaling
15 * factors (from top-left of the first pixel to bottom-right
16 * of the last pixel, as opposed to the pixel centers).
17 *
18 * For 4:2:0 subsampled chroma planes we obviously have to
19 * adjust that so that the chroma sample position lands in
20 * the right spot.
21 *
22 * Note that for packed YCbCr 4:2:2 formats there is no way to
23 * control chroma siting. The hardware simply replicates the
24 * chroma samples for both of the luma samples, and thus we don't
25 * actually get the expected MPEG2 chroma siting convention :(
26 * The same behaviour is observed on pre-SKL platforms as well.
27 *
28 * Theory behind the formula (note that we ignore sub-pixel
29 * source coordinates):
30 * s = source sample position
31 * d = destination sample position
32 *
33 * Downscaling 4:1:
34 * -0.5
35 * | 0.0
36 * | | 1.5 (initial phase)
37 * | | |
38 * v v v
39 * | s | s | s | s |
40 * | d |
41 *
42 * Upscaling 1:4:
43 * -0.5
44 * | -0.375 (initial phase)
45 * | | 0.0
46 * | | |
47 * v v v
48 * | s |
49 * | d | d | d | d |
50 */
skl_scaler_calc_phase(int sub,int scale,bool chroma_cosited)51 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
52 {
53 int phase = -0x8000;
54 u16 trip = 0;
55
56 if (chroma_cosited)
57 phase += (sub - 1) * 0x8000 / sub;
58
59 phase += scale / (2 * sub);
60
61 /*
62 * Hardware initial phase limited to [-0.5:1.5].
63 * Since the max hardware scale factor is 3.0, we
64 * should never actually excdeed 1.0 here.
65 */
66 WARN_ON(phase < -0x8000 || phase > 0x18000);
67
68 if (phase < 0)
69 phase = 0x10000 + phase;
70 else
71 trip = PS_PHASE_TRIP;
72
73 return ((phase >> 2) & PS_PHASE_MASK) | trip;
74 }
75
76 #define SKL_MIN_SRC_W 8
77 #define SKL_MAX_SRC_W 4096
78 #define SKL_MIN_SRC_H 8
79 #define SKL_MAX_SRC_H 4096
80 #define SKL_MIN_DST_W 8
81 #define SKL_MAX_DST_W 4096
82 #define SKL_MIN_DST_H 8
83 #define SKL_MAX_DST_H 4096
84 #define ICL_MAX_SRC_W 5120
85 #define ICL_MAX_SRC_H 4096
86 #define ICL_MAX_DST_W 5120
87 #define ICL_MAX_DST_H 4096
88 #define SKL_MIN_YUV_420_SRC_W 16
89 #define SKL_MIN_YUV_420_SRC_H 16
90
91 static int
skl_update_scaler(struct intel_crtc_state * crtc_state,bool force_detach,unsigned int scaler_user,int * scaler_id,int src_w,int src_h,int dst_w,int dst_h,const struct drm_format_info * format,u64 modifier,bool need_scaler)92 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
93 unsigned int scaler_user, int *scaler_id,
94 int src_w, int src_h, int dst_w, int dst_h,
95 const struct drm_format_info *format,
96 u64 modifier, bool need_scaler)
97 {
98 struct intel_crtc_scaler_state *scaler_state =
99 &crtc_state->scaler_state;
100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
102 const struct drm_display_mode *adjusted_mode =
103 &crtc_state->hw.adjusted_mode;
104
105 /*
106 * Src coordinates are already rotated by 270 degrees for
107 * the 90/270 degree plane rotation cases (to match the
108 * GTT mapping), hence no need to account for rotation here.
109 */
110 if (src_w != dst_w || src_h != dst_h)
111 need_scaler = true;
112
113 /*
114 * Scaling/fitting not supported in IF-ID mode in GEN9+
115 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
116 * Once NV12 is enabled, handle it here while allocating scaler
117 * for NV12.
118 */
119 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
120 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
121 drm_dbg_kms(&dev_priv->drm,
122 "Pipe/Plane scaling not supported with IF-ID mode\n");
123 return -EINVAL;
124 }
125
126 /*
127 * if plane is being disabled or scaler is no more required or force detach
128 * - free scaler binded to this plane/crtc
129 * - in order to do this, update crtc->scaler_usage
130 *
131 * Here scaler state in crtc_state is set free so that
132 * scaler can be assigned to other user. Actual register
133 * update to free the scaler is done in plane/panel-fit programming.
134 * For this purpose crtc/plane_state->scaler_id isn't reset here.
135 */
136 if (force_detach || !need_scaler) {
137 if (*scaler_id >= 0) {
138 scaler_state->scaler_users &= ~(1 << scaler_user);
139 scaler_state->scalers[*scaler_id].in_use = 0;
140
141 drm_dbg_kms(&dev_priv->drm,
142 "scaler_user index %u.%u: "
143 "Staged freeing scaler id %d scaler_users = 0x%x\n",
144 crtc->pipe, scaler_user, *scaler_id,
145 scaler_state->scaler_users);
146 *scaler_id = -1;
147 }
148 return 0;
149 }
150
151 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
152 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
153 drm_dbg_kms(&dev_priv->drm,
154 "Planar YUV: src dimensions not met\n");
155 return -EINVAL;
156 }
157
158 /* range checks */
159 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
160 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
161 (DISPLAY_VER(dev_priv) >= 11 &&
162 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
163 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
164 (DISPLAY_VER(dev_priv) < 11 &&
165 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
166 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
167 drm_dbg_kms(&dev_priv->drm,
168 "scaler_user index %u.%u: src %ux%u dst %ux%u "
169 "size is out of scaler range\n",
170 crtc->pipe, scaler_user, src_w, src_h,
171 dst_w, dst_h);
172 return -EINVAL;
173 }
174
175 /* mark this plane as a scaler user in crtc_state */
176 scaler_state->scaler_users |= (1 << scaler_user);
177 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
178 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
179 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
180 scaler_state->scaler_users);
181
182 return 0;
183 }
184
skl_update_scaler_crtc(struct intel_crtc_state * crtc_state)185 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
186 {
187 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
188 int width, height;
189
190 if (crtc_state->pch_pfit.enabled) {
191 width = drm_rect_width(&crtc_state->pch_pfit.dst);
192 height = drm_rect_height(&crtc_state->pch_pfit.dst);
193 } else {
194 width = pipe_mode->crtc_hdisplay;
195 height = pipe_mode->crtc_vdisplay;
196 }
197 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
198 SKL_CRTC_INDEX,
199 &crtc_state->scaler_state.scaler_id,
200 drm_rect_width(&crtc_state->pipe_src),
201 drm_rect_height(&crtc_state->pipe_src),
202 width, height, NULL, 0,
203 crtc_state->pch_pfit.enabled);
204 }
205
206 /**
207 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
208 * @crtc_state: crtc's scaler state
209 * @plane_state: atomic plane state to update
210 *
211 * Return
212 * 0 - scaler_usage updated successfully
213 * error - requested scaling cannot be supported or other error condition
214 */
skl_update_scaler_plane(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)215 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
216 struct intel_plane_state *plane_state)
217 {
218 struct intel_plane *intel_plane =
219 to_intel_plane(plane_state->uapi.plane);
220 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
221 struct drm_framebuffer *fb = plane_state->hw.fb;
222 int ret;
223 bool force_detach = !fb || !plane_state->uapi.visible;
224 bool need_scaler = false;
225
226 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
227 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
228 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
229 need_scaler = true;
230
231 ret = skl_update_scaler(crtc_state, force_detach,
232 drm_plane_index(&intel_plane->base),
233 &plane_state->scaler_id,
234 drm_rect_width(&plane_state->uapi.src) >> 16,
235 drm_rect_height(&plane_state->uapi.src) >> 16,
236 drm_rect_width(&plane_state->uapi.dst),
237 drm_rect_height(&plane_state->uapi.dst),
238 fb ? fb->format : NULL,
239 fb ? fb->modifier : 0,
240 need_scaler);
241
242 if (ret || plane_state->scaler_id < 0)
243 return ret;
244
245 /* check colorkey */
246 if (plane_state->ckey.flags) {
247 drm_dbg_kms(&dev_priv->drm,
248 "[PLANE:%d:%s] scaling with color key not allowed",
249 intel_plane->base.base.id,
250 intel_plane->base.name);
251 return -EINVAL;
252 }
253
254 /* Check src format */
255 switch (fb->format->format) {
256 case DRM_FORMAT_RGB565:
257 case DRM_FORMAT_XBGR8888:
258 case DRM_FORMAT_XRGB8888:
259 case DRM_FORMAT_ABGR8888:
260 case DRM_FORMAT_ARGB8888:
261 case DRM_FORMAT_XRGB2101010:
262 case DRM_FORMAT_XBGR2101010:
263 case DRM_FORMAT_ARGB2101010:
264 case DRM_FORMAT_ABGR2101010:
265 case DRM_FORMAT_YUYV:
266 case DRM_FORMAT_YVYU:
267 case DRM_FORMAT_UYVY:
268 case DRM_FORMAT_VYUY:
269 case DRM_FORMAT_NV12:
270 case DRM_FORMAT_XYUV8888:
271 case DRM_FORMAT_P010:
272 case DRM_FORMAT_P012:
273 case DRM_FORMAT_P016:
274 case DRM_FORMAT_Y210:
275 case DRM_FORMAT_Y212:
276 case DRM_FORMAT_Y216:
277 case DRM_FORMAT_XVYU2101010:
278 case DRM_FORMAT_XVYU12_16161616:
279 case DRM_FORMAT_XVYU16161616:
280 break;
281 case DRM_FORMAT_XBGR16161616F:
282 case DRM_FORMAT_ABGR16161616F:
283 case DRM_FORMAT_XRGB16161616F:
284 case DRM_FORMAT_ARGB16161616F:
285 if (DISPLAY_VER(dev_priv) >= 11)
286 break;
287 fallthrough;
288 default:
289 drm_dbg_kms(&dev_priv->drm,
290 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
291 intel_plane->base.base.id, intel_plane->base.name,
292 fb->base.id, fb->format->format);
293 return -EINVAL;
294 }
295
296 return 0;
297 }
298
glk_coef_tap(int i)299 static int glk_coef_tap(int i)
300 {
301 return i % 7;
302 }
303
glk_nearest_filter_coef(int t)304 static u16 glk_nearest_filter_coef(int t)
305 {
306 return t == 3 ? 0x0800 : 0x3000;
307 }
308
309 /*
310 * Theory behind setting nearest-neighbor integer scaling:
311 *
312 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
313 * The letter represents the filter tap (D is the center tap) and the number
314 * represents the coefficient set for a phase (0-16).
315 *
316 * +------------+------------------------+------------------------+
317 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
318 * +------------+------------------------+------------------------+
319 * | 00h | B0 | A0 |
320 * +------------+------------------------+------------------------+
321 * | 01h | D0 | C0 |
322 * +------------+------------------------+------------------------+
323 * | 02h | F0 | E0 |
324 * +------------+------------------------+------------------------+
325 * | 03h | A1 | G0 |
326 * +------------+------------------------+------------------------+
327 * | 04h | C1 | B1 |
328 * +------------+------------------------+------------------------+
329 * | ... | ... | ... |
330 * +------------+------------------------+------------------------+
331 * | 38h | B16 | A16 |
332 * +------------+------------------------+------------------------+
333 * | 39h | D16 | C16 |
334 * +------------+------------------------+------------------------+
335 * | 3Ah | F16 | C16 |
336 * +------------+------------------------+------------------------+
337 * | 3Bh | Reserved | G16 |
338 * +------------+------------------------+------------------------+
339 *
340 * To enable nearest-neighbor scaling: program scaler coefficents with
341 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
342 * SCALER_COEFFICIENT_FORMAT
343 *
344 */
345
glk_program_nearest_filter_coefs(struct drm_i915_private * dev_priv,enum pipe pipe,int id,int set)346 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
347 enum pipe pipe, int id, int set)
348 {
349 int i;
350
351 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
352 PS_COEE_INDEX_AUTO_INC);
353
354 for (i = 0; i < 17 * 7; i += 2) {
355 u32 tmp;
356 int t;
357
358 t = glk_coef_tap(i);
359 tmp = glk_nearest_filter_coef(t);
360
361 t = glk_coef_tap(i + 1);
362 tmp |= glk_nearest_filter_coef(t) << 16;
363
364 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
365 tmp);
366 }
367
368 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
369 }
370
skl_scaler_get_filter_select(enum drm_scaling_filter filter,int set)371 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
372 {
373 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
374 return (PS_FILTER_PROGRAMMED |
375 PS_Y_VERT_FILTER_SELECT(set) |
376 PS_Y_HORZ_FILTER_SELECT(set) |
377 PS_UV_VERT_FILTER_SELECT(set) |
378 PS_UV_HORZ_FILTER_SELECT(set));
379 }
380
381 return PS_FILTER_MEDIUM;
382 }
383
skl_scaler_setup_filter(struct drm_i915_private * dev_priv,enum pipe pipe,int id,int set,enum drm_scaling_filter filter)384 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
385 int id, int set, enum drm_scaling_filter filter)
386 {
387 switch (filter) {
388 case DRM_SCALING_FILTER_DEFAULT:
389 break;
390 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
391 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
392 break;
393 default:
394 MISSING_CASE(filter);
395 }
396 }
397
skl_pfit_enable(const struct intel_crtc_state * crtc_state)398 void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
399 {
400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
402 const struct intel_crtc_scaler_state *scaler_state =
403 &crtc_state->scaler_state;
404 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
405 u16 uv_rgb_hphase, uv_rgb_vphase;
406 enum pipe pipe = crtc->pipe;
407 int width = drm_rect_width(dst);
408 int height = drm_rect_height(dst);
409 int x = dst->x1;
410 int y = dst->y1;
411 int hscale, vscale;
412 struct drm_rect src;
413 int id;
414 u32 ps_ctrl;
415
416 if (!crtc_state->pch_pfit.enabled)
417 return;
418
419 if (drm_WARN_ON(&dev_priv->drm,
420 crtc_state->scaler_state.scaler_id < 0))
421 return;
422
423 drm_rect_init(&src, 0, 0,
424 drm_rect_width(&crtc_state->pipe_src) << 16,
425 drm_rect_height(&crtc_state->pipe_src) << 16);
426
427 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
428 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
429
430 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
431 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
432
433 id = scaler_state->scaler_id;
434
435 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
436 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
437
438 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
439 crtc_state->hw.scaling_filter);
440
441 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
442
443 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
444 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
445 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
446 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
447 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
448 x << 16 | y);
449 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
450 width << 16 | height);
451 }
452
453 void
skl_program_plane_scaler(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)454 skl_program_plane_scaler(struct intel_plane *plane,
455 const struct intel_crtc_state *crtc_state,
456 const struct intel_plane_state *plane_state)
457 {
458 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
459 const struct drm_framebuffer *fb = plane_state->hw.fb;
460 enum pipe pipe = plane->pipe;
461 int scaler_id = plane_state->scaler_id;
462 const struct intel_scaler *scaler =
463 &crtc_state->scaler_state.scalers[scaler_id];
464 int crtc_x = plane_state->uapi.dst.x1;
465 int crtc_y = plane_state->uapi.dst.y1;
466 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
467 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
468 u16 y_hphase, uv_rgb_hphase;
469 u16 y_vphase, uv_rgb_vphase;
470 int hscale, vscale;
471 u32 ps_ctrl;
472
473 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
474 &plane_state->uapi.dst,
475 0, INT_MAX);
476 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
477 &plane_state->uapi.dst,
478 0, INT_MAX);
479
480 /* TODO: handle sub-pixel coordinates */
481 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
482 !icl_is_hdr_plane(dev_priv, plane->id)) {
483 y_hphase = skl_scaler_calc_phase(1, hscale, false);
484 y_vphase = skl_scaler_calc_phase(1, vscale, false);
485
486 /* MPEG2 chroma siting convention */
487 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
488 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
489 } else {
490 /* not used */
491 y_hphase = 0;
492 y_vphase = 0;
493
494 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
495 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
496 }
497
498 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
499 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
500
501 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
502 plane_state->hw.scaling_filter);
503
504 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
505 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
506 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
507 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
508 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
509 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
510 (crtc_x << 16) | crtc_y);
511 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
512 (crtc_w << 16) | crtc_h);
513 }
514
skl_detach_scaler(struct intel_crtc * crtc,int id)515 static void skl_detach_scaler(struct intel_crtc *crtc, int id)
516 {
517 struct drm_device *dev = crtc->base.dev;
518 struct drm_i915_private *dev_priv = to_i915(dev);
519
520 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
521 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
522 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
523 }
524
525 /*
526 * This function detaches (aka. unbinds) unused scalers in hardware
527 */
skl_detach_scalers(const struct intel_crtc_state * crtc_state)528 void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
529 {
530 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
531 const struct intel_crtc_scaler_state *scaler_state =
532 &crtc_state->scaler_state;
533 int i;
534
535 /* loop through and disable scalers that aren't in use */
536 for (i = 0; i < crtc->num_scalers; i++) {
537 if (!scaler_state->scalers[i].in_use)
538 skl_detach_scaler(crtc, i);
539 }
540 }
541
skl_scaler_disable(const struct intel_crtc_state * old_crtc_state)542 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
543 {
544 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
545 int i;
546
547 for (i = 0; i < crtc->num_scalers; i++)
548 skl_detach_scaler(crtc, i);
549 }
550