1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #ifndef __DML2_DISPLAY_MODE_VBA_H__
28 #define __DML2_DISPLAY_MODE_VBA_H__
29 
30 struct display_mode_lib;
31 
32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
33 
34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
35 
36 dml_get_attr_decl(clk_dcf_deepsleep);
37 dml_get_attr_decl(wm_urgent);
38 dml_get_attr_decl(wm_memory_trip);
39 dml_get_attr_decl(wm_writeback_urgent);
40 dml_get_attr_decl(wm_stutter_exit);
41 dml_get_attr_decl(wm_stutter_enter_exit);
42 dml_get_attr_decl(wm_z8_stutter_exit);
43 dml_get_attr_decl(wm_z8_stutter_enter_exit);
44 dml_get_attr_decl(stutter_efficiency_z8);
45 dml_get_attr_decl(stutter_num_bursts_z8);
46 dml_get_attr_decl(wm_dram_clock_change);
47 dml_get_attr_decl(wm_writeback_dram_clock_change);
48 dml_get_attr_decl(stutter_efficiency_no_vblank);
49 dml_get_attr_decl(stutter_efficiency);
50 dml_get_attr_decl(stutter_period);
51 dml_get_attr_decl(urgent_latency);
52 dml_get_attr_decl(urgent_extra_latency);
53 dml_get_attr_decl(nonurgent_latency);
54 dml_get_attr_decl(dram_clock_change_latency);
55 dml_get_attr_decl(dispclk_calculated);
56 dml_get_attr_decl(total_data_read_bw);
57 dml_get_attr_decl(return_bw);
58 dml_get_attr_decl(tcalc);
59 dml_get_attr_decl(fraction_of_urgent_bandwidth);
60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
61 dml_get_attr_decl(cstate_max_cap_mode);
62 dml_get_attr_decl(comp_buffer_size_kbytes);
63 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
65 dml_get_attr_decl(meta_chunk_size_in_kbyte);
66 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
67 dml_get_attr_decl(min_meta_chunk_size_in_byte);
68 dml_get_attr_decl(fclk_watermark);
69 dml_get_attr_decl(usr_retraining_watermark);
70 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
71 dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
72 dml_get_attr_decl(comp_buffer_reserved_space_zs);
73 dml_get_attr_decl(unbounded_request_enabled);
74 
75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
76 
77 dml_get_pipe_attr_decl(dsc_delay);
78 dml_get_pipe_attr_decl(dppclk_calculated);
79 dml_get_pipe_attr_decl(dscclk_calculated);
80 dml_get_pipe_attr_decl(min_ttu_vblank);
81 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
82 dml_get_pipe_attr_decl(vratio_prefetch_l);
83 dml_get_pipe_attr_decl(vratio_prefetch_c);
84 dml_get_pipe_attr_decl(dst_x_after_scaler);
85 dml_get_pipe_attr_decl(dst_y_after_scaler);
86 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
87 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
88 dml_get_pipe_attr_decl(dst_y_prefetch);
89 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
90 dml_get_pipe_attr_decl(dst_y_per_row_flip);
91 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
92 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
93 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
94 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
95 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
96 dml_get_pipe_attr_decl(swath_height_l);
97 dml_get_pipe_attr_decl(swath_height_c);
98 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
99 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
100 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
101 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
102 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
103 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
104 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
105 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
106 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
107 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
108 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
109 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
110 dml_get_pipe_attr_decl(pte_buffer_mode);
111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
115 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
116 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
117 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
118 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
119 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
120 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
121 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
122 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
123 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
124 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
125 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
126 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
127 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
128 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
129 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
130 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
133 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
134 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
135 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
136 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
137 
138 dml_get_pipe_attr_decl(vstartup);
139 dml_get_pipe_attr_decl(vupdate_offset);
140 dml_get_pipe_attr_decl(vupdate_width);
141 dml_get_pipe_attr_decl(vready_offset);
142 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
143 dml_get_pipe_attr_decl(min_dst_y_next_start);
144 dml_get_pipe_attr_decl(vstartup_calculated);
145 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
146 
147 double get_total_immediate_flip_bytes(
148 		struct display_mode_lib *mode_lib,
149 		const display_e2e_pipe_params_st *pipes,
150 		unsigned int num_pipes);
151 double get_total_immediate_flip_bw(
152 		struct display_mode_lib *mode_lib,
153 		const display_e2e_pipe_params_st *pipes,
154 		unsigned int num_pipes);
155 double get_total_prefetch_bw(
156 		struct display_mode_lib *mode_lib,
157 		const display_e2e_pipe_params_st *pipes,
158 		unsigned int num_pipes);
159 unsigned int dml_get_voltage_level(
160 		struct display_mode_lib *mode_lib,
161 		const display_e2e_pipe_params_st *pipes,
162 		unsigned int num_pipes);
163 
164 unsigned int get_total_surface_size_in_mall_bytes(
165 		struct display_mode_lib *mode_lib,
166 		const display_e2e_pipe_params_st *pipes,
167 		unsigned int num_pipes);
168 
169 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
170 		const display_e2e_pipe_params_st *pipes,
171 		unsigned int num_pipes,
172 		unsigned int pipe_idx);
173 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
174 
175 void Calculate256BBlockSizes(
176 		enum source_format_class SourcePixelFormat,
177 		enum dm_swizzle_mode SurfaceTiling,
178 		unsigned int BytePerPixelY,
179 		unsigned int BytePerPixelC,
180 		unsigned int *BlockHeight256BytesY,
181 		unsigned int *BlockHeight256BytesC,
182 		unsigned int *BlockWidth256BytesY,
183 		unsigned int *BlockWidth256BytesC);
184 
185 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
186 	unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
187 	double dummy_single_array[2][DC__NUM_DPP__MAX];
188 	unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
189 	double dummy_double_array[2][DC__NUM_DPP__MAX];
190 	bool dummy_boolean_array[DC__NUM_DPP__MAX];
191 	bool dummy_boolean;
192 	bool dummy_boolean2;
193 	enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
194 	DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
195 	bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
196 	unsigned int ReorderBytes;
197 	unsigned int VMDataOnlyReturnBW;
198 	double HostVMInefficiencyFactor;
199 	DmlPipe myPipe;
200 	SOCParametersList mmSOCParameters;
201 	double dummy_unit_vector[DC__NUM_DPP__MAX];
202 	double dummy_single[2];
203 	enum clock_change_support dummy_dramchange_support;
204 	enum dm_fclock_change_support dummy_fclkchange_support;
205 	bool dummy_USRRetrainingSupport;
206 };
207 
208 struct dml32_ModeSupportAndSystemConfigurationFull {
209 	unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
210 	double dummy_double_array[2][DC__NUM_DPP__MAX];
211 	DmlPipe SurfParameters[DC__NUM_DPP__MAX];
212 	double dummy_single[5];
213 	double dummy_single2[5];
214 	SOCParametersList mSOCParameters;
215 	unsigned int MaximumSwathWidthSupportLuma;
216 	unsigned int MaximumSwathWidthSupportChroma;
217 	double DSTYAfterScaler[DC__NUM_DPP__MAX];
218 	double DSTXAfterScaler[DC__NUM_DPP__MAX];
219 	double MaxTotalVActiveRDBandwidth;
220 	bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
221 	enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
222 	DmlPipe myPipe;
223 	unsigned int dummy_integer[4];
224 	unsigned int TotalNumberOfActiveOTG;
225 	unsigned int TotalNumberOfActiveHDMIFRL;
226 	unsigned int TotalNumberOfActiveDP2p0;
227 	unsigned int TotalNumberOfActiveDP2p0Outputs;
228 	unsigned int TotalDSCUnitsRequired;
229 	unsigned int ReorderingBytes;
230 	unsigned int TotalSlots;
231 	unsigned int NumberOfDPPDSC;
232 	unsigned int NumberOfDPPNoDSC;
233 	unsigned int NextPrefetchModeState;
234 	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
235 	bool MPCCombineMethodAsPossible;
236 	bool FullFrameMALLPStateMethod;
237 	bool SubViewportMALLPStateMethod;
238 	bool PhantomPipeMALLPStateMethod;
239 	bool NoChroma;
240 	bool TotalAvailablePipesSupportNoDSC;
241 	bool TotalAvailablePipesSupportDSC;
242 	enum odm_combine_mode ODMModeNoDSC;
243 	enum odm_combine_mode ODMModeDSC;
244 	double RequiredDISPCLKPerSurfaceNoDSC;
245 	double RequiredDISPCLKPerSurfaceDSC;
246 	double BWOfNonCombinedSurfaceOfMaximumBandwidth;
247 	double VMDataOnlyReturnBWPerState;
248 	double HostVMInefficiencyFactor;
249 	bool dummy_boolean[2];
250 };
251 
252 struct dummy_vars {
253 	struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
254 	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
255 	struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
256 };
257 
258 struct vba_vars_st {
259 	ip_params_st ip;
260 	soc_bounding_box_st soc;
261 
262 	int maxMpcComb;
263 	bool UseMaximumVStartup;
264 
265 	double WritebackDISPCLK;
266 	double DPPCLKUsingSingleDPPLuma;
267 	double DPPCLKUsingSingleDPPChroma;
268 	double DISPCLKWithRamping;
269 	double DISPCLKWithoutRamping;
270 	double GlobalDPPCLK;
271 	double DISPCLKWithRampingRoundedToDFSGranularity;
272 	double DISPCLKWithoutRampingRoundedToDFSGranularity;
273 	double MaxDispclkRoundedToDFSGranularity;
274 	bool DCCEnabledAnyPlane;
275 	double ReturnBandwidthToDCN;
276 	unsigned int TotalActiveDPP;
277 	unsigned int TotalDCCActiveDPP;
278 	double UrgentRoundTripAndOutOfOrderLatency;
279 	double StutterPeriod;
280 	double FrameTimeForMinFullDETBufferingTime;
281 	double AverageReadBandwidth;
282 	double TotalRowReadBandwidth;
283 	double PartOfBurstThatFitsInROB;
284 	double StutterBurstTime;
285 	unsigned int NextPrefetchMode;
286 	double NextMaxVStartup;
287 	double VBlankTime;
288 	double SmallestVBlank;
289 	enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
290 	double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
291 	double EffectiveDETPlusLBLinesLuma;
292 	double EffectiveDETPlusLBLinesChroma;
293 	double UrgentLatencySupportUsLuma;
294 	double UrgentLatencySupportUsChroma;
295 	unsigned int DSCFormatFactor;
296 
297 	bool DummyPStateCheck;
298 	bool DRAMClockChangeSupportsVActive;
299 	bool PrefetchModeSupported;
300 	bool PrefetchAndImmediateFlipSupported;
301 	enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
302 	double XFCRemoteSurfaceFlipDelay;
303 	double TInitXFill;
304 	double TslvChk;
305 	double SrcActiveDrainRate;
306 	bool ImmediateFlipSupported;
307 	enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
308 
309 	bool PrefetchERROR;
310 
311 	unsigned int VStartupLines;
312 	unsigned int ActiveDPPs;
313 	unsigned int LBLatencyHidingSourceLinesY;
314 	unsigned int LBLatencyHidingSourceLinesC;
315 	double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state
316 	double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
317 	double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
318 	double MinActiveDRAMClockChangeMargin;
319 	double InitFillLevel;
320 	double FinalFillMargin;
321 	double FinalFillLevel;
322 	double RemainingFillLevel;
323 	double TFinalxFill;
324 
325 	//
326 	// SOC Bounding Box Parameters
327 	//
328 	double SRExitTime;
329 	double SREnterPlusExitTime;
330 	double UrgentLatencyPixelDataOnly;
331 	double UrgentLatencyPixelMixedWithVMData;
332 	double UrgentLatencyVMDataOnly;
333 	double UrgentLatency; // max of the above three
334 	double USRRetrainingLatency;
335 	double SMNLatency;
336 	double FCLKChangeLatency;
337 	unsigned int MALLAllocatedForDCNFinal;
338 	double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
339 	double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
340 	double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
341 	double WritebackLatency;
342 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
343 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
344 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
345 	double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
346 	double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
347 	double NumberOfChannels;
348 	double DRAMChannelWidth;
349 	double FabricDatapathToDCNDataReturn;
350 	double ReturnBusWidth;
351 	double Downspreading;
352 	double DISPCLKDPPCLKDSCCLKDownSpreading;
353 	double DISPCLKDPPCLKVCOSpeed;
354 	double RoundTripPingLatencyCycles;
355 	double UrgentOutOfOrderReturnPerChannel;
356 	double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
357 	double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
358 	double UrgentOutOfOrderReturnPerChannelVMDataOnly;
359 	unsigned int VMMPageSize;
360 	double DRAMClockChangeLatency;
361 	double XFCBusTransportTime;
362 	bool UseUrgentBurstBandwidth;
363 	double XFCXBUFLatencyTolerance;
364 
365 	//
366 	// IP Parameters
367 	//
368 	unsigned int ROBBufferSizeInKByte;
369 	unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
370 	double DETBufferSizeInTime;
371 	unsigned int DPPOutputBufferPixels;
372 	unsigned int OPPOutputBufferLines;
373 	unsigned int PixelChunkSizeInKByte;
374 	double ReturnBW;
375 	bool GPUVMEnable;
376 	bool HostVMEnable;
377 	unsigned int GPUVMMaxPageTableLevels;
378 	unsigned int HostVMMaxPageTableLevels;
379 	unsigned int HostVMCachedPageTableLevels;
380 	unsigned int OverrideGPUVMPageTableLevels;
381 	unsigned int OverrideHostVMPageTableLevels;
382 	unsigned int MetaChunkSize;
383 	unsigned int MinMetaChunkSizeBytes;
384 	unsigned int WritebackChunkSize;
385 	bool ODMCapability;
386 	unsigned int NumberOfDSC;
387 	unsigned int LineBufferSize;
388 	unsigned int MaxLineBufferLines;
389 	unsigned int WritebackInterfaceLumaBufferSize;
390 	unsigned int WritebackInterfaceChromaBufferSize;
391 	unsigned int WritebackChromaLineBufferWidth;
392 	enum writeback_config WritebackConfiguration;
393 	double MaxDCHUBToPSCLThroughput;
394 	double MaxPSCLToLBThroughput;
395 	unsigned int PTEBufferSizeInRequestsLuma;
396 	unsigned int PTEBufferSizeInRequestsChroma;
397 	double DISPCLKRampingMargin;
398 	unsigned int MaxInterDCNTileRepeaters;
399 	bool XFCSupported;
400 	double XFCSlvChunkSize;
401 	double XFCFillBWOverhead;
402 	double XFCFillConstant;
403 	double XFCTSlvVupdateOffset;
404 	double XFCTSlvVupdateWidth;
405 	double XFCTSlvVreadyOffset;
406 	double DPPCLKDelaySubtotal;
407 	double DPPCLKDelaySCL;
408 	double DPPCLKDelaySCLLBOnly;
409 	double DPPCLKDelayCNVCFormater;
410 	double DPPCLKDelayCNVCCursor;
411 	double DISPCLKDelaySubtotal;
412 	bool ProgressiveToInterlaceUnitInOPP;
413 	unsigned int CompressedBufferSegmentSizeInkByteFinal;
414 	unsigned int CompbufReservedSpace64B;
415 	unsigned int CompbufReservedSpaceZs;
416 	unsigned int LineBufferSizeFinal;
417 	unsigned int MaximumPixelsPerLinePerDSCUnit;
418 	unsigned int AlphaPixelChunkSizeInKByte;
419 	double MinPixelChunkSizeBytes;
420 	unsigned int DCCMetaBufferSizeBytes;
421 	// Pipe/Plane Parameters
422 	int VoltageLevel;
423 	double FabricClock;
424 	double DRAMSpeed;
425 	double DISPCLK;
426 	double SOCCLK;
427 	double DCFCLK;
428 	unsigned int MaxTotalDETInKByte;
429 	unsigned int MinCompressedBufferSizeInKByte;
430 	unsigned int NumberOfActiveSurfaces;
431 	bool ViewportStationary[DC__NUM_DPP__MAX];
432 	unsigned int RefreshRate[DC__NUM_DPP__MAX];
433 	double       OutputBPP[DC__NUM_DPP__MAX];
434 	unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
435 	bool SynchronizeTimingsFinal;
436 	bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
437 	bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
438 	unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
439 	unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
440 	enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
441 	bool DRRDisplay[DC__NUM_DPP__MAX];
442 	bool PteBufferMode[DC__NUM_DPP__MAX];
443 	enum dm_output_type OutputType[DC__NUM_DPP__MAX];
444 	enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
445 
446 	unsigned int NumberOfActivePlanes;
447 	unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
448 	unsigned int ViewportWidth[DC__NUM_DPP__MAX];
449 	unsigned int ViewportHeight[DC__NUM_DPP__MAX];
450 	unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
451 	unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
452 	unsigned int PitchY[DC__NUM_DPP__MAX];
453 	unsigned int PitchC[DC__NUM_DPP__MAX];
454 	double HRatio[DC__NUM_DPP__MAX];
455 	double VRatio[DC__NUM_DPP__MAX];
456 	unsigned int htaps[DC__NUM_DPP__MAX];
457 	unsigned int vtaps[DC__NUM_DPP__MAX];
458 	unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
459 	unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
460 	unsigned int HTotal[DC__NUM_DPP__MAX];
461 	unsigned int VTotal[DC__NUM_DPP__MAX];
462 	unsigned int VTotal_Max[DC__NUM_DPP__MAX];
463 	unsigned int VTotal_Min[DC__NUM_DPP__MAX];
464 	int DPPPerPlane[DC__NUM_DPP__MAX];
465 	double PixelClock[DC__NUM_DPP__MAX];
466 	double PixelClockBackEnd[DC__NUM_DPP__MAX];
467 	bool DCCEnable[DC__NUM_DPP__MAX];
468 	bool FECEnable[DC__NUM_DPP__MAX];
469 	unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
470 	unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
471 	enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
472 	enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
473 	bool WritebackEnable[DC__NUM_DPP__MAX];
474 	unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
475 	double WritebackDestinationWidth[DC__NUM_DPP__MAX];
476 	double WritebackDestinationHeight[DC__NUM_DPP__MAX];
477 	double WritebackSourceHeight[DC__NUM_DPP__MAX];
478 	enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
479 	unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
480 	unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
481 	unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
482 	unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
483 	double WritebackHRatio[DC__NUM_DPP__MAX];
484 	double WritebackVRatio[DC__NUM_DPP__MAX];
485 	unsigned int HActive[DC__NUM_DPP__MAX];
486 	unsigned int VActive[DC__NUM_DPP__MAX];
487 	bool Interlace[DC__NUM_DPP__MAX];
488 	enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
489 	unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
490 	bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
491 	int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
492 	unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
493 	double DCCRate[DC__NUM_DPP__MAX];
494 	double AverageDCCCompressionRate;
495 	enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
496 	double OutputBpp[DC__NUM_DPP__MAX];
497 	bool DSCEnabled[DC__NUM_DPP__MAX];
498 	unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
499 	enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
500 	enum output_encoder_class Output[DC__NUM_DPP__MAX];
501 	bool skip_dio_check[DC__NUM_DPP__MAX];
502 	unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
503 	bool SynchronizedVBlank;
504 	unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
505 	unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
506 	unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
507 	bool XFCEnabled[DC__NUM_DPP__MAX];
508 	bool ScalerEnabled[DC__NUM_DPP__MAX];
509 	unsigned int VBlankNom[DC__NUM_DPP__MAX];
510 	bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
511 
512 	// Intermediates/Informational
513 	bool ImmediateFlipSupport;
514 	unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
515 	unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
516 	unsigned int SwathHeightY[DC__NUM_DPP__MAX];
517 	unsigned int SwathHeightC[DC__NUM_DPP__MAX];
518 	unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
519 	double LastPixelOfLineExtraWatermark;
520 	double TotalDataReadBandwidth;
521 	unsigned int TotalActiveWriteback;
522 	unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
523 	unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
524 	double BandwidthAvailableForImmediateFlip;
525 	unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
526 	unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
527 	unsigned int MinPrefetchMode;
528 	unsigned int MaxPrefetchMode;
529 	bool AnyLinesForVMOrRowTooLarge;
530 	double MaxVStartup;
531 	bool IgnoreViewportPositioning;
532 	bool ErrorResult[DC__NUM_DPP__MAX];
533 	//
534 	// Calculated dml_ml->vba.Outputs
535 	//
536 	double DCFCLKDeepSleep;
537 	double UrgentWatermark;
538 	double UrgentExtraLatency;
539 	double WritebackUrgentWatermark;
540 	double StutterExitWatermark;
541 	double StutterEnterPlusExitWatermark;
542 	double DRAMClockChangeWatermark;
543 	double WritebackDRAMClockChangeWatermark;
544 	double StutterEfficiency;
545 	double StutterEfficiencyNotIncludingVBlank;
546 	double NonUrgentLatencyTolerance;
547 	double MinActiveDRAMClockChangeLatencySupported;
548 	double Z8StutterEfficiencyBestCase;
549 	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
550 	double Z8StutterEfficiencyNotIncludingVBlankBestCase;
551 	double StutterPeriodBestCase;
552 	Watermarks      Watermark;
553 	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
554 	unsigned int CompBufReservedSpaceKBytes;
555 	unsigned int CompBufReservedSpace64B;
556 	unsigned int CompBufReservedSpaceZs;
557 	bool CompBufReservedSpaceNeedAdjustment;
558 
559 	// These are the clocks calcuated by the library but they are not actually
560 	// used explicitly. They are fetched by tests and then possibly used. The
561 	// ultimate values to use are the ones specified by the parameters to DML
562 	double DISPCLK_calculated;
563 	double DPPCLK_calculated[DC__NUM_DPP__MAX];
564 
565 	bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
566 
567 	bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
568 	bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
569 	unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
570 	double VUpdateWidthPix[DC__NUM_DPP__MAX];
571 	double VReadyOffsetPix[DC__NUM_DPP__MAX];
572 
573 	unsigned int TotImmediateFlipBytes;
574 	double TCalc;
575 
576 	display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
577 	unsigned int cache_num_pipes;
578 	unsigned int pipe_plane[DC__NUM_DPP__MAX];
579 
580 	/* vba mode support */
581 	/*inputs*/
582 	bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
583 	double MaxHSCLRatio;
584 	double MaxVSCLRatio;
585 	unsigned int MaxNumWriteback;
586 	bool WritebackLumaAndChromaScalingSupported;
587 	bool Cursor64BppSupport;
588 	double DCFCLKPerState[DC__VOLTAGE_STATES];
589 	double DCFCLKState[DC__VOLTAGE_STATES][2];
590 	double FabricClockPerState[DC__VOLTAGE_STATES];
591 	double SOCCLKPerState[DC__VOLTAGE_STATES];
592 	double PHYCLKPerState[DC__VOLTAGE_STATES];
593 	double DTBCLKPerState[DC__VOLTAGE_STATES];
594 	double MaxDppclk[DC__VOLTAGE_STATES];
595 	double MaxDSCCLK[DC__VOLTAGE_STATES];
596 	double DRAMSpeedPerState[DC__VOLTAGE_STATES];
597 	double MaxDispclk[DC__VOLTAGE_STATES];
598 	int VoltageOverrideLevel;
599 	double PHYCLKD32PerState[DC__VOLTAGE_STATES];
600 
601 	/*outputs*/
602 	bool ScaleRatioAndTapsSupport;
603 	bool SourceFormatPixelAndScanSupport;
604 	double TotalBandwidthConsumedGBytePerSecond;
605 	bool DCCEnabledInAnyPlane;
606 	bool WritebackLatencySupport;
607 	bool WritebackModeSupport;
608 	bool Writeback10bpc420Supported;
609 	bool BandwidthSupport[DC__VOLTAGE_STATES];
610 	unsigned int TotalNumberOfActiveWriteback;
611 	double CriticalPoint;
612 	double ReturnBWToDCNPerState;
613 	bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
614 	bool prefetch_vm_bw_valid;
615 	bool prefetch_row_bw_valid;
616 	bool NumberOfOTGSupport;
617 	bool NonsupportedDSCInputBPC;
618 	bool WritebackScaleRatioAndTapsSupport;
619 	bool CursorSupport;
620 	bool PitchSupport;
621 	enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
622 
623 	/* Mode Support Reason */
624 	bool P2IWith420;
625 	bool DSCOnlyIfNecessaryWithBPP;
626 	bool DSC422NativeNotSupported;
627 	bool LinkRateDoesNotMatchDPVersion;
628 	bool LinkRateForMultistreamNotIndicated;
629 	bool BPPForMultistreamNotIndicated;
630 	bool MultistreamWithHDMIOreDP;
631 	bool MSOOrODMSplitWithNonDPLink;
632 	bool NotEnoughLanesForMSO;
633 	bool ViewportExceedsSurface;
634 
635 	bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
636 	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
637 	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
638 	bool InvalidCombinationOfMALLUseForPState;
639 
640 	enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
641 	double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
642 	double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
643 	double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
644 	double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
645 	double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
646 	double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
647 	double MetaRowBytesThisState[DC__NUM_DPP__MAX];
648 	bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
649 	bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
650 	bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
651 	bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
652 
653 	unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
654 	double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
655 	unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
656 	unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
657 	unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
658 	unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
659 	bool ImmediateFlipRequiredFinal;
660 	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
661 	bool EnoughWritebackUnits;
662 	bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
663 	bool NumberOfDP2p0Support;
664 	unsigned int MaxNumDP2p0Streams;
665 	unsigned int MaxNumDP2p0Outputs;
666 	enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
667 	enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
668 	double WritebackLineBufferLumaBufferSize;
669 	double WritebackLineBufferChromaBufferSize;
670 	double WritebackMinHSCLRatio;
671 	double WritebackMinVSCLRatio;
672 	double WritebackMaxHSCLRatio;
673 	double WritebackMaxVSCLRatio;
674 	double WritebackMaxHSCLTaps;
675 	double WritebackMaxVSCLTaps;
676 	unsigned int MaxNumDPP;
677 	unsigned int MaxNumOTG;
678 	double CursorBufferSize;
679 	double CursorChunkSize;
680 	unsigned int Mode;
681 	double OutputLinkDPLanes[DC__NUM_DPP__MAX];
682 	double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
683 	double ImmediateFlipBW[DC__NUM_DPP__MAX];
684 	double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
685 
686 	double WritebackLumaVExtra;
687 	double WritebackChromaVExtra;
688 	double WritebackRequiredDISPCLK;
689 	double MaximumSwathWidthSupport;
690 	double MaximumSwathWidthInDETBuffer;
691 	double MaximumSwathWidthInLineBuffer;
692 	double MaxDispclkRoundedDownToDFSGranularity;
693 	double MaxDppclkRoundedDownToDFSGranularity;
694 	double PlaneRequiredDISPCLKWithoutODMCombine;
695 	double PlaneRequiredDISPCLKWithODMCombine;
696 	double PlaneRequiredDISPCLK;
697 	double TotalNumberOfActiveOTG;
698 	double FECOverhead;
699 	double EffectiveFECOverhead;
700 	double Outbpp;
701 	unsigned int OutbppDSC;
702 	double TotalDSCUnitsRequired;
703 	double bpp;
704 	unsigned int slices;
705 	double SwathWidthGranularityY;
706 	double RoundedUpMaxSwathSizeBytesY;
707 	double SwathWidthGranularityC;
708 	double RoundedUpMaxSwathSizeBytesC;
709 	double EffectiveDETLBLinesLuma;
710 	double EffectiveDETLBLinesChroma;
711 	double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
712 	double PDEAndMetaPTEBytesPerFrameY;
713 	double PDEAndMetaPTEBytesPerFrameC;
714 	unsigned int MetaRowBytesY;
715 	unsigned int MetaRowBytesC;
716 	unsigned int DPTEBytesPerRowC;
717 	unsigned int DPTEBytesPerRowY;
718 	double ExtraLatency;
719 	double TimeCalc;
720 	double TWait;
721 	double MaximumReadBandwidthWithPrefetch;
722 	double MaximumReadBandwidthWithoutPrefetch;
723 	double total_dcn_read_bw_with_flip;
724 	double total_dcn_read_bw_with_flip_no_urgent_burst;
725 	double FractionOfUrgentBandwidth;
726 	double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
727 
728 	/* ms locals */
729 	double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
730 	unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
731 	int NoOfDPPThisState[DC__NUM_DPP__MAX];
732 	enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
733 	double SwathWidthYThisState[DC__NUM_DPP__MAX];
734 	unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
735 	unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
736 	unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
737 	double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
738 	double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
739 	double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
740 	double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
741 	double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
742 	double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
743 	bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
744 	bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
745 	bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
746 	bool PrefetchSupported[DC__VOLTAGE_STATES][2];
747 	bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
748 	double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
749 	bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
750 	bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
751 	unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
752 	unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
753 	bool ModeSupport[DC__VOLTAGE_STATES][2];
754 	double ReturnBWPerState[DC__VOLTAGE_STATES][2];
755 	bool DIOSupport[DC__VOLTAGE_STATES];
756 	bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
757 	bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
758 	bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
759 	double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
760 	bool ROBSupport[DC__VOLTAGE_STATES][2];
761 	//based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
762 	bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
763 	bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
764 	bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
765 	double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
766 	double PrefetchBW[DC__NUM_DPP__MAX];
767 	double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
768 	double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
769 	double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
770 	double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
771 	double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
772 	unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
773 	unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
774 	double PrefillY[DC__NUM_DPP__MAX];
775 	double PrefillC[DC__NUM_DPP__MAX];
776 	double LineTimesForPrefetch[DC__NUM_DPP__MAX];
777 	double LinesForMetaPTE[DC__NUM_DPP__MAX];
778 	double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
779 	double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
780 	double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
781 	double BytePerPixelInDETY[DC__NUM_DPP__MAX];
782 	double BytePerPixelInDETC[DC__NUM_DPP__MAX];
783 	bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
784 	unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
785 	double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
786 	double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
787 	double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
788 	bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
789 	unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
790 	unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
791 	unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
792 	unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
793 	double MaxSwathHeightY[DC__NUM_DPP__MAX];
794 	double MaxSwathHeightC[DC__NUM_DPP__MAX];
795 	double MinSwathHeightY[DC__NUM_DPP__MAX];
796 	double MinSwathHeightC[DC__NUM_DPP__MAX];
797 	double ReadBandwidthLuma[DC__NUM_DPP__MAX];
798 	double ReadBandwidthChroma[DC__NUM_DPP__MAX];
799 	double ReadBandwidth[DC__NUM_DPP__MAX];
800 	double WriteBandwidth[DC__NUM_DPP__MAX];
801 	double PSCL_FACTOR[DC__NUM_DPP__MAX];
802 	double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
803 	double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
804 	double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
805 	double AlignedYPitch[DC__NUM_DPP__MAX];
806 	double AlignedCPitch[DC__NUM_DPP__MAX];
807 	double MaximumSwathWidth[DC__NUM_DPP__MAX];
808 	double cursor_bw[DC__NUM_DPP__MAX];
809 	double cursor_bw_pre[DC__NUM_DPP__MAX];
810 	double Tno_bw[DC__NUM_DPP__MAX];
811 	double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
812 	double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
813 	double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
814 	double final_flip_bw[DC__NUM_DPP__MAX];
815 	bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
816 	double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
817 	unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
818 	unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
819 	unsigned int dpte_row_height[DC__NUM_DPP__MAX];
820 	unsigned int meta_req_height[DC__NUM_DPP__MAX];
821 	unsigned int meta_req_width[DC__NUM_DPP__MAX];
822 	unsigned int meta_row_height[DC__NUM_DPP__MAX];
823 	unsigned int meta_row_width[DC__NUM_DPP__MAX];
824 	unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
825 	unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
826 	unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
827 	unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
828 	unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
829 	bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
830 	double meta_row_bw[DC__NUM_DPP__MAX];
831 	double dpte_row_bw[DC__NUM_DPP__MAX];
832 	double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
833 	double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
834 	double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
835 	double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
836 	enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
837 	double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
838 	double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
839 	double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
840 	double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
841 	double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
842 	double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
843 
844 
845 	bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
846 	double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
847 	double         MaximumSwathWidthInLineBufferLuma;
848 	double         MaximumSwathWidthInLineBufferChroma;
849 	double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
850 	double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
851 	enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
852 	double         dummy1[DC__NUM_DPP__MAX];
853 	double         dummy2[DC__NUM_DPP__MAX];
854 	unsigned int   dummy3[DC__NUM_DPP__MAX];
855 	unsigned int   dummy4[DC__NUM_DPP__MAX];
856 	double         dummy5;
857 	double         dummy6;
858 	double         dummy7[DC__NUM_DPP__MAX];
859 	double         dummy8[DC__NUM_DPP__MAX];
860 	double         dummy13[DC__NUM_DPP__MAX];
861 	double         dummy_double_array[2][DC__NUM_DPP__MAX];
862 	unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
863 	unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
864 	unsigned int        dummyinteger5;
865 	unsigned int        dummyinteger6;
866 	unsigned int        dummyinteger7;
867 	unsigned int        dummyinteger8;
868 	unsigned int        dummyinteger9;
869 	unsigned int        dummyinteger10;
870 	unsigned int        dummyinteger11;
871 	unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
872 
873 	bool           dummysinglestring;
874 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
875 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
876 	double         PlaneRequiredDISPCLKWithODMCombine4To1;
877 	unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
878 	bool           LinkDSCEnable;
879 	bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
880 	enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
881 	double   SwathWidthCThisState[DC__NUM_DPP__MAX];
882 	bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
883 	double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
884 	double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
885 
886 	unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
887 	unsigned int NotEnoughUrgentLatencyHidingPre;
888 	int PTEBufferSizeInRequestsForLuma;
889 	int PTEBufferSizeInRequestsForChroma;
890 
891 	// Missing from VBA
892 	int dpte_group_bytes_chroma;
893 	unsigned int vm_group_bytes_chroma;
894 	double dst_x_after_scaler;
895 	double dst_y_after_scaler;
896 	unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
897 
898 	/* perf locals*/
899 	double PrefetchBandwidth[DC__NUM_DPP__MAX];
900 	double VInitPreFillY[DC__NUM_DPP__MAX];
901 	double VInitPreFillC[DC__NUM_DPP__MAX];
902 	unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
903 	unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
904 	unsigned int VStartup[DC__NUM_DPP__MAX];
905 	double DSTYAfterScaler[DC__NUM_DPP__MAX];
906 	double DSTXAfterScaler[DC__NUM_DPP__MAX];
907 	bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
908 	bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
909 	double VRatioPrefetchY[DC__NUM_DPP__MAX];
910 	double VRatioPrefetchC[DC__NUM_DPP__MAX];
911 	double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
912 	double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
913 	double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
914 	double MinTTUVBlank[DC__NUM_DPP__MAX];
915 	double BytePerPixelDETY[DC__NUM_DPP__MAX];
916 	double BytePerPixelDETC[DC__NUM_DPP__MAX];
917 	double SwathWidthY[DC__NUM_DPP__MAX];
918 	double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
919 	double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
920 	double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
921 	double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
922 	double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
923 	double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
924 	double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
925 	double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
926 	double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
927 	double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
928 	double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
929 	double MetaRowByte[DC__NUM_DPP__MAX];
930 	double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
931 	double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
932 	double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
933 	double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
934 	double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
935 	double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
936 	double DSCCLK_calculated[DC__NUM_DPP__MAX];
937 	unsigned int DSCDelay[DC__NUM_DPP__MAX];
938 	unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
939 	double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
940 	double DPPCLK[DC__NUM_DPP__MAX];
941 	unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
942 	unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
943 	unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
944 	double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
945 	unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
946 	unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
947 	unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
948 	unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
949 	double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
950 	double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
951 	double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
952 	double XFCTransferDelay[DC__NUM_DPP__MAX];
953 	double XFCPrechargeDelay[DC__NUM_DPP__MAX];
954 	double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
955 	double XFCPrefetchMargin[DC__NUM_DPP__MAX];
956 	unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
957 	unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
958 	double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
959 	double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
960 	double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
961 	double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
962 	double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
963 	double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
964 	double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
965 	double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
966 	unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
967 	unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
968 	unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
969 	unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
970 	unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
971 	unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
972 	unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
973 	unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
974 	double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
975 	double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
976 	double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
977 	double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
978 	double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
979 	double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
980 	double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
981 	double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
982 	double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
983 	double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
984 	unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
985 	unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
986 	unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
987 	unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
988 	double LinesToFinishSwathTransferStutterCriticalPlane;
989 	unsigned int BytePerPixelYCriticalPlane;
990 	double SwathWidthYCriticalPlane;
991 	double LinesInDETY[DC__NUM_DPP__MAX];
992 	double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
993 
994 	double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
995 	double SwathWidthC[DC__NUM_DPP__MAX];
996 	unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
997 	unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
998 	unsigned int dummyinteger1;
999 	unsigned int dummyinteger2;
1000 	double FinalDRAMClockChangeLatency;
1001 	double Tdmdl_vm[DC__NUM_DPP__MAX];
1002 	double Tdmdl[DC__NUM_DPP__MAX];
1003 	double TSetup[DC__NUM_DPP__MAX];
1004 	unsigned int ThisVStartup;
1005 	bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1006 	double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1007 	double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1008 	double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1009 	double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1010 	unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1011 	unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1012 	double VStartupMargin;
1013 	bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1014 
1015 	/* Missing from VBA */
1016 	unsigned int MaximumMaxVStartupLines;
1017 	double FabricAndDRAMBandwidth;
1018 	double LinesInDETLuma;
1019 	double LinesInDETChroma;
1020 	unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1021 	unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1022 	unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1023 	double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1024 	double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1025 	double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1026 	bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1027 	unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1028 	unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1029 	double qual_row_bw[DC__NUM_DPP__MAX];
1030 	double prefetch_row_bw[DC__NUM_DPP__MAX];
1031 	double prefetch_vm_bw[DC__NUM_DPP__MAX];
1032 
1033 	double PTEGroupSize;
1034 	unsigned int PDEProcessingBufIn64KBReqs;
1035 
1036 	double MaxTotalVActiveRDBandwidth;
1037 	bool DoUrgentLatencyAdjustment;
1038 	double UrgentLatencyAdjustmentFabricClockComponent;
1039 	double UrgentLatencyAdjustmentFabricClockReference;
1040 	double MinUrgentLatencySupportUs;
1041 	double MinFullDETBufferingTime;
1042 	double AverageReadBandwidthGBytePerSecond;
1043 	bool   FirstMainPlane;
1044 	bool NotEnoughDETSwathFillLatencyHiding;
1045 
1046 	unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1047 	unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1048 	double HRatioChroma[DC__NUM_DPP__MAX];
1049 	double VRatioChroma[DC__NUM_DPP__MAX];
1050 	int WritebackSourceWidth[DC__NUM_DPP__MAX];
1051 
1052 	bool ModeIsSupported;
1053 	bool ODMCombine4To1Supported;
1054 
1055 	unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1056 	unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1057 	unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1058 	unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1059 	unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1060 	unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1061 	bool DSCEnable[DC__NUM_DPP__MAX];
1062 
1063 	double DRAMClockChangeLatencyOverride;
1064 
1065 	double GPUVMMinPageSize;
1066 	double HostVMMinPageSize;
1067 
1068 	bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1069 	unsigned int HostVMMaxNonCachedPageTableLevels;
1070 	bool   DynamicMetadataVMEnabled;
1071 	double       WritebackInterfaceBufferSize;
1072 	double       WritebackLineBufferSize;
1073 
1074 	double DCCRateLuma[DC__NUM_DPP__MAX];
1075 	double DCCRateChroma[DC__NUM_DPP__MAX];
1076 
1077 	double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1078 
1079 	bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1080 	bool NumberOfHDMIFRLSupport;
1081 	unsigned int MaxNumHDMIFRLOutputs;
1082 	int    AudioSampleRate[DC__NUM_DPP__MAX];
1083 	int    AudioSampleLayout[DC__NUM_DPP__MAX];
1084 
1085 	int PercentMarginOverMinimumRequiredDCFCLK;
1086 	bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1087 	enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1088 	unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1089 	unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1090 	bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1091 	bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1092 	int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1093 	int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1094 	double UrgLatency[DC__VOLTAGE_STATES];
1095 	double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1096 	double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1097 	bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1098 	bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1099 	double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1100 	double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1101 	double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1102 	double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1103 	unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1104 	unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1105 	bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1106 	unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1107 	unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1108 	unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1109 	unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1110 	double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1111 	double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1112 	double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1113 	double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1114 	double WritebackDelayTime[DC__NUM_DPP__MAX];
1115 	unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1116 	unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1117 	unsigned int dummyinteger17;
1118 	unsigned int dummyinteger18;
1119 	unsigned int dummyinteger19;
1120 	unsigned int dummyinteger20;
1121 	unsigned int dummyinteger21;
1122 	unsigned int dummyinteger22;
1123 	unsigned int dummyinteger23;
1124 	unsigned int dummyinteger24;
1125 	unsigned int dummyinteger25;
1126 	unsigned int dummyinteger26;
1127 	unsigned int dummyinteger27;
1128 	unsigned int dummyinteger28;
1129 	unsigned int dummyinteger29;
1130 	bool dummystring[DC__NUM_DPP__MAX];
1131 	double BPP;
1132 	enum odm_combine_policy ODMCombinePolicy;
1133 	bool UseMinimumRequiredDCFCLK;
1134 	bool ClampMinDCFCLK;
1135 	bool AllowDramClockChangeOneDisplayVactive;
1136 
1137 	double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1138 	double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1139 	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1140 	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1141 	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1142 	double SRExitZ8Time;
1143 	double SREnterPlusExitZ8Time;
1144 	double Z8StutterExitWatermark;
1145 	double Z8StutterEnterPlusExitWatermark;
1146 	double Z8StutterEfficiencyNotIncludingVBlank;
1147 	double Z8StutterEfficiency;
1148 	double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1149 	double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1150 	double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1151 	double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1152 	double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1153 	double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1154 	double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1155 	double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1156 	bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1157 	bool LinkCapacitySupport[DC__VOLTAGE_STATES];
1158 	bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1159 	unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1160 	unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1161 	int ConfigReturnBufferSizeInKByte;
1162 	enum unbounded_requesting_policy UseUnboundedRequesting;
1163 	int CompressedBufferSegmentSizeInkByte;
1164 	int CompressedBufferSizeInkByte;
1165 	int MetaFIFOSizeInKEntries;
1166 	int ZeroSizeBufferEntries;
1167 	int COMPBUF_RESERVED_SPACE_64B;
1168 	int COMPBUF_RESERVED_SPACE_ZS;
1169 	bool UnboundedRequestEnabled;
1170 	bool DSC422NativeSupport;
1171 	bool NoEnoughUrgentLatencyHiding;
1172 	bool NoEnoughUrgentLatencyHidingPre;
1173 	int NumberOfStutterBurstsPerFrame;
1174 	int Z8NumberOfStutterBurstsPerFrame;
1175 	unsigned int MaximumDSCBitsPerComponent;
1176 	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1177 	double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1178 	double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1179 	double SurfaceRequiredDISPCLKWithoutODMCombine;
1180 	double SurfaceRequiredDISPCLK;
1181 	double MinActiveFCLKChangeLatencySupported;
1182 	int MinVoltageLevel;
1183 	int MaxVoltageLevel;
1184 	unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1185 	unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1186 	unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1187 	unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1188 	unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1189 	bool ExceededMALLSize;
1190 	bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1191 	unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1192 	unsigned int CompressedBufferSizeInkByteThisState;
1193 	enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1194 	bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1195 	enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1196 	bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1197 	bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1198 	enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1199 	bool UnboundedRequestEnabledThisState;
1200 	bool DRAMClockChangeRequirementFinal;
1201 	bool FCLKChangeRequirementFinal;
1202 	bool USRRetrainingRequiredFinal;
1203 	unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1204 	unsigned int nomDETInKByte;
1205 	enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1206 	bool MPCCombineMethodIncompatible;
1207 	unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1208 	bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1209 	enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1210 	unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1211 	bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1212 	bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1213 	double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1214 	double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1215 	bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1216 	bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1217 	bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1218 	bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1219 	bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1220 	unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1221 	unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1222 	unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1223 	unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1224 	unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1225 	unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1226 	unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1227 	bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1228 	bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2];
1229 	struct dummy_vars dummy_vars;
1230 };
1231 
1232 bool CalculateMinAndMaxPrefetchMode(
1233 		enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1234 		unsigned int *MinPrefetchMode,
1235 		unsigned int *MaxPrefetchMode);
1236 
1237 double CalculateWriteBackDISPCLK(
1238 		enum source_format_class WritebackPixelFormat,
1239 		double PixelClock,
1240 		double WritebackHRatio,
1241 		double WritebackVRatio,
1242 		unsigned int WritebackLumaHTaps,
1243 		unsigned int WritebackLumaVTaps,
1244 		unsigned int WritebackChromaHTaps,
1245 		unsigned int WritebackChromaVTaps,
1246 		double WritebackDestinationWidth,
1247 		unsigned int HTotal,
1248 		unsigned int WritebackChromaLineBufferWidth);
1249 
1250 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */
1251