1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * Macros and functions to access KVM PTEs (also known as SPTEs)
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2020 Red Hat, Inc. and/or its affiliates.
9 */
10
11
12 #include <linux/kvm_host.h>
13 #include "mmu.h"
14 #include "mmu_internal.h"
15 #include "x86.h"
16 #include "spte.h"
17
18 #include <asm/e820/api.h>
19 #include <asm/memtype.h>
20 #include <asm/vmx.h>
21
22 bool __read_mostly enable_mmio_caching = true;
23 static bool __ro_after_init allow_mmio_caching;
24 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444);
25 EXPORT_SYMBOL_GPL(enable_mmio_caching);
26
27 u64 __read_mostly shadow_host_writable_mask;
28 u64 __read_mostly shadow_mmu_writable_mask;
29 u64 __read_mostly shadow_nx_mask;
30 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
31 u64 __read_mostly shadow_user_mask;
32 u64 __read_mostly shadow_accessed_mask;
33 u64 __read_mostly shadow_dirty_mask;
34 u64 __read_mostly shadow_mmio_value;
35 u64 __read_mostly shadow_mmio_mask;
36 u64 __read_mostly shadow_mmio_access_mask;
37 u64 __read_mostly shadow_present_mask;
38 u64 __read_mostly shadow_memtype_mask;
39 u64 __read_mostly shadow_me_value;
40 u64 __read_mostly shadow_me_mask;
41 u64 __read_mostly shadow_acc_track_mask;
42
43 u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
44 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
45
46 u8 __read_mostly shadow_phys_bits;
47
kvm_mmu_spte_module_init(void)48 void __init kvm_mmu_spte_module_init(void)
49 {
50 /*
51 * Snapshot userspace's desire to allow MMIO caching. Whether or not
52 * KVM can actually enable MMIO caching depends on vendor-specific
53 * hardware capabilities and other module params that can't be resolved
54 * until the vendor module is loaded, i.e. enable_mmio_caching can and
55 * will change when the vendor module is (re)loaded.
56 */
57 allow_mmio_caching = enable_mmio_caching;
58 }
59
generation_mmio_spte_mask(u64 gen)60 static u64 generation_mmio_spte_mask(u64 gen)
61 {
62 u64 mask;
63
64 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
65
66 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK;
67 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK;
68 return mask;
69 }
70
make_mmio_spte(struct kvm_vcpu * vcpu,u64 gfn,unsigned int access)71 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
72 {
73 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
74 u64 spte = generation_mmio_spte_mask(gen);
75 u64 gpa = gfn << PAGE_SHIFT;
76
77 WARN_ON_ONCE(!shadow_mmio_value);
78
79 access &= shadow_mmio_access_mask;
80 spte |= shadow_mmio_value | access;
81 spte |= gpa | shadow_nonpresent_or_rsvd_mask;
82 spte |= (gpa & shadow_nonpresent_or_rsvd_mask)
83 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
84
85 return spte;
86 }
87
kvm_is_mmio_pfn(kvm_pfn_t pfn)88 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
89 {
90 if (pfn_valid(pfn))
91 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
92 /*
93 * Some reserved pages, such as those from NVDIMM
94 * DAX devices, are not for MMIO, and can be mapped
95 * with cached memory type for better performance.
96 * However, the above check misconceives those pages
97 * as MMIO, and results in KVM mapping them with UC
98 * memory type, which would hurt the performance.
99 * Therefore, we check the host memory type in addition
100 * and only treat UC/UC-/WC pages as MMIO.
101 */
102 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
103
104 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
105 pfn_to_hpa(pfn + 1) - 1,
106 E820_TYPE_RAM);
107 }
108
109 /*
110 * Returns true if the SPTE has bits that may be set without holding mmu_lock.
111 * The caller is responsible for checking if the SPTE is shadow-present, and
112 * for determining whether or not the caller cares about non-leaf SPTEs.
113 */
spte_has_volatile_bits(u64 spte)114 bool spte_has_volatile_bits(u64 spte)
115 {
116 /*
117 * Always atomically update spte if it can be updated
118 * out of mmu-lock, it can ensure dirty bit is not lost,
119 * also, it can help us to get a stable is_writable_pte()
120 * to ensure tlb flush is not missed.
121 */
122 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte))
123 return true;
124
125 if (is_access_track_spte(spte))
126 return true;
127
128 if (spte_ad_enabled(spte)) {
129 if (!(spte & shadow_accessed_mask) ||
130 (is_writable_pte(spte) && !(spte & shadow_dirty_mask)))
131 return true;
132 }
133
134 return false;
135 }
136
make_spte(struct kvm_vcpu * vcpu,struct kvm_mmu_page * sp,const struct kvm_memory_slot * slot,unsigned int pte_access,gfn_t gfn,kvm_pfn_t pfn,u64 old_spte,bool prefetch,bool can_unsync,bool host_writable,u64 * new_spte)137 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
138 const struct kvm_memory_slot *slot,
139 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,
140 u64 old_spte, bool prefetch, bool can_unsync,
141 bool host_writable, u64 *new_spte)
142 {
143 int level = sp->role.level;
144 u64 spte = SPTE_MMU_PRESENT_MASK;
145 bool wrprot = false;
146
147 WARN_ON_ONCE(!pte_access && !shadow_present_mask);
148
149 if (sp->role.ad_disabled)
150 spte |= SPTE_TDP_AD_DISABLED_MASK;
151 else if (kvm_mmu_page_ad_need_write_protect(sp))
152 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK;
153
154 /*
155 * For the EPT case, shadow_present_mask is 0 if hardware
156 * supports exec-only page table entries. In that case,
157 * ACC_USER_MASK and shadow_user_mask are used to represent
158 * read access. See FNAME(gpte_access) in paging_tmpl.h.
159 */
160 spte |= shadow_present_mask;
161 if (!prefetch)
162 spte |= spte_shadow_accessed_mask(spte);
163
164 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) &&
165 is_nx_huge_page_enabled(vcpu->kvm)) {
166 pte_access &= ~ACC_EXEC_MASK;
167 }
168
169 if (pte_access & ACC_EXEC_MASK)
170 spte |= shadow_x_mask;
171 else
172 spte |= shadow_nx_mask;
173
174 if (pte_access & ACC_USER_MASK)
175 spte |= shadow_user_mask;
176
177 if (level > PG_LEVEL_4K)
178 spte |= PT_PAGE_SIZE_MASK;
179
180 if (shadow_memtype_mask)
181 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn,
182 kvm_is_mmio_pfn(pfn));
183 if (host_writable)
184 spte |= shadow_host_writable_mask;
185 else
186 pte_access &= ~ACC_WRITE_MASK;
187
188 if (shadow_me_value && !kvm_is_mmio_pfn(pfn))
189 spte |= shadow_me_value;
190
191 spte |= (u64)pfn << PAGE_SHIFT;
192
193 if (pte_access & ACC_WRITE_MASK) {
194 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask;
195
196 /*
197 * Optimization: for pte sync, if spte was writable the hash
198 * lookup is unnecessary (and expensive). Write protection
199 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots.
200 * Same reasoning can be applied to dirty page accounting.
201 */
202 if (is_writable_pte(old_spte))
203 goto out;
204
205 /*
206 * Unsync shadow pages that are reachable by the new, writable
207 * SPTE. Write-protect the SPTE if the page can't be unsync'd,
208 * e.g. it's write-tracked (upper-level SPs) or has one or more
209 * shadow pages and unsync'ing pages is not allowed.
210 */
211 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) {
212 pgprintk("%s: found shadow page for %llx, marking ro\n",
213 __func__, gfn);
214 wrprot = true;
215 pte_access &= ~ACC_WRITE_MASK;
216 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask);
217 }
218 }
219
220 if (pte_access & ACC_WRITE_MASK)
221 spte |= spte_shadow_dirty_mask(spte);
222
223 out:
224 if (prefetch)
225 spte = mark_spte_for_access_track(spte);
226
227 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level),
228 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level,
229 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level));
230
231 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) {
232 /* Enforced by kvm_mmu_hugepage_adjust. */
233 WARN_ON(level > PG_LEVEL_4K);
234 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn);
235 }
236
237 *new_spte = spte;
238 return wrprot;
239 }
240
make_spte_executable(u64 spte)241 static u64 make_spte_executable(u64 spte)
242 {
243 bool is_access_track = is_access_track_spte(spte);
244
245 if (is_access_track)
246 spte = restore_acc_track_spte(spte);
247
248 spte &= ~shadow_nx_mask;
249 spte |= shadow_x_mask;
250
251 if (is_access_track)
252 spte = mark_spte_for_access_track(spte);
253
254 return spte;
255 }
256
257 /*
258 * Construct an SPTE that maps a sub-page of the given huge page SPTE where
259 * `index` identifies which sub-page.
260 *
261 * This is used during huge page splitting to build the SPTEs that make up the
262 * new page table.
263 */
make_huge_page_split_spte(struct kvm * kvm,u64 huge_spte,union kvm_mmu_page_role role,int index)264 u64 make_huge_page_split_spte(struct kvm *kvm, u64 huge_spte, union kvm_mmu_page_role role,
265 int index)
266 {
267 u64 child_spte;
268
269 if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte)))
270 return 0;
271
272 if (WARN_ON_ONCE(!is_large_pte(huge_spte)))
273 return 0;
274
275 child_spte = huge_spte;
276
277 /*
278 * The child_spte already has the base address of the huge page being
279 * split. So we just have to OR in the offset to the page at the next
280 * lower level for the given index.
281 */
282 child_spte |= (index * KVM_PAGES_PER_HPAGE(role.level)) << PAGE_SHIFT;
283
284 if (role.level == PG_LEVEL_4K) {
285 child_spte &= ~PT_PAGE_SIZE_MASK;
286
287 /*
288 * When splitting to a 4K page where execution is allowed, mark
289 * the page executable as the NX hugepage mitigation no longer
290 * applies.
291 */
292 if ((role.access & ACC_EXEC_MASK) && is_nx_huge_page_enabled(kvm))
293 child_spte = make_spte_executable(child_spte);
294 }
295
296 return child_spte;
297 }
298
299
make_nonleaf_spte(u64 * child_pt,bool ad_disabled)300 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled)
301 {
302 u64 spte = SPTE_MMU_PRESENT_MASK;
303
304 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK |
305 shadow_user_mask | shadow_x_mask | shadow_me_value;
306
307 if (ad_disabled)
308 spte |= SPTE_TDP_AD_DISABLED_MASK;
309 else
310 spte |= shadow_accessed_mask;
311
312 return spte;
313 }
314
kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte,kvm_pfn_t new_pfn)315 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn)
316 {
317 u64 new_spte;
318
319 new_spte = old_spte & ~SPTE_BASE_ADDR_MASK;
320 new_spte |= (u64)new_pfn << PAGE_SHIFT;
321
322 new_spte &= ~PT_WRITABLE_MASK;
323 new_spte &= ~shadow_host_writable_mask;
324 new_spte &= ~shadow_mmu_writable_mask;
325
326 new_spte = mark_spte_for_access_track(new_spte);
327
328 return new_spte;
329 }
330
mark_spte_for_access_track(u64 spte)331 u64 mark_spte_for_access_track(u64 spte)
332 {
333 if (spte_ad_enabled(spte))
334 return spte & ~shadow_accessed_mask;
335
336 if (is_access_track_spte(spte))
337 return spte;
338
339 check_spte_writable_invariants(spte);
340
341 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
342 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT),
343 "kvm: Access Tracking saved bit locations are not zero\n");
344
345 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) <<
346 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT;
347 spte &= ~shadow_acc_track_mask;
348
349 return spte;
350 }
351
kvm_mmu_set_mmio_spte_mask(u64 mmio_value,u64 mmio_mask,u64 access_mask)352 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask)
353 {
354 BUG_ON((u64)(unsigned)access_mask != access_mask);
355 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);
356
357 /*
358 * Reset to the original module param value to honor userspace's desire
359 * to (dis)allow MMIO caching. Update the param itself so that
360 * userspace can see whether or not KVM is actually using MMIO caching.
361 */
362 enable_mmio_caching = allow_mmio_caching;
363 if (!enable_mmio_caching)
364 mmio_value = 0;
365
366 /*
367 * The mask must contain only bits that are carved out specifically for
368 * the MMIO SPTE mask, e.g. to ensure there's no overlap with the MMIO
369 * generation.
370 */
371 if (WARN_ON(mmio_mask & ~SPTE_MMIO_ALLOWED_MASK))
372 mmio_value = 0;
373
374 /*
375 * Disable MMIO caching if the MMIO value collides with the bits that
376 * are used to hold the relocated GFN when the L1TF mitigation is
377 * enabled. This should never fire as there is no known hardware that
378 * can trigger this condition, e.g. SME/SEV CPUs that require a custom
379 * MMIO value are not susceptible to L1TF.
380 */
381 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask <<
382 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)))
383 mmio_value = 0;
384
385 /*
386 * The masked MMIO value must obviously match itself and a removed SPTE
387 * must not get a false positive. Removed SPTEs and MMIO SPTEs should
388 * never collide as MMIO must set some RWX bits, and removed SPTEs must
389 * not set any RWX bits.
390 */
391 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) ||
392 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value))
393 mmio_value = 0;
394
395 if (!mmio_value)
396 enable_mmio_caching = false;
397
398 shadow_mmio_value = mmio_value;
399 shadow_mmio_mask = mmio_mask;
400 shadow_mmio_access_mask = access_mask;
401 }
402 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
403
kvm_mmu_set_me_spte_mask(u64 me_value,u64 me_mask)404 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask)
405 {
406 /* shadow_me_value must be a subset of shadow_me_mask */
407 if (WARN_ON(me_value & ~me_mask))
408 me_value = me_mask = 0;
409
410 shadow_me_value = me_value;
411 shadow_me_mask = me_mask;
412 }
413 EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask);
414
kvm_mmu_set_ept_masks(bool has_ad_bits,bool has_exec_only)415 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
416 {
417 shadow_user_mask = VMX_EPT_READABLE_MASK;
418 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull;
419 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;
420 shadow_nx_mask = 0ull;
421 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK;
422 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;
423 /*
424 * EPT overrides the host MTRRs, and so KVM must program the desired
425 * memtype directly into the SPTEs. Note, this mask is just the mask
426 * of all bits that factor into the memtype, the actual memtype must be
427 * dynamically calculated, e.g. to ensure host MMIO is mapped UC.
428 */
429 shadow_memtype_mask = VMX_EPT_MT_MASK | VMX_EPT_IPAT_BIT;
430 shadow_acc_track_mask = VMX_EPT_RWX_MASK;
431 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE;
432 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE;
433
434 /*
435 * EPT Misconfigurations are generated if the value of bits 2:0
436 * of an EPT paging-structure entry is 110b (write/execute).
437 */
438 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,
439 VMX_EPT_RWX_MASK, 0);
440 }
441 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks);
442
kvm_mmu_reset_all_pte_masks(void)443 void kvm_mmu_reset_all_pte_masks(void)
444 {
445 u8 low_phys_bits;
446 u64 mask;
447
448 shadow_phys_bits = kvm_get_shadow_phys_bits();
449
450 /*
451 * If the CPU has 46 or less physical address bits, then set an
452 * appropriate mask to guard against L1TF attacks. Otherwise, it is
453 * assumed that the CPU is not vulnerable to L1TF.
454 *
455 * Some Intel CPUs address the L1 cache using more PA bits than are
456 * reported by CPUID. Use the PA width of the L1 cache when possible
457 * to achieve more effective mitigation, e.g. if system RAM overlaps
458 * the most significant bits of legal physical address space.
459 */
460 shadow_nonpresent_or_rsvd_mask = 0;
461 low_phys_bits = boot_cpu_data.x86_phys_bits;
462 if (boot_cpu_has_bug(X86_BUG_L1TF) &&
463 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >=
464 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) {
465 low_phys_bits = boot_cpu_data.x86_cache_bits
466 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
467 shadow_nonpresent_or_rsvd_mask =
468 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);
469 }
470
471 shadow_nonpresent_or_rsvd_lower_gfn_mask =
472 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
473
474 shadow_user_mask = PT_USER_MASK;
475 shadow_accessed_mask = PT_ACCESSED_MASK;
476 shadow_dirty_mask = PT_DIRTY_MASK;
477 shadow_nx_mask = PT64_NX_MASK;
478 shadow_x_mask = 0;
479 shadow_present_mask = PT_PRESENT_MASK;
480
481 /*
482 * For shadow paging and NPT, KVM uses PAT entry '0' to encode WB
483 * memtype in the SPTEs, i.e. relies on host MTRRs to provide the
484 * correct memtype (WB is the "weakest" memtype).
485 */
486 shadow_memtype_mask = 0;
487 shadow_acc_track_mask = 0;
488 shadow_me_mask = 0;
489 shadow_me_value = 0;
490
491 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE;
492 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE;
493
494 /*
495 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
496 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
497 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
498 * 52-bit physical addresses then there are no reserved PA bits in the
499 * PTEs and so the reserved PA approach must be disabled.
500 */
501 if (shadow_phys_bits < 52)
502 mask = BIT_ULL(51) | PT_PRESENT_MASK;
503 else
504 mask = 0;
505
506 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);
507 }
508