1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * Macros and functions to access KVM PTEs (also known as SPTEs)
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2020 Red Hat, Inc. and/or its affiliates.
9 */
10
11
12 #include <linux/kvm_host.h>
13 #include "mmu.h"
14 #include "mmu_internal.h"
15 #include "x86.h"
16 #include "spte.h"
17
18 #include <asm/e820/api.h>
19 #include <asm/memtype.h>
20 #include <asm/vmx.h>
21
22 bool __read_mostly enable_mmio_caching = true;
23 static bool __ro_after_init allow_mmio_caching;
24 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444);
25 EXPORT_SYMBOL_GPL(enable_mmio_caching);
26
27 u64 __read_mostly shadow_host_writable_mask;
28 u64 __read_mostly shadow_mmu_writable_mask;
29 u64 __read_mostly shadow_nx_mask;
30 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
31 u64 __read_mostly shadow_user_mask;
32 u64 __read_mostly shadow_accessed_mask;
33 u64 __read_mostly shadow_dirty_mask;
34 u64 __read_mostly shadow_mmio_value;
35 u64 __read_mostly shadow_mmio_mask;
36 u64 __read_mostly shadow_mmio_access_mask;
37 u64 __read_mostly shadow_present_mask;
38 u64 __read_mostly shadow_me_value;
39 u64 __read_mostly shadow_me_mask;
40 u64 __read_mostly shadow_acc_track_mask;
41
42 u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
43 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
44
45 u8 __read_mostly shadow_phys_bits;
46
kvm_mmu_spte_module_init(void)47 void __init kvm_mmu_spte_module_init(void)
48 {
49 /*
50 * Snapshot userspace's desire to allow MMIO caching. Whether or not
51 * KVM can actually enable MMIO caching depends on vendor-specific
52 * hardware capabilities and other module params that can't be resolved
53 * until the vendor module is loaded, i.e. enable_mmio_caching can and
54 * will change when the vendor module is (re)loaded.
55 */
56 allow_mmio_caching = enable_mmio_caching;
57 }
58
generation_mmio_spte_mask(u64 gen)59 static u64 generation_mmio_spte_mask(u64 gen)
60 {
61 u64 mask;
62
63 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
64
65 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK;
66 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK;
67 return mask;
68 }
69
make_mmio_spte(struct kvm_vcpu * vcpu,u64 gfn,unsigned int access)70 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
71 {
72 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
73 u64 spte = generation_mmio_spte_mask(gen);
74 u64 gpa = gfn << PAGE_SHIFT;
75
76 WARN_ON_ONCE(!shadow_mmio_value);
77
78 access &= shadow_mmio_access_mask;
79 spte |= shadow_mmio_value | access;
80 spte |= gpa | shadow_nonpresent_or_rsvd_mask;
81 spte |= (gpa & shadow_nonpresent_or_rsvd_mask)
82 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
83
84 return spte;
85 }
86
kvm_is_mmio_pfn(kvm_pfn_t pfn)87 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
88 {
89 if (pfn_valid(pfn))
90 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
91 /*
92 * Some reserved pages, such as those from NVDIMM
93 * DAX devices, are not for MMIO, and can be mapped
94 * with cached memory type for better performance.
95 * However, the above check misconceives those pages
96 * as MMIO, and results in KVM mapping them with UC
97 * memory type, which would hurt the performance.
98 * Therefore, we check the host memory type in addition
99 * and only treat UC/UC-/WC pages as MMIO.
100 */
101 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
102
103 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
104 pfn_to_hpa(pfn + 1) - 1,
105 E820_TYPE_RAM);
106 }
107
108 /*
109 * Returns true if the SPTE has bits that may be set without holding mmu_lock.
110 * The caller is responsible for checking if the SPTE is shadow-present, and
111 * for determining whether or not the caller cares about non-leaf SPTEs.
112 */
spte_has_volatile_bits(u64 spte)113 bool spte_has_volatile_bits(u64 spte)
114 {
115 /*
116 * Always atomically update spte if it can be updated
117 * out of mmu-lock, it can ensure dirty bit is not lost,
118 * also, it can help us to get a stable is_writable_pte()
119 * to ensure tlb flush is not missed.
120 */
121 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte))
122 return true;
123
124 if (is_access_track_spte(spte))
125 return true;
126
127 if (spte_ad_enabled(spte)) {
128 if (!(spte & shadow_accessed_mask) ||
129 (is_writable_pte(spte) && !(spte & shadow_dirty_mask)))
130 return true;
131 }
132
133 return false;
134 }
135
make_spte(struct kvm_vcpu * vcpu,struct kvm_mmu_page * sp,const struct kvm_memory_slot * slot,unsigned int pte_access,gfn_t gfn,kvm_pfn_t pfn,u64 old_spte,bool prefetch,bool can_unsync,bool host_writable,u64 * new_spte)136 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
137 const struct kvm_memory_slot *slot,
138 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,
139 u64 old_spte, bool prefetch, bool can_unsync,
140 bool host_writable, u64 *new_spte)
141 {
142 int level = sp->role.level;
143 u64 spte = SPTE_MMU_PRESENT_MASK;
144 bool wrprot = false;
145
146 WARN_ON_ONCE(!pte_access && !shadow_present_mask);
147
148 if (sp->role.ad_disabled)
149 spte |= SPTE_TDP_AD_DISABLED_MASK;
150 else if (kvm_mmu_page_ad_need_write_protect(sp))
151 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK;
152
153 /*
154 * For the EPT case, shadow_present_mask is 0 if hardware
155 * supports exec-only page table entries. In that case,
156 * ACC_USER_MASK and shadow_user_mask are used to represent
157 * read access. See FNAME(gpte_access) in paging_tmpl.h.
158 */
159 spte |= shadow_present_mask;
160 if (!prefetch)
161 spte |= spte_shadow_accessed_mask(spte);
162
163 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) &&
164 is_nx_huge_page_enabled()) {
165 pte_access &= ~ACC_EXEC_MASK;
166 }
167
168 if (pte_access & ACC_EXEC_MASK)
169 spte |= shadow_x_mask;
170 else
171 spte |= shadow_nx_mask;
172
173 if (pte_access & ACC_USER_MASK)
174 spte |= shadow_user_mask;
175
176 if (level > PG_LEVEL_4K)
177 spte |= PT_PAGE_SIZE_MASK;
178 if (tdp_enabled)
179 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn,
180 kvm_is_mmio_pfn(pfn));
181
182 if (host_writable)
183 spte |= shadow_host_writable_mask;
184 else
185 pte_access &= ~ACC_WRITE_MASK;
186
187 if (shadow_me_value && !kvm_is_mmio_pfn(pfn))
188 spte |= shadow_me_value;
189
190 spte |= (u64)pfn << PAGE_SHIFT;
191
192 if (pte_access & ACC_WRITE_MASK) {
193 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask;
194
195 /*
196 * Optimization: for pte sync, if spte was writable the hash
197 * lookup is unnecessary (and expensive). Write protection
198 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots.
199 * Same reasoning can be applied to dirty page accounting.
200 */
201 if (is_writable_pte(old_spte))
202 goto out;
203
204 /*
205 * Unsync shadow pages that are reachable by the new, writable
206 * SPTE. Write-protect the SPTE if the page can't be unsync'd,
207 * e.g. it's write-tracked (upper-level SPs) or has one or more
208 * shadow pages and unsync'ing pages is not allowed.
209 */
210 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) {
211 pgprintk("%s: found shadow page for %llx, marking ro\n",
212 __func__, gfn);
213 wrprot = true;
214 pte_access &= ~ACC_WRITE_MASK;
215 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask);
216 }
217 }
218
219 if (pte_access & ACC_WRITE_MASK)
220 spte |= spte_shadow_dirty_mask(spte);
221
222 out:
223 if (prefetch)
224 spte = mark_spte_for_access_track(spte);
225
226 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level),
227 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level,
228 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level));
229
230 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) {
231 /* Enforced by kvm_mmu_hugepage_adjust. */
232 WARN_ON(level > PG_LEVEL_4K);
233 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn);
234 }
235
236 *new_spte = spte;
237 return wrprot;
238 }
239
make_spte_executable(u64 spte)240 static u64 make_spte_executable(u64 spte)
241 {
242 bool is_access_track = is_access_track_spte(spte);
243
244 if (is_access_track)
245 spte = restore_acc_track_spte(spte);
246
247 spte &= ~shadow_nx_mask;
248 spte |= shadow_x_mask;
249
250 if (is_access_track)
251 spte = mark_spte_for_access_track(spte);
252
253 return spte;
254 }
255
256 /*
257 * Construct an SPTE that maps a sub-page of the given huge page SPTE where
258 * `index` identifies which sub-page.
259 *
260 * This is used during huge page splitting to build the SPTEs that make up the
261 * new page table.
262 */
make_huge_page_split_spte(u64 huge_spte,int huge_level,int index)263 u64 make_huge_page_split_spte(u64 huge_spte, int huge_level, int index)
264 {
265 u64 child_spte;
266 int child_level;
267
268 if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte)))
269 return 0;
270
271 if (WARN_ON_ONCE(!is_large_pte(huge_spte)))
272 return 0;
273
274 child_spte = huge_spte;
275 child_level = huge_level - 1;
276
277 /*
278 * The child_spte already has the base address of the huge page being
279 * split. So we just have to OR in the offset to the page at the next
280 * lower level for the given index.
281 */
282 child_spte |= (index * KVM_PAGES_PER_HPAGE(child_level)) << PAGE_SHIFT;
283
284 if (child_level == PG_LEVEL_4K) {
285 child_spte &= ~PT_PAGE_SIZE_MASK;
286
287 /*
288 * When splitting to a 4K page, mark the page executable as the
289 * NX hugepage mitigation no longer applies.
290 */
291 if (is_nx_huge_page_enabled())
292 child_spte = make_spte_executable(child_spte);
293 }
294
295 return child_spte;
296 }
297
298
make_nonleaf_spte(u64 * child_pt,bool ad_disabled)299 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled)
300 {
301 u64 spte = SPTE_MMU_PRESENT_MASK;
302
303 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK |
304 shadow_user_mask | shadow_x_mask | shadow_me_value;
305
306 if (ad_disabled)
307 spte |= SPTE_TDP_AD_DISABLED_MASK;
308 else
309 spte |= shadow_accessed_mask;
310
311 return spte;
312 }
313
kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte,kvm_pfn_t new_pfn)314 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn)
315 {
316 u64 new_spte;
317
318 new_spte = old_spte & ~PT64_BASE_ADDR_MASK;
319 new_spte |= (u64)new_pfn << PAGE_SHIFT;
320
321 new_spte &= ~PT_WRITABLE_MASK;
322 new_spte &= ~shadow_host_writable_mask;
323 new_spte &= ~shadow_mmu_writable_mask;
324
325 new_spte = mark_spte_for_access_track(new_spte);
326
327 return new_spte;
328 }
329
mark_spte_for_access_track(u64 spte)330 u64 mark_spte_for_access_track(u64 spte)
331 {
332 if (spte_ad_enabled(spte))
333 return spte & ~shadow_accessed_mask;
334
335 if (is_access_track_spte(spte))
336 return spte;
337
338 check_spte_writable_invariants(spte);
339
340 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
341 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT),
342 "kvm: Access Tracking saved bit locations are not zero\n");
343
344 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) <<
345 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT;
346 spte &= ~shadow_acc_track_mask;
347
348 return spte;
349 }
350
kvm_mmu_set_mmio_spte_mask(u64 mmio_value,u64 mmio_mask,u64 access_mask)351 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask)
352 {
353 BUG_ON((u64)(unsigned)access_mask != access_mask);
354 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);
355
356 /*
357 * Reset to the original module param value to honor userspace's desire
358 * to (dis)allow MMIO caching. Update the param itself so that
359 * userspace can see whether or not KVM is actually using MMIO caching.
360 */
361 enable_mmio_caching = allow_mmio_caching;
362 if (!enable_mmio_caching)
363 mmio_value = 0;
364
365 /*
366 * Disable MMIO caching if the MMIO value collides with the bits that
367 * are used to hold the relocated GFN when the L1TF mitigation is
368 * enabled. This should never fire as there is no known hardware that
369 * can trigger this condition, e.g. SME/SEV CPUs that require a custom
370 * MMIO value are not susceptible to L1TF.
371 */
372 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask <<
373 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)))
374 mmio_value = 0;
375
376 /*
377 * The masked MMIO value must obviously match itself and a removed SPTE
378 * must not get a false positive. Removed SPTEs and MMIO SPTEs should
379 * never collide as MMIO must set some RWX bits, and removed SPTEs must
380 * not set any RWX bits.
381 */
382 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) ||
383 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value))
384 mmio_value = 0;
385
386 if (!mmio_value)
387 enable_mmio_caching = false;
388
389 shadow_mmio_value = mmio_value;
390 shadow_mmio_mask = mmio_mask;
391 shadow_mmio_access_mask = access_mask;
392 }
393 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
394
kvm_mmu_set_me_spte_mask(u64 me_value,u64 me_mask)395 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask)
396 {
397 /* shadow_me_value must be a subset of shadow_me_mask */
398 if (WARN_ON(me_value & ~me_mask))
399 me_value = me_mask = 0;
400
401 shadow_me_value = me_value;
402 shadow_me_mask = me_mask;
403 }
404 EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask);
405
kvm_mmu_set_ept_masks(bool has_ad_bits,bool has_exec_only)406 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
407 {
408 shadow_user_mask = VMX_EPT_READABLE_MASK;
409 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull;
410 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;
411 shadow_nx_mask = 0ull;
412 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK;
413 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;
414 shadow_acc_track_mask = VMX_EPT_RWX_MASK;
415 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE;
416 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE;
417
418 /*
419 * EPT Misconfigurations are generated if the value of bits 2:0
420 * of an EPT paging-structure entry is 110b (write/execute).
421 */
422 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,
423 VMX_EPT_RWX_MASK, 0);
424 }
425 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks);
426
kvm_mmu_reset_all_pte_masks(void)427 void kvm_mmu_reset_all_pte_masks(void)
428 {
429 u8 low_phys_bits;
430 u64 mask;
431
432 shadow_phys_bits = kvm_get_shadow_phys_bits();
433
434 /*
435 * If the CPU has 46 or less physical address bits, then set an
436 * appropriate mask to guard against L1TF attacks. Otherwise, it is
437 * assumed that the CPU is not vulnerable to L1TF.
438 *
439 * Some Intel CPUs address the L1 cache using more PA bits than are
440 * reported by CPUID. Use the PA width of the L1 cache when possible
441 * to achieve more effective mitigation, e.g. if system RAM overlaps
442 * the most significant bits of legal physical address space.
443 */
444 shadow_nonpresent_or_rsvd_mask = 0;
445 low_phys_bits = boot_cpu_data.x86_phys_bits;
446 if (boot_cpu_has_bug(X86_BUG_L1TF) &&
447 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >=
448 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) {
449 low_phys_bits = boot_cpu_data.x86_cache_bits
450 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
451 shadow_nonpresent_or_rsvd_mask =
452 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);
453 }
454
455 shadow_nonpresent_or_rsvd_lower_gfn_mask =
456 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
457
458 shadow_user_mask = PT_USER_MASK;
459 shadow_accessed_mask = PT_ACCESSED_MASK;
460 shadow_dirty_mask = PT_DIRTY_MASK;
461 shadow_nx_mask = PT64_NX_MASK;
462 shadow_x_mask = 0;
463 shadow_present_mask = PT_PRESENT_MASK;
464 shadow_acc_track_mask = 0;
465 shadow_me_mask = 0;
466 shadow_me_value = 0;
467
468 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE;
469 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE;
470
471 /*
472 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
473 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
474 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
475 * 52-bit physical addresses then there are no reserved PA bits in the
476 * PTEs and so the reserved PA approach must be disabled.
477 */
478 if (shadow_phys_bits < 52)
479 mask = BIT_ULL(51) | PT_PRESENT_MASK;
480 else
481 mask = 0;
482
483 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);
484 }
485