1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 */
10
11 #define DRV_NAME "sh-pfc"
12
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/math.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/psci.h>
26 #include <linux/slab.h>
27 #include <linux/sys_soc.h>
28
29 #include "core.h"
30
sh_pfc_map_resources(struct sh_pfc * pfc,struct platform_device * pdev)31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
32 struct platform_device *pdev)
33 {
34 struct sh_pfc_window *windows;
35 unsigned int *irqs = NULL;
36 unsigned int num_windows;
37 struct resource *res;
38 unsigned int i;
39 int num_irqs;
40
41 /* Count the MEM and IRQ resources. */
42 for (num_windows = 0;; num_windows++) {
43 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
44 if (!res)
45 break;
46 }
47 if (num_windows == 0)
48 return -EINVAL;
49
50 num_irqs = platform_irq_count(pdev);
51 if (num_irqs < 0)
52 return num_irqs;
53
54 /* Allocate memory windows and IRQs arrays. */
55 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
56 GFP_KERNEL);
57 if (windows == NULL)
58 return -ENOMEM;
59
60 pfc->num_windows = num_windows;
61 pfc->windows = windows;
62
63 if (num_irqs) {
64 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
65 GFP_KERNEL);
66 if (irqs == NULL)
67 return -ENOMEM;
68
69 pfc->num_irqs = num_irqs;
70 pfc->irqs = irqs;
71 }
72
73 /* Fill them. */
74 for (i = 0; i < num_windows; i++) {
75 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
76 if (IS_ERR(windows->virt))
77 return -ENOMEM;
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows++;
81 }
82 for (i = 0; i < num_irqs; i++)
83 *irqs++ = platform_get_irq(pdev, i);
84
85 return 0;
86 }
87
sh_pfc_phys_to_virt(struct sh_pfc * pfc,u32 reg)88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
89 {
90 struct sh_pfc_window *window;
91 phys_addr_t address = reg;
92 unsigned int i;
93
94 /* scan through physical windows and convert address */
95 for (i = 0; i < pfc->num_windows; i++) {
96 window = pfc->windows + i;
97
98 if (address < window->phys)
99 continue;
100
101 if (address >= (window->phys + window->size))
102 continue;
103
104 return window->virt + (address - window->phys);
105 }
106
107 BUG();
108 return NULL;
109 }
110
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
112 {
113 unsigned int offset;
114 unsigned int i;
115
116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
117 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
118
119 if (pin <= range->end)
120 return pin >= range->start
121 ? offset + pin - range->start : -1;
122
123 offset += range->end - range->start + 1;
124 }
125
126 return -EINVAL;
127 }
128
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
130 {
131 if (enum_id < r->begin)
132 return 0;
133
134 if (enum_id > r->end)
135 return 0;
136
137 return 1;
138 }
139
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
141 {
142 switch (reg_width) {
143 case 8:
144 return ioread8(mapped_reg);
145 case 16:
146 return ioread16(mapped_reg);
147 case 32:
148 return ioread32(mapped_reg);
149 }
150
151 BUG();
152 return 0;
153 }
154
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
156 u32 data)
157 {
158 switch (reg_width) {
159 case 8:
160 iowrite8(data, mapped_reg);
161 return;
162 case 16:
163 iowrite16(data, mapped_reg);
164 return;
165 case 32:
166 iowrite32(data, mapped_reg);
167 return;
168 }
169
170 BUG();
171 }
172
sh_pfc_read(struct sh_pfc * pfc,u32 reg)173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
174 {
175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
176 }
177
sh_pfc_unlock_reg(struct sh_pfc * pfc,u32 reg,u32 data)178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
179 {
180 u32 unlock;
181
182 if (!pfc->info->unlock_reg)
183 return;
184
185 if (pfc->info->unlock_reg >= 0x80000000UL)
186 unlock = pfc->info->unlock_reg;
187 else
188 /* unlock_reg is a mask */
189 unlock = reg & ~pfc->info->unlock_reg;
190
191 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
192 }
193
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
195 {
196 sh_pfc_unlock_reg(pfc, reg, data);
197 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
198 }
199
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
201 const struct pinmux_cfg_reg *crp,
202 unsigned int in_pos,
203 void __iomem **mapped_regp, u32 *maskp,
204 unsigned int *posp)
205 {
206 unsigned int k;
207
208 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
209
210 if (crp->field_width) {
211 *maskp = (1 << crp->field_width) - 1;
212 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
213 } else {
214 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
215 *posp = crp->reg_width;
216 for (k = 0; k <= in_pos; k++)
217 *posp -= abs(crp->var_field_width[k]);
218 }
219 }
220
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
222 const struct pinmux_cfg_reg *crp,
223 unsigned int field, u32 value)
224 {
225 void __iomem *mapped_reg;
226 unsigned int pos;
227 u32 mask, data;
228
229 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
230
231 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
232 "r_width = %u, f_width = %u\n",
233 crp->reg, value, field, crp->reg_width, hweight32(mask));
234
235 mask = ~(mask << pos);
236 value = value << pos;
237
238 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
239 data &= mask;
240 data |= value;
241
242 sh_pfc_unlock_reg(pfc, crp->reg, data);
243 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
244 }
245
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
247 const struct pinmux_cfg_reg **crp,
248 unsigned int *fieldp, u32 *valuep)
249 {
250 unsigned int k = 0;
251
252 while (1) {
253 const struct pinmux_cfg_reg *config_reg =
254 pfc->info->cfg_regs + k;
255 unsigned int r_width = config_reg->reg_width;
256 unsigned int f_width = config_reg->field_width;
257 unsigned int curr_width;
258 unsigned int bit_pos;
259 unsigned int pos = 0;
260 unsigned int m = 0;
261
262 if (!r_width)
263 break;
264
265 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
266 u32 ncomb;
267 u32 n;
268
269 if (f_width) {
270 curr_width = f_width;
271 } else {
272 curr_width = abs(config_reg->var_field_width[m]);
273 if (config_reg->var_field_width[m] < 0)
274 continue;
275 }
276
277 ncomb = 1 << curr_width;
278 for (n = 0; n < ncomb; n++) {
279 if (config_reg->enum_ids[pos + n] == enum_id) {
280 *crp = config_reg;
281 *fieldp = m;
282 *valuep = n;
283 return 0;
284 }
285 }
286 pos += ncomb;
287 }
288 k++;
289 }
290
291 return -EINVAL;
292 }
293
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)294 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
295 u16 *enum_idp)
296 {
297 const u16 *data = pfc->info->pinmux_data;
298 unsigned int k;
299
300 if (pos) {
301 *enum_idp = data[pos + 1];
302 return pos + 1;
303 }
304
305 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
306 if (data[k] == mark) {
307 *enum_idp = data[k + 1];
308 return k + 1;
309 }
310 }
311
312 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
313 mark);
314 return -EINVAL;
315 }
316
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)317 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
318 {
319 const struct pinmux_range *range;
320 int pos = 0;
321
322 switch (pinmux_type) {
323 case PINMUX_TYPE_GPIO:
324 case PINMUX_TYPE_FUNCTION:
325 range = NULL;
326 break;
327
328 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
329 case PINMUX_TYPE_OUTPUT:
330 range = &pfc->info->output;
331 break;
332
333 case PINMUX_TYPE_INPUT:
334 range = &pfc->info->input;
335 break;
336 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
337
338 default:
339 return -EINVAL;
340 }
341
342 /* Iterate over all the configuration fields we need to update. */
343 while (1) {
344 const struct pinmux_cfg_reg *cr;
345 unsigned int field;
346 u16 enum_id;
347 u32 value;
348 int in_range;
349 int ret;
350
351 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
352 if (pos < 0)
353 return pos;
354
355 if (!enum_id)
356 break;
357
358 /* Check if the configuration field selects a function. If it
359 * doesn't, skip the field if it's not applicable to the
360 * requested pinmux type.
361 */
362 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
363 if (!in_range) {
364 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
365 /* Functions are allowed to modify all
366 * fields.
367 */
368 in_range = 1;
369 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
370 /* Input/output types can only modify fields
371 * that correspond to their respective ranges.
372 */
373 in_range = sh_pfc_enum_in_range(enum_id, range);
374
375 /*
376 * special case pass through for fixed
377 * input-only or output-only pins without
378 * function enum register association.
379 */
380 if (in_range && enum_id == range->force)
381 continue;
382 }
383 /* GPIOs are only allowed to modify function fields. */
384 }
385
386 if (!in_range)
387 continue;
388
389 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
390 if (ret < 0)
391 return ret;
392
393 sh_pfc_write_config_reg(pfc, cr, field, value);
394 }
395
396 return 0;
397 }
398
sh_pfc_init_ranges(struct sh_pfc * pfc)399 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
400 {
401 struct sh_pfc_pin_range *range;
402 unsigned int nr_ranges;
403 unsigned int i;
404
405 if (pfc->info->pins[0].pin == (u16)-1) {
406 /* Pin number -1 denotes that the SoC doesn't report pin numbers
407 * in its pin arrays yet. Consider the pin numbers range as
408 * continuous and allocate a single range.
409 */
410 pfc->nr_ranges = 1;
411 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
412 GFP_KERNEL);
413 if (pfc->ranges == NULL)
414 return -ENOMEM;
415
416 pfc->ranges->start = 0;
417 pfc->ranges->end = pfc->info->nr_pins - 1;
418 pfc->nr_gpio_pins = pfc->info->nr_pins;
419
420 return 0;
421 }
422
423 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
424 * be sorted by pin numbers, and pins without a GPIO port must come
425 * last.
426 */
427 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
428 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
429 nr_ranges++;
430 }
431
432 pfc->nr_ranges = nr_ranges;
433 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
434 GFP_KERNEL);
435 if (pfc->ranges == NULL)
436 return -ENOMEM;
437
438 range = pfc->ranges;
439 range->start = pfc->info->pins[0].pin;
440
441 for (i = 1; i < pfc->info->nr_pins; ++i) {
442 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
443 continue;
444
445 range->end = pfc->info->pins[i-1].pin;
446 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
447 pfc->nr_gpio_pins = range->end + 1;
448
449 range++;
450 range->start = pfc->info->pins[i].pin;
451 }
452
453 range->end = pfc->info->pins[i-1].pin;
454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
455 pfc->nr_gpio_pins = range->end + 1;
456
457 return 0;
458 }
459
460 #ifdef CONFIG_OF
461 static const struct of_device_id sh_pfc_of_table[] = {
462 #ifdef CONFIG_PINCTRL_PFC_EMEV2
463 {
464 .compatible = "renesas,pfc-emev2",
465 .data = &emev2_pinmux_info,
466 },
467 #endif
468 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
469 {
470 .compatible = "renesas,pfc-r8a73a4",
471 .data = &r8a73a4_pinmux_info,
472 },
473 #endif
474 #ifdef CONFIG_PINCTRL_PFC_R8A7740
475 {
476 .compatible = "renesas,pfc-r8a7740",
477 .data = &r8a7740_pinmux_info,
478 },
479 #endif
480 #ifdef CONFIG_PINCTRL_PFC_R8A7742
481 {
482 .compatible = "renesas,pfc-r8a7742",
483 .data = &r8a7742_pinmux_info,
484 },
485 #endif
486 #ifdef CONFIG_PINCTRL_PFC_R8A7743
487 {
488 .compatible = "renesas,pfc-r8a7743",
489 .data = &r8a7743_pinmux_info,
490 },
491 #endif
492 #ifdef CONFIG_PINCTRL_PFC_R8A7744
493 {
494 .compatible = "renesas,pfc-r8a7744",
495 .data = &r8a7744_pinmux_info,
496 },
497 #endif
498 #ifdef CONFIG_PINCTRL_PFC_R8A7745
499 {
500 .compatible = "renesas,pfc-r8a7745",
501 .data = &r8a7745_pinmux_info,
502 },
503 #endif
504 #ifdef CONFIG_PINCTRL_PFC_R8A77470
505 {
506 .compatible = "renesas,pfc-r8a77470",
507 .data = &r8a77470_pinmux_info,
508 },
509 #endif
510 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
511 {
512 .compatible = "renesas,pfc-r8a774a1",
513 .data = &r8a774a1_pinmux_info,
514 },
515 #endif
516 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
517 {
518 .compatible = "renesas,pfc-r8a774b1",
519 .data = &r8a774b1_pinmux_info,
520 },
521 #endif
522 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
523 {
524 .compatible = "renesas,pfc-r8a774c0",
525 .data = &r8a774c0_pinmux_info,
526 },
527 #endif
528 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
529 {
530 .compatible = "renesas,pfc-r8a774e1",
531 .data = &r8a774e1_pinmux_info,
532 },
533 #endif
534 #ifdef CONFIG_PINCTRL_PFC_R8A7778
535 {
536 .compatible = "renesas,pfc-r8a7778",
537 .data = &r8a7778_pinmux_info,
538 },
539 #endif
540 #ifdef CONFIG_PINCTRL_PFC_R8A7779
541 {
542 .compatible = "renesas,pfc-r8a7779",
543 .data = &r8a7779_pinmux_info,
544 },
545 #endif
546 #ifdef CONFIG_PINCTRL_PFC_R8A7790
547 {
548 .compatible = "renesas,pfc-r8a7790",
549 .data = &r8a7790_pinmux_info,
550 },
551 #endif
552 #ifdef CONFIG_PINCTRL_PFC_R8A7791
553 {
554 .compatible = "renesas,pfc-r8a7791",
555 .data = &r8a7791_pinmux_info,
556 },
557 #endif
558 #ifdef CONFIG_PINCTRL_PFC_R8A7792
559 {
560 .compatible = "renesas,pfc-r8a7792",
561 .data = &r8a7792_pinmux_info,
562 },
563 #endif
564 #ifdef CONFIG_PINCTRL_PFC_R8A7793
565 {
566 .compatible = "renesas,pfc-r8a7793",
567 .data = &r8a7793_pinmux_info,
568 },
569 #endif
570 #ifdef CONFIG_PINCTRL_PFC_R8A7794
571 {
572 .compatible = "renesas,pfc-r8a7794",
573 .data = &r8a7794_pinmux_info,
574 },
575 #endif
576 /*
577 * Both r8a7795 entries must be present to make sanity checks work, but only
578 * the first entry is actually used.
579 * R-Car H3 ES1.x is matched using soc_device_match() instead.
580 */
581 #ifdef CONFIG_PINCTRL_PFC_R8A77951
582 {
583 .compatible = "renesas,pfc-r8a7795",
584 .data = &r8a77951_pinmux_info,
585 },
586 #endif
587 #ifdef CONFIG_PINCTRL_PFC_R8A77950
588 {
589 .compatible = "renesas,pfc-r8a7795",
590 .data = &r8a77950_pinmux_info,
591 },
592 #endif
593 #ifdef CONFIG_PINCTRL_PFC_R8A77960
594 {
595 .compatible = "renesas,pfc-r8a7796",
596 .data = &r8a77960_pinmux_info,
597 },
598 #endif
599 #ifdef CONFIG_PINCTRL_PFC_R8A77961
600 {
601 .compatible = "renesas,pfc-r8a77961",
602 .data = &r8a77961_pinmux_info,
603 },
604 #endif
605 #ifdef CONFIG_PINCTRL_PFC_R8A77965
606 {
607 .compatible = "renesas,pfc-r8a77965",
608 .data = &r8a77965_pinmux_info,
609 },
610 #endif
611 #ifdef CONFIG_PINCTRL_PFC_R8A77970
612 {
613 .compatible = "renesas,pfc-r8a77970",
614 .data = &r8a77970_pinmux_info,
615 },
616 #endif
617 #ifdef CONFIG_PINCTRL_PFC_R8A77980
618 {
619 .compatible = "renesas,pfc-r8a77980",
620 .data = &r8a77980_pinmux_info,
621 },
622 #endif
623 #ifdef CONFIG_PINCTRL_PFC_R8A77990
624 {
625 .compatible = "renesas,pfc-r8a77990",
626 .data = &r8a77990_pinmux_info,
627 },
628 #endif
629 #ifdef CONFIG_PINCTRL_PFC_R8A77995
630 {
631 .compatible = "renesas,pfc-r8a77995",
632 .data = &r8a77995_pinmux_info,
633 },
634 #endif
635 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
636 {
637 .compatible = "renesas,pfc-r8a779a0",
638 .data = &r8a779a0_pinmux_info,
639 },
640 #endif
641 #ifdef CONFIG_PINCTRL_PFC_R8A779F0
642 {
643 .compatible = "renesas,pfc-r8a779f0",
644 .data = &r8a779f0_pinmux_info,
645 },
646 #endif
647 #ifdef CONFIG_PINCTRL_PFC_SH73A0
648 {
649 .compatible = "renesas,pfc-sh73a0",
650 .data = &sh73a0_pinmux_info,
651 },
652 #endif
653 { },
654 };
655 #endif
656
657 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
sh_pfc_nop_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)658 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
659 {
660 }
661
sh_pfc_save_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)662 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
663 {
664 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
665 }
666
sh_pfc_restore_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)667 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
668 {
669 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
670 }
671
sh_pfc_walk_regs(struct sh_pfc * pfc,void (* do_reg)(struct sh_pfc * pfc,u32 reg,unsigned int idx))672 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
673 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
674 {
675 unsigned int i, n = 0;
676
677 if (pfc->info->cfg_regs)
678 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
679 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
680
681 if (pfc->info->drive_regs)
682 for (i = 0; pfc->info->drive_regs[i].reg; i++)
683 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
684
685 if (pfc->info->bias_regs)
686 for (i = 0; pfc->info->bias_regs[i].puen ||
687 pfc->info->bias_regs[i].pud; i++) {
688 if (pfc->info->bias_regs[i].puen)
689 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
690 if (pfc->info->bias_regs[i].pud)
691 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
692 }
693
694 if (pfc->info->ioctrl_regs)
695 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
696 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
697
698 return n;
699 }
700
sh_pfc_suspend_init(struct sh_pfc * pfc)701 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
702 {
703 unsigned int n;
704
705 /* This is the best we can do to check for the presence of PSCI */
706 if (!psci_ops.cpu_suspend)
707 return 0;
708
709 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
710 if (!n)
711 return 0;
712
713 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
714 sizeof(*pfc->saved_regs),
715 GFP_KERNEL);
716 if (!pfc->saved_regs)
717 return -ENOMEM;
718
719 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
720 return 0;
721 }
722
sh_pfc_suspend_noirq(struct device * dev)723 static int sh_pfc_suspend_noirq(struct device *dev)
724 {
725 struct sh_pfc *pfc = dev_get_drvdata(dev);
726
727 if (pfc->saved_regs)
728 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
729 return 0;
730 }
731
sh_pfc_resume_noirq(struct device * dev)732 static int sh_pfc_resume_noirq(struct device *dev)
733 {
734 struct sh_pfc *pfc = dev_get_drvdata(dev);
735
736 if (pfc->saved_regs)
737 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
738 return 0;
739 }
740
741 static const struct dev_pm_ops sh_pfc_pm = {
742 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
743 };
744 #define DEV_PM_OPS &sh_pfc_pm
745 #else
sh_pfc_suspend_init(struct sh_pfc * pfc)746 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
747 #define DEV_PM_OPS NULL
748 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
749
750 #ifdef DEBUG
751 #define SH_PFC_MAX_REGS 300
752 #define SH_PFC_MAX_ENUMS 5000
753
754 static unsigned int sh_pfc_errors __initdata;
755 static unsigned int sh_pfc_warnings __initdata;
756 static bool sh_pfc_bias_done __initdata;
757 static bool sh_pfc_drive_done __initdata;
758 static bool sh_pfc_power_done __initdata;
759 static struct {
760 u32 reg;
761 u32 bits;
762 } *sh_pfc_regs __initdata;
763 static u32 sh_pfc_num_regs __initdata;
764 static u16 *sh_pfc_enums __initdata;
765 static u32 sh_pfc_num_enums __initdata;
766
767 #define sh_pfc_err(fmt, ...) \
768 do { \
769 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
770 sh_pfc_errors++; \
771 } while (0)
772
773 #define sh_pfc_err_once(type, fmt, ...) \
774 do { \
775 if (!sh_pfc_ ## type ## _done) { \
776 sh_pfc_ ## type ## _done = true; \
777 sh_pfc_err(fmt, ##__VA_ARGS__); \
778 } \
779 } while (0)
780
781 #define sh_pfc_warn(fmt, ...) \
782 do { \
783 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
784 sh_pfc_warnings++; \
785 } while (0)
786
is0s(const u16 * enum_ids,unsigned int n)787 static bool __init is0s(const u16 *enum_ids, unsigned int n)
788 {
789 unsigned int i;
790
791 for (i = 0; i < n; i++)
792 if (enum_ids[i])
793 return false;
794
795 return true;
796 }
797
same_name(const char * a,const char * b)798 static bool __init same_name(const char *a, const char *b)
799 {
800 return a && b && !strcmp(a, b);
801 }
802
sh_pfc_check_reg(const char * drvname,u32 reg,u32 bits)803 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
804 {
805 unsigned int i;
806
807 for (i = 0; i < sh_pfc_num_regs; i++) {
808 if (reg != sh_pfc_regs[i].reg)
809 continue;
810
811 if (bits & sh_pfc_regs[i].bits)
812 sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg,
813 bits & sh_pfc_regs[i].bits);
814
815 sh_pfc_regs[i].bits |= bits;
816 return;
817 }
818
819 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
820 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
821 return;
822 }
823
824 sh_pfc_regs[sh_pfc_num_regs].reg = reg;
825 sh_pfc_regs[sh_pfc_num_regs].bits = bits;
826 sh_pfc_num_regs++;
827 }
828
sh_pfc_check_enum(const char * drvname,u16 enum_id)829 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
830 {
831 unsigned int i;
832
833 for (i = 0; i < sh_pfc_num_enums; i++) {
834 if (enum_id == sh_pfc_enums[i])
835 return -EINVAL;
836 }
837
838 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
839 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
840 return 0;
841 }
842
843 sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
844 return 0;
845 }
846
sh_pfc_check_reg_enums(const char * drvname,u32 reg,const u16 * enums,unsigned int n)847 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
848 const u16 *enums, unsigned int n)
849 {
850 unsigned int i;
851
852 for (i = 0; i < n; i++) {
853 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
854 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
855 enums[i]);
856 }
857 }
858
sh_pfc_find_pin(const struct sh_pfc_soc_info * info,u32 reg,unsigned int pin)859 static const struct sh_pfc_pin __init *sh_pfc_find_pin(
860 const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
861 {
862 const char *drvname = info->name;
863 unsigned int i;
864
865 if (pin == SH_PFC_PIN_NONE)
866 return NULL;
867
868 for (i = 0; i < info->nr_pins; i++) {
869 if (pin == info->pins[i].pin)
870 return &info->pins[i];
871 }
872
873 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
874 return NULL;
875 }
876
sh_pfc_check_cfg_reg(const char * drvname,const struct pinmux_cfg_reg * cfg_reg)877 static void __init sh_pfc_check_cfg_reg(const char *drvname,
878 const struct pinmux_cfg_reg *cfg_reg)
879 {
880 unsigned int i, n, rw, r;
881 int fw;
882
883 sh_pfc_check_reg(drvname, cfg_reg->reg,
884 GENMASK(cfg_reg->reg_width - 1, 0));
885
886 if (cfg_reg->field_width) {
887 fw = cfg_reg->field_width;
888 n = (cfg_reg->reg_width / fw) << fw;
889 for (i = 0, r = 0; i < n; i += 1 << fw) {
890 if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
891 r++;
892 }
893
894 if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
895 sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
896 cfg_reg->reg);
897
898 /* Skip field checks (done at build time) */
899 goto check_enum_ids;
900 }
901
902 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
903 if (fw < 0) {
904 rw += -fw;
905 } else {
906 if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
907 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
908 cfg_reg->reg, rw, rw + fw - 1);
909 n += 1 << fw;
910 rw += fw;
911 }
912 }
913
914 if (rw != cfg_reg->reg_width)
915 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
916 cfg_reg->reg, rw, cfg_reg->reg_width);
917
918 if (n != cfg_reg->nr_enum_ids)
919 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
920 cfg_reg->reg, cfg_reg->nr_enum_ids, n);
921
922 check_enum_ids:
923 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
924 }
925
sh_pfc_check_drive_reg(const struct sh_pfc_soc_info * info,const struct pinmux_drive_reg * drive)926 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
927 const struct pinmux_drive_reg *drive)
928 {
929 const char *drvname = info->name;
930 const struct sh_pfc_pin *pin;
931 unsigned int i;
932
933 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
934 const struct pinmux_drive_reg_field *field = &drive->fields[i];
935
936 if (!field->pin && !field->offset && !field->size)
937 continue;
938
939 sh_pfc_check_reg(info->name, drive->reg,
940 GENMASK(field->offset + field->size - 1,
941 field->offset));
942
943 pin = sh_pfc_find_pin(info, drive->reg, field->pin);
944 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
945 sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
946 drive->reg, i, pin->name);
947 }
948 }
949
sh_pfc_check_bias_reg(const struct sh_pfc_soc_info * info,const struct pinmux_bias_reg * bias)950 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
951 const struct pinmux_bias_reg *bias)
952 {
953 const char *drvname = info->name;
954 const struct sh_pfc_pin *pin;
955 unsigned int i;
956 u32 bits;
957
958 for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++)
959 if (bias->pins[i] != SH_PFC_PIN_NONE)
960 bits |= BIT(i);
961
962 if (bias->puen)
963 sh_pfc_check_reg(info->name, bias->puen, bits);
964 if (bias->pud)
965 sh_pfc_check_reg(info->name, bias->pud, bits);
966 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
967 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
968 if (!pin)
969 continue;
970
971 if (bias->puen && bias->pud) {
972 /*
973 * Pull-enable and pull-up/down control registers
974 * As some SoCs have pins that support only pull-up
975 * or pull-down, we just check for one of them
976 */
977 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
978 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
979 bias->puen, i, pin->name);
980 } else if (bias->puen) {
981 /* Pull-up control register only */
982 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
983 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
984 bias->puen, i, pin->name);
985 } else if (bias->pud) {
986 /* Pull-down control register only */
987 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
988 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
989 bias->pud, i, pin->name);
990 }
991 }
992 }
993
sh_pfc_compare_groups(const char * drvname,const struct sh_pfc_pin_group * a,const struct sh_pfc_pin_group * b)994 static void __init sh_pfc_compare_groups(const char *drvname,
995 const struct sh_pfc_pin_group *a,
996 const struct sh_pfc_pin_group *b)
997 {
998 unsigned int i;
999 size_t len;
1000
1001 if (same_name(a->name, b->name))
1002 sh_pfc_err("group %s: name conflict\n", a->name);
1003
1004 if (a->nr_pins > b->nr_pins)
1005 swap(a, b);
1006
1007 len = a->nr_pins * sizeof(a->pins[0]);
1008 for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
1009 if (a->pins == b->pins + i || a->mux == b->mux + i ||
1010 memcmp(a->pins, b->pins + i, len) ||
1011 memcmp(a->mux, b->mux + i, len))
1012 continue;
1013
1014 if (a->nr_pins == b->nr_pins)
1015 sh_pfc_warn("group %s can be an alias for %s\n",
1016 a->name, b->name);
1017 else
1018 sh_pfc_warn("group %s is a subset of %s\n", a->name,
1019 b->name);
1020 }
1021 }
1022
sh_pfc_check_info(const struct sh_pfc_soc_info * info)1023 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
1024 {
1025 const struct pinmux_drive_reg *drive_regs = info->drive_regs;
1026 #define drive_nfields ARRAY_SIZE(drive_regs->fields)
1027 #define drive_ofs(i) drive_regs[(i) / drive_nfields]
1028 #define drive_reg(i) drive_ofs(i).reg
1029 #define drive_bit(i) ((i) % drive_nfields)
1030 #define drive_field(i) drive_ofs(i).fields[drive_bit(i)]
1031 const struct pinmux_bias_reg *bias_regs = info->bias_regs;
1032 #define bias_npins ARRAY_SIZE(bias_regs->pins)
1033 #define bias_ofs(i) bias_regs[(i) / bias_npins]
1034 #define bias_puen(i) bias_ofs(i).puen
1035 #define bias_pud(i) bias_ofs(i).pud
1036 #define bias_bit(i) ((i) % bias_npins)
1037 #define bias_pin(i) bias_ofs(i).pins[bias_bit(i)]
1038 const char *drvname = info->name;
1039 unsigned int *refcnts;
1040 unsigned int i, j, k;
1041
1042 pr_info("sh_pfc: Checking %s\n", drvname);
1043 sh_pfc_num_regs = 0;
1044 sh_pfc_num_enums = 0;
1045 sh_pfc_bias_done = false;
1046 sh_pfc_drive_done = false;
1047 sh_pfc_power_done = false;
1048
1049 /* Check pins */
1050 for (i = 0; i < info->nr_pins; i++) {
1051 const struct sh_pfc_pin *pin = &info->pins[i];
1052 unsigned int x;
1053
1054 if (!pin->name) {
1055 sh_pfc_err("empty pin %u\n", i);
1056 continue;
1057 }
1058 for (j = 0; j < i; j++) {
1059 const struct sh_pfc_pin *pin2 = &info->pins[j];
1060
1061 if (same_name(pin->name, pin2->name))
1062 sh_pfc_err("pin %s: name conflict\n",
1063 pin->name);
1064
1065 if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
1066 sh_pfc_err("pin %s/%s: pin %u conflict\n",
1067 pin->name, pin2->name, pin->pin);
1068
1069 if (pin->enum_id && pin->enum_id == pin2->enum_id)
1070 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
1071 pin->name, pin2->name,
1072 pin->enum_id);
1073 }
1074
1075 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
1076 if (!info->ops || !info->ops->get_bias ||
1077 !info->ops->set_bias)
1078 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
1079
1080 if (!bias_regs &&
1081 (!info->ops || !info->ops->pin_to_portcr))
1082 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
1083 }
1084
1085 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
1086 const struct pinmux_bias_reg *bias_reg =
1087 rcar_pin_to_bias_reg(info, pin->pin, &x);
1088
1089 if (!bias_reg ||
1090 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
1091 !bias_reg->puen))
1092 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
1093 pin->name);
1094
1095 if (!bias_reg ||
1096 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
1097 !bias_reg->pud))
1098 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
1099 pin->name);
1100 }
1101
1102 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
1103 if (!drive_regs) {
1104 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
1105 } else {
1106 for (j = 0; drive_reg(j); j++) {
1107 if (!drive_field(j).pin &&
1108 !drive_field(j).offset &&
1109 !drive_field(j).size)
1110 continue;
1111
1112 if (drive_field(j).pin == pin->pin)
1113 break;
1114 }
1115
1116 if (!drive_reg(j))
1117 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
1118 pin->name);
1119 }
1120 }
1121
1122 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
1123 if (!info->ops || !info->ops->pin_to_pocctrl)
1124 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
1125 else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
1126 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
1127 pin->name);
1128 } else if (info->ops && info->ops->pin_to_pocctrl &&
1129 info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
1130 sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
1131 pin->name);
1132 }
1133 }
1134
1135 /* Check groups and functions */
1136 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
1137 if (!refcnts)
1138 return;
1139
1140 for (i = 0; i < info->nr_functions; i++) {
1141 const struct sh_pfc_function *func = &info->functions[i];
1142
1143 if (!func->name) {
1144 sh_pfc_err("empty function %u\n", i);
1145 continue;
1146 }
1147 for (j = 0; j < i; j++) {
1148 if (same_name(func->name, info->functions[j].name))
1149 sh_pfc_err("function %s: name conflict\n",
1150 func->name);
1151 }
1152 for (j = 0; j < func->nr_groups; j++) {
1153 for (k = 0; k < info->nr_groups; k++) {
1154 if (same_name(func->groups[j],
1155 info->groups[k].name)) {
1156 refcnts[k]++;
1157 break;
1158 }
1159 }
1160
1161 if (k == info->nr_groups)
1162 sh_pfc_err("function %s: group %s not found\n",
1163 func->name, func->groups[j]);
1164 }
1165 }
1166
1167 for (i = 0; i < info->nr_groups; i++) {
1168 const struct sh_pfc_pin_group *group = &info->groups[i];
1169
1170 if (!group->name) {
1171 sh_pfc_err("empty group %u\n", i);
1172 continue;
1173 }
1174 for (j = 0; j < i; j++)
1175 sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1176
1177 if (!refcnts[i])
1178 sh_pfc_err("orphan group %s\n", group->name);
1179 else if (refcnts[i] > 1)
1180 sh_pfc_warn("group %s referenced by %u functions\n",
1181 group->name, refcnts[i]);
1182 }
1183
1184 kfree(refcnts);
1185
1186 /* Check config register descriptions */
1187 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1188 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1189
1190 /* Check drive strength registers */
1191 for (i = 0; drive_regs && drive_regs[i].reg; i++)
1192 sh_pfc_check_drive_reg(info, &drive_regs[i]);
1193
1194 for (i = 0; drive_regs && drive_reg(i); i++) {
1195 if (!drive_field(i).pin && !drive_field(i).offset &&
1196 !drive_field(i).size)
1197 continue;
1198
1199 for (j = 0; j < i; j++) {
1200 if (drive_field(i).pin == drive_field(j).pin &&
1201 drive_field(j).offset && drive_field(j).size) {
1202 sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1203 drive_reg(i), drive_bit(i),
1204 drive_reg(j), drive_bit(j));
1205 }
1206 }
1207 }
1208
1209 /* Check bias registers */
1210 for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
1211 sh_pfc_check_bias_reg(info, &bias_regs[i]);
1212
1213 for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
1214 if (bias_pin(i) == SH_PFC_PIN_NONE)
1215 continue;
1216
1217 for (j = 0; j < i; j++) {
1218 if (bias_pin(i) != bias_pin(j))
1219 continue;
1220
1221 if (bias_puen(i) && bias_puen(j))
1222 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1223 bias_puen(i), bias_bit(i),
1224 bias_puen(j), bias_bit(j));
1225 if (bias_pud(i) && bias_pud(j))
1226 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1227 bias_pud(i), bias_bit(i),
1228 bias_pud(j), bias_bit(j));
1229 }
1230 }
1231
1232 /* Check ioctrl registers */
1233 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1234 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
1235
1236 /* Check data registers */
1237 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1238 sh_pfc_check_reg(drvname, info->data_regs[i].reg,
1239 GENMASK(info->data_regs[i].reg_width - 1, 0));
1240 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1241 info->data_regs[i].enum_ids,
1242 info->data_regs[i].reg_width);
1243 }
1244
1245 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1246 /* Check function GPIOs */
1247 for (i = 0; i < info->nr_func_gpios; i++) {
1248 const struct pinmux_func *func = &info->func_gpios[i];
1249
1250 if (!func->name) {
1251 sh_pfc_err("empty function gpio %u\n", i);
1252 continue;
1253 }
1254 for (j = 0; j < i; j++) {
1255 if (same_name(func->name, info->func_gpios[j].name))
1256 sh_pfc_err("func_gpio %s: name conflict\n",
1257 func->name);
1258 }
1259 if (sh_pfc_check_enum(drvname, func->enum_id))
1260 sh_pfc_err("%s enum_id %u conflict\n", func->name,
1261 func->enum_id);
1262 }
1263 #endif
1264 }
1265
sh_pfc_check_driver(const struct platform_driver * pdrv)1266 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1267 {
1268 unsigned int i;
1269
1270 if (!IS_ENABLED(CONFIG_SUPERH) &&
1271 !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1272 return;
1273
1274 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1275 GFP_KERNEL);
1276 if (!sh_pfc_regs)
1277 return;
1278
1279 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1280 GFP_KERNEL);
1281 if (!sh_pfc_enums)
1282 goto free_regs;
1283
1284 pr_warn("sh_pfc: Checking builtin pinmux tables\n");
1285
1286 for (i = 0; pdrv->id_table[i].name[0]; i++)
1287 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1288
1289 #ifdef CONFIG_OF
1290 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1291 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1292 #endif
1293
1294 pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors,
1295 sh_pfc_warnings);
1296
1297 kfree(sh_pfc_enums);
1298 free_regs:
1299 kfree(sh_pfc_regs);
1300 }
1301
1302 #else /* !DEBUG */
sh_pfc_check_driver(struct platform_driver * pdrv)1303 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1304 #endif /* !DEBUG */
1305
1306 #ifdef CONFIG_OF
sh_pfc_quirk_match(void)1307 static const void *sh_pfc_quirk_match(void)
1308 {
1309 #ifdef CONFIG_PINCTRL_PFC_R8A77950
1310 const struct soc_device_attribute *match;
1311 static const struct soc_device_attribute quirks[] = {
1312 {
1313 .soc_id = "r8a7795", .revision = "ES1.*",
1314 .data = &r8a77950_pinmux_info,
1315 },
1316 { /* sentinel */ }
1317 };
1318
1319 match = soc_device_match(quirks);
1320 if (match)
1321 return match->data;
1322 #endif /* CONFIG_PINCTRL_PFC_R8A77950 */
1323
1324 return NULL;
1325 }
1326 #endif /* CONFIG_OF */
1327
sh_pfc_probe(struct platform_device * pdev)1328 static int sh_pfc_probe(struct platform_device *pdev)
1329 {
1330 const struct sh_pfc_soc_info *info;
1331 struct sh_pfc *pfc;
1332 int ret;
1333
1334 #ifdef CONFIG_OF
1335 if (pdev->dev.of_node) {
1336 info = sh_pfc_quirk_match();
1337 if (!info)
1338 info = of_device_get_match_data(&pdev->dev);
1339 } else
1340 #endif
1341 info = (const void *)platform_get_device_id(pdev)->driver_data;
1342
1343 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1344 if (pfc == NULL)
1345 return -ENOMEM;
1346
1347 pfc->info = info;
1348 pfc->dev = &pdev->dev;
1349
1350 ret = sh_pfc_map_resources(pfc, pdev);
1351 if (unlikely(ret < 0))
1352 return ret;
1353
1354 spin_lock_init(&pfc->lock);
1355
1356 if (info->ops && info->ops->init) {
1357 ret = info->ops->init(pfc);
1358 if (ret < 0)
1359 return ret;
1360
1361 /* .init() may have overridden pfc->info */
1362 info = pfc->info;
1363 }
1364
1365 ret = sh_pfc_suspend_init(pfc);
1366 if (ret)
1367 return ret;
1368
1369 /* Enable dummy states for those platforms without pinctrl support */
1370 if (!of_have_populated_dt())
1371 pinctrl_provide_dummies();
1372
1373 ret = sh_pfc_init_ranges(pfc);
1374 if (ret < 0)
1375 return ret;
1376
1377 /*
1378 * Initialize pinctrl bindings first
1379 */
1380 ret = sh_pfc_register_pinctrl(pfc);
1381 if (unlikely(ret != 0))
1382 return ret;
1383
1384 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1385 /*
1386 * Then the GPIO chip
1387 */
1388 ret = sh_pfc_register_gpiochip(pfc);
1389 if (unlikely(ret != 0)) {
1390 /*
1391 * If the GPIO chip fails to come up we still leave the
1392 * PFC state as it is, given that there are already
1393 * extant users of it that have succeeded by this point.
1394 */
1395 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1396 }
1397 #endif
1398
1399 platform_set_drvdata(pdev, pfc);
1400
1401 dev_info(pfc->dev, "%s support registered\n", info->name);
1402
1403 return 0;
1404 }
1405
1406 static const struct platform_device_id sh_pfc_id_table[] = {
1407 #ifdef CONFIG_PINCTRL_PFC_SH7203
1408 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1409 #endif
1410 #ifdef CONFIG_PINCTRL_PFC_SH7264
1411 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1412 #endif
1413 #ifdef CONFIG_PINCTRL_PFC_SH7269
1414 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1415 #endif
1416 #ifdef CONFIG_PINCTRL_PFC_SH7720
1417 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1418 #endif
1419 #ifdef CONFIG_PINCTRL_PFC_SH7722
1420 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1421 #endif
1422 #ifdef CONFIG_PINCTRL_PFC_SH7723
1423 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1424 #endif
1425 #ifdef CONFIG_PINCTRL_PFC_SH7724
1426 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1427 #endif
1428 #ifdef CONFIG_PINCTRL_PFC_SH7734
1429 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1430 #endif
1431 #ifdef CONFIG_PINCTRL_PFC_SH7757
1432 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1433 #endif
1434 #ifdef CONFIG_PINCTRL_PFC_SH7785
1435 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1436 #endif
1437 #ifdef CONFIG_PINCTRL_PFC_SH7786
1438 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1439 #endif
1440 #ifdef CONFIG_PINCTRL_PFC_SHX3
1441 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1442 #endif
1443 { },
1444 };
1445
1446 static struct platform_driver sh_pfc_driver = {
1447 .probe = sh_pfc_probe,
1448 .id_table = sh_pfc_id_table,
1449 .driver = {
1450 .name = DRV_NAME,
1451 .of_match_table = of_match_ptr(sh_pfc_of_table),
1452 .pm = DEV_PM_OPS,
1453 },
1454 };
1455
sh_pfc_init(void)1456 static int __init sh_pfc_init(void)
1457 {
1458 sh_pfc_check_driver(&sh_pfc_driver);
1459 return platform_driver_register(&sh_pfc_driver);
1460 }
1461 postcore_initcall(sh_pfc_init);
1462