1 /*
2 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
3 *
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
7 */
8
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11
12 #include <asm/io.h>
13 #include <asm/bootinfo.h>
14 #include <asm/sgialib.h>
15 #include <asm/sgi/mc.h>
16 #include <asm/sgi/hpc3.h>
17 #include <asm/sgi/ip22.h>
18
19 struct sgimc_regs *sgimc;
20
get_bank_addr(unsigned int memconfig)21 static inline unsigned long get_bank_addr(unsigned int memconfig)
22 {
23 return ((memconfig & SGIMC_MCONFIG_BASEADDR) <<
24 ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22));
25 }
26
get_bank_size(unsigned int memconfig)27 static inline unsigned long get_bank_size(unsigned int memconfig)
28 {
29 return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) <<
30 ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
31 }
32
get_bank_config(int bank)33 static inline unsigned int get_bank_config(int bank)
34 {
35 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
36 return bank % 2 ? res & 0xffff : res >> 16;
37 }
38
39 struct mem {
40 unsigned long addr;
41 unsigned long size;
42 };
43
44 /*
45 * Detect installed memory, do some sanity checks and notify kernel about it
46 */
probe_memory(void)47 static void probe_memory(void)
48 {
49 int i, j, found, cnt = 0;
50 struct mem bank[4];
51 struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
52
53 printk(KERN_INFO "MC: Probing memory configuration:\n");
54 for (i = 0; i < ARRAY_SIZE(bank); i++) {
55 unsigned int tmp = get_bank_config(i);
56 if (!(tmp & SGIMC_MCONFIG_BVALID))
57 continue;
58
59 bank[cnt].size = get_bank_size(tmp);
60 bank[cnt].addr = get_bank_addr(tmp);
61 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
62 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
63 cnt++;
64 }
65
66 /* And you thought bubble sort is dead algorithm... */
67 do {
68 unsigned long addr, size;
69
70 found = 0;
71 for (i = 1; i < cnt; i++)
72 if (bank[i-1].addr > bank[i].addr) {
73 addr = bank[i].addr;
74 size = bank[i].size;
75 bank[i].addr = bank[i-1].addr;
76 bank[i].size = bank[i-1].size;
77 bank[i-1].addr = addr;
78 bank[i-1].size = size;
79 found = 1;
80 }
81 } while (found);
82
83 /* Figure out how are memory banks mapped into spaces */
84 for (i = 0; i < cnt; i++) {
85 found = 0;
86 for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
87 if (space[j].addr + space[j].size == bank[i].addr) {
88 space[j].size += bank[i].size;
89 found = 1;
90 }
91 /* There is either hole or overlapping memory */
92 if (!found)
93 printk(KERN_CRIT "MC: Memory configuration mismatch "
94 "(%08lx), expect Bus Error soon\n",
95 bank[i].addr);
96 }
97
98 for (i = 0; i < ARRAY_SIZE(space); i++)
99 if (space[i].size)
100 add_memory_region(space[i].addr, space[i].size,
101 BOOT_MEM_RAM);
102 }
103
sgimc_init(void)104 void __init sgimc_init(void)
105 {
106 u32 tmp;
107
108 /* ioremap can't fail */
109 sgimc = (struct sgimc_regs *)
110 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
111
112 printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
113 (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
114
115 /* Place the MC into a known state. This must be done before
116 * interrupts are first enabled etc.
117 */
118
119 /* Step 0: Make sure we turn off the watchdog in case it's
120 * still running (which might be the case after a
121 * soft reboot).
122 */
123 tmp = sgimc->cpuctrl0;
124 tmp &= ~SGIMC_CCTRL0_WDOG;
125 sgimc->cpuctrl0 = tmp;
126
127 /* Step 1: The CPU/GIO error status registers will not latch
128 * up a new error status until the register has been
129 * cleared by the cpu. These status registers are
130 * cleared by writing any value to them.
131 */
132 sgimc->cstat = sgimc->gstat = 0;
133
134 /* Step 2: Enable all parity checking in cpu control register
135 * zero.
136 */
137 tmp = sgimc->cpuctrl0;
138 tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
139 SGIMC_CCTRL0_R4KNOCHKPARR);
140 sgimc->cpuctrl0 = tmp;
141
142 /* Step 3: Setup the MC write buffer depth, this is controlled
143 * in cpu control register 1 in the lower 4 bits.
144 */
145 tmp = sgimc->cpuctrl1;
146 tmp &= ~0xf;
147 tmp |= 0xd;
148 sgimc->cpuctrl1 = tmp;
149
150 /* Step 4: Initialize the RPSS divider register to run as fast
151 * as it can correctly operate. The register is laid
152 * out as follows:
153 *
154 * ----------------------------------------
155 * | RESERVED | INCREMENT | DIVIDER |
156 * ----------------------------------------
157 * 31 16 15 8 7 0
158 *
159 * DIVIDER determines how often a 'tick' happens,
160 * INCREMENT determines by how the RPSS increment
161 * registers value increases at each 'tick'. Thus,
162 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
163 */
164 sgimc->divider = 0x101;
165
166 /* Step 5: Initialize GIO64 arbitrator configuration register.
167 *
168 * NOTE: HPC init code in sgihpc_init() must run before us because
169 * we need to know Guiness vs. FullHouse and the board
170 * revision on this machine. You have been warned.
171 */
172
173 /* First the basic invariants across all GIO64 implementations. */
174 tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
175 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
176
177 if (ip22_is_fullhouse()) {
178 /* Fullhouse specific settings. */
179 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
180 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
181 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
182 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
183 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
184 } else {
185 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
186 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
187 tmp |= SGIMC_GIOPAR_PLINEEXP1;
188 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
189 tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */
190 }
191 } else {
192 /* Guiness specific settings. */
193 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
194 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
195 }
196 sgimc->giopar = tmp; /* poof */
197
198 probe_memory();
199 }
200
prom_meminit(void)201 void __init prom_meminit(void) {}
prom_free_prom_memory(void)202 void __init prom_free_prom_memory (void) {}
203