1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
13 #include <linux/io.h>
14
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/hypervisor.h>
19 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <linux/topology.h>
22 #include <linux/cpumask.h>
23 #include <asm/pgtable.h>
24 #include <asm/atomic.h>
25 #include <asm/proto.h>
26 #include <asm/setup.h>
27 #include <asm/apic.h>
28 #include <asm/desc.h>
29 #include <asm/i387.h>
30 #include <asm/mtrr.h>
31 #include <linux/numa.h>
32 #include <asm/asm.h>
33 #include <asm/cpu.h>
34 #include <asm/mce.h>
35 #include <asm/msr.h>
36 #include <asm/pat.h>
37
38 #ifdef CONFIG_X86_LOCAL_APIC
39 #include <asm/uv/uv.h>
40 #endif
41
42 #include "cpu.h"
43
44 /* all of these masks are initialized in setup_cpu_local_masks() */
45 cpumask_var_t cpu_initialized_mask;
46 cpumask_var_t cpu_callout_mask;
47 cpumask_var_t cpu_callin_mask;
48
49 /* representing cpus for which sibling maps can be computed */
50 cpumask_var_t cpu_sibling_setup_mask;
51
52 /* correctly size the local cpu masks */
setup_cpu_local_masks(void)53 void __init setup_cpu_local_masks(void)
54 {
55 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
56 alloc_bootmem_cpumask_var(&cpu_callin_mask);
57 alloc_bootmem_cpumask_var(&cpu_callout_mask);
58 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
59 }
60
default_init(struct cpuinfo_x86 * c)61 static void __cpuinit default_init(struct cpuinfo_x86 *c)
62 {
63 #ifdef CONFIG_X86_64
64 cpu_detect_cache_sizes(c);
65 #else
66 /* Not much we can do here... */
67 /* Check if at least it has cpuid */
68 if (c->cpuid_level == -1) {
69 /* No cpuid. It must be an ancient CPU */
70 if (c->x86 == 4)
71 strcpy(c->x86_model_id, "486");
72 else if (c->x86 == 3)
73 strcpy(c->x86_model_id, "386");
74 }
75 #endif
76 }
77
78 static const struct cpu_dev __cpuinitconst default_cpu = {
79 .c_init = default_init,
80 .c_vendor = "Unknown",
81 .c_x86_vendor = X86_VENDOR_UNKNOWN,
82 };
83
84 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
85
86 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
87 #ifdef CONFIG_X86_64
88 /*
89 * We need valid kernel segments for data and code in long mode too
90 * IRET will check the segment types kkeil 2000/10/28
91 * Also sysret mandates a special GDT layout
92 *
93 * TLS descriptors are currently at a different place compared to i386.
94 * Hopefully nobody expects them at a fixed place (Wine?)
95 */
96 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
97 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
99 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
102 #else
103 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
107 /*
108 * Segments used for calling PnP BIOS have byte granularity.
109 * They code segments and data segments have fixed 64k limits,
110 * the transfer segment sizes are set at run time.
111 */
112 /* 32-bit code */
113 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
114 /* 16-bit code */
115 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
116 /* 16-bit data */
117 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
118 /* 16-bit data */
119 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
120 /* 16-bit data */
121 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 /*
123 * The APM segments have byte granularity and their bases
124 * are set at run time. All have 64k limits.
125 */
126 /* 32-bit code */
127 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
128 /* 16-bit code */
129 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
130 /* data */
131 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
132
133 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 GDT_STACK_CANARY_INIT
136 #endif
137 } };
138 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
139
x86_xsave_setup(char * s)140 static int __init x86_xsave_setup(char *s)
141 {
142 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
143 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
144 return 1;
145 }
146 __setup("noxsave", x86_xsave_setup);
147
x86_xsaveopt_setup(char * s)148 static int __init x86_xsaveopt_setup(char *s)
149 {
150 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
151 return 1;
152 }
153 __setup("noxsaveopt", x86_xsaveopt_setup);
154
155 #ifdef CONFIG_X86_32
156 static int cachesize_override __cpuinitdata = -1;
157 static int disable_x86_serial_nr __cpuinitdata = 1;
158
cachesize_setup(char * str)159 static int __init cachesize_setup(char *str)
160 {
161 get_option(&str, &cachesize_override);
162 return 1;
163 }
164 __setup("cachesize=", cachesize_setup);
165
x86_fxsr_setup(char * s)166 static int __init x86_fxsr_setup(char *s)
167 {
168 setup_clear_cpu_cap(X86_FEATURE_FXSR);
169 setup_clear_cpu_cap(X86_FEATURE_XMM);
170 return 1;
171 }
172 __setup("nofxsr", x86_fxsr_setup);
173
x86_sep_setup(char * s)174 static int __init x86_sep_setup(char *s)
175 {
176 setup_clear_cpu_cap(X86_FEATURE_SEP);
177 return 1;
178 }
179 __setup("nosep", x86_sep_setup);
180
181 /* Standard macro to see if a specific flag is changeable */
flag_is_changeable_p(u32 flag)182 static inline int flag_is_changeable_p(u32 flag)
183 {
184 u32 f1, f2;
185
186 /*
187 * Cyrix and IDT cpus allow disabling of CPUID
188 * so the code below may return different results
189 * when it is executed before and after enabling
190 * the CPUID. Add "volatile" to not allow gcc to
191 * optimize the subsequent calls to this function.
192 */
193 asm volatile ("pushfl \n\t"
194 "pushfl \n\t"
195 "popl %0 \n\t"
196 "movl %0, %1 \n\t"
197 "xorl %2, %0 \n\t"
198 "pushl %0 \n\t"
199 "popfl \n\t"
200 "pushfl \n\t"
201 "popl %0 \n\t"
202 "popfl \n\t"
203
204 : "=&r" (f1), "=&r" (f2)
205 : "ir" (flag));
206
207 return ((f1^f2) & flag) != 0;
208 }
209
210 /* Probe for the CPUID instruction */
have_cpuid_p(void)211 static int __cpuinit have_cpuid_p(void)
212 {
213 return flag_is_changeable_p(X86_EFLAGS_ID);
214 }
215
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)216 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
217 {
218 unsigned long lo, hi;
219
220 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
221 return;
222
223 /* Disable processor serial number: */
224
225 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
226 lo |= 0x200000;
227 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
228
229 printk(KERN_NOTICE "CPU serial number disabled.\n");
230 clear_cpu_cap(c, X86_FEATURE_PN);
231
232 /* Disabling the serial number may affect the cpuid level */
233 c->cpuid_level = cpuid_eax(0);
234 }
235
x86_serial_nr_setup(char * s)236 static int __init x86_serial_nr_setup(char *s)
237 {
238 disable_x86_serial_nr = 0;
239 return 1;
240 }
241 __setup("serialnumber", x86_serial_nr_setup);
242 #else
flag_is_changeable_p(u32 flag)243 static inline int flag_is_changeable_p(u32 flag)
244 {
245 return 1;
246 }
247 /* Probe for the CPUID instruction */
have_cpuid_p(void)248 static inline int have_cpuid_p(void)
249 {
250 return 1;
251 }
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)252 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
253 {
254 }
255 #endif
256
257 /*
258 * Some CPU features depend on higher CPUID levels, which may not always
259 * be available due to CPUID level capping or broken virtualization
260 * software. Add those features to this table to auto-disable them.
261 */
262 struct cpuid_dependent_feature {
263 u32 feature;
264 u32 level;
265 };
266
267 static const struct cpuid_dependent_feature __cpuinitconst
268 cpuid_dependent_features[] = {
269 { X86_FEATURE_MWAIT, 0x00000005 },
270 { X86_FEATURE_DCA, 0x00000009 },
271 { X86_FEATURE_XSAVE, 0x0000000d },
272 { 0, 0 }
273 };
274
filter_cpuid_features(struct cpuinfo_x86 * c,bool warn)275 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
276 {
277 const struct cpuid_dependent_feature *df;
278
279 for (df = cpuid_dependent_features; df->feature; df++) {
280
281 if (!cpu_has(c, df->feature))
282 continue;
283 /*
284 * Note: cpuid_level is set to -1 if unavailable, but
285 * extended_extended_level is set to 0 if unavailable
286 * and the legitimate extended levels are all negative
287 * when signed; hence the weird messing around with
288 * signs here...
289 */
290 if (!((s32)df->level < 0 ?
291 (u32)df->level > (u32)c->extended_cpuid_level :
292 (s32)df->level > (s32)c->cpuid_level))
293 continue;
294
295 clear_cpu_cap(c, df->feature);
296 if (!warn)
297 continue;
298
299 printk(KERN_WARNING
300 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
301 x86_cap_flags[df->feature], df->level);
302 }
303 }
304
305 /*
306 * Naming convention should be: <Name> [(<Codename>)]
307 * This table only is used unless init_<vendor>() below doesn't set it;
308 * in particular, if CPUID levels 0x80000002..4 are supported, this
309 * isn't used
310 */
311
312 /* Look up CPU names by table lookup. */
table_lookup_model(struct cpuinfo_x86 * c)313 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
314 {
315 const struct cpu_model_info *info;
316
317 if (c->x86_model >= 16)
318 return NULL; /* Range check */
319
320 if (!this_cpu)
321 return NULL;
322
323 info = this_cpu->c_models;
324
325 while (info && info->family) {
326 if (info->family == c->x86)
327 return info->model_names[c->x86_model];
328 info++;
329 }
330 return NULL; /* Not found */
331 }
332
333 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
334 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
335
load_percpu_segment(int cpu)336 void load_percpu_segment(int cpu)
337 {
338 #ifdef CONFIG_X86_32
339 loadsegment(fs, __KERNEL_PERCPU);
340 #else
341 loadsegment(gs, 0);
342 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
343 #endif
344 load_stack_canary_segment();
345 }
346
347 /*
348 * Current gdt points %fs at the "master" per-cpu area: after this,
349 * it's on the real one.
350 */
switch_to_new_gdt(int cpu)351 void switch_to_new_gdt(int cpu)
352 {
353 struct desc_ptr gdt_descr;
354
355 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
356 gdt_descr.size = GDT_SIZE - 1;
357 load_gdt(&gdt_descr);
358 /* Reload the per-cpu base */
359
360 load_percpu_segment(cpu);
361 }
362
363 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
364
get_model_name(struct cpuinfo_x86 * c)365 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
366 {
367 unsigned int *v;
368 char *p, *q;
369
370 if (c->extended_cpuid_level < 0x80000004)
371 return;
372
373 v = (unsigned int *)c->x86_model_id;
374 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
375 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
376 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
377 c->x86_model_id[48] = 0;
378
379 /*
380 * Intel chips right-justify this string for some dumb reason;
381 * undo that brain damage:
382 */
383 p = q = &c->x86_model_id[0];
384 while (*p == ' ')
385 p++;
386 if (p != q) {
387 while (*p)
388 *q++ = *p++;
389 while (q <= &c->x86_model_id[48])
390 *q++ = '\0'; /* Zero-pad the rest */
391 }
392 }
393
cpu_detect_cache_sizes(struct cpuinfo_x86 * c)394 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
395 {
396 unsigned int n, dummy, ebx, ecx, edx, l2size;
397
398 n = c->extended_cpuid_level;
399
400 if (n >= 0x80000005) {
401 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
402 c->x86_cache_size = (ecx>>24) + (edx>>24);
403 #ifdef CONFIG_X86_64
404 /* On K8 L1 TLB is inclusive, so don't count it */
405 c->x86_tlbsize = 0;
406 #endif
407 }
408
409 if (n < 0x80000006) /* Some chips just has a large L1. */
410 return;
411
412 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
413 l2size = ecx >> 16;
414
415 #ifdef CONFIG_X86_64
416 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
417 #else
418 /* do processor-specific cache resizing */
419 if (this_cpu->c_size_cache)
420 l2size = this_cpu->c_size_cache(c, l2size);
421
422 /* Allow user to override all this if necessary. */
423 if (cachesize_override != -1)
424 l2size = cachesize_override;
425
426 if (l2size == 0)
427 return; /* Again, no L2 cache is possible */
428 #endif
429
430 c->x86_cache_size = l2size;
431 }
432
detect_ht(struct cpuinfo_x86 * c)433 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
434 {
435 #ifdef CONFIG_X86_HT
436 u32 eax, ebx, ecx, edx;
437 int index_msb, core_bits;
438 static bool printed;
439
440 if (!cpu_has(c, X86_FEATURE_HT))
441 return;
442
443 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
444 goto out;
445
446 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
447 return;
448
449 cpuid(1, &eax, &ebx, &ecx, &edx);
450
451 smp_num_siblings = (ebx & 0xff0000) >> 16;
452
453 if (smp_num_siblings == 1) {
454 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
455 goto out;
456 }
457
458 if (smp_num_siblings <= 1)
459 goto out;
460
461 if (smp_num_siblings > nr_cpu_ids) {
462 pr_warning("CPU: Unsupported number of siblings %d",
463 smp_num_siblings);
464 smp_num_siblings = 1;
465 return;
466 }
467
468 index_msb = get_count_order(smp_num_siblings);
469 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
470
471 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
472
473 index_msb = get_count_order(smp_num_siblings);
474
475 core_bits = get_count_order(c->x86_max_cores);
476
477 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
478 ((1 << core_bits) - 1);
479
480 out:
481 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
482 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
483 c->phys_proc_id);
484 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
485 c->cpu_core_id);
486 printed = 1;
487 }
488 #endif
489 }
490
get_cpu_vendor(struct cpuinfo_x86 * c)491 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
492 {
493 char *v = c->x86_vendor_id;
494 int i;
495
496 for (i = 0; i < X86_VENDOR_NUM; i++) {
497 if (!cpu_devs[i])
498 break;
499
500 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
501 (cpu_devs[i]->c_ident[1] &&
502 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
503
504 this_cpu = cpu_devs[i];
505 c->x86_vendor = this_cpu->c_x86_vendor;
506 return;
507 }
508 }
509
510 printk_once(KERN_ERR
511 "CPU: vendor_id '%s' unknown, using generic init.\n" \
512 "CPU: Your system may be unstable.\n", v);
513
514 c->x86_vendor = X86_VENDOR_UNKNOWN;
515 this_cpu = &default_cpu;
516 }
517
cpu_detect(struct cpuinfo_x86 * c)518 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
519 {
520 /* Get vendor name */
521 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
522 (unsigned int *)&c->x86_vendor_id[0],
523 (unsigned int *)&c->x86_vendor_id[8],
524 (unsigned int *)&c->x86_vendor_id[4]);
525
526 c->x86 = 4;
527 /* Intel-defined flags: level 0x00000001 */
528 if (c->cpuid_level >= 0x00000001) {
529 u32 junk, tfms, cap0, misc;
530
531 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
532 c->x86 = (tfms >> 8) & 0xf;
533 c->x86_model = (tfms >> 4) & 0xf;
534 c->x86_mask = tfms & 0xf;
535
536 if (c->x86 == 0xf)
537 c->x86 += (tfms >> 20) & 0xff;
538 if (c->x86 >= 0x6)
539 c->x86_model += ((tfms >> 16) & 0xf) << 4;
540
541 if (cap0 & (1<<19)) {
542 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
543 c->x86_cache_alignment = c->x86_clflush_size;
544 }
545 }
546 }
547
get_cpu_cap(struct cpuinfo_x86 * c)548 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
549 {
550 u32 tfms, xlvl;
551 u32 ebx;
552
553 /* Intel-defined flags: level 0x00000001 */
554 if (c->cpuid_level >= 0x00000001) {
555 u32 capability, excap;
556
557 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
558 c->x86_capability[0] = capability;
559 c->x86_capability[4] = excap;
560 }
561
562 /* Additional Intel-defined flags: level 0x00000007 */
563 if (c->cpuid_level >= 0x00000007) {
564 u32 eax, ebx, ecx, edx;
565
566 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
567
568 if (eax > 0)
569 c->x86_capability[9] = ebx;
570 }
571
572 /* AMD-defined flags: level 0x80000001 */
573 xlvl = cpuid_eax(0x80000000);
574 c->extended_cpuid_level = xlvl;
575
576 if ((xlvl & 0xffff0000) == 0x80000000) {
577 if (xlvl >= 0x80000001) {
578 c->x86_capability[1] = cpuid_edx(0x80000001);
579 c->x86_capability[6] = cpuid_ecx(0x80000001);
580 }
581 }
582
583 if (c->extended_cpuid_level >= 0x80000008) {
584 u32 eax = cpuid_eax(0x80000008);
585
586 c->x86_virt_bits = (eax >> 8) & 0xff;
587 c->x86_phys_bits = eax & 0xff;
588 }
589 #ifdef CONFIG_X86_32
590 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
591 c->x86_phys_bits = 36;
592 #endif
593
594 if (c->extended_cpuid_level >= 0x80000007)
595 c->x86_power = cpuid_edx(0x80000007);
596
597 init_scattered_cpuid_features(c);
598 }
599
identify_cpu_without_cpuid(struct cpuinfo_x86 * c)600 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
601 {
602 #ifdef CONFIG_X86_32
603 int i;
604
605 /*
606 * First of all, decide if this is a 486 or higher
607 * It's a 486 if we can modify the AC flag
608 */
609 if (flag_is_changeable_p(X86_EFLAGS_AC))
610 c->x86 = 4;
611 else
612 c->x86 = 3;
613
614 for (i = 0; i < X86_VENDOR_NUM; i++)
615 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
616 c->x86_vendor_id[0] = 0;
617 cpu_devs[i]->c_identify(c);
618 if (c->x86_vendor_id[0]) {
619 get_cpu_vendor(c);
620 break;
621 }
622 }
623 #endif
624 }
625
626 /*
627 * Do minimum CPU detection early.
628 * Fields really needed: vendor, cpuid_level, family, model, mask,
629 * cache alignment.
630 * The others are not touched to avoid unwanted side effects.
631 *
632 * WARNING: this function is only called on the BP. Don't add code here
633 * that is supposed to run on all CPUs.
634 */
early_identify_cpu(struct cpuinfo_x86 * c)635 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
636 {
637 #ifdef CONFIG_X86_64
638 c->x86_clflush_size = 64;
639 c->x86_phys_bits = 36;
640 c->x86_virt_bits = 48;
641 #else
642 c->x86_clflush_size = 32;
643 c->x86_phys_bits = 32;
644 c->x86_virt_bits = 32;
645 #endif
646 c->x86_cache_alignment = c->x86_clflush_size;
647
648 memset(&c->x86_capability, 0, sizeof c->x86_capability);
649 c->extended_cpuid_level = 0;
650
651 if (!have_cpuid_p())
652 identify_cpu_without_cpuid(c);
653
654 /* cyrix could have cpuid enabled via c_identify()*/
655 if (!have_cpuid_p())
656 return;
657
658 cpu_detect(c);
659
660 get_cpu_vendor(c);
661
662 get_cpu_cap(c);
663
664 if (this_cpu->c_early_init)
665 this_cpu->c_early_init(c);
666
667 #ifdef CONFIG_SMP
668 c->cpu_index = 0;
669 #endif
670 filter_cpuid_features(c, false);
671 }
672
early_cpu_init(void)673 void __init early_cpu_init(void)
674 {
675 const struct cpu_dev *const *cdev;
676 int count = 0;
677
678 #ifdef CONFIG_PROCESSOR_SELECT
679 printk(KERN_INFO "KERNEL supported cpus:\n");
680 #endif
681
682 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
683 const struct cpu_dev *cpudev = *cdev;
684
685 if (count >= X86_VENDOR_NUM)
686 break;
687 cpu_devs[count] = cpudev;
688 count++;
689
690 #ifdef CONFIG_PROCESSOR_SELECT
691 {
692 unsigned int j;
693
694 for (j = 0; j < 2; j++) {
695 if (!cpudev->c_ident[j])
696 continue;
697 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
698 cpudev->c_ident[j]);
699 }
700 }
701 #endif
702 }
703 early_identify_cpu(&boot_cpu_data);
704 }
705
706 /*
707 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
708 * unfortunately, that's not true in practice because of early VIA
709 * chips and (more importantly) broken virtualizers that are not easy
710 * to detect. In the latter case it doesn't even *fail* reliably, so
711 * probing for it doesn't even work. Disable it completely on 32-bit
712 * unless we can find a reliable way to detect all the broken cases.
713 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
714 */
detect_nopl(struct cpuinfo_x86 * c)715 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
716 {
717 #ifdef CONFIG_X86_32
718 clear_cpu_cap(c, X86_FEATURE_NOPL);
719 #else
720 set_cpu_cap(c, X86_FEATURE_NOPL);
721 #endif
722 }
723
generic_identify(struct cpuinfo_x86 * c)724 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
725 {
726 c->extended_cpuid_level = 0;
727
728 if (!have_cpuid_p())
729 identify_cpu_without_cpuid(c);
730
731 /* cyrix could have cpuid enabled via c_identify()*/
732 if (!have_cpuid_p())
733 return;
734
735 cpu_detect(c);
736
737 get_cpu_vendor(c);
738
739 get_cpu_cap(c);
740
741 if (c->cpuid_level >= 0x00000001) {
742 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
743 #ifdef CONFIG_X86_32
744 # ifdef CONFIG_X86_HT
745 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
746 # else
747 c->apicid = c->initial_apicid;
748 # endif
749 #endif
750
751 #ifdef CONFIG_X86_HT
752 c->phys_proc_id = c->initial_apicid;
753 #endif
754 }
755
756 get_model_name(c); /* Default name */
757
758 detect_nopl(c);
759 }
760
761 /*
762 * This does the hard work of actually picking apart the CPU stuff...
763 */
identify_cpu(struct cpuinfo_x86 * c)764 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
765 {
766 int i;
767
768 c->loops_per_jiffy = loops_per_jiffy;
769 c->x86_cache_size = -1;
770 c->x86_vendor = X86_VENDOR_UNKNOWN;
771 c->x86_model = c->x86_mask = 0; /* So far unknown... */
772 c->x86_vendor_id[0] = '\0'; /* Unset */
773 c->x86_model_id[0] = '\0'; /* Unset */
774 c->x86_max_cores = 1;
775 c->x86_coreid_bits = 0;
776 #ifdef CONFIG_X86_64
777 c->x86_clflush_size = 64;
778 c->x86_phys_bits = 36;
779 c->x86_virt_bits = 48;
780 #else
781 c->cpuid_level = -1; /* CPUID not detected */
782 c->x86_clflush_size = 32;
783 c->x86_phys_bits = 32;
784 c->x86_virt_bits = 32;
785 #endif
786 c->x86_cache_alignment = c->x86_clflush_size;
787 memset(&c->x86_capability, 0, sizeof c->x86_capability);
788
789 generic_identify(c);
790
791 if (this_cpu->c_identify)
792 this_cpu->c_identify(c);
793
794 /* Clear/Set all flags overriden by options, after probe */
795 for (i = 0; i < NCAPINTS; i++) {
796 c->x86_capability[i] &= ~cpu_caps_cleared[i];
797 c->x86_capability[i] |= cpu_caps_set[i];
798 }
799
800 #ifdef CONFIG_X86_64
801 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
802 #endif
803
804 /*
805 * Vendor-specific initialization. In this section we
806 * canonicalize the feature flags, meaning if there are
807 * features a certain CPU supports which CPUID doesn't
808 * tell us, CPUID claiming incorrect flags, or other bugs,
809 * we handle them here.
810 *
811 * At the end of this section, c->x86_capability better
812 * indicate the features this CPU genuinely supports!
813 */
814 if (this_cpu->c_init)
815 this_cpu->c_init(c);
816
817 /* Disable the PN if appropriate */
818 squash_the_stupid_serial_number(c);
819
820 /*
821 * The vendor-specific functions might have changed features.
822 * Now we do "generic changes."
823 */
824
825 /* Filter out anything that depends on CPUID levels we don't have */
826 filter_cpuid_features(c, true);
827
828 /* If the model name is still unset, do table lookup. */
829 if (!c->x86_model_id[0]) {
830 const char *p;
831 p = table_lookup_model(c);
832 if (p)
833 strcpy(c->x86_model_id, p);
834 else
835 /* Last resort... */
836 sprintf(c->x86_model_id, "%02x/%02x",
837 c->x86, c->x86_model);
838 }
839
840 #ifdef CONFIG_X86_64
841 detect_ht(c);
842 #endif
843
844 init_hypervisor(c);
845
846 /*
847 * Clear/Set all flags overriden by options, need do it
848 * before following smp all cpus cap AND.
849 */
850 for (i = 0; i < NCAPINTS; i++) {
851 c->x86_capability[i] &= ~cpu_caps_cleared[i];
852 c->x86_capability[i] |= cpu_caps_set[i];
853 }
854
855 /*
856 * On SMP, boot_cpu_data holds the common feature set between
857 * all CPUs; so make sure that we indicate which features are
858 * common between the CPUs. The first time this routine gets
859 * executed, c == &boot_cpu_data.
860 */
861 if (c != &boot_cpu_data) {
862 /* AND the already accumulated flags with these */
863 for (i = 0; i < NCAPINTS; i++)
864 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
865 }
866
867 /* Init Machine Check Exception if available. */
868 mcheck_cpu_init(c);
869
870 select_idle_routine(c);
871
872 #ifdef CONFIG_NUMA
873 numa_add_cpu(smp_processor_id());
874 #endif
875 }
876
877 #ifdef CONFIG_X86_64
vgetcpu_set_mode(void)878 static void vgetcpu_set_mode(void)
879 {
880 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
881 vgetcpu_mode = VGETCPU_RDTSCP;
882 else
883 vgetcpu_mode = VGETCPU_LSL;
884 }
885 #endif
886
identify_boot_cpu(void)887 void __init identify_boot_cpu(void)
888 {
889 identify_cpu(&boot_cpu_data);
890 init_c1e_mask();
891 #ifdef CONFIG_X86_32
892 sysenter_setup();
893 enable_sep_cpu();
894 #else
895 vgetcpu_set_mode();
896 #endif
897 }
898
identify_secondary_cpu(struct cpuinfo_x86 * c)899 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
900 {
901 BUG_ON(c == &boot_cpu_data);
902 identify_cpu(c);
903 #ifdef CONFIG_X86_32
904 enable_sep_cpu();
905 #endif
906 mtrr_ap_init();
907 }
908
909 struct msr_range {
910 unsigned min;
911 unsigned max;
912 };
913
914 static const struct msr_range msr_range_array[] __cpuinitconst = {
915 { 0x00000000, 0x00000418},
916 { 0xc0000000, 0xc000040b},
917 { 0xc0010000, 0xc0010142},
918 { 0xc0011000, 0xc001103b},
919 };
920
print_cpu_msr(void)921 static void __cpuinit print_cpu_msr(void)
922 {
923 unsigned index_min, index_max;
924 unsigned index;
925 u64 val;
926 int i;
927
928 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
929 index_min = msr_range_array[i].min;
930 index_max = msr_range_array[i].max;
931
932 for (index = index_min; index < index_max; index++) {
933 if (rdmsrl_amd_safe(index, &val))
934 continue;
935 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
936 }
937 }
938 }
939
940 static int show_msr __cpuinitdata;
941
setup_show_msr(char * arg)942 static __init int setup_show_msr(char *arg)
943 {
944 int num;
945
946 get_option(&arg, &num);
947
948 if (num > 0)
949 show_msr = num;
950 return 1;
951 }
952 __setup("show_msr=", setup_show_msr);
953
setup_noclflush(char * arg)954 static __init int setup_noclflush(char *arg)
955 {
956 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
957 return 1;
958 }
959 __setup("noclflush", setup_noclflush);
960
print_cpu_info(struct cpuinfo_x86 * c)961 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
962 {
963 const char *vendor = NULL;
964
965 if (c->x86_vendor < X86_VENDOR_NUM) {
966 vendor = this_cpu->c_vendor;
967 } else {
968 if (c->cpuid_level >= 0)
969 vendor = c->x86_vendor_id;
970 }
971
972 if (vendor && !strstr(c->x86_model_id, vendor))
973 printk(KERN_CONT "%s ", vendor);
974
975 if (c->x86_model_id[0])
976 printk(KERN_CONT "%s", c->x86_model_id);
977 else
978 printk(KERN_CONT "%d86", c->x86);
979
980 if (c->x86_mask || c->cpuid_level >= 0)
981 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
982 else
983 printk(KERN_CONT "\n");
984
985 #ifdef CONFIG_SMP
986 if (c->cpu_index < show_msr)
987 print_cpu_msr();
988 #else
989 if (show_msr)
990 print_cpu_msr();
991 #endif
992 }
993
setup_disablecpuid(char * arg)994 static __init int setup_disablecpuid(char *arg)
995 {
996 int bit;
997
998 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
999 setup_clear_cpu_cap(bit);
1000 else
1001 return 0;
1002
1003 return 1;
1004 }
1005 __setup("clearcpuid=", setup_disablecpuid);
1006
1007 #ifdef CONFIG_X86_64
1008 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1009
1010 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1011 irq_stack_union) __aligned(PAGE_SIZE);
1012
1013 /*
1014 * The following four percpu variables are hot. Align current_task to
1015 * cacheline size such that all four fall in the same cacheline.
1016 */
1017 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1018 &init_task;
1019 EXPORT_PER_CPU_SYMBOL(current_task);
1020
1021 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1022 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1023 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1024
1025 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1026 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1027
1028 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1029
1030 /*
1031 * Special IST stacks which the CPU switches to when it calls
1032 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1033 * limit), all of them are 4K, except the debug stack which
1034 * is 8K.
1035 */
1036 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1037 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1038 [DEBUG_STACK - 1] = DEBUG_STKSZ
1039 };
1040
1041 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1042 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1043
1044 /* May not be marked __init: used by software suspend */
syscall_init(void)1045 void syscall_init(void)
1046 {
1047 /*
1048 * LSTAR and STAR live in a bit strange symbiosis.
1049 * They both write to the same internal register. STAR allows to
1050 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1051 */
1052 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1053 wrmsrl(MSR_LSTAR, system_call);
1054 wrmsrl(MSR_CSTAR, ignore_sysret);
1055
1056 #ifdef CONFIG_IA32_EMULATION
1057 syscall32_cpu_init();
1058 #endif
1059
1060 /* Flags to clear on syscall */
1061 wrmsrl(MSR_SYSCALL_MASK,
1062 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1063 }
1064
1065 unsigned long kernel_eflags;
1066
1067 /*
1068 * Copies of the original ist values from the tss are only accessed during
1069 * debugging, no special alignment required.
1070 */
1071 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1072
1073 #else /* CONFIG_X86_64 */
1074
1075 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1076 EXPORT_PER_CPU_SYMBOL(current_task);
1077
1078 #ifdef CONFIG_CC_STACKPROTECTOR
1079 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1080 #endif
1081
1082 /* Make sure %fs and %gs are initialized properly in idle threads */
idle_regs(struct pt_regs * regs)1083 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1084 {
1085 memset(regs, 0, sizeof(struct pt_regs));
1086 regs->fs = __KERNEL_PERCPU;
1087 regs->gs = __KERNEL_STACK_CANARY;
1088
1089 return regs;
1090 }
1091 #endif /* CONFIG_X86_64 */
1092
1093 /*
1094 * Clear all 6 debug registers:
1095 */
clear_all_debug_regs(void)1096 static void clear_all_debug_regs(void)
1097 {
1098 int i;
1099
1100 for (i = 0; i < 8; i++) {
1101 /* Ignore db4, db5 */
1102 if ((i == 4) || (i == 5))
1103 continue;
1104
1105 set_debugreg(0, i);
1106 }
1107 }
1108
1109 #ifdef CONFIG_KGDB
1110 /*
1111 * Restore debug regs if using kgdbwait and you have a kernel debugger
1112 * connection established.
1113 */
dbg_restore_debug_regs(void)1114 static void dbg_restore_debug_regs(void)
1115 {
1116 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1117 arch_kgdb_ops.correct_hw_break();
1118 }
1119 #else /* ! CONFIG_KGDB */
1120 #define dbg_restore_debug_regs()
1121 #endif /* ! CONFIG_KGDB */
1122
1123 /*
1124 * cpu_init() initializes state that is per-CPU. Some data is already
1125 * initialized (naturally) in the bootstrap process, such as the GDT
1126 * and IDT. We reload them nevertheless, this function acts as a
1127 * 'CPU state barrier', nothing should get across.
1128 * A lot of state is already set up in PDA init for 64 bit
1129 */
1130 #ifdef CONFIG_X86_64
1131
cpu_init(void)1132 void __cpuinit cpu_init(void)
1133 {
1134 struct orig_ist *oist;
1135 struct task_struct *me;
1136 struct tss_struct *t;
1137 unsigned long v;
1138 int cpu;
1139 int i;
1140
1141 cpu = stack_smp_processor_id();
1142 t = &per_cpu(init_tss, cpu);
1143 oist = &per_cpu(orig_ist, cpu);
1144
1145 #ifdef CONFIG_NUMA
1146 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1147 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1148 set_numa_node(early_cpu_to_node(cpu));
1149 #endif
1150
1151 me = current;
1152
1153 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1154 panic("CPU#%d already initialized!\n", cpu);
1155
1156 pr_debug("Initializing CPU#%d\n", cpu);
1157
1158 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1159
1160 /*
1161 * Initialize the per-CPU GDT with the boot GDT,
1162 * and set up the GDT descriptor:
1163 */
1164
1165 switch_to_new_gdt(cpu);
1166 loadsegment(fs, 0);
1167
1168 load_idt((const struct desc_ptr *)&idt_descr);
1169
1170 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1171 syscall_init();
1172
1173 wrmsrl(MSR_FS_BASE, 0);
1174 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1175 barrier();
1176
1177 x86_configure_nx();
1178 if (cpu != 0)
1179 enable_x2apic();
1180
1181 /*
1182 * set up and load the per-CPU TSS
1183 */
1184 if (!oist->ist[0]) {
1185 char *estacks = per_cpu(exception_stacks, cpu);
1186
1187 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1188 estacks += exception_stack_sizes[v];
1189 oist->ist[v] = t->x86_tss.ist[v] =
1190 (unsigned long)estacks;
1191 }
1192 }
1193
1194 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1195
1196 /*
1197 * <= is required because the CPU will access up to
1198 * 8 bits beyond the end of the IO permission bitmap.
1199 */
1200 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1201 t->io_bitmap[i] = ~0UL;
1202
1203 atomic_inc(&init_mm.mm_count);
1204 me->active_mm = &init_mm;
1205 BUG_ON(me->mm);
1206 enter_lazy_tlb(&init_mm, me);
1207
1208 load_sp0(t, ¤t->thread);
1209 set_tss_desc(cpu, t);
1210 load_TR_desc();
1211 load_LDT(&init_mm.context);
1212
1213 clear_all_debug_regs();
1214 dbg_restore_debug_regs();
1215
1216 fpu_init();
1217 xsave_init();
1218
1219 raw_local_save_flags(kernel_eflags);
1220
1221 if (is_uv_system())
1222 uv_cpu_init();
1223 }
1224
1225 #else
1226
cpu_init(void)1227 void __cpuinit cpu_init(void)
1228 {
1229 int cpu = smp_processor_id();
1230 struct task_struct *curr = current;
1231 struct tss_struct *t = &per_cpu(init_tss, cpu);
1232 struct thread_struct *thread = &curr->thread;
1233
1234 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1235 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1236 for (;;)
1237 local_irq_enable();
1238 }
1239
1240 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1241
1242 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1243 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1244
1245 load_idt(&idt_descr);
1246 switch_to_new_gdt(cpu);
1247
1248 /*
1249 * Set up and load the per-CPU TSS and LDT
1250 */
1251 atomic_inc(&init_mm.mm_count);
1252 curr->active_mm = &init_mm;
1253 BUG_ON(curr->mm);
1254 enter_lazy_tlb(&init_mm, curr);
1255
1256 load_sp0(t, thread);
1257 set_tss_desc(cpu, t);
1258 load_TR_desc();
1259 load_LDT(&init_mm.context);
1260
1261 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1262
1263 #ifdef CONFIG_DOUBLEFAULT
1264 /* Set up doublefault TSS pointer in the GDT */
1265 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1266 #endif
1267
1268 clear_all_debug_regs();
1269 dbg_restore_debug_regs();
1270
1271 fpu_init();
1272 xsave_init();
1273 }
1274 #endif
1275