1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #ifndef __XGBE_H__
118 #define __XGBE_H__
119
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/timecounter.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
130 #include <linux/completion.h>
131 #include <linux/cpumask.h>
132 #include <linux/interrupt.h>
133 #include <linux/dcache.h>
134 #include <linux/ethtool.h>
135 #include <linux/list.h>
136
137 #define XGBE_DRV_NAME "amd-xgbe"
138 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
139
140 /* Descriptor related defines */
141 #define XGBE_TX_DESC_CNT 512
142 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
143 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
144 #define XGBE_RX_DESC_CNT 512
145
146 #define XGBE_TX_DESC_CNT_MIN 64
147 #define XGBE_TX_DESC_CNT_MAX 4096
148 #define XGBE_RX_DESC_CNT_MIN 64
149 #define XGBE_RX_DESC_CNT_MAX 4096
150
151 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
152
153 /* Descriptors required for maximum contiguous TSO/GSO packet */
154 #define XGBE_TX_MAX_SPLIT \
155 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
156
157 /* Maximum possible descriptors needed for an SKB:
158 * - Maximum number of SKB frags
159 * - Maximum descriptors for contiguous TSO/GSO packet
160 * - Possible context descriptor
161 * - Possible TSO header descriptor
162 */
163 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
164
165 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
166 #define XGBE_RX_BUF_ALIGN 64
167 #define XGBE_SKB_ALLOC_SIZE 256
168 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
169
170 #define XGBE_MAX_DMA_CHANNELS 16
171 #define XGBE_MAX_QUEUES 16
172 #define XGBE_PRIORITY_QUEUES 8
173 #define XGBE_DMA_STOP_TIMEOUT 1
174
175 /* DMA cache settings - Outer sharable, write-back, write-allocate */
176 #define XGBE_DMA_OS_ARCR 0x002b2b2b
177 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
178
179 /* DMA cache settings - System, no caches used */
180 #define XGBE_DMA_SYS_ARCR 0x00303030
181 #define XGBE_DMA_SYS_AWCR 0x30303030
182
183 /* DMA cache settings - PCI device */
184 #define XGBE_DMA_PCI_ARCR 0x000f0f0f
185 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f
186 #define XGBE_DMA_PCI_AWARCR 0x00000f0f
187
188 /* DMA channel interrupt modes */
189 #define XGBE_IRQ_MODE_EDGE 0
190 #define XGBE_IRQ_MODE_LEVEL 1
191
192 #define XGMAC_MIN_PACKET 60
193 #define XGMAC_STD_PACKET_MTU 1500
194 #define XGMAC_MAX_STD_PACKET 1518
195 #define XGMAC_JUMBO_PACKET_MTU 9000
196 #define XGMAC_MAX_JUMBO_PACKET 9018
197 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
198
199 #define XGMAC_PFC_DATA_LEN 46
200 #define XGMAC_PFC_DELAYS 14000
201
202 #define XGMAC_PRIO_QUEUES(_cnt) \
203 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
204
205 /* Common property names */
206 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
207 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
208 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
209 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
210
211 /* Device-tree clock names */
212 #define XGBE_DMA_CLOCK "dma_clk"
213 #define XGBE_PTP_CLOCK "ptp_clk"
214
215 /* ACPI property names */
216 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
217 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
218
219 /* PCI BAR mapping */
220 #define XGBE_XGMAC_BAR 0
221 #define XGBE_XPCS_BAR 1
222 #define XGBE_MAC_PROP_OFFSET 0x1d000
223 #define XGBE_I2C_CTRL_OFFSET 0x1e000
224
225 /* PCI MSI/MSIx support */
226 #define XGBE_MSI_BASE_COUNT 4
227 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
228
229 /* PCI clock frequencies */
230 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
231 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
232
233 /* Timestamp support - values based on 50MHz PTP clock
234 * 50MHz => 20 nsec
235 */
236 #define XGBE_TSTAMP_SSINC 20
237 #define XGBE_TSTAMP_SNSINC 0
238
239 /* Driver PMT macros */
240 #define XGMAC_DRIVER_CONTEXT 1
241 #define XGMAC_IOCTL_CONTEXT 2
242
243 #define XGMAC_FIFO_MIN_ALLOC 2048
244 #define XGMAC_FIFO_UNIT 256
245 #define XGMAC_FIFO_ALIGN(_x) \
246 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
247 #define XGMAC_FIFO_FC_OFF 2048
248 #define XGMAC_FIFO_FC_MIN 4096
249
250 #define XGBE_TC_MIN_QUANTUM 10
251
252 /* Helper macro for descriptor handling
253 * Always use XGBE_GET_DESC_DATA to access the descriptor data
254 * since the index is free-running and needs to be and-ed
255 * with the descriptor count value of the ring to index to
256 * the proper descriptor data.
257 */
258 #define XGBE_GET_DESC_DATA(_ring, _idx) \
259 ((_ring)->rdata + \
260 ((_idx) & ((_ring)->rdesc_count - 1)))
261
262 /* Default coalescing parameters */
263 #define XGMAC_INIT_DMA_TX_USECS 1000
264 #define XGMAC_INIT_DMA_TX_FRAMES 25
265
266 #define XGMAC_MAX_DMA_RIWT 0xff
267 #define XGMAC_INIT_DMA_RX_USECS 30
268 #define XGMAC_INIT_DMA_RX_FRAMES 25
269
270 /* Flow control queue count */
271 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
272
273 /* Flow control threshold units */
274 #define XGMAC_FLOW_CONTROL_UNIT 512
275 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
276 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
277 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
278 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
279 #define XGMAC_FLOW_CONTROL_MAX 33280
280
281 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
282 #define XGBE_MAC_HASH_TABLE_SIZE 8
283
284 /* Receive Side Scaling */
285 #define XGBE_RSS_HASH_KEY_SIZE 40
286 #define XGBE_RSS_MAX_TABLE_SIZE 256
287 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
288 #define XGBE_RSS_HASH_KEY_TYPE 1
289
290 /* Auto-negotiation */
291 #define XGBE_AN_MS_TIMEOUT 500
292 #define XGBE_LINK_TIMEOUT 5
293 #define XGBE_KR_TRAINING_WAIT_ITER 50
294
295 #define XGBE_SGMII_AN_LINK_STATUS BIT(1)
296 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
297 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
298 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
299 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
300
301 /* ECC correctable error notification window (seconds) */
302 #define XGBE_ECC_LIMIT 60
303
304 /* MDIO port types */
305 #define XGMAC_MAX_C22_PORT 3
306
307 /* Link mode bit operations */
308 #define XGBE_ZERO_SUP(_ls) \
309 ethtool_link_ksettings_zero_link_mode((_ls), supported)
310
311 #define XGBE_SET_SUP(_ls, _mode) \
312 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
313
314 #define XGBE_CLR_SUP(_ls, _mode) \
315 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
316
317 #define XGBE_IS_SUP(_ls, _mode) \
318 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
319
320 #define XGBE_ZERO_ADV(_ls) \
321 ethtool_link_ksettings_zero_link_mode((_ls), advertising)
322
323 #define XGBE_SET_ADV(_ls, _mode) \
324 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
325
326 #define XGBE_CLR_ADV(_ls, _mode) \
327 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
328
329 #define XGBE_ADV(_ls, _mode) \
330 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
331
332 #define XGBE_ZERO_LP_ADV(_ls) \
333 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
334
335 #define XGBE_SET_LP_ADV(_ls, _mode) \
336 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
337
338 #define XGBE_CLR_LP_ADV(_ls, _mode) \
339 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
340
341 #define XGBE_LP_ADV(_ls, _mode) \
342 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
343
344 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \
345 bitmap_copy((_dst)->link_modes._dname, \
346 (_src)->link_modes._sname, \
347 __ETHTOOL_LINK_MODE_MASK_NBITS)
348
349 struct xgbe_prv_data;
350
351 struct xgbe_packet_data {
352 struct sk_buff *skb;
353
354 unsigned int attributes;
355
356 unsigned int errors;
357
358 unsigned int rdesc_count;
359 unsigned int length;
360
361 unsigned int header_len;
362 unsigned int tcp_header_len;
363 unsigned int tcp_payload_len;
364 unsigned short mss;
365
366 unsigned short vlan_ctag;
367
368 u64 rx_tstamp;
369
370 u32 rss_hash;
371 enum pkt_hash_types rss_hash_type;
372
373 unsigned int tx_packets;
374 unsigned int tx_bytes;
375 };
376
377 /* Common Rx and Tx descriptor mapping */
378 struct xgbe_ring_desc {
379 __le32 desc0;
380 __le32 desc1;
381 __le32 desc2;
382 __le32 desc3;
383 };
384
385 /* Page allocation related values */
386 struct xgbe_page_alloc {
387 struct page *pages;
388 unsigned int pages_len;
389 unsigned int pages_offset;
390
391 dma_addr_t pages_dma;
392 };
393
394 /* Ring entry buffer data */
395 struct xgbe_buffer_data {
396 struct xgbe_page_alloc pa;
397 struct xgbe_page_alloc pa_unmap;
398
399 dma_addr_t dma_base;
400 unsigned long dma_off;
401 unsigned int dma_len;
402 };
403
404 /* Tx-related ring data */
405 struct xgbe_tx_ring_data {
406 unsigned int packets; /* BQL packet count */
407 unsigned int bytes; /* BQL byte count */
408 };
409
410 /* Rx-related ring data */
411 struct xgbe_rx_ring_data {
412 struct xgbe_buffer_data hdr; /* Header locations */
413 struct xgbe_buffer_data buf; /* Payload locations */
414
415 unsigned short hdr_len; /* Length of received header */
416 unsigned short len; /* Length of received packet */
417 };
418
419 /* Structure used to hold information related to the descriptor
420 * and the packet associated with the descriptor (always use
421 * the XGBE_GET_DESC_DATA macro to access this data from the ring)
422 */
423 struct xgbe_ring_data {
424 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
425 dma_addr_t rdesc_dma; /* DMA address of descriptor */
426
427 struct sk_buff *skb; /* Virtual address of SKB */
428 dma_addr_t skb_dma; /* DMA address of SKB data */
429 unsigned int skb_dma_len; /* Length of SKB DMA area */
430
431 struct xgbe_tx_ring_data tx; /* Tx-related data */
432 struct xgbe_rx_ring_data rx; /* Rx-related data */
433
434 unsigned int mapped_as_page;
435
436 /* Incomplete receive save location. If the budget is exhausted
437 * or the last descriptor (last normal descriptor or a following
438 * context descriptor) has not been DMA'd yet the current state
439 * of the receive processing needs to be saved.
440 */
441 unsigned int state_saved;
442 struct {
443 struct sk_buff *skb;
444 unsigned int len;
445 unsigned int error;
446 } state;
447 };
448
449 struct xgbe_ring {
450 /* Ring lock - used just for TX rings at the moment */
451 spinlock_t lock;
452
453 /* Per packet related information */
454 struct xgbe_packet_data packet_data;
455
456 /* Virtual/DMA addresses and count of allocated descriptor memory */
457 struct xgbe_ring_desc *rdesc;
458 dma_addr_t rdesc_dma;
459 unsigned int rdesc_count;
460
461 /* Array of descriptor data corresponding the descriptor memory
462 * (always use the XGBE_GET_DESC_DATA macro to access this data)
463 */
464 struct xgbe_ring_data *rdata;
465
466 /* Page allocation for RX buffers */
467 struct xgbe_page_alloc rx_hdr_pa;
468 struct xgbe_page_alloc rx_buf_pa;
469 int node;
470
471 /* Ring index values
472 * cur - Tx: index of descriptor to be used for current transfer
473 * Rx: index of descriptor to check for packet availability
474 * dirty - Tx: index of descriptor to check for transfer complete
475 * Rx: index of descriptor to check for buffer reallocation
476 */
477 unsigned int cur;
478 unsigned int dirty;
479
480 /* Coalesce frame count used for interrupt bit setting */
481 unsigned int coalesce_count;
482
483 union {
484 struct {
485 unsigned int queue_stopped;
486 unsigned int xmit_more;
487 unsigned short cur_mss;
488 unsigned short cur_vlan_ctag;
489 } tx;
490 };
491 } ____cacheline_aligned;
492
493 /* Structure used to describe the descriptor rings associated with
494 * a DMA channel.
495 */
496 struct xgbe_channel {
497 char name[16];
498
499 /* Address of private data area for device */
500 struct xgbe_prv_data *pdata;
501
502 /* Queue index and base address of queue's DMA registers */
503 unsigned int queue_index;
504 void __iomem *dma_regs;
505
506 /* Per channel interrupt irq number */
507 int dma_irq;
508 char dma_irq_name[IFNAMSIZ + 32];
509
510 /* Netdev related settings */
511 struct napi_struct napi;
512
513 /* Per channel interrupt enablement tracker */
514 unsigned int curr_ier;
515 unsigned int saved_ier;
516
517 unsigned int tx_timer_active;
518 struct timer_list tx_timer;
519
520 struct xgbe_ring *tx_ring;
521 struct xgbe_ring *rx_ring;
522
523 int node;
524 cpumask_t affinity_mask;
525 } ____cacheline_aligned;
526
527 enum xgbe_state {
528 XGBE_DOWN,
529 XGBE_LINK_INIT,
530 XGBE_LINK_ERR,
531 XGBE_STOPPED,
532 };
533
534 enum xgbe_int {
535 XGMAC_INT_DMA_CH_SR_TI,
536 XGMAC_INT_DMA_CH_SR_TPS,
537 XGMAC_INT_DMA_CH_SR_TBU,
538 XGMAC_INT_DMA_CH_SR_RI,
539 XGMAC_INT_DMA_CH_SR_RBU,
540 XGMAC_INT_DMA_CH_SR_RPS,
541 XGMAC_INT_DMA_CH_SR_TI_RI,
542 XGMAC_INT_DMA_CH_SR_FBE,
543 XGMAC_INT_DMA_ALL,
544 };
545
546 enum xgbe_int_state {
547 XGMAC_INT_STATE_SAVE,
548 XGMAC_INT_STATE_RESTORE,
549 };
550
551 enum xgbe_ecc_sec {
552 XGBE_ECC_SEC_TX,
553 XGBE_ECC_SEC_RX,
554 XGBE_ECC_SEC_DESC,
555 };
556
557 enum xgbe_speed {
558 XGBE_SPEED_1000 = 0,
559 XGBE_SPEED_2500,
560 XGBE_SPEED_10000,
561 XGBE_SPEEDS,
562 };
563
564 enum xgbe_xpcs_access {
565 XGBE_XPCS_ACCESS_V1 = 0,
566 XGBE_XPCS_ACCESS_V2,
567 };
568
569 enum xgbe_an_mode {
570 XGBE_AN_MODE_CL73 = 0,
571 XGBE_AN_MODE_CL73_REDRV,
572 XGBE_AN_MODE_CL37,
573 XGBE_AN_MODE_CL37_SGMII,
574 XGBE_AN_MODE_NONE,
575 };
576
577 enum xgbe_an {
578 XGBE_AN_READY = 0,
579 XGBE_AN_PAGE_RECEIVED,
580 XGBE_AN_INCOMPAT_LINK,
581 XGBE_AN_COMPLETE,
582 XGBE_AN_NO_LINK,
583 XGBE_AN_ERROR,
584 };
585
586 enum xgbe_rx {
587 XGBE_RX_BPA = 0,
588 XGBE_RX_XNP,
589 XGBE_RX_COMPLETE,
590 XGBE_RX_ERROR,
591 };
592
593 enum xgbe_mode {
594 XGBE_MODE_KX_1000 = 0,
595 XGBE_MODE_KX_2500,
596 XGBE_MODE_KR,
597 XGBE_MODE_X,
598 XGBE_MODE_SGMII_100,
599 XGBE_MODE_SGMII_1000,
600 XGBE_MODE_SFI,
601 XGBE_MODE_UNKNOWN,
602 };
603
604 enum xgbe_speedset {
605 XGBE_SPEEDSET_1000_10000 = 0,
606 XGBE_SPEEDSET_2500_10000,
607 };
608
609 enum xgbe_mdio_mode {
610 XGBE_MDIO_MODE_NONE = 0,
611 XGBE_MDIO_MODE_CL22,
612 XGBE_MDIO_MODE_CL45,
613 };
614
615 enum xgbe_mb_cmd {
616 XGBE_MB_CMD_POWER_OFF = 0,
617 XGBE_MB_CMD_SET_1G,
618 XGBE_MB_CMD_SET_2_5G,
619 XGBE_MB_CMD_SET_10G_SFI,
620 XGBE_MB_CMD_SET_10G_KR,
621 XGBE_MB_CMD_RRC
622 };
623
624 enum xgbe_mb_subcmd {
625 XGBE_MB_SUBCMD_NONE = 0,
626
627 /* 10GbE SFP subcommands */
628 XGBE_MB_SUBCMD_ACTIVE = 0,
629 XGBE_MB_SUBCMD_PASSIVE_1M,
630 XGBE_MB_SUBCMD_PASSIVE_3M,
631 XGBE_MB_SUBCMD_PASSIVE_OTHER,
632
633 /* 1GbE Mode subcommands */
634 XGBE_MB_SUBCMD_10MBITS = 0,
635 XGBE_MB_SUBCMD_100MBITS,
636 XGBE_MB_SUBCMD_1G_SGMII,
637 XGBE_MB_SUBCMD_1G_KX
638 };
639
640 struct xgbe_phy {
641 struct ethtool_link_ksettings lks;
642
643 int address;
644
645 int autoneg;
646 int speed;
647 int duplex;
648
649 int link;
650
651 int pause_autoneg;
652 int tx_pause;
653 int rx_pause;
654 };
655
656 enum xgbe_i2c_cmd {
657 XGBE_I2C_CMD_READ = 0,
658 XGBE_I2C_CMD_WRITE,
659 };
660
661 struct xgbe_i2c_op {
662 enum xgbe_i2c_cmd cmd;
663
664 unsigned int target;
665
666 void *buf;
667 unsigned int len;
668 };
669
670 struct xgbe_i2c_op_state {
671 struct xgbe_i2c_op *op;
672
673 unsigned int tx_len;
674 unsigned char *tx_buf;
675
676 unsigned int rx_len;
677 unsigned char *rx_buf;
678
679 unsigned int tx_abort_source;
680
681 int ret;
682 };
683
684 struct xgbe_i2c {
685 unsigned int started;
686 unsigned int max_speed_mode;
687 unsigned int rx_fifo_size;
688 unsigned int tx_fifo_size;
689
690 struct xgbe_i2c_op_state op_state;
691 };
692
693 struct xgbe_mmc_stats {
694 /* Tx Stats */
695 u64 txoctetcount_gb;
696 u64 txframecount_gb;
697 u64 txbroadcastframes_g;
698 u64 txmulticastframes_g;
699 u64 tx64octets_gb;
700 u64 tx65to127octets_gb;
701 u64 tx128to255octets_gb;
702 u64 tx256to511octets_gb;
703 u64 tx512to1023octets_gb;
704 u64 tx1024tomaxoctets_gb;
705 u64 txunicastframes_gb;
706 u64 txmulticastframes_gb;
707 u64 txbroadcastframes_gb;
708 u64 txunderflowerror;
709 u64 txoctetcount_g;
710 u64 txframecount_g;
711 u64 txpauseframes;
712 u64 txvlanframes_g;
713
714 /* Rx Stats */
715 u64 rxframecount_gb;
716 u64 rxoctetcount_gb;
717 u64 rxoctetcount_g;
718 u64 rxbroadcastframes_g;
719 u64 rxmulticastframes_g;
720 u64 rxcrcerror;
721 u64 rxrunterror;
722 u64 rxjabbererror;
723 u64 rxundersize_g;
724 u64 rxoversize_g;
725 u64 rx64octets_gb;
726 u64 rx65to127octets_gb;
727 u64 rx128to255octets_gb;
728 u64 rx256to511octets_gb;
729 u64 rx512to1023octets_gb;
730 u64 rx1024tomaxoctets_gb;
731 u64 rxunicastframes_g;
732 u64 rxlengtherror;
733 u64 rxoutofrangetype;
734 u64 rxpauseframes;
735 u64 rxfifooverflow;
736 u64 rxvlanframes_gb;
737 u64 rxwatchdogerror;
738 };
739
740 struct xgbe_ext_stats {
741 u64 tx_tso_packets;
742 u64 rx_split_header_packets;
743 u64 rx_buffer_unavailable;
744
745 u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
746 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
747 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
748 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
749
750 u64 tx_vxlan_packets;
751 u64 rx_vxlan_packets;
752 u64 rx_csum_errors;
753 u64 rx_vxlan_csum_errors;
754 };
755
756 struct xgbe_hw_if {
757 int (*tx_complete)(struct xgbe_ring_desc *);
758
759 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
760 int (*config_rx_mode)(struct xgbe_prv_data *);
761
762 int (*enable_rx_csum)(struct xgbe_prv_data *);
763 int (*disable_rx_csum)(struct xgbe_prv_data *);
764
765 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
766 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
767 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
768 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
769 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
770
771 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
772 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
773 int (*set_speed)(struct xgbe_prv_data *, int);
774
775 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
776 enum xgbe_mdio_mode);
777 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int);
778 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16);
779
780 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
781 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
782
783 void (*enable_tx)(struct xgbe_prv_data *);
784 void (*disable_tx)(struct xgbe_prv_data *);
785 void (*enable_rx)(struct xgbe_prv_data *);
786 void (*disable_rx)(struct xgbe_prv_data *);
787
788 void (*powerup_tx)(struct xgbe_prv_data *);
789 void (*powerdown_tx)(struct xgbe_prv_data *);
790 void (*powerup_rx)(struct xgbe_prv_data *);
791 void (*powerdown_rx)(struct xgbe_prv_data *);
792
793 int (*init)(struct xgbe_prv_data *);
794 int (*exit)(struct xgbe_prv_data *);
795
796 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
797 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
798 void (*dev_xmit)(struct xgbe_channel *);
799 int (*dev_read)(struct xgbe_channel *);
800 void (*tx_desc_init)(struct xgbe_channel *);
801 void (*rx_desc_init)(struct xgbe_channel *);
802 void (*tx_desc_reset)(struct xgbe_ring_data *);
803 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
804 unsigned int);
805 int (*is_last_desc)(struct xgbe_ring_desc *);
806 int (*is_context_desc)(struct xgbe_ring_desc *);
807 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
808
809 /* For FLOW ctrl */
810 int (*config_tx_flow_control)(struct xgbe_prv_data *);
811 int (*config_rx_flow_control)(struct xgbe_prv_data *);
812
813 /* For RX coalescing */
814 int (*config_rx_coalesce)(struct xgbe_prv_data *);
815 int (*config_tx_coalesce)(struct xgbe_prv_data *);
816 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
817 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
818
819 /* For RX and TX threshold config */
820 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
821 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
822
823 /* For RX and TX Store and Forward Mode config */
824 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
825 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
826
827 /* For TX DMA Operate on Second Frame config */
828 int (*config_osp_mode)(struct xgbe_prv_data *);
829
830 /* For MMC statistics */
831 void (*rx_mmc_int)(struct xgbe_prv_data *);
832 void (*tx_mmc_int)(struct xgbe_prv_data *);
833 void (*read_mmc_stats)(struct xgbe_prv_data *);
834
835 /* For Timestamp config */
836 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
837 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
838 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
839 unsigned int nsec);
840 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
841 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
842
843 /* For Data Center Bridging config */
844 void (*config_tc)(struct xgbe_prv_data *);
845 void (*config_dcb_tc)(struct xgbe_prv_data *);
846 void (*config_dcb_pfc)(struct xgbe_prv_data *);
847
848 /* For Receive Side Scaling */
849 int (*enable_rss)(struct xgbe_prv_data *);
850 int (*disable_rss)(struct xgbe_prv_data *);
851 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
852 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
853
854 /* For ECC */
855 void (*disable_ecc_ded)(struct xgbe_prv_data *);
856 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
857
858 /* For VXLAN */
859 void (*enable_vxlan)(struct xgbe_prv_data *);
860 void (*disable_vxlan)(struct xgbe_prv_data *);
861 void (*set_vxlan_id)(struct xgbe_prv_data *);
862 };
863
864 /* This structure represents implementation specific routines for an
865 * implementation of a PHY. All routines are required unless noted below.
866 * Optional routines:
867 * an_pre, an_post
868 * kr_training_pre, kr_training_post
869 * module_info, module_eeprom
870 */
871 struct xgbe_phy_impl_if {
872 /* Perform Setup/teardown actions */
873 int (*init)(struct xgbe_prv_data *);
874 void (*exit)(struct xgbe_prv_data *);
875
876 /* Perform start/stop specific actions */
877 int (*reset)(struct xgbe_prv_data *);
878 int (*start)(struct xgbe_prv_data *);
879 void (*stop)(struct xgbe_prv_data *);
880
881 /* Return the link status */
882 int (*link_status)(struct xgbe_prv_data *, int *);
883
884 /* Indicate if a particular speed is valid */
885 bool (*valid_speed)(struct xgbe_prv_data *, int);
886
887 /* Check if the specified mode can/should be used */
888 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
889 /* Switch the PHY into various modes */
890 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
891 /* Retrieve mode needed for a specific speed */
892 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
893 /* Retrieve new/next mode when trying to auto-negotiate */
894 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
895 /* Retrieve current mode */
896 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
897
898 /* Retrieve current auto-negotiation mode */
899 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
900
901 /* Configure auto-negotiation settings */
902 int (*an_config)(struct xgbe_prv_data *);
903
904 /* Set/override auto-negotiation advertisement settings */
905 void (*an_advertising)(struct xgbe_prv_data *,
906 struct ethtool_link_ksettings *);
907
908 /* Process results of auto-negotiation */
909 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
910
911 /* Pre/Post auto-negotiation support */
912 void (*an_pre)(struct xgbe_prv_data *);
913 void (*an_post)(struct xgbe_prv_data *);
914
915 /* Pre/Post KR training enablement support */
916 void (*kr_training_pre)(struct xgbe_prv_data *);
917 void (*kr_training_post)(struct xgbe_prv_data *);
918
919 /* SFP module related info */
920 int (*module_info)(struct xgbe_prv_data *pdata,
921 struct ethtool_modinfo *modinfo);
922 int (*module_eeprom)(struct xgbe_prv_data *pdata,
923 struct ethtool_eeprom *eeprom, u8 *data);
924 };
925
926 struct xgbe_phy_if {
927 /* For PHY setup/teardown */
928 int (*phy_init)(struct xgbe_prv_data *);
929 void (*phy_exit)(struct xgbe_prv_data *);
930
931 /* For PHY support when setting device up/down */
932 int (*phy_reset)(struct xgbe_prv_data *);
933 int (*phy_start)(struct xgbe_prv_data *);
934 void (*phy_stop)(struct xgbe_prv_data *);
935
936 /* For PHY support while device is up */
937 void (*phy_status)(struct xgbe_prv_data *);
938 int (*phy_config_aneg)(struct xgbe_prv_data *);
939
940 /* For PHY settings validation */
941 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
942
943 /* For single interrupt support */
944 irqreturn_t (*an_isr)(struct xgbe_prv_data *);
945
946 /* For ethtool PHY support */
947 int (*module_info)(struct xgbe_prv_data *pdata,
948 struct ethtool_modinfo *modinfo);
949 int (*module_eeprom)(struct xgbe_prv_data *pdata,
950 struct ethtool_eeprom *eeprom, u8 *data);
951
952 /* PHY implementation specific services */
953 struct xgbe_phy_impl_if phy_impl;
954 };
955
956 struct xgbe_i2c_if {
957 /* For initial I2C setup */
958 int (*i2c_init)(struct xgbe_prv_data *);
959
960 /* For I2C support when setting device up/down */
961 int (*i2c_start)(struct xgbe_prv_data *);
962 void (*i2c_stop)(struct xgbe_prv_data *);
963
964 /* For performing I2C operations */
965 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
966
967 /* For single interrupt support */
968 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
969 };
970
971 struct xgbe_desc_if {
972 int (*alloc_ring_resources)(struct xgbe_prv_data *);
973 void (*free_ring_resources)(struct xgbe_prv_data *);
974 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
975 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
976 struct xgbe_ring_data *);
977 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
978 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
979 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
980 };
981
982 /* This structure contains flags that indicate what hardware features
983 * or configurations are present in the device.
984 */
985 struct xgbe_hw_features {
986 /* HW Version */
987 unsigned int version;
988
989 /* HW Feature Register0 */
990 unsigned int gmii; /* 1000 Mbps support */
991 unsigned int vlhash; /* VLAN Hash Filter */
992 unsigned int sma; /* SMA(MDIO) Interface */
993 unsigned int rwk; /* PMT remote wake-up packet */
994 unsigned int mgk; /* PMT magic packet */
995 unsigned int mmc; /* RMON module */
996 unsigned int aoe; /* ARP Offload */
997 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
998 unsigned int eee; /* Energy Efficient Ethernet */
999 unsigned int tx_coe; /* Tx Checksum Offload */
1000 unsigned int rx_coe; /* Rx Checksum Offload */
1001 unsigned int addn_mac; /* Additional MAC Addresses */
1002 unsigned int ts_src; /* Timestamp Source */
1003 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
1004 unsigned int vxn; /* VXLAN/NVGRE */
1005
1006 /* HW Feature Register1 */
1007 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
1008 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
1009 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
1010 unsigned int dma_width; /* DMA width */
1011 unsigned int dcb; /* DCB Feature */
1012 unsigned int sph; /* Split Header Feature */
1013 unsigned int tso; /* TCP Segmentation Offload */
1014 unsigned int dma_debug; /* DMA Debug Registers */
1015 unsigned int rss; /* Receive Side Scaling */
1016 unsigned int tc_cnt; /* Number of Traffic Classes */
1017 unsigned int hash_table_size; /* Hash Table Size */
1018 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
1019
1020 /* HW Feature Register2 */
1021 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
1022 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
1023 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
1024 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
1025 unsigned int pps_out_num; /* Number of PPS outputs */
1026 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
1027 };
1028
1029 struct xgbe_version_data {
1030 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
1031 enum xgbe_xpcs_access xpcs_access;
1032 unsigned int mmc_64bit;
1033 unsigned int tx_max_fifo_size;
1034 unsigned int rx_max_fifo_size;
1035 unsigned int tx_tstamp_workaround;
1036 unsigned int ecc_support;
1037 unsigned int i2c_support;
1038 unsigned int irq_reissue_support;
1039 unsigned int tx_desc_prefetch;
1040 unsigned int rx_desc_prefetch;
1041 unsigned int an_cdr_workaround;
1042 unsigned int enable_rrc;
1043 };
1044
1045 struct xgbe_prv_data {
1046 struct net_device *netdev;
1047 struct pci_dev *pcidev;
1048 struct platform_device *platdev;
1049 struct acpi_device *adev;
1050 struct device *dev;
1051 struct platform_device *phy_platdev;
1052 struct device *phy_dev;
1053
1054 /* Version related data */
1055 struct xgbe_version_data *vdata;
1056
1057 /* ACPI or DT flag */
1058 unsigned int use_acpi;
1059
1060 /* XGMAC/XPCS related mmio registers */
1061 void __iomem *xgmac_regs; /* XGMAC CSRs */
1062 void __iomem *xpcs_regs; /* XPCS MMD registers */
1063 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
1064 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
1065 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
1066 void __iomem *xprop_regs; /* XGBE property registers */
1067 void __iomem *xi2c_regs; /* XGBE I2C CSRs */
1068
1069 /* Port property registers */
1070 unsigned int pp0;
1071 unsigned int pp1;
1072 unsigned int pp2;
1073 unsigned int pp3;
1074 unsigned int pp4;
1075
1076 /* Overall device lock */
1077 spinlock_t lock;
1078
1079 /* XPCS indirect addressing lock */
1080 spinlock_t xpcs_lock;
1081 unsigned int xpcs_window_def_reg;
1082 unsigned int xpcs_window_sel_reg;
1083 unsigned int xpcs_window;
1084 unsigned int xpcs_window_size;
1085 unsigned int xpcs_window_mask;
1086
1087 /* RSS addressing mutex */
1088 struct mutex rss_mutex;
1089
1090 /* Flags representing xgbe_state */
1091 unsigned long dev_state;
1092
1093 /* ECC support */
1094 unsigned long tx_sec_period;
1095 unsigned long tx_ded_period;
1096 unsigned long rx_sec_period;
1097 unsigned long rx_ded_period;
1098 unsigned long desc_sec_period;
1099 unsigned long desc_ded_period;
1100
1101 unsigned int tx_sec_count;
1102 unsigned int tx_ded_count;
1103 unsigned int rx_sec_count;
1104 unsigned int rx_ded_count;
1105 unsigned int desc_ded_count;
1106 unsigned int desc_sec_count;
1107
1108 int dev_irq;
1109 int ecc_irq;
1110 int i2c_irq;
1111 int channel_irq[XGBE_MAX_DMA_CHANNELS];
1112
1113 unsigned int per_channel_irq;
1114 unsigned int irq_count;
1115 unsigned int channel_irq_count;
1116 unsigned int channel_irq_mode;
1117
1118 char ecc_name[IFNAMSIZ + 32];
1119
1120 struct xgbe_hw_if hw_if;
1121 struct xgbe_phy_if phy_if;
1122 struct xgbe_desc_if desc_if;
1123 struct xgbe_i2c_if i2c_if;
1124
1125 /* AXI DMA settings */
1126 unsigned int coherent;
1127 unsigned int arcr;
1128 unsigned int awcr;
1129 unsigned int awarcr;
1130
1131 /* Service routine support */
1132 struct workqueue_struct *dev_workqueue;
1133 struct work_struct service_work;
1134 struct timer_list service_timer;
1135
1136 /* Rings for Tx/Rx on a DMA channel */
1137 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1138 unsigned int tx_max_channel_count;
1139 unsigned int rx_max_channel_count;
1140 unsigned int channel_count;
1141 unsigned int tx_ring_count;
1142 unsigned int tx_desc_count;
1143 unsigned int rx_ring_count;
1144 unsigned int rx_desc_count;
1145
1146 unsigned int new_tx_ring_count;
1147 unsigned int new_rx_ring_count;
1148
1149 unsigned int tx_max_q_count;
1150 unsigned int rx_max_q_count;
1151 unsigned int tx_q_count;
1152 unsigned int rx_q_count;
1153
1154 /* Tx/Rx common settings */
1155 unsigned int blen;
1156 unsigned int pbl;
1157 unsigned int aal;
1158 unsigned int rd_osr_limit;
1159 unsigned int wr_osr_limit;
1160
1161 /* Tx settings */
1162 unsigned int tx_sf_mode;
1163 unsigned int tx_threshold;
1164 unsigned int tx_osp_mode;
1165 unsigned int tx_max_fifo_size;
1166
1167 /* Rx settings */
1168 unsigned int rx_sf_mode;
1169 unsigned int rx_threshold;
1170 unsigned int rx_max_fifo_size;
1171
1172 /* Tx coalescing settings */
1173 unsigned int tx_usecs;
1174 unsigned int tx_frames;
1175
1176 /* Rx coalescing settings */
1177 unsigned int rx_riwt;
1178 unsigned int rx_usecs;
1179 unsigned int rx_frames;
1180
1181 /* Current Rx buffer size */
1182 unsigned int rx_buf_size;
1183
1184 /* Flow control settings */
1185 unsigned int pause_autoneg;
1186 unsigned int tx_pause;
1187 unsigned int rx_pause;
1188 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1189 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1190
1191 /* Receive Side Scaling settings */
1192 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1193 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1194 u32 rss_options;
1195
1196 /* VXLAN settings */
1197 u16 vxlan_port;
1198
1199 /* Netdev related settings */
1200 unsigned char mac_addr[ETH_ALEN];
1201 netdev_features_t netdev_features;
1202 struct napi_struct napi;
1203 struct xgbe_mmc_stats mmc_stats;
1204 struct xgbe_ext_stats ext_stats;
1205
1206 /* Filtering support */
1207 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1208
1209 /* Device clocks */
1210 struct clk *sysclk;
1211 unsigned long sysclk_rate;
1212 struct clk *ptpclk;
1213 unsigned long ptpclk_rate;
1214
1215 /* Timestamp support */
1216 spinlock_t tstamp_lock;
1217 struct ptp_clock_info ptp_clock_info;
1218 struct ptp_clock *ptp_clock;
1219 struct hwtstamp_config tstamp_config;
1220 struct cyclecounter tstamp_cc;
1221 struct timecounter tstamp_tc;
1222 unsigned int tstamp_addend;
1223 struct work_struct tx_tstamp_work;
1224 struct sk_buff *tx_tstamp_skb;
1225 u64 tx_tstamp;
1226
1227 /* DCB support */
1228 struct ieee_ets *ets;
1229 struct ieee_pfc *pfc;
1230 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1231 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1232 unsigned int pfcq[XGBE_MAX_QUEUES];
1233 unsigned int pfc_rfa;
1234 u8 num_tcs;
1235
1236 /* Hardware features of the device */
1237 struct xgbe_hw_features hw_feat;
1238
1239 /* Device work structures */
1240 struct work_struct restart_work;
1241 struct work_struct stopdev_work;
1242
1243 /* Keeps track of power mode */
1244 unsigned int power_down;
1245
1246 /* Network interface message level setting */
1247 u32 msg_enable;
1248
1249 /* Current PHY settings */
1250 phy_interface_t phy_mode;
1251 int phy_link;
1252 int phy_speed;
1253
1254 /* MDIO/PHY related settings */
1255 unsigned int phy_started;
1256 void *phy_data;
1257 struct xgbe_phy phy;
1258 int mdio_mmd;
1259 unsigned long link_check;
1260 struct completion mdio_complete;
1261
1262 unsigned int kr_redrv;
1263
1264 char an_name[IFNAMSIZ + 32];
1265 struct workqueue_struct *an_workqueue;
1266
1267 int an_irq;
1268 struct work_struct an_irq_work;
1269
1270 /* Auto-negotiation state machine support */
1271 unsigned int an_int;
1272 unsigned int an_status;
1273 struct mutex an_mutex;
1274 enum xgbe_an an_result;
1275 enum xgbe_an an_state;
1276 enum xgbe_rx kr_state;
1277 enum xgbe_rx kx_state;
1278 struct work_struct an_work;
1279 unsigned int an_again;
1280 unsigned int an_supported;
1281 unsigned int parallel_detect;
1282 unsigned int fec_ability;
1283 unsigned long an_start;
1284 unsigned long kr_start_time;
1285 enum xgbe_an_mode an_mode;
1286
1287 /* I2C support */
1288 struct xgbe_i2c i2c;
1289 struct mutex i2c_mutex;
1290 struct completion i2c_complete;
1291 char i2c_name[IFNAMSIZ + 32];
1292
1293 unsigned int lpm_ctrl; /* CTRL1 for resume */
1294
1295 unsigned int isr_as_tasklet;
1296 struct tasklet_struct tasklet_dev;
1297 struct tasklet_struct tasklet_ecc;
1298 struct tasklet_struct tasklet_i2c;
1299 struct tasklet_struct tasklet_an;
1300
1301 struct dentry *xgbe_debugfs;
1302
1303 unsigned int debugfs_xgmac_reg;
1304
1305 unsigned int debugfs_xpcs_mmd;
1306 unsigned int debugfs_xpcs_reg;
1307
1308 unsigned int debugfs_xprop_reg;
1309
1310 unsigned int debugfs_xi2c_reg;
1311
1312 bool debugfs_an_cdr_workaround;
1313 bool debugfs_an_cdr_track_early;
1314 };
1315
1316 /* Function prototypes*/
1317 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1318 void xgbe_free_pdata(struct xgbe_prv_data *);
1319 void xgbe_set_counts(struct xgbe_prv_data *);
1320 int xgbe_config_netdev(struct xgbe_prv_data *);
1321 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1322
1323 int xgbe_platform_init(void);
1324 void xgbe_platform_exit(void);
1325 #ifdef CONFIG_PCI
1326 int xgbe_pci_init(void);
1327 void xgbe_pci_exit(void);
1328 #else
xgbe_pci_init(void)1329 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1330 static inline void xgbe_pci_exit(void) { }
1331 #endif
1332
1333 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1334 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1335 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1336 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1337 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1338 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1339 const struct net_device_ops *xgbe_get_netdev_ops(void);
1340 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1341 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1342
1343 #ifdef CONFIG_AMD_XGBE_DCB
1344 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1345 #endif
1346
1347 void xgbe_ptp_register(struct xgbe_prv_data *);
1348 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1349 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1350 unsigned int, unsigned int, unsigned int);
1351 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1352 unsigned int);
1353 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1354 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1355 int xgbe_powerup(struct net_device *, unsigned int);
1356 int xgbe_powerdown(struct net_device *, unsigned int);
1357 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1358 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1359 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1360 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1361
1362 #ifdef CONFIG_DEBUG_FS
1363 void xgbe_debugfs_init(struct xgbe_prv_data *);
1364 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1365 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1366 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1367 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1368 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1369 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1370 #endif /* CONFIG_DEBUG_FS */
1371
1372 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1373 #if 0
1374 #define YDEBUG
1375 #define YDEBUG_MDIO
1376 #endif
1377
1378 /* For debug prints */
1379 #ifdef YDEBUG
1380 #define DBGPR(x...) pr_alert(x)
1381 #else
1382 #define DBGPR(x...) do { } while (0)
1383 #endif
1384
1385 #ifdef YDEBUG_MDIO
1386 #define DBGPR_MDIO(x...) pr_alert(x)
1387 #else
1388 #define DBGPR_MDIO(x...) do { } while (0)
1389 #endif
1390
1391 #endif
1392