1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40
41 /**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
53 *
54 */
55 struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61 };
62
63 /**
64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
65 *
66 * @num: Numerator of the duty cycle ratio
67 * @den: Denominator of the duty cycle ratio
68 */
69 struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72 };
73
74 /**
75 * struct clk_ops - Callback operations for hardware clocks; these are to
76 * be provided by the clock implementation, and will be called by drivers
77 * through the clk_* api.
78 *
79 * @prepare: Prepare the clock for enabling. This must not return until
80 * the clock is fully prepared, and it's safe to call clk_enable.
81 * This callback is intended to allow clock implementations to
82 * do any initialisation that may sleep. Called with
83 * prepare_lock held.
84 *
85 * @unprepare: Release the clock from its prepared state. This will typically
86 * undo any work done in the @prepare callback. Called with
87 * prepare_lock held.
88 *
89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 * This function is allowed to sleep. Optional, if this op is not
91 * set then the prepare count will be used.
92 *
93 * @unprepare_unused: Unprepare the clock atomically. Only called from
94 * clk_disable_unused for prepare clocks with special needs.
95 * Called with prepare mutex held. This function may sleep.
96 *
97 * @enable: Enable the clock atomically. This must not return until the
98 * clock is generating a valid clock signal, usable by consumer
99 * devices. Called with enable_lock held. This function must not
100 * sleep.
101 *
102 * @disable: Disable the clock atomically. Called with enable_lock held.
103 * This function must not sleep.
104 *
105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 * This function must not sleep. Optional, if this op is not
107 * set then the enable count will be used.
108 *
109 * @disable_unused: Disable the clock atomically. Only called from
110 * clk_disable_unused for gate clocks with special needs.
111 * Called with enable_lock held. This function must not
112 * sleep.
113 *
114 * @save_context: Save the context of the clock in prepration for poweroff.
115 *
116 * @restore_context: Restore the context of the clock after a restoration
117 * of power.
118 *
119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
121 * ensure that the prepare_mutex is held across this call.
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
124 *
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
127 * parameter.
128 *
129 * @determine_rate: Given a target rate as input, returns the closest rate
130 * actually supported by the clock, and optionally the parent clock
131 * that should be used to provide the clock rate.
132 *
133 * @set_parent: Change the input source of this clock; for clocks with multiple
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
136 * or .parents arrays. This function in affect translates an
137 * array index into the value programmed into the hardware.
138 * Returns 0 on success, -EERROR otherwise.
139 *
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
141 * return value is a u8 which specifies the index corresponding to
142 * the parent clock. This index can be applied to either the
143 * .parent_names or .parents arrays. In short, this function
144 * translates the parent value read from hardware into an array
145 * index. Currently only called when the clock is initialized by
146 * __clk_init. This callback is mandatory for clocks with
147 * multiple parents. It is optional (and unnecessary) for clocks
148 * with 0 or 1 parents.
149 *
150 * @set_rate: Change the rate of this clock. The requested rate is specified
151 * by the second argument, which should typically be the return
152 * of .round_rate call. The third argument gives the parent rate
153 * which is likely helpful for most .set_rate implementation.
154 * Returns 0 on success, -EERROR otherwise.
155 *
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
158 * should typically be the return of .round_rate call. The
159 * third argument gives the parent rate which is likely helpful
160 * for most .set_rate_and_parent implementation. The fourth
161 * argument gives the parent index. This callback is optional (and
162 * unnecessary) for clocks with 0 or 1 parents as well as
163 * for clocks that can tolerate switching the rate and the parent
164 * separately via calls to .set_parent and .set_rate.
165 * Returns 0 on success, -EERROR otherwise.
166 *
167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 * is expressed in ppb (parts per billion). The parent accuracy is
169 * an input parameter.
170 * Returns the calculated accuracy. Optional - if this op is not
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
173 *
174 * @get_phase: Queries the hardware to get the current phase of a clock.
175 * Returned values are 0-359 degrees on success, negative
176 * error codes on failure.
177 *
178 * @set_phase: Shift the phase this clock signal in degrees specified
179 * by the second argument. Valid values for degrees are
180 * 0-359. Return 0 on success, otherwise -EERROR.
181 *
182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 * of a clock. Returned values denominator cannot be 0 and must be
184 * superior or equal to the numerator.
185 *
186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 * the numerator (2nd argurment) and denominator (3rd argument).
188 * Argument must be a valid ratio (denominator > 0
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
190 *
191 * @init: Perform platform-specific initialization magic.
192 * This is not used by any of the basic clock types.
193 * This callback exist for HW which needs to perform some
194 * initialisation magic for CCF to get an accurate view of the
195 * clock. It may also be used dynamic resource allocation is
196 * required. It shall not used to deal with clock parameters,
197 * such as rate or parents.
198 * Returns 0 on success, -EERROR otherwise.
199 *
200 * @terminate: Free any resource allocated by init.
201 *
202 * @debug_init: Set up type-specific debugfs entries for this clock. This
203 * is called once, after the debugfs directory entry for this
204 * clock has been created. The dentry pointer representing that
205 * directory is provided as an argument. Called with
206 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
207 *
208 *
209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
210 * implementations to split any work between atomic (enable) and sleepable
211 * (prepare) contexts. If enabling a clock requires code that might sleep,
212 * this must be done in clk_prepare. Clock enable code that will never be
213 * called in a sleepable context may be implemented in clk_enable.
214 *
215 * Typically, drivers will call clk_prepare when a clock may be needed later
216 * (eg. when a device is opened), and clk_enable when the clock is actually
217 * required (eg. from an interrupt). Note that clk_prepare MUST have been
218 * called before clk_enable.
219 */
220 struct clk_ops {
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw,
232 unsigned long parent_rate);
233 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long *parent_rate);
235 int (*determine_rate)(struct clk_hw *hw,
236 struct clk_rate_request *req);
237 int (*set_parent)(struct clk_hw *hw, u8 index);
238 u8 (*get_parent)(struct clk_hw *hw);
239 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate);
241 int (*set_rate_and_parent)(struct clk_hw *hw,
242 unsigned long rate,
243 unsigned long parent_rate, u8 index);
244 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 unsigned long parent_accuracy);
246 int (*get_phase)(struct clk_hw *hw);
247 int (*set_phase)(struct clk_hw *hw, int degrees);
248 int (*get_duty_cycle)(struct clk_hw *hw,
249 struct clk_duty *duty);
250 int (*set_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
255 };
256
257 /**
258 * struct clk_parent_data - clk parent information
259 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
260 * @fw_name: parent name local to provider registering clk
261 * @name: globally unique parent name (used as a fallback)
262 * @index: parent index local to provider registering clk (if @fw_name absent)
263 */
264 struct clk_parent_data {
265 const struct clk_hw *hw;
266 const char *fw_name;
267 const char *name;
268 int index;
269 };
270
271 /**
272 * struct clk_init_data - holds init data that's common to all clocks and is
273 * shared between the clock provider and the common clock framework.
274 *
275 * @name: clock name
276 * @ops: operations this clock supports
277 * @parent_names: array of string names for all possible parents
278 * @parent_data: array of parent data for all possible parents (when some
279 * parents are external to the clk controller)
280 * @parent_hws: array of pointers to all possible parents (when all parents
281 * are internal to the clk controller)
282 * @num_parents: number of possible parents
283 * @flags: framework-level hints and quirks
284 */
285 struct clk_init_data {
286 const char *name;
287 const struct clk_ops *ops;
288 /* Only one of the following three should be assigned */
289 const char * const *parent_names;
290 const struct clk_parent_data *parent_data;
291 const struct clk_hw **parent_hws;
292 u8 num_parents;
293 unsigned long flags;
294 };
295
296 /**
297 * struct clk_hw - handle for traversing from a struct clk to its corresponding
298 * hardware-specific structure. struct clk_hw should be declared within struct
299 * clk_foo and then referenced by the struct clk instance that uses struct
300 * clk_foo's clk_ops
301 *
302 * @core: pointer to the struct clk_core instance that points back to this
303 * struct clk_hw instance
304 *
305 * @clk: pointer to the per-user struct clk instance that can be used to call
306 * into the clk API
307 *
308 * @init: pointer to struct clk_init_data that contains the init data shared
309 * with the common clock framework. This pointer will be set to NULL once
310 * a clk_register() variant is called on this clk_hw pointer.
311 */
312 struct clk_hw {
313 struct clk_core *core;
314 struct clk *clk;
315 const struct clk_init_data *init;
316 };
317
318 /*
319 * DOC: Basic clock implementations common to many platforms
320 *
321 * Each basic clock hardware type is comprised of a structure describing the
322 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
323 * unique flags for that hardware type, a registration function and an
324 * alternative macro for static initialization
325 */
326
327 /**
328 * struct clk_fixed_rate - fixed-rate clock
329 * @hw: handle between common and hardware-specific interfaces
330 * @fixed_rate: constant frequency of clock
331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
332 * @flags: hardware specific flags
333 *
334 * Flags:
335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
336 * instead of what's set in @fixed_accuracy.
337 */
338 struct clk_fixed_rate {
339 struct clk_hw hw;
340 unsigned long fixed_rate;
341 unsigned long fixed_accuracy;
342 unsigned long flags;
343 };
344
345 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
346
347 extern const struct clk_ops clk_fixed_rate_ops;
348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags);
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate);
357 /**
358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
359 * framework
360 * @dev: device that is registering this clock
361 * @name: name of this clock
362 * @parent_name: name of clock's parent
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
365 */
366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0)
369 /**
370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
371 * the clock framework
372 * @dev: device that is registering this clock
373 * @name: name of this clock
374 * @parent_hw: pointer to parent clk
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
377 */
378 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 NULL, (flags), (fixed_rate), 0, 0)
382 /**
383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
384 * the clock framework
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_data: parent clk data
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
390 */
391 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 fixed_rate) \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 (parent_data), (flags), (fixed_rate), 0, \
395 0)
396 /**
397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_name: name of clock's parent
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 * @fixed_accuracy: non-adjustable clock accuracy
405 */
406 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 flags, fixed_rate, \
408 fixed_accuracy) \
409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 NULL, NULL, (flags), (fixed_rate), \
411 (fixed_accuracy), 0)
412 /**
413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
414 * clock with the clock framework
415 * @dev: device that is registering this clock
416 * @name: name of this clock
417 * @parent_hw: pointer to parent clk
418 * @flags: framework-specific flags
419 * @fixed_rate: non-adjustable clock rate
420 * @fixed_accuracy: non-adjustable clock accuracy
421 */
422 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 parent_hw, flags, fixed_rate, fixed_accuracy) \
424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 NULL, NULL, (flags), (fixed_rate), \
426 (fixed_accuracy), 0)
427 /**
428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
429 * clock with the clock framework
430 * @dev: device that is registering this clock
431 * @name: name of this clock
432 * @parent_name: name of clock's parent
433 * @flags: framework-specific flags
434 * @fixed_rate: non-adjustable clock rate
435 * @fixed_accuracy: non-adjustable clock accuracy
436 */
437 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 parent_data, flags, fixed_rate, fixed_accuracy) \
439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 (parent_data), NULL, (flags), \
441 (fixed_rate), (fixed_accuracy), 0)
442
443 void clk_unregister_fixed_rate(struct clk *clk);
444 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
445
446 void of_fixed_clk_setup(struct device_node *np);
447
448 /**
449 * struct clk_gate - gating clock
450 *
451 * @hw: handle between common and hardware-specific interfaces
452 * @reg: register controlling gate
453 * @bit_idx: single bit controlling gate
454 * @flags: hardware-specific flags
455 * @lock: register lock
456 *
457 * Clock which can gate its output. Implements .enable & .disable
458 *
459 * Flags:
460 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
461 * enable the clock. Setting this flag does the opposite: setting the bit
462 * disable the clock and clearing it enables the clock
463 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464 * of this register, and mask of gate bits are in higher 16-bit of this
465 * register. While setting the gate bits, higher 16-bit should also be
466 * updated to indicate changing gate bits.
467 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
468 * the gate register. Setting this flag makes the register accesses big
469 * endian.
470 */
471 struct clk_gate {
472 struct clk_hw hw;
473 void __iomem *reg;
474 u8 bit_idx;
475 u8 flags;
476 spinlock_t *lock;
477 };
478
479 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
480
481 #define CLK_GATE_SET_TO_DISABLE BIT(0)
482 #define CLK_GATE_HIWORD_MASK BIT(1)
483 #define CLK_GATE_BIG_ENDIAN BIT(2)
484
485 extern const struct clk_ops clk_gate_ops;
486 struct clk_hw *__clk_hw_register_gate(struct device *dev,
487 struct device_node *np, const char *name,
488 const char *parent_name, const struct clk_hw *parent_hw,
489 const struct clk_parent_data *parent_data,
490 unsigned long flags,
491 void __iomem *reg, u8 bit_idx,
492 u8 clk_gate_flags, spinlock_t *lock);
493 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
494 struct device_node *np, const char *name,
495 const char *parent_name, const struct clk_hw *parent_hw,
496 const struct clk_parent_data *parent_data,
497 unsigned long flags,
498 void __iomem *reg, u8 bit_idx,
499 u8 clk_gate_flags, spinlock_t *lock);
500 struct clk *clk_register_gate(struct device *dev, const char *name,
501 const char *parent_name, unsigned long flags,
502 void __iomem *reg, u8 bit_idx,
503 u8 clk_gate_flags, spinlock_t *lock);
504 /**
505 * clk_hw_register_gate - register a gate clock with the clock framework
506 * @dev: device that is registering this clock
507 * @name: name of this clock
508 * @parent_name: name of this clock's parent
509 * @flags: framework-specific flags for this clock
510 * @reg: register address to control gating of this clock
511 * @bit_idx: which bit in the register controls gating of this clock
512 * @clk_gate_flags: gate-specific flags for this clock
513 * @lock: shared register lock for this clock
514 */
515 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
516 clk_gate_flags, lock) \
517 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
518 NULL, (flags), (reg), (bit_idx), \
519 (clk_gate_flags), (lock))
520 /**
521 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
522 * framework
523 * @dev: device that is registering this clock
524 * @name: name of this clock
525 * @parent_hw: pointer to parent clk
526 * @flags: framework-specific flags for this clock
527 * @reg: register address to control gating of this clock
528 * @bit_idx: which bit in the register controls gating of this clock
529 * @clk_gate_flags: gate-specific flags for this clock
530 * @lock: shared register lock for this clock
531 */
532 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
533 bit_idx, clk_gate_flags, lock) \
534 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
535 NULL, (flags), (reg), (bit_idx), \
536 (clk_gate_flags), (lock))
537 /**
538 * clk_hw_register_gate_parent_data - register a gate clock with the clock
539 * framework
540 * @dev: device that is registering this clock
541 * @name: name of this clock
542 * @parent_data: parent clk data
543 * @flags: framework-specific flags for this clock
544 * @reg: register address to control gating of this clock
545 * @bit_idx: which bit in the register controls gating of this clock
546 * @clk_gate_flags: gate-specific flags for this clock
547 * @lock: shared register lock for this clock
548 */
549 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
550 bit_idx, clk_gate_flags, lock) \
551 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
552 (flags), (reg), (bit_idx), \
553 (clk_gate_flags), (lock))
554 /**
555 * devm_clk_hw_register_gate - register a gate clock with the clock framework
556 * @dev: device that is registering this clock
557 * @name: name of this clock
558 * @parent_name: name of this clock's parent
559 * @flags: framework-specific flags for this clock
560 * @reg: register address to control gating of this clock
561 * @bit_idx: which bit in the register controls gating of this clock
562 * @clk_gate_flags: gate-specific flags for this clock
563 * @lock: shared register lock for this clock
564 */
565 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
566 clk_gate_flags, lock) \
567 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
568 NULL, (flags), (reg), (bit_idx), \
569 (clk_gate_flags), (lock))
570 void clk_unregister_gate(struct clk *clk);
571 void clk_hw_unregister_gate(struct clk_hw *hw);
572 int clk_gate_is_enabled(struct clk_hw *hw);
573
574 struct clk_div_table {
575 unsigned int val;
576 unsigned int div;
577 };
578
579 /**
580 * struct clk_divider - adjustable divider clock
581 *
582 * @hw: handle between common and hardware-specific interfaces
583 * @reg: register containing the divider
584 * @shift: shift to the divider bit field
585 * @width: width of the divider bit field
586 * @table: array of value/divider pairs, last entry should have div = 0
587 * @lock: register lock
588 *
589 * Clock with an adjustable divider affecting its output frequency. Implements
590 * .recalc_rate, .set_rate and .round_rate
591 *
592 * Flags:
593 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
594 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
595 * the raw value read from the register, with the value of zero considered
596 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
597 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
598 * the hardware register
599 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
600 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
601 * Some hardware implementations gracefully handle this case and allow a
602 * zero divisor by not modifying their input clock
603 * (divide by one / bypass).
604 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
605 * of this register, and mask of divider bits are in higher 16-bit of this
606 * register. While setting the divider bits, higher 16-bit should also be
607 * updated to indicate changing divider bits.
608 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
609 * to the closest integer instead of the up one.
610 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
611 * not be changed by the clock framework.
612 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
613 * except when the value read from the register is zero, the divisor is
614 * 2^width of the field.
615 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
616 * for the divider register. Setting this flag makes the register accesses
617 * big endian.
618 */
619 struct clk_divider {
620 struct clk_hw hw;
621 void __iomem *reg;
622 u8 shift;
623 u8 width;
624 u8 flags;
625 const struct clk_div_table *table;
626 spinlock_t *lock;
627 };
628
629 #define clk_div_mask(width) ((1 << (width)) - 1)
630 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
631
632 #define CLK_DIVIDER_ONE_BASED BIT(0)
633 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
634 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
635 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
636 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
637 #define CLK_DIVIDER_READ_ONLY BIT(5)
638 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
639 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
640
641 extern const struct clk_ops clk_divider_ops;
642 extern const struct clk_ops clk_divider_ro_ops;
643
644 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
645 unsigned int val, const struct clk_div_table *table,
646 unsigned long flags, unsigned long width);
647 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
648 unsigned long rate, unsigned long *prate,
649 const struct clk_div_table *table,
650 u8 width, unsigned long flags);
651 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
652 unsigned long rate, unsigned long *prate,
653 const struct clk_div_table *table, u8 width,
654 unsigned long flags, unsigned int val);
655 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
656 const struct clk_div_table *table, u8 width,
657 unsigned long flags);
658 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
659 const struct clk_div_table *table, u8 width,
660 unsigned long flags, unsigned int val);
661 int divider_get_val(unsigned long rate, unsigned long parent_rate,
662 const struct clk_div_table *table, u8 width,
663 unsigned long flags);
664
665 struct clk_hw *__clk_hw_register_divider(struct device *dev,
666 struct device_node *np, const char *name,
667 const char *parent_name, const struct clk_hw *parent_hw,
668 const struct clk_parent_data *parent_data, unsigned long flags,
669 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
670 const struct clk_div_table *table, spinlock_t *lock);
671 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
672 struct device_node *np, const char *name,
673 const char *parent_name, const struct clk_hw *parent_hw,
674 const struct clk_parent_data *parent_data, unsigned long flags,
675 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
676 const struct clk_div_table *table, spinlock_t *lock);
677 struct clk *clk_register_divider_table(struct device *dev, const char *name,
678 const char *parent_name, unsigned long flags,
679 void __iomem *reg, u8 shift, u8 width,
680 u8 clk_divider_flags, const struct clk_div_table *table,
681 spinlock_t *lock);
682 /**
683 * clk_register_divider - register a divider clock with the clock framework
684 * @dev: device registering this clock
685 * @name: name of this clock
686 * @parent_name: name of clock's parent
687 * @flags: framework-specific flags
688 * @reg: register address to adjust divider
689 * @shift: number of bits to shift the bitfield
690 * @width: width of the bitfield
691 * @clk_divider_flags: divider-specific flags for this clock
692 * @lock: shared register lock for this clock
693 */
694 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
695 clk_divider_flags, lock) \
696 clk_register_divider_table((dev), (name), (parent_name), (flags), \
697 (reg), (shift), (width), \
698 (clk_divider_flags), NULL, (lock))
699 /**
700 * clk_hw_register_divider - register a divider clock with the clock framework
701 * @dev: device registering this clock
702 * @name: name of this clock
703 * @parent_name: name of clock's parent
704 * @flags: framework-specific flags
705 * @reg: register address to adjust divider
706 * @shift: number of bits to shift the bitfield
707 * @width: width of the bitfield
708 * @clk_divider_flags: divider-specific flags for this clock
709 * @lock: shared register lock for this clock
710 */
711 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
712 width, clk_divider_flags, lock) \
713 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
714 NULL, (flags), (reg), (shift), (width), \
715 (clk_divider_flags), NULL, (lock))
716 /**
717 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
718 * framework
719 * @dev: device registering this clock
720 * @name: name of this clock
721 * @parent_hw: pointer to parent clk
722 * @flags: framework-specific flags
723 * @reg: register address to adjust divider
724 * @shift: number of bits to shift the bitfield
725 * @width: width of the bitfield
726 * @clk_divider_flags: divider-specific flags for this clock
727 * @lock: shared register lock for this clock
728 */
729 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
730 shift, width, clk_divider_flags, \
731 lock) \
732 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
733 NULL, (flags), (reg), (shift), (width), \
734 (clk_divider_flags), NULL, (lock))
735 /**
736 * clk_hw_register_divider_parent_data - register a divider clock with the clock
737 * framework
738 * @dev: device registering this clock
739 * @name: name of this clock
740 * @parent_data: parent clk data
741 * @flags: framework-specific flags
742 * @reg: register address to adjust divider
743 * @shift: number of bits to shift the bitfield
744 * @width: width of the bitfield
745 * @clk_divider_flags: divider-specific flags for this clock
746 * @lock: shared register lock for this clock
747 */
748 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
749 reg, shift, width, \
750 clk_divider_flags, lock) \
751 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
752 (parent_data), (flags), (reg), (shift), \
753 (width), (clk_divider_flags), NULL, (lock))
754 /**
755 * clk_hw_register_divider_table - register a table based divider clock with
756 * the clock framework
757 * @dev: device registering this clock
758 * @name: name of this clock
759 * @parent_name: name of clock's parent
760 * @flags: framework-specific flags
761 * @reg: register address to adjust divider
762 * @shift: number of bits to shift the bitfield
763 * @width: width of the bitfield
764 * @clk_divider_flags: divider-specific flags for this clock
765 * @table: array of divider/value pairs ending with a div set to 0
766 * @lock: shared register lock for this clock
767 */
768 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
769 shift, width, clk_divider_flags, table, \
770 lock) \
771 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
772 NULL, (flags), (reg), (shift), (width), \
773 (clk_divider_flags), (table), (lock))
774 /**
775 * clk_hw_register_divider_table_parent_hw - register a table based divider
776 * clock with the clock framework
777 * @dev: device registering this clock
778 * @name: name of this clock
779 * @parent_hw: pointer to parent clk
780 * @flags: framework-specific flags
781 * @reg: register address to adjust divider
782 * @shift: number of bits to shift the bitfield
783 * @width: width of the bitfield
784 * @clk_divider_flags: divider-specific flags for this clock
785 * @table: array of divider/value pairs ending with a div set to 0
786 * @lock: shared register lock for this clock
787 */
788 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
789 reg, shift, width, \
790 clk_divider_flags, table, \
791 lock) \
792 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
793 NULL, (flags), (reg), (shift), (width), \
794 (clk_divider_flags), (table), (lock))
795 /**
796 * clk_hw_register_divider_table_parent_data - register a table based divider
797 * clock with the clock framework
798 * @dev: device registering this clock
799 * @name: name of this clock
800 * @parent_data: parent clk data
801 * @flags: framework-specific flags
802 * @reg: register address to adjust divider
803 * @shift: number of bits to shift the bitfield
804 * @width: width of the bitfield
805 * @clk_divider_flags: divider-specific flags for this clock
806 * @table: array of divider/value pairs ending with a div set to 0
807 * @lock: shared register lock for this clock
808 */
809 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
810 flags, reg, shift, width, \
811 clk_divider_flags, table, \
812 lock) \
813 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
814 (parent_data), (flags), (reg), (shift), \
815 (width), (clk_divider_flags), (table), \
816 (lock))
817 /**
818 * devm_clk_hw_register_divider - register a divider clock with the clock framework
819 * @dev: device registering this clock
820 * @name: name of this clock
821 * @parent_name: name of clock's parent
822 * @flags: framework-specific flags
823 * @reg: register address to adjust divider
824 * @shift: number of bits to shift the bitfield
825 * @width: width of the bitfield
826 * @clk_divider_flags: divider-specific flags for this clock
827 * @lock: shared register lock for this clock
828 */
829 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
830 width, clk_divider_flags, lock) \
831 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
832 NULL, (flags), (reg), (shift), (width), \
833 (clk_divider_flags), NULL, (lock))
834 /**
835 * devm_clk_hw_register_divider_table - register a table based divider clock
836 * with the clock framework (devres variant)
837 * @dev: device registering this clock
838 * @name: name of this clock
839 * @parent_name: name of clock's parent
840 * @flags: framework-specific flags
841 * @reg: register address to adjust divider
842 * @shift: number of bits to shift the bitfield
843 * @width: width of the bitfield
844 * @clk_divider_flags: divider-specific flags for this clock
845 * @table: array of divider/value pairs ending with a div set to 0
846 * @lock: shared register lock for this clock
847 */
848 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
849 reg, shift, width, \
850 clk_divider_flags, table, lock) \
851 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
852 NULL, NULL, (flags), (reg), (shift), \
853 (width), (clk_divider_flags), (table), \
854 (lock))
855
856 void clk_unregister_divider(struct clk *clk);
857 void clk_hw_unregister_divider(struct clk_hw *hw);
858
859 /**
860 * struct clk_mux - multiplexer clock
861 *
862 * @hw: handle between common and hardware-specific interfaces
863 * @reg: register controlling multiplexer
864 * @table: array of register values corresponding to the parent index
865 * @shift: shift to multiplexer bit field
866 * @mask: mask of mutliplexer bit field
867 * @flags: hardware-specific flags
868 * @lock: register lock
869 *
870 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
871 * and .recalc_rate
872 *
873 * Flags:
874 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
875 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
876 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
877 * register, and mask of mux bits are in higher 16-bit of this register.
878 * While setting the mux bits, higher 16-bit should also be updated to
879 * indicate changing mux bits.
880 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
881 * .get_parent clk_op.
882 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
883 * frequency.
884 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
885 * the mux register. Setting this flag makes the register accesses big
886 * endian.
887 */
888 struct clk_mux {
889 struct clk_hw hw;
890 void __iomem *reg;
891 const u32 *table;
892 u32 mask;
893 u8 shift;
894 u8 flags;
895 spinlock_t *lock;
896 };
897
898 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
899
900 #define CLK_MUX_INDEX_ONE BIT(0)
901 #define CLK_MUX_INDEX_BIT BIT(1)
902 #define CLK_MUX_HIWORD_MASK BIT(2)
903 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
904 #define CLK_MUX_ROUND_CLOSEST BIT(4)
905 #define CLK_MUX_BIG_ENDIAN BIT(5)
906
907 extern const struct clk_ops clk_mux_ops;
908 extern const struct clk_ops clk_mux_ro_ops;
909
910 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
911 const char *name, u8 num_parents,
912 const char * const *parent_names,
913 const struct clk_hw **parent_hws,
914 const struct clk_parent_data *parent_data,
915 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
916 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
917 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
918 const char *name, u8 num_parents,
919 const char * const *parent_names,
920 const struct clk_hw **parent_hws,
921 const struct clk_parent_data *parent_data,
922 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
923 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
924 struct clk *clk_register_mux_table(struct device *dev, const char *name,
925 const char * const *parent_names, u8 num_parents,
926 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
927 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
928
929 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
930 shift, width, clk_mux_flags, lock) \
931 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
932 (flags), (reg), (shift), BIT((width)) - 1, \
933 (clk_mux_flags), NULL, (lock))
934 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
935 flags, reg, shift, mask, clk_mux_flags, \
936 table, lock) \
937 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
938 (parent_names), NULL, NULL, (flags), (reg), \
939 (shift), (mask), (clk_mux_flags), (table), \
940 (lock))
941 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
942 shift, width, clk_mux_flags, lock) \
943 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
944 (parent_names), NULL, NULL, (flags), (reg), \
945 (shift), BIT((width)) - 1, (clk_mux_flags), \
946 NULL, (lock))
947 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
948 reg, shift, width, clk_mux_flags, lock) \
949 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
950 (parent_hws), NULL, (flags), (reg), (shift), \
951 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
952 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
953 flags, reg, shift, width, \
954 clk_mux_flags, lock) \
955 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
956 (parent_data), (flags), (reg), (shift), \
957 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
958 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
959 shift, width, clk_mux_flags, lock) \
960 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
961 (parent_names), NULL, NULL, (flags), (reg), \
962 (shift), BIT((width)) - 1, (clk_mux_flags), \
963 NULL, (lock))
964
965 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
966 unsigned int val);
967 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
968
969 void clk_unregister_mux(struct clk *clk);
970 void clk_hw_unregister_mux(struct clk_hw *hw);
971
972 void of_fixed_factor_clk_setup(struct device_node *node);
973
974 /**
975 * struct clk_fixed_factor - fixed multiplier and divider clock
976 *
977 * @hw: handle between common and hardware-specific interfaces
978 * @mult: multiplier
979 * @div: divider
980 *
981 * Clock with a fixed multiplier and divider. The output frequency is the
982 * parent clock rate divided by div and multiplied by mult.
983 * Implements .recalc_rate, .set_rate and .round_rate
984 */
985
986 struct clk_fixed_factor {
987 struct clk_hw hw;
988 unsigned int mult;
989 unsigned int div;
990 };
991
992 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
993
994 extern const struct clk_ops clk_fixed_factor_ops;
995 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
996 const char *parent_name, unsigned long flags,
997 unsigned int mult, unsigned int div);
998 void clk_unregister_fixed_factor(struct clk *clk);
999 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1000 const char *name, const char *parent_name, unsigned long flags,
1001 unsigned int mult, unsigned int div);
1002 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1003 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1004 const char *name, const char *parent_name, unsigned long flags,
1005 unsigned int mult, unsigned int div);
1006 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1007 const char *name, unsigned int index, unsigned long flags,
1008 unsigned int mult, unsigned int div);
1009 /**
1010 * struct clk_fractional_divider - adjustable fractional divider clock
1011 *
1012 * @hw: handle between common and hardware-specific interfaces
1013 * @reg: register containing the divider
1014 * @mshift: shift to the numerator bit field
1015 * @mwidth: width of the numerator bit field
1016 * @nshift: shift to the denominator bit field
1017 * @nwidth: width of the denominator bit field
1018 * @lock: register lock
1019 *
1020 * Clock with adjustable fractional divider affecting its output frequency.
1021 *
1022 * Flags:
1023 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1024 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1025 * is set then the numerator and denominator are both the value read
1026 * plus one.
1027 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1028 * used for the divider register. Setting this flag makes the register
1029 * accesses big endian.
1030 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1031 * be saturated and the caller will get quite far from the good enough
1032 * approximation. Instead the caller may require, by setting this flag,
1033 * to shift left by a few bits in case, when the asked one is quite small
1034 * to satisfy the desired range of denominator. It assumes that on the
1035 * caller's side the power-of-two capable prescaler exists.
1036 */
1037 struct clk_fractional_divider {
1038 struct clk_hw hw;
1039 void __iomem *reg;
1040 u8 mshift;
1041 u8 mwidth;
1042 u32 mmask;
1043 u8 nshift;
1044 u8 nwidth;
1045 u32 nmask;
1046 u8 flags;
1047 void (*approximation)(struct clk_hw *hw,
1048 unsigned long rate, unsigned long *parent_rate,
1049 unsigned long *m, unsigned long *n);
1050 spinlock_t *lock;
1051 };
1052
1053 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1054
1055 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1056 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1057 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1058
1059 struct clk *clk_register_fractional_divider(struct device *dev,
1060 const char *name, const char *parent_name, unsigned long flags,
1061 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1062 u8 clk_divider_flags, spinlock_t *lock);
1063 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1064 const char *name, const char *parent_name, unsigned long flags,
1065 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1066 u8 clk_divider_flags, spinlock_t *lock);
1067 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1068
1069 /**
1070 * struct clk_multiplier - adjustable multiplier clock
1071 *
1072 * @hw: handle between common and hardware-specific interfaces
1073 * @reg: register containing the multiplier
1074 * @shift: shift to the multiplier bit field
1075 * @width: width of the multiplier bit field
1076 * @lock: register lock
1077 *
1078 * Clock with an adjustable multiplier affecting its output frequency.
1079 * Implements .recalc_rate, .set_rate and .round_rate
1080 *
1081 * Flags:
1082 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1083 * from the register, with 0 being a valid value effectively
1084 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1085 * set, then a null multiplier will be considered as a bypass,
1086 * leaving the parent rate unmodified.
1087 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1088 * rounded to the closest integer instead of the down one.
1089 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1090 * used for the multiplier register. Setting this flag makes the register
1091 * accesses big endian.
1092 */
1093 struct clk_multiplier {
1094 struct clk_hw hw;
1095 void __iomem *reg;
1096 u8 shift;
1097 u8 width;
1098 u8 flags;
1099 spinlock_t *lock;
1100 };
1101
1102 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1103
1104 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1105 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1106 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1107
1108 extern const struct clk_ops clk_multiplier_ops;
1109
1110 /***
1111 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1112 *
1113 * @hw: handle between common and hardware-specific interfaces
1114 * @mux_hw: handle between composite and hardware-specific mux clock
1115 * @rate_hw: handle between composite and hardware-specific rate clock
1116 * @gate_hw: handle between composite and hardware-specific gate clock
1117 * @mux_ops: clock ops for mux
1118 * @rate_ops: clock ops for rate
1119 * @gate_ops: clock ops for gate
1120 */
1121 struct clk_composite {
1122 struct clk_hw hw;
1123 struct clk_ops ops;
1124
1125 struct clk_hw *mux_hw;
1126 struct clk_hw *rate_hw;
1127 struct clk_hw *gate_hw;
1128
1129 const struct clk_ops *mux_ops;
1130 const struct clk_ops *rate_ops;
1131 const struct clk_ops *gate_ops;
1132 };
1133
1134 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1135
1136 struct clk *clk_register_composite(struct device *dev, const char *name,
1137 const char * const *parent_names, int num_parents,
1138 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1139 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1140 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1141 unsigned long flags);
1142 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1143 const struct clk_parent_data *parent_data, int num_parents,
1144 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1145 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1146 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1147 unsigned long flags);
1148 void clk_unregister_composite(struct clk *clk);
1149 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1150 const char * const *parent_names, int num_parents,
1151 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1152 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1153 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1154 unsigned long flags);
1155 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1156 const char *name,
1157 const struct clk_parent_data *parent_data, int num_parents,
1158 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1159 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1160 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1161 unsigned long flags);
1162 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1163 const char *name, const struct clk_parent_data *parent_data,
1164 int num_parents,
1165 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1166 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1167 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1168 unsigned long flags);
1169 void clk_hw_unregister_composite(struct clk_hw *hw);
1170
1171 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1172 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1173
1174 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1175 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1176 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1177
1178 void clk_unregister(struct clk *clk);
1179 void devm_clk_unregister(struct device *dev, struct clk *clk);
1180
1181 void clk_hw_unregister(struct clk_hw *hw);
1182 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1183
1184 /* helper functions */
1185 const char *__clk_get_name(const struct clk *clk);
1186 const char *clk_hw_get_name(const struct clk_hw *hw);
1187 #ifdef CONFIG_COMMON_CLK
1188 struct clk_hw *__clk_get_hw(struct clk *clk);
1189 #else
__clk_get_hw(struct clk * clk)1190 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1191 {
1192 return (struct clk_hw *)clk;
1193 }
1194 #endif
1195
1196 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1197 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1198 const char *con_id);
1199
1200 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1201 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1202 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1203 unsigned int index);
1204 int clk_hw_get_parent_index(struct clk_hw *hw);
1205 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1206 unsigned int __clk_get_enable_count(struct clk *clk);
1207 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1208 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1209 #define clk_hw_can_set_rate_parent(hw) \
1210 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1211
1212 bool clk_hw_is_prepared(const struct clk_hw *hw);
1213 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1214 bool clk_hw_is_enabled(const struct clk_hw *hw);
1215 bool __clk_is_enabled(struct clk *clk);
1216 struct clk *__clk_lookup(const char *name);
1217 int __clk_mux_determine_rate(struct clk_hw *hw,
1218 struct clk_rate_request *req);
1219 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1220 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1221 struct clk_rate_request *req);
1222 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1223 struct clk_rate_request *req,
1224 unsigned long flags);
1225 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1226 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1227 unsigned long max_rate);
1228
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1229 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1230 {
1231 dst->clk = src->clk;
1232 dst->core = src->core;
1233 }
1234
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1235 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1236 unsigned long *prate,
1237 const struct clk_div_table *table,
1238 u8 width, unsigned long flags)
1239 {
1240 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1241 rate, prate, table, width, flags);
1242 }
1243
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1244 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1245 unsigned long *prate,
1246 const struct clk_div_table *table,
1247 u8 width, unsigned long flags,
1248 unsigned int val)
1249 {
1250 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1251 rate, prate, table, width, flags,
1252 val);
1253 }
1254
1255 /*
1256 * FIXME clock api without lock protection
1257 */
1258 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1259
1260 struct clk_onecell_data {
1261 struct clk **clks;
1262 unsigned int clk_num;
1263 };
1264
1265 struct clk_hw_onecell_data {
1266 unsigned int num;
1267 struct clk_hw *hws[];
1268 };
1269
1270 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1271
1272 /*
1273 * Use this macro when you have a driver that requires two initialization
1274 * routines, one at of_clk_init(), and one at platform device probe
1275 */
1276 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1277 static void __init name##_of_clk_init_driver(struct device_node *np) \
1278 { \
1279 of_node_clear_flag(np, OF_POPULATED); \
1280 fn(np); \
1281 } \
1282 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1283
1284 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1285 (&(struct clk_init_data) { \
1286 .flags = _flags, \
1287 .name = _name, \
1288 .parent_names = (const char *[]) { _parent }, \
1289 .num_parents = 1, \
1290 .ops = _ops, \
1291 })
1292
1293 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1294 (&(struct clk_init_data) { \
1295 .flags = _flags, \
1296 .name = _name, \
1297 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1298 .num_parents = 1, \
1299 .ops = _ops, \
1300 })
1301
1302 /*
1303 * This macro is intended for drivers to be able to share the otherwise
1304 * individual struct clk_hw[] compound literals created by the compiler
1305 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1306 */
1307 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1308 (&(struct clk_init_data) { \
1309 .flags = _flags, \
1310 .name = _name, \
1311 .parent_hws = _parent, \
1312 .num_parents = 1, \
1313 .ops = _ops, \
1314 })
1315
1316 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1317 (&(struct clk_init_data) { \
1318 .flags = _flags, \
1319 .name = _name, \
1320 .parent_data = (const struct clk_parent_data[]) { \
1321 { .fw_name = _parent }, \
1322 }, \
1323 .num_parents = 1, \
1324 .ops = _ops, \
1325 })
1326
1327 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1328 (&(struct clk_init_data) { \
1329 .flags = _flags, \
1330 .name = _name, \
1331 .parent_names = _parents, \
1332 .num_parents = ARRAY_SIZE(_parents), \
1333 .ops = _ops, \
1334 })
1335
1336 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1337 (&(struct clk_init_data) { \
1338 .flags = _flags, \
1339 .name = _name, \
1340 .parent_hws = _parents, \
1341 .num_parents = ARRAY_SIZE(_parents), \
1342 .ops = _ops, \
1343 })
1344
1345 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1346 (&(struct clk_init_data) { \
1347 .flags = _flags, \
1348 .name = _name, \
1349 .parent_data = _parents, \
1350 .num_parents = ARRAY_SIZE(_parents), \
1351 .ops = _ops, \
1352 })
1353
1354 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1355 (&(struct clk_init_data) { \
1356 .flags = _flags, \
1357 .name = _name, \
1358 .parent_names = NULL, \
1359 .num_parents = 0, \
1360 .ops = _ops, \
1361 })
1362
1363 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1364 _div, _mult, _flags) \
1365 struct clk_fixed_factor _struct = { \
1366 .div = _div, \
1367 .mult = _mult, \
1368 .hw.init = CLK_HW_INIT(_name, \
1369 _parent, \
1370 &clk_fixed_factor_ops, \
1371 _flags), \
1372 }
1373
1374 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1375 _div, _mult, _flags) \
1376 struct clk_fixed_factor _struct = { \
1377 .div = _div, \
1378 .mult = _mult, \
1379 .hw.init = CLK_HW_INIT_HW(_name, \
1380 _parent, \
1381 &clk_fixed_factor_ops, \
1382 _flags), \
1383 }
1384
1385 /*
1386 * This macro allows the driver to reuse the _parent array for multiple
1387 * fixed factor clk declarations.
1388 */
1389 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1390 _div, _mult, _flags) \
1391 struct clk_fixed_factor _struct = { \
1392 .div = _div, \
1393 .mult = _mult, \
1394 .hw.init = CLK_HW_INIT_HWS(_name, \
1395 _parent, \
1396 &clk_fixed_factor_ops, \
1397 _flags), \
1398 }
1399
1400 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1401 _div, _mult, _flags) \
1402 struct clk_fixed_factor _struct = { \
1403 .div = _div, \
1404 .mult = _mult, \
1405 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1406 _parent, \
1407 &clk_fixed_factor_ops, \
1408 _flags), \
1409 }
1410
1411 #ifdef CONFIG_OF
1412 int of_clk_add_provider(struct device_node *np,
1413 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1414 void *data),
1415 void *data);
1416 int of_clk_add_hw_provider(struct device_node *np,
1417 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1418 void *data),
1419 void *data);
1420 int devm_of_clk_add_hw_provider(struct device *dev,
1421 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1422 void *data),
1423 void *data);
1424 void of_clk_del_provider(struct device_node *np);
1425 void devm_of_clk_del_provider(struct device *dev);
1426 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1427 void *data);
1428 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1429 void *data);
1430 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1431 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1432 void *data);
1433 int of_clk_parent_fill(struct device_node *np, const char **parents,
1434 unsigned int size);
1435 int of_clk_detect_critical(struct device_node *np, int index,
1436 unsigned long *flags);
1437
1438 #else /* !CONFIG_OF */
1439
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1440 static inline int of_clk_add_provider(struct device_node *np,
1441 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1442 void *data),
1443 void *data)
1444 {
1445 return 0;
1446 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1447 static inline int of_clk_add_hw_provider(struct device_node *np,
1448 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1449 void *data),
1450 void *data)
1451 {
1452 return 0;
1453 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1454 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1455 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1456 void *data),
1457 void *data)
1458 {
1459 return 0;
1460 }
of_clk_del_provider(struct device_node * np)1461 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1462 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1463 static inline struct clk *of_clk_src_simple_get(
1464 struct of_phandle_args *clkspec, void *data)
1465 {
1466 return ERR_PTR(-ENOENT);
1467 }
1468 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1469 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1470 {
1471 return ERR_PTR(-ENOENT);
1472 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1473 static inline struct clk *of_clk_src_onecell_get(
1474 struct of_phandle_args *clkspec, void *data)
1475 {
1476 return ERR_PTR(-ENOENT);
1477 }
1478 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1479 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1480 {
1481 return ERR_PTR(-ENOENT);
1482 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1483 static inline int of_clk_parent_fill(struct device_node *np,
1484 const char **parents, unsigned int size)
1485 {
1486 return 0;
1487 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1488 static inline int of_clk_detect_critical(struct device_node *np, int index,
1489 unsigned long *flags)
1490 {
1491 return 0;
1492 }
1493 #endif /* CONFIG_OF */
1494
1495 void clk_gate_restore_context(struct clk_hw *hw);
1496
1497 #endif /* CLK_PROVIDER_H */
1498