1 /*
2 * linux/arch/cris/kernel/irq.c
3 *
4 * Copyright (c) 2000-2002 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (bjornw@axis.com)
7 *
8 * This file contains the interrupt vectors and some
9 * helper functions
10 *
11 */
12
13 #include <asm/irq.h>
14 #include <asm/current.h>
15 #include <linux/irq.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19
20 #define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
21 #define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
22
23 /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
24 * global just so that the kernel gdb can use it.
25 */
26
27 void
set_int_vector(int n,irqvectptr addr)28 set_int_vector(int n, irqvectptr addr)
29 {
30 etrax_irv->v[n + 0x20] = (irqvectptr)addr;
31 }
32
33 /* the breakpoint vector is obviously not made just like the normal irq handlers
34 * but needs to contain _code_ to jump to addr.
35 *
36 * the BREAK n instruction jumps to IBR + n * 8
37 */
38
39 void
set_break_vector(int n,irqvectptr addr)40 set_break_vector(int n, irqvectptr addr)
41 {
42 unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2];
43 unsigned long *jaddr = (unsigned long *)(jinstr + 1);
44
45 /* if you don't know what this does, do not touch it! */
46
47 *jinstr = 0x0d3f;
48 *jaddr = (unsigned long)addr;
49
50 /* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
51 }
52
53 /*
54 * This builds up the IRQ handler stubs using some ugly macros in irq.h
55 *
56 * These macros create the low-level assembly IRQ routines that do all
57 * the operations that are needed. They are also written to be fast - and to
58 * disable interrupts as little as humanly possible.
59 *
60 */
61
62 /* IRQ0 and 1 are special traps */
63 void hwbreakpoint(void);
64 void IRQ1_interrupt(void);
65 BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
66 BUILD_IRQ(3, 0x08)
67 BUILD_IRQ(4, 0x10)
68 BUILD_IRQ(5, 0x20)
69 BUILD_IRQ(6, 0x40)
70 BUILD_IRQ(7, 0x80)
71 BUILD_IRQ(8, 0x100)
72 BUILD_IRQ(9, 0x200)
73 BUILD_IRQ(10, 0x400)
74 BUILD_IRQ(11, 0x800)
75 BUILD_IRQ(12, 0x1000)
76 BUILD_IRQ(13, 0x2000)
77 void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
78 void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
79 BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */
80 BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */
81 BUILD_IRQ(18, 0x40000)
82 BUILD_IRQ(19, 0x80000)
83 BUILD_IRQ(20, 0x100000)
84 BUILD_IRQ(21, 0x200000)
85 BUILD_IRQ(22, 0x400000)
86 BUILD_IRQ(23, 0x800000)
87 BUILD_IRQ(24, 0x1000000)
88 BUILD_IRQ(25, 0x2000000)
89 /* IRQ 26-30 are reserved */
90 BUILD_IRQ(31, 0x80000000)
91
92 /*
93 * Pointers to the low-level handlers
94 */
95
96 static void (*interrupt[NR_IRQS])(void) = {
97 NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
98 IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
99 IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
100 IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
101 IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
102 IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
103 IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
104 IRQ31_interrupt
105 };
106
enable_crisv10_irq(struct irq_data * data)107 static void enable_crisv10_irq(struct irq_data *data)
108 {
109 crisv10_unmask_irq(data->irq);
110 }
111
disable_crisv10_irq(struct irq_data * data)112 static void disable_crisv10_irq(struct irq_data *data)
113 {
114 crisv10_mask_irq(data->irq);
115 }
116
117 static struct irq_chip crisv10_irq_type = {
118 .name = "CRISv10",
119 .irq_shutdown = disable_crisv10_irq,
120 .irq_enable = enable_crisv10_irq,
121 .irq_disable = disable_crisv10_irq,
122 };
123
124 void weird_irq(void);
125 void system_call(void); /* from entry.S */
126 void do_sigtrap(void); /* from entry.S */
127 void gdb_handle_breakpoint(void); /* from entry.S */
128
129 extern void do_IRQ(int irq, struct pt_regs * regs);
130
131 /* Handle multiple IRQs */
do_multiple_IRQ(struct pt_regs * regs)132 void do_multiple_IRQ(struct pt_regs* regs)
133 {
134 int bit;
135 unsigned masked;
136 unsigned mask;
137 unsigned ethmask = 0;
138
139 /* Get interrupts to mask and handle */
140 mask = masked = *R_VECT_MASK_RD;
141
142 /* Never mask timer IRQ */
143 mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
144
145 /*
146 * If either ethernet interrupt (rx or tx) is active then block
147 * the other one too. Unblock afterwards also.
148 */
149 if (mask &
150 (IO_STATE(R_VECT_MASK_RD, dma0, active) |
151 IO_STATE(R_VECT_MASK_RD, dma1, active))) {
152 ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
153 IO_MASK(R_VECT_MASK_RD, dma1));
154 }
155
156 /* Block them */
157 *R_VECT_MASK_CLR = (mask | ethmask);
158
159 /* An extra irq_enter here to prevent softIRQs to run after
160 * each do_IRQ. This will decrease the interrupt latency.
161 */
162 irq_enter();
163
164 /* Handle all IRQs */
165 for (bit = 2; bit < 32; bit++) {
166 if (masked & (1 << bit)) {
167 do_IRQ(bit, regs);
168 }
169 }
170
171 /* This irq_exit() will trigger the soft IRQs. */
172 irq_exit();
173
174 /* Unblock the IRQs again */
175 *R_VECT_MASK_SET = (masked | ethmask);
176 }
177
178 /* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
179 setting the irq vector table.
180 */
181
182 void __init
init_IRQ(void)183 init_IRQ(void)
184 {
185 int i;
186
187 /* clear all interrupt masks */
188
189 #ifndef CONFIG_SVINTO_SIM
190 *R_IRQ_MASK0_CLR = 0xffffffff;
191 *R_IRQ_MASK1_CLR = 0xffffffff;
192 *R_IRQ_MASK2_CLR = 0xffffffff;
193 #endif
194
195 *R_VECT_MASK_CLR = 0xffffffff;
196
197 for (i = 0; i < 256; i++)
198 etrax_irv->v[i] = weird_irq;
199
200 /* Initialize IRQ handler descriptors. */
201 for(i = 2; i < NR_IRQS; i++) {
202 irq_set_chip_and_handler(i, &crisv10_irq_type,
203 handle_simple_irq);
204 set_int_vector(i, interrupt[i]);
205 }
206
207 /* the entries in the break vector contain actual code to be
208 executed by the associated break handler, rather than just a jump
209 address. therefore we need to setup a default breakpoint handler
210 for all breakpoints */
211
212 for (i = 0; i < 16; i++)
213 set_break_vector(i, do_sigtrap);
214
215 /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
216
217 set_int_vector(15, multiple_interrupt);
218
219 /* 0 and 1 which are special breakpoint/NMI traps */
220
221 set_int_vector(0, hwbreakpoint);
222 set_int_vector(1, IRQ1_interrupt);
223
224 /* and irq 14 which is the mmu bus fault handler */
225
226 set_int_vector(14, mmu_bus_fault);
227
228 /* setup the system-call trap, which is reached by BREAK 13 */
229
230 set_break_vector(13, system_call);
231
232 /* setup a breakpoint handler for debugging used for both user and
233 kernel mode debugging (which is why it is not inside an ifdef
234 CONFIG_ETRAX_KGDB) */
235 set_break_vector(8, gdb_handle_breakpoint);
236
237 #ifdef CONFIG_ETRAX_KGDB
238 /* setup kgdb if its enabled, and break into the debugger */
239 kgdb_init();
240 breakpoint();
241 #endif
242 }
243