1 #ifdef __KERNEL__
2 #ifndef _ASM_PCI_BRIDGE_H
3 #define _ASM_PCI_BRIDGE_H
4
5 #include <linux/ioport.h>
6 #include <linux/pci.h>
7
8 struct device_node;
9 struct pci_controller;
10
11 /*
12 * pci_io_base returns the memory address at which you can access
13 * the I/O space for PCI bus number `bus' (or NULL on error).
14 */
15 extern void *pci_bus_io_base(unsigned int bus);
16 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
17 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
18
19 /* Allocate a new PCI host bridge structure */
20 extern struct pci_controller* pcibios_alloc_controller(void);
21
22 /* Helper function for setting up resources */
23 extern void pci_init_resource(struct resource *res, unsigned long start,
24 unsigned long end, int flags, char *name);
25
26 /*
27 * PCI <-> OF matching functions
28 */
29 extern int pci_device_from_OF_node(struct device_node *node,
30 u8* bus, u8* devfn);
31 extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
32 extern void pci_create_OF_bus_map(void);
33
34 /* Get the PCI host controller for a bus */
35 extern struct pci_controller* pci_bus_to_hose(int bus);
36
37 /* Get the PCI host controller for an OF device */
38 extern struct pci_controller*
39 pci_find_hose_for_OF_device(struct device_node* node);
40
41 /* Fill up host controller resources from the OF node */
42 extern void
43 pci_process_bridge_OF_ranges(struct pci_controller *hose,
44 struct device_node *dev, int primary);
45
46 /*
47 * Structure of a PCI controller (host bridge)
48 */
49 struct pci_controller {
50 int index; /* used for pci_controller_num */
51 struct pci_controller *next;
52 struct pci_bus *bus;
53 void *arch_data;
54
55 int first_busno;
56 int last_busno;
57 int bus_offset;
58
59 void *io_base_virt;
60 unsigned long io_base_phys;
61
62 /* Some machines (PReP) have a non 1:1 mapping of
63 * the PCI memory space in the CPU bus space
64 */
65 unsigned long pci_mem_offset;
66
67 struct pci_ops *ops;
68 volatile unsigned int *cfg_addr;
69 volatile unsigned char *cfg_data;
70 /*
71 * If set, indirect method will set the cfg_type bit as
72 * needed to generate type 1 configuration transactions.
73 */
74 int set_cfg_type;
75
76 /* Currently, we limit ourselves to 1 IO range and 3 mem
77 * ranges since the common pci_bus structure can't handle more
78 */
79 struct resource io_resource;
80 struct resource mem_resources[3];
81 int mem_resource_count;
82
83 /* Host bridge I/O and Memory space
84 * Used for BAR placement algorithms
85 */
86 struct resource io_space;
87 struct resource mem_space;
88 };
89
90 /* These are used for config access before all the PCI probing
91 has been done. */
92 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
93 int where, u8 *val);
94 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
95 int where, u16 *val);
96 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
97 int where, u32 *val);
98 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
99 int where, u8 val);
100 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
101 int where, u16 val);
102 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
103 int where, u32 val);
104
105 extern void setup_indirect_pci(struct pci_controller* hose,
106 u32 cfg_addr, u32 cfg_data);
107 extern void setup_grackle(struct pci_controller *hose);
108
109 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
110
111 /*
112 * The following code swizzles for exactly one bridge. The routine
113 * common_swizzle below handles multiple bridges. But there are a
114 * some boards that don't follow the PCI spec's suggestion so we
115 * break this piece out separately.
116 */
bridge_swizzle(unsigned char pin,unsigned char idsel)117 static inline unsigned char bridge_swizzle(unsigned char pin,
118 unsigned char idsel)
119 {
120 return (((pin-1) + idsel) % 4) + 1;
121 }
122
123 /*
124 * The following macro is used to lookup irqs in a standard table
125 * format for those PPC systems that do not already have PCI
126 * interrupts properly routed.
127 */
128 /* FIXME - double check this */
129 #define PCI_IRQ_TABLE_LOOKUP \
130 ({ long _ctl_ = -1; \
131 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
132 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
133 _ctl_; })
134
135 /*
136 * Scan the buses below a given PCI host bridge and assign suitable
137 * resources to all devices found.
138 */
139 extern int pciauto_bus_scan(struct pci_controller *, int);
140
141 #endif
142 #endif /* __KERNEL__ */
143