1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/console.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/sysrq.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/tty.h>
25 #include <linux/ratelimit.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/nmi.h>
30 #include <linux/mutex.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/ktime.h>
35 
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 
39 #include "8250.h"
40 
41 /* Nuvoton NPCM timeout register */
42 #define UART_NPCM_TOR          7
43 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
44 
45 /*
46  * Debugging.
47  */
48 #if 0
49 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
50 #else
51 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
52 #endif
53 
54 /*
55  * Here we define the default xmit fifo size used for each type of UART.
56  */
57 static const struct serial8250_config uart_config[] = {
58 	[PORT_UNKNOWN] = {
59 		.name		= "unknown",
60 		.fifo_size	= 1,
61 		.tx_loadsz	= 1,
62 	},
63 	[PORT_8250] = {
64 		.name		= "8250",
65 		.fifo_size	= 1,
66 		.tx_loadsz	= 1,
67 	},
68 	[PORT_16450] = {
69 		.name		= "16450",
70 		.fifo_size	= 1,
71 		.tx_loadsz	= 1,
72 	},
73 	[PORT_16550] = {
74 		.name		= "16550",
75 		.fifo_size	= 1,
76 		.tx_loadsz	= 1,
77 	},
78 	[PORT_16550A] = {
79 		.name		= "16550A",
80 		.fifo_size	= 16,
81 		.tx_loadsz	= 16,
82 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 		.rxtrig_bytes	= {1, 4, 8, 14},
84 		.flags		= UART_CAP_FIFO,
85 	},
86 	[PORT_CIRRUS] = {
87 		.name		= "Cirrus",
88 		.fifo_size	= 1,
89 		.tx_loadsz	= 1,
90 	},
91 	[PORT_16650] = {
92 		.name		= "ST16650",
93 		.fifo_size	= 1,
94 		.tx_loadsz	= 1,
95 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
96 	},
97 	[PORT_16650V2] = {
98 		.name		= "ST16650V2",
99 		.fifo_size	= 32,
100 		.tx_loadsz	= 16,
101 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 				  UART_FCR_T_TRIG_00,
103 		.rxtrig_bytes	= {8, 16, 24, 28},
104 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 	},
106 	[PORT_16750] = {
107 		.name		= "TI16750",
108 		.fifo_size	= 64,
109 		.tx_loadsz	= 64,
110 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 				  UART_FCR7_64BYTE,
112 		.rxtrig_bytes	= {1, 16, 32, 56},
113 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
114 	},
115 	[PORT_STARTECH] = {
116 		.name		= "Startech",
117 		.fifo_size	= 1,
118 		.tx_loadsz	= 1,
119 	},
120 	[PORT_16C950] = {
121 		.name		= "16C950/954",
122 		.fifo_size	= 128,
123 		.tx_loadsz	= 128,
124 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
125 		.rxtrig_bytes	= {16, 32, 112, 120},
126 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
128 	},
129 	[PORT_16654] = {
130 		.name		= "ST16654",
131 		.fifo_size	= 64,
132 		.tx_loadsz	= 32,
133 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 				  UART_FCR_T_TRIG_10,
135 		.rxtrig_bytes	= {8, 16, 56, 60},
136 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
137 	},
138 	[PORT_16850] = {
139 		.name		= "XR16850",
140 		.fifo_size	= 128,
141 		.tx_loadsz	= 128,
142 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 	},
145 	[PORT_RSA] = {
146 		.name		= "RSA",
147 		.fifo_size	= 2048,
148 		.tx_loadsz	= 2048,
149 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 		.flags		= UART_CAP_FIFO,
151 	},
152 	[PORT_NS16550A] = {
153 		.name		= "NS16550A",
154 		.fifo_size	= 16,
155 		.tx_loadsz	= 16,
156 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
158 	},
159 	[PORT_XSCALE] = {
160 		.name		= "XScale",
161 		.fifo_size	= 32,
162 		.tx_loadsz	= 32,
163 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
165 	},
166 	[PORT_OCTEON] = {
167 		.name		= "OCTEON",
168 		.fifo_size	= 64,
169 		.tx_loadsz	= 64,
170 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 		.flags		= UART_CAP_FIFO,
172 	},
173 	[PORT_AR7] = {
174 		.name		= "AR7",
175 		.fifo_size	= 16,
176 		.tx_loadsz	= 16,
177 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
179 	},
180 	[PORT_U6_16550A] = {
181 		.name		= "U6_16550A",
182 		.fifo_size	= 64,
183 		.tx_loadsz	= 64,
184 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
186 	},
187 	[PORT_TEGRA] = {
188 		.name		= "Tegra",
189 		.fifo_size	= 32,
190 		.tx_loadsz	= 8,
191 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 				  UART_FCR_T_TRIG_01,
193 		.rxtrig_bytes	= {1, 4, 8, 14},
194 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
195 	},
196 	[PORT_XR17D15X] = {
197 		.name		= "XR17D15X",
198 		.fifo_size	= 64,
199 		.tx_loadsz	= 64,
200 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
202 				  UART_CAP_SLEEP,
203 	},
204 	[PORT_XR17V35X] = {
205 		.name		= "XR17V35X",
206 		.fifo_size	= 256,
207 		.tx_loadsz	= 256,
208 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 				  UART_FCR_T_TRIG_11,
210 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 				  UART_CAP_SLEEP,
212 	},
213 	[PORT_LPC3220] = {
214 		.name		= "LPC3220",
215 		.fifo_size	= 64,
216 		.tx_loadsz	= 32,
217 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 		.flags		= UART_CAP_FIFO,
220 	},
221 	[PORT_BRCM_TRUMANAGE] = {
222 		.name		= "TruManage",
223 		.fifo_size	= 1,
224 		.tx_loadsz	= 1024,
225 		.flags		= UART_CAP_HFIFO,
226 	},
227 	[PORT_8250_CIR] = {
228 		.name		= "CIR port"
229 	},
230 	[PORT_ALTR_16550_F32] = {
231 		.name		= "Altera 16550 FIFO32",
232 		.fifo_size	= 32,
233 		.tx_loadsz	= 32,
234 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 		.rxtrig_bytes	= {1, 8, 16, 30},
236 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
237 	},
238 	[PORT_ALTR_16550_F64] = {
239 		.name		= "Altera 16550 FIFO64",
240 		.fifo_size	= 64,
241 		.tx_loadsz	= 64,
242 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 		.rxtrig_bytes	= {1, 16, 32, 62},
244 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
245 	},
246 	[PORT_ALTR_16550_F128] = {
247 		.name		= "Altera 16550 FIFO128",
248 		.fifo_size	= 128,
249 		.tx_loadsz	= 128,
250 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 		.rxtrig_bytes	= {1, 32, 64, 126},
252 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
253 	},
254 	/*
255 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 	 * workaround of errata A-008006 which states that tx_loadsz should
257 	 * be configured less than Maximum supported fifo bytes.
258 	 */
259 	[PORT_16550A_FSL64] = {
260 		.name		= "16550A_FSL64",
261 		.fifo_size	= 64,
262 		.tx_loadsz	= 63,
263 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 				  UART_FCR7_64BYTE,
265 		.flags		= UART_CAP_FIFO | UART_CAP_NOTEMT,
266 	},
267 	[PORT_RT2880] = {
268 		.name		= "Palmchip BK-3103",
269 		.fifo_size	= 16,
270 		.tx_loadsz	= 16,
271 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 		.rxtrig_bytes	= {1, 4, 8, 14},
273 		.flags		= UART_CAP_FIFO,
274 	},
275 	[PORT_DA830] = {
276 		.name		= "TI DA8xx/66AK2x",
277 		.fifo_size	= 16,
278 		.tx_loadsz	= 16,
279 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 				  UART_FCR_R_TRIG_10,
281 		.rxtrig_bytes	= {1, 4, 8, 14},
282 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
283 	},
284 	[PORT_MTK_BTIF] = {
285 		.name		= "MediaTek BTIF",
286 		.fifo_size	= 16,
287 		.tx_loadsz	= 16,
288 		.fcr		= UART_FCR_ENABLE_FIFO |
289 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 		.flags		= UART_CAP_FIFO,
291 	},
292 	[PORT_NPCM] = {
293 		.name		= "Nuvoton 16550",
294 		.fifo_size	= 16,
295 		.tx_loadsz	= 16,
296 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 		.rxtrig_bytes	= {1, 4, 8, 14},
299 		.flags		= UART_CAP_FIFO,
300 	},
301 	[PORT_SUNIX] = {
302 		.name		= "Sunix",
303 		.fifo_size	= 128,
304 		.tx_loadsz	= 128,
305 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 		.rxtrig_bytes	= {1, 32, 64, 112},
307 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
308 	},
309 	[PORT_ASPEED_VUART] = {
310 		.name		= "ASPEED VUART",
311 		.fifo_size	= 16,
312 		.tx_loadsz	= 16,
313 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
314 		.rxtrig_bytes	= {1, 4, 8, 14},
315 		.flags		= UART_CAP_FIFO,
316 	},
317 	[PORT_MCHP16550A] = {
318 		.name           = "MCHP16550A",
319 		.fifo_size      = 256,
320 		.tx_loadsz      = 256,
321 		.fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
322 		.rxtrig_bytes   = {2, 66, 130, 194},
323 		.flags          = UART_CAP_FIFO,
324 	},
325 	[PORT_BCM7271] = {
326 		.name		= "Broadcom BCM7271 UART",
327 		.fifo_size	= 32,
328 		.tx_loadsz	= 32,
329 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
330 		.rxtrig_bytes	= {1, 8, 16, 30},
331 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
332 	},
333 };
334 
335 /* Uart divisor latch read */
default_serial_dl_read(struct uart_8250_port * up)336 static u32 default_serial_dl_read(struct uart_8250_port *up)
337 {
338 	/* Assign these in pieces to truncate any bits above 7.  */
339 	unsigned char dll = serial_in(up, UART_DLL);
340 	unsigned char dlm = serial_in(up, UART_DLM);
341 
342 	return dll | dlm << 8;
343 }
344 
345 /* Uart divisor latch write */
default_serial_dl_write(struct uart_8250_port * up,u32 value)346 static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
347 {
348 	serial_out(up, UART_DLL, value & 0xff);
349 	serial_out(up, UART_DLM, value >> 8 & 0xff);
350 }
351 
hub6_serial_in(struct uart_port * p,int offset)352 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
353 {
354 	offset = offset << p->regshift;
355 	outb(p->hub6 - 1 + offset, p->iobase);
356 	return inb(p->iobase + 1);
357 }
358 
hub6_serial_out(struct uart_port * p,int offset,int value)359 static void hub6_serial_out(struct uart_port *p, int offset, int value)
360 {
361 	offset = offset << p->regshift;
362 	outb(p->hub6 - 1 + offset, p->iobase);
363 	outb(value, p->iobase + 1);
364 }
365 
mem_serial_in(struct uart_port * p,int offset)366 static unsigned int mem_serial_in(struct uart_port *p, int offset)
367 {
368 	offset = offset << p->regshift;
369 	return readb(p->membase + offset);
370 }
371 
mem_serial_out(struct uart_port * p,int offset,int value)372 static void mem_serial_out(struct uart_port *p, int offset, int value)
373 {
374 	offset = offset << p->regshift;
375 	writeb(value, p->membase + offset);
376 }
377 
mem16_serial_out(struct uart_port * p,int offset,int value)378 static void mem16_serial_out(struct uart_port *p, int offset, int value)
379 {
380 	offset = offset << p->regshift;
381 	writew(value, p->membase + offset);
382 }
383 
mem16_serial_in(struct uart_port * p,int offset)384 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
385 {
386 	offset = offset << p->regshift;
387 	return readw(p->membase + offset);
388 }
389 
mem32_serial_out(struct uart_port * p,int offset,int value)390 static void mem32_serial_out(struct uart_port *p, int offset, int value)
391 {
392 	offset = offset << p->regshift;
393 	writel(value, p->membase + offset);
394 }
395 
mem32_serial_in(struct uart_port * p,int offset)396 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
397 {
398 	offset = offset << p->regshift;
399 	return readl(p->membase + offset);
400 }
401 
mem32be_serial_out(struct uart_port * p,int offset,int value)402 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
403 {
404 	offset = offset << p->regshift;
405 	iowrite32be(value, p->membase + offset);
406 }
407 
mem32be_serial_in(struct uart_port * p,int offset)408 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
409 {
410 	offset = offset << p->regshift;
411 	return ioread32be(p->membase + offset);
412 }
413 
io_serial_in(struct uart_port * p,int offset)414 static unsigned int io_serial_in(struct uart_port *p, int offset)
415 {
416 	offset = offset << p->regshift;
417 	return inb(p->iobase + offset);
418 }
419 
io_serial_out(struct uart_port * p,int offset,int value)420 static void io_serial_out(struct uart_port *p, int offset, int value)
421 {
422 	offset = offset << p->regshift;
423 	outb(value, p->iobase + offset);
424 }
425 
426 static int serial8250_default_handle_irq(struct uart_port *port);
427 
set_io_from_upio(struct uart_port * p)428 static void set_io_from_upio(struct uart_port *p)
429 {
430 	struct uart_8250_port *up = up_to_u8250p(p);
431 
432 	up->dl_read = default_serial_dl_read;
433 	up->dl_write = default_serial_dl_write;
434 
435 	switch (p->iotype) {
436 	case UPIO_HUB6:
437 		p->serial_in = hub6_serial_in;
438 		p->serial_out = hub6_serial_out;
439 		break;
440 
441 	case UPIO_MEM:
442 		p->serial_in = mem_serial_in;
443 		p->serial_out = mem_serial_out;
444 		break;
445 
446 	case UPIO_MEM16:
447 		p->serial_in = mem16_serial_in;
448 		p->serial_out = mem16_serial_out;
449 		break;
450 
451 	case UPIO_MEM32:
452 		p->serial_in = mem32_serial_in;
453 		p->serial_out = mem32_serial_out;
454 		break;
455 
456 	case UPIO_MEM32BE:
457 		p->serial_in = mem32be_serial_in;
458 		p->serial_out = mem32be_serial_out;
459 		break;
460 
461 	default:
462 		p->serial_in = io_serial_in;
463 		p->serial_out = io_serial_out;
464 		break;
465 	}
466 	/* Remember loaded iotype */
467 	up->cur_iotype = p->iotype;
468 	p->handle_irq = serial8250_default_handle_irq;
469 }
470 
471 static void
serial_port_out_sync(struct uart_port * p,int offset,int value)472 serial_port_out_sync(struct uart_port *p, int offset, int value)
473 {
474 	switch (p->iotype) {
475 	case UPIO_MEM:
476 	case UPIO_MEM16:
477 	case UPIO_MEM32:
478 	case UPIO_MEM32BE:
479 	case UPIO_AU:
480 		p->serial_out(p, offset, value);
481 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
482 		break;
483 	default:
484 		p->serial_out(p, offset, value);
485 	}
486 }
487 
488 /*
489  * FIFO support.
490  */
serial8250_clear_fifos(struct uart_8250_port * p)491 static void serial8250_clear_fifos(struct uart_8250_port *p)
492 {
493 	if (p->capabilities & UART_CAP_FIFO) {
494 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
495 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
496 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
497 		serial_out(p, UART_FCR, 0);
498 	}
499 }
500 
501 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
502 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
503 
serial8250_clear_and_reinit_fifos(struct uart_8250_port * p)504 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
505 {
506 	serial8250_clear_fifos(p);
507 	serial_out(p, UART_FCR, p->fcr);
508 }
509 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
510 
serial8250_rpm_get(struct uart_8250_port * p)511 void serial8250_rpm_get(struct uart_8250_port *p)
512 {
513 	if (!(p->capabilities & UART_CAP_RPM))
514 		return;
515 	pm_runtime_get_sync(p->port.dev);
516 }
517 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
518 
serial8250_rpm_put(struct uart_8250_port * p)519 void serial8250_rpm_put(struct uart_8250_port *p)
520 {
521 	if (!(p->capabilities & UART_CAP_RPM))
522 		return;
523 	pm_runtime_mark_last_busy(p->port.dev);
524 	pm_runtime_put_autosuspend(p->port.dev);
525 }
526 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
527 
528 /**
529  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
530  *	@p:	uart_8250_port port instance
531  *
532  *	The function is used to start rs485 software emulating on the
533  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
534  *	transmission. The function is idempotent, so it is safe to call it
535  *	multiple times.
536  *
537  *	The caller MUST enable interrupt on empty shift register before
538  *	calling serial8250_em485_init(). This interrupt is not a part of
539  *	8250 standard, but implementation defined.
540  *
541  *	The function is supposed to be called from .rs485_config callback
542  *	or from any other callback protected with p->port.lock spinlock.
543  *
544  *	See also serial8250_em485_destroy()
545  *
546  *	Return 0 - success, -errno - otherwise
547  */
serial8250_em485_init(struct uart_8250_port * p)548 static int serial8250_em485_init(struct uart_8250_port *p)
549 {
550 	/* Port locked to synchronize UART_IER access against the console. */
551 	lockdep_assert_held_once(&p->port.lock);
552 
553 	if (p->em485)
554 		goto deassert_rts;
555 
556 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
557 	if (!p->em485)
558 		return -ENOMEM;
559 
560 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
561 		     HRTIMER_MODE_REL);
562 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
563 		     HRTIMER_MODE_REL);
564 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
565 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
566 	p->em485->port = p;
567 	p->em485->active_timer = NULL;
568 	p->em485->tx_stopped = true;
569 
570 deassert_rts:
571 	if (p->em485->tx_stopped)
572 		p->rs485_stop_tx(p);
573 
574 	return 0;
575 }
576 
577 /**
578  *	serial8250_em485_destroy() - put uart_8250_port into normal state
579  *	@p:	uart_8250_port port instance
580  *
581  *	The function is used to stop rs485 software emulating on the
582  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
583  *	call it multiple times.
584  *
585  *	The function is supposed to be called from .rs485_config callback
586  *	or from any other callback protected with p->port.lock spinlock.
587  *
588  *	See also serial8250_em485_init()
589  */
serial8250_em485_destroy(struct uart_8250_port * p)590 void serial8250_em485_destroy(struct uart_8250_port *p)
591 {
592 	if (!p->em485)
593 		return;
594 
595 	hrtimer_cancel(&p->em485->start_tx_timer);
596 	hrtimer_cancel(&p->em485->stop_tx_timer);
597 
598 	kfree(p->em485);
599 	p->em485 = NULL;
600 }
601 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
602 
603 struct serial_rs485 serial8250_em485_supported = {
604 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
605 		 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
606 	.delay_rts_before_send = 1,
607 	.delay_rts_after_send = 1,
608 };
609 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
610 
611 /**
612  * serial8250_em485_config() - generic ->rs485_config() callback
613  * @port: uart port
614  * @termios: termios structure
615  * @rs485: rs485 settings
616  *
617  * Generic callback usable by 8250 uart drivers to activate rs485 settings
618  * if the uart is incapable of driving RTS as a Transmit Enable signal in
619  * hardware, relying on software emulation instead.
620  */
serial8250_em485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)621 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
622 			    struct serial_rs485 *rs485)
623 {
624 	struct uart_8250_port *up = up_to_u8250p(port);
625 
626 	/* pick sane settings if the user hasn't */
627 	if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
628 	    !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
629 		rs485->flags |= SER_RS485_RTS_ON_SEND;
630 		rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
631 	}
632 
633 	/*
634 	 * Both serial8250_em485_init() and serial8250_em485_destroy()
635 	 * are idempotent.
636 	 */
637 	if (rs485->flags & SER_RS485_ENABLED)
638 		return serial8250_em485_init(up);
639 
640 	serial8250_em485_destroy(up);
641 	return 0;
642 }
643 EXPORT_SYMBOL_GPL(serial8250_em485_config);
644 
645 /*
646  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
647  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
648  * empty and the HW can idle again.
649  */
serial8250_rpm_get_tx(struct uart_8250_port * p)650 void serial8250_rpm_get_tx(struct uart_8250_port *p)
651 {
652 	unsigned char rpm_active;
653 
654 	if (!(p->capabilities & UART_CAP_RPM))
655 		return;
656 
657 	rpm_active = xchg(&p->rpm_tx_active, 1);
658 	if (rpm_active)
659 		return;
660 	pm_runtime_get_sync(p->port.dev);
661 }
662 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
663 
serial8250_rpm_put_tx(struct uart_8250_port * p)664 void serial8250_rpm_put_tx(struct uart_8250_port *p)
665 {
666 	unsigned char rpm_active;
667 
668 	if (!(p->capabilities & UART_CAP_RPM))
669 		return;
670 
671 	rpm_active = xchg(&p->rpm_tx_active, 0);
672 	if (!rpm_active)
673 		return;
674 	pm_runtime_mark_last_busy(p->port.dev);
675 	pm_runtime_put_autosuspend(p->port.dev);
676 }
677 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
678 
679 /*
680  * IER sleep support.  UARTs which have EFRs need the "extended
681  * capability" bit enabled.  Note that on XR16C850s, we need to
682  * reset LCR to write to IER.
683  */
serial8250_set_sleep(struct uart_8250_port * p,int sleep)684 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
685 {
686 	unsigned char lcr = 0, efr = 0;
687 
688 	serial8250_rpm_get(p);
689 
690 	if (p->capabilities & UART_CAP_SLEEP) {
691 		/* Synchronize UART_IER access against the console. */
692 		spin_lock_irq(&p->port.lock);
693 		if (p->capabilities & UART_CAP_EFR) {
694 			lcr = serial_in(p, UART_LCR);
695 			efr = serial_in(p, UART_EFR);
696 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 			serial_out(p, UART_EFR, UART_EFR_ECB);
698 			serial_out(p, UART_LCR, 0);
699 		}
700 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
701 		if (p->capabilities & UART_CAP_EFR) {
702 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
703 			serial_out(p, UART_EFR, efr);
704 			serial_out(p, UART_LCR, lcr);
705 		}
706 		spin_unlock_irq(&p->port.lock);
707 	}
708 
709 	serial8250_rpm_put(p);
710 }
711 
serial8250_clear_IER(struct uart_8250_port * up)712 static void serial8250_clear_IER(struct uart_8250_port *up)
713 {
714 	if (up->capabilities & UART_CAP_UUE)
715 		serial_out(up, UART_IER, UART_IER_UUE);
716 	else
717 		serial_out(up, UART_IER, 0);
718 }
719 
720 #ifdef CONFIG_SERIAL_8250_RSA
721 /*
722  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
723  * We set the port uart clock rate if we succeed.
724  */
__enable_rsa(struct uart_8250_port * up)725 static int __enable_rsa(struct uart_8250_port *up)
726 {
727 	unsigned char mode;
728 	int result;
729 
730 	mode = serial_in(up, UART_RSA_MSR);
731 	result = mode & UART_RSA_MSR_FIFO;
732 
733 	if (!result) {
734 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
735 		mode = serial_in(up, UART_RSA_MSR);
736 		result = mode & UART_RSA_MSR_FIFO;
737 	}
738 
739 	if (result)
740 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
741 
742 	return result;
743 }
744 
enable_rsa(struct uart_8250_port * up)745 static void enable_rsa(struct uart_8250_port *up)
746 {
747 	if (up->port.type == PORT_RSA) {
748 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
749 			spin_lock_irq(&up->port.lock);
750 			__enable_rsa(up);
751 			spin_unlock_irq(&up->port.lock);
752 		}
753 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
754 			serial_out(up, UART_RSA_FRR, 0);
755 	}
756 }
757 
758 /*
759  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
760  * It is unknown why interrupts were disabled in here.  However,
761  * the caller is expected to preserve this behaviour by grabbing
762  * the spinlock before calling this function.
763  */
disable_rsa(struct uart_8250_port * up)764 static void disable_rsa(struct uart_8250_port *up)
765 {
766 	unsigned char mode;
767 	int result;
768 
769 	if (up->port.type == PORT_RSA &&
770 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
771 		spin_lock_irq(&up->port.lock);
772 
773 		mode = serial_in(up, UART_RSA_MSR);
774 		result = !(mode & UART_RSA_MSR_FIFO);
775 
776 		if (!result) {
777 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
778 			mode = serial_in(up, UART_RSA_MSR);
779 			result = !(mode & UART_RSA_MSR_FIFO);
780 		}
781 
782 		if (result)
783 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
784 		spin_unlock_irq(&up->port.lock);
785 	}
786 }
787 #endif /* CONFIG_SERIAL_8250_RSA */
788 
789 /*
790  * This is a quickie test to see how big the FIFO is.
791  * It doesn't work at all the time, more's the pity.
792  */
size_fifo(struct uart_8250_port * up)793 static int size_fifo(struct uart_8250_port *up)
794 {
795 	unsigned char old_fcr, old_mcr, old_lcr;
796 	u32 old_dl;
797 	int count;
798 
799 	old_lcr = serial_in(up, UART_LCR);
800 	serial_out(up, UART_LCR, 0);
801 	old_fcr = serial_in(up, UART_FCR);
802 	old_mcr = serial8250_in_MCR(up);
803 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
804 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
805 	serial8250_out_MCR(up, UART_MCR_LOOP);
806 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
807 	old_dl = serial_dl_read(up);
808 	serial_dl_write(up, 0x0001);
809 	serial_out(up, UART_LCR, UART_LCR_WLEN8);
810 	for (count = 0; count < 256; count++)
811 		serial_out(up, UART_TX, count);
812 	mdelay(20);/* FIXME - schedule_timeout */
813 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
814 	     (count < 256); count++)
815 		serial_in(up, UART_RX);
816 	serial_out(up, UART_FCR, old_fcr);
817 	serial8250_out_MCR(up, old_mcr);
818 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
819 	serial_dl_write(up, old_dl);
820 	serial_out(up, UART_LCR, old_lcr);
821 
822 	return count;
823 }
824 
825 /*
826  * Read UART ID using the divisor method - set DLL and DLM to zero
827  * and the revision will be in DLL and device type in DLM.  We
828  * preserve the device state across this.
829  */
autoconfig_read_divisor_id(struct uart_8250_port * p)830 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
831 {
832 	unsigned char old_lcr;
833 	unsigned int id, old_dl;
834 
835 	old_lcr = serial_in(p, UART_LCR);
836 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
837 	old_dl = serial_dl_read(p);
838 	serial_dl_write(p, 0);
839 	id = serial_dl_read(p);
840 	serial_dl_write(p, old_dl);
841 
842 	serial_out(p, UART_LCR, old_lcr);
843 
844 	return id;
845 }
846 
847 /*
848  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
849  * When this function is called we know it is at least a StarTech
850  * 16650 V2, but it might be one of several StarTech UARTs, or one of
851  * its clones.  (We treat the broken original StarTech 16650 V1 as a
852  * 16550, and why not?  Startech doesn't seem to even acknowledge its
853  * existence.)
854  *
855  * What evil have men's minds wrought...
856  */
autoconfig_has_efr(struct uart_8250_port * up)857 static void autoconfig_has_efr(struct uart_8250_port *up)
858 {
859 	unsigned int id1, id2, id3, rev;
860 
861 	/*
862 	 * Everything with an EFR has SLEEP
863 	 */
864 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
865 
866 	/*
867 	 * First we check to see if it's an Oxford Semiconductor UART.
868 	 *
869 	 * If we have to do this here because some non-National
870 	 * Semiconductor clone chips lock up if you try writing to the
871 	 * LSR register (which serial_icr_read does)
872 	 */
873 
874 	/*
875 	 * Check for Oxford Semiconductor 16C950.
876 	 *
877 	 * EFR [4] must be set else this test fails.
878 	 *
879 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
880 	 * claims that it's needed for 952 dual UART's (which are not
881 	 * recommended for new designs).
882 	 */
883 	up->acr = 0;
884 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
885 	serial_out(up, UART_EFR, UART_EFR_ECB);
886 	serial_out(up, UART_LCR, 0x00);
887 	id1 = serial_icr_read(up, UART_ID1);
888 	id2 = serial_icr_read(up, UART_ID2);
889 	id3 = serial_icr_read(up, UART_ID3);
890 	rev = serial_icr_read(up, UART_REV);
891 
892 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
893 
894 	if (id1 == 0x16 && id2 == 0xC9 &&
895 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
896 		up->port.type = PORT_16C950;
897 
898 		/*
899 		 * Enable work around for the Oxford Semiconductor 952 rev B
900 		 * chip which causes it to seriously miscalculate baud rates
901 		 * when DLL is 0.
902 		 */
903 		if (id3 == 0x52 && rev == 0x01)
904 			up->bugs |= UART_BUG_QUOT;
905 		return;
906 	}
907 
908 	/*
909 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
910 	 * reading back DLL and DLM.  The chip type depends on the DLM
911 	 * value read back:
912 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
913 	 *  0x12 - XR16C2850.
914 	 *  0x14 - XR16C854.
915 	 */
916 	id1 = autoconfig_read_divisor_id(up);
917 	DEBUG_AUTOCONF("850id=%04x ", id1);
918 
919 	id2 = id1 >> 8;
920 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
921 		up->port.type = PORT_16850;
922 		return;
923 	}
924 
925 	/*
926 	 * It wasn't an XR16C850.
927 	 *
928 	 * We distinguish between the '654 and the '650 by counting
929 	 * how many bytes are in the FIFO.  I'm using this for now,
930 	 * since that's the technique that was sent to me in the
931 	 * serial driver update, but I'm not convinced this works.
932 	 * I've had problems doing this in the past.  -TYT
933 	 */
934 	if (size_fifo(up) == 64)
935 		up->port.type = PORT_16654;
936 	else
937 		up->port.type = PORT_16650V2;
938 }
939 
940 /*
941  * We detected a chip without a FIFO.  Only two fall into
942  * this category - the original 8250 and the 16450.  The
943  * 16450 has a scratch register (accessible with LCR=0)
944  */
autoconfig_8250(struct uart_8250_port * up)945 static void autoconfig_8250(struct uart_8250_port *up)
946 {
947 	unsigned char scratch, status1, status2;
948 
949 	up->port.type = PORT_8250;
950 
951 	scratch = serial_in(up, UART_SCR);
952 	serial_out(up, UART_SCR, 0xa5);
953 	status1 = serial_in(up, UART_SCR);
954 	serial_out(up, UART_SCR, 0x5a);
955 	status2 = serial_in(up, UART_SCR);
956 	serial_out(up, UART_SCR, scratch);
957 
958 	if (status1 == 0xa5 && status2 == 0x5a)
959 		up->port.type = PORT_16450;
960 }
961 
broken_efr(struct uart_8250_port * up)962 static int broken_efr(struct uart_8250_port *up)
963 {
964 	/*
965 	 * Exar ST16C2550 "A2" devices incorrectly detect as
966 	 * having an EFR, and report an ID of 0x0201.  See
967 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
968 	 */
969 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
970 		return 1;
971 
972 	return 0;
973 }
974 
975 /*
976  * We know that the chip has FIFOs.  Does it have an EFR?  The
977  * EFR is located in the same register position as the IIR and
978  * we know the top two bits of the IIR are currently set.  The
979  * EFR should contain zero.  Try to read the EFR.
980  */
autoconfig_16550a(struct uart_8250_port * up)981 static void autoconfig_16550a(struct uart_8250_port *up)
982 {
983 	unsigned char status1, status2;
984 	unsigned int iersave;
985 
986 	/* Port locked to synchronize UART_IER access against the console. */
987 	lockdep_assert_held_once(&up->port.lock);
988 
989 	up->port.type = PORT_16550A;
990 	up->capabilities |= UART_CAP_FIFO;
991 
992 	if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
993 	    !(up->port.flags & UPF_FULL_PROBE))
994 		return;
995 
996 	/*
997 	 * Check for presence of the EFR when DLAB is set.
998 	 * Only ST16C650V1 UARTs pass this test.
999 	 */
1000 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 	if (serial_in(up, UART_EFR) == 0) {
1002 		serial_out(up, UART_EFR, 0xA8);
1003 		if (serial_in(up, UART_EFR) != 0) {
1004 			DEBUG_AUTOCONF("EFRv1 ");
1005 			up->port.type = PORT_16650;
1006 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1007 		} else {
1008 			serial_out(up, UART_LCR, 0);
1009 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1010 				   UART_FCR7_64BYTE);
1011 			status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
1012 							     UART_IIR_FIFO_ENABLED);
1013 			serial_out(up, UART_FCR, 0);
1014 			serial_out(up, UART_LCR, 0);
1015 
1016 			if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
1017 				up->port.type = PORT_16550A_FSL64;
1018 			else
1019 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1020 		}
1021 		serial_out(up, UART_EFR, 0);
1022 		return;
1023 	}
1024 
1025 	/*
1026 	 * Maybe it requires 0xbf to be written to the LCR.
1027 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1028 	 */
1029 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1031 		DEBUG_AUTOCONF("EFRv2 ");
1032 		autoconfig_has_efr(up);
1033 		return;
1034 	}
1035 
1036 	/*
1037 	 * Check for a National Semiconductor SuperIO chip.
1038 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1039 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1040 	 * switch back to bank 2, read it from EXCR1 again and check
1041 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1042 	 */
1043 	serial_out(up, UART_LCR, 0);
1044 	status1 = serial8250_in_MCR(up);
1045 	serial_out(up, UART_LCR, 0xE0);
1046 	status2 = serial_in(up, 0x02); /* EXCR1 */
1047 
1048 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1049 		serial_out(up, UART_LCR, 0);
1050 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1051 		serial_out(up, UART_LCR, 0xE0);
1052 		status2 = serial_in(up, 0x02); /* EXCR1 */
1053 		serial_out(up, UART_LCR, 0);
1054 		serial8250_out_MCR(up, status1);
1055 
1056 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1057 			unsigned short quot;
1058 
1059 			serial_out(up, UART_LCR, 0xE0);
1060 
1061 			quot = serial_dl_read(up);
1062 			quot <<= 3;
1063 
1064 			if (ns16550a_goto_highspeed(up))
1065 				serial_dl_write(up, quot);
1066 
1067 			serial_out(up, UART_LCR, 0);
1068 
1069 			up->port.uartclk = 921600*16;
1070 			up->port.type = PORT_NS16550A;
1071 			up->capabilities |= UART_NATSEMI;
1072 			return;
1073 		}
1074 	}
1075 
1076 	/*
1077 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1078 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1079 	 * Try setting it with and without DLAB set.  Cheap clones
1080 	 * set bit 5 without DLAB set.
1081 	 */
1082 	serial_out(up, UART_LCR, 0);
1083 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1084 	status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1085 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1086 
1087 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1088 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1089 	status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1090 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1091 
1092 	serial_out(up, UART_LCR, 0);
1093 
1094 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1095 
1096 	if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1097 	    status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
1098 		up->port.type = PORT_16750;
1099 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1100 		return;
1101 	}
1102 
1103 	/*
1104 	 * Try writing and reading the UART_IER_UUE bit (b6).
1105 	 * If it works, this is probably one of the Xscale platform's
1106 	 * internal UARTs.
1107 	 * We're going to explicitly set the UUE bit to 0 before
1108 	 * trying to write and read a 1 just to make sure it's not
1109 	 * already a 1 and maybe locked there before we even start.
1110 	 */
1111 	iersave = serial_in(up, UART_IER);
1112 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1113 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1114 		/*
1115 		 * OK it's in a known zero state, try writing and reading
1116 		 * without disturbing the current state of the other bits.
1117 		 */
1118 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1119 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1120 			/*
1121 			 * It's an Xscale.
1122 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1123 			 */
1124 			DEBUG_AUTOCONF("Xscale ");
1125 			up->port.type = PORT_XSCALE;
1126 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1127 			return;
1128 		}
1129 	} else {
1130 		/*
1131 		 * If we got here we couldn't force the IER_UUE bit to 0.
1132 		 * Log it and continue.
1133 		 */
1134 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1135 	}
1136 	serial_out(up, UART_IER, iersave);
1137 
1138 	/*
1139 	 * We distinguish between 16550A and U6 16550A by counting
1140 	 * how many bytes are in the FIFO.
1141 	 */
1142 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1143 		up->port.type = PORT_U6_16550A;
1144 		up->capabilities |= UART_CAP_AFE;
1145 	}
1146 }
1147 
1148 /*
1149  * This routine is called by rs_init() to initialize a specific serial
1150  * port.  It determines what type of UART chip this serial port is
1151  * using: 8250, 16450, 16550, 16550A.  The important question is
1152  * whether or not this UART is a 16550A or not, since this will
1153  * determine whether or not we can use its FIFO features or not.
1154  */
autoconfig(struct uart_8250_port * up)1155 static void autoconfig(struct uart_8250_port *up)
1156 {
1157 	unsigned char status1, scratch, scratch2, scratch3;
1158 	unsigned char save_lcr, save_mcr;
1159 	struct uart_port *port = &up->port;
1160 	unsigned long flags;
1161 	unsigned int old_capabilities;
1162 
1163 	if (!port->iobase && !port->mapbase && !port->membase)
1164 		return;
1165 
1166 	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1167 		       port->name, port->iobase, port->membase);
1168 
1169 	/*
1170 	 * We really do need global IRQs disabled here - we're going to
1171 	 * be frobbing the chips IRQ enable register to see if it exists.
1172 	 *
1173 	 * Synchronize UART_IER access against the console.
1174 	 */
1175 	spin_lock_irqsave(&port->lock, flags);
1176 
1177 	up->capabilities = 0;
1178 	up->bugs = 0;
1179 
1180 	if (!(port->flags & UPF_BUGGY_UART)) {
1181 		/*
1182 		 * Do a simple existence test first; if we fail this,
1183 		 * there's no point trying anything else.
1184 		 *
1185 		 * 0x80 is used as a nonsense port to prevent against
1186 		 * false positives due to ISA bus float.  The
1187 		 * assumption is that 0x80 is a non-existent port;
1188 		 * which should be safe since include/asm/io.h also
1189 		 * makes this assumption.
1190 		 *
1191 		 * Note: this is safe as long as MCR bit 4 is clear
1192 		 * and the device is in "PC" mode.
1193 		 */
1194 		scratch = serial_in(up, UART_IER);
1195 		serial_out(up, UART_IER, 0);
1196 #ifdef __i386__
1197 		outb(0xff, 0x080);
1198 #endif
1199 		/*
1200 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1201 		 * 16C754B) allow only to modify them if an EFR bit is set.
1202 		 */
1203 		scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1204 		serial_out(up, UART_IER, UART_IER_ALL_INTR);
1205 #ifdef __i386__
1206 		outb(0, 0x080);
1207 #endif
1208 		scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1209 		serial_out(up, UART_IER, scratch);
1210 		if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1211 			/*
1212 			 * We failed; there's nothing here
1213 			 */
1214 			spin_unlock_irqrestore(&port->lock, flags);
1215 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1216 				       scratch2, scratch3);
1217 			goto out;
1218 		}
1219 	}
1220 
1221 	save_mcr = serial8250_in_MCR(up);
1222 	save_lcr = serial_in(up, UART_LCR);
1223 
1224 	/*
1225 	 * Check to see if a UART is really there.  Certain broken
1226 	 * internal modems based on the Rockwell chipset fail this
1227 	 * test, because they apparently don't implement the loopback
1228 	 * test mode.  So this test is skipped on the COM 1 through
1229 	 * COM 4 ports.  This *should* be safe, since no board
1230 	 * manufacturer would be stupid enough to design a board
1231 	 * that conflicts with COM 1-4 --- we hope!
1232 	 */
1233 	if (!(port->flags & UPF_SKIP_TEST)) {
1234 		serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1235 		status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1236 		serial8250_out_MCR(up, save_mcr);
1237 		if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1238 			spin_unlock_irqrestore(&port->lock, flags);
1239 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1240 				       status1);
1241 			goto out;
1242 		}
1243 	}
1244 
1245 	/*
1246 	 * We're pretty sure there's a port here.  Lets find out what
1247 	 * type of port it is.  The IIR top two bits allows us to find
1248 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1249 	 * determines what we test for next.
1250 	 *
1251 	 * We also initialise the EFR (if any) to zero for later.  The
1252 	 * EFR occupies the same register location as the FCR and IIR.
1253 	 */
1254 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1255 	serial_out(up, UART_EFR, 0);
1256 	serial_out(up, UART_LCR, 0);
1257 
1258 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1259 
1260 	switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1261 	case UART_IIR_FIFO_ENABLED_8250:
1262 		autoconfig_8250(up);
1263 		break;
1264 	case UART_IIR_FIFO_ENABLED_16550:
1265 		port->type = PORT_16550;
1266 		break;
1267 	case UART_IIR_FIFO_ENABLED_16550A:
1268 		autoconfig_16550a(up);
1269 		break;
1270 	default:
1271 		port->type = PORT_UNKNOWN;
1272 		break;
1273 	}
1274 
1275 #ifdef CONFIG_SERIAL_8250_RSA
1276 	/*
1277 	 * Only probe for RSA ports if we got the region.
1278 	 */
1279 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1280 	    __enable_rsa(up))
1281 		port->type = PORT_RSA;
1282 #endif
1283 
1284 	serial_out(up, UART_LCR, save_lcr);
1285 
1286 	port->fifosize = uart_config[up->port.type].fifo_size;
1287 	old_capabilities = up->capabilities;
1288 	up->capabilities = uart_config[port->type].flags;
1289 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1290 
1291 	if (port->type == PORT_UNKNOWN)
1292 		goto out_unlock;
1293 
1294 	/*
1295 	 * Reset the UART.
1296 	 */
1297 #ifdef CONFIG_SERIAL_8250_RSA
1298 	if (port->type == PORT_RSA)
1299 		serial_out(up, UART_RSA_FRR, 0);
1300 #endif
1301 	serial8250_out_MCR(up, save_mcr);
1302 	serial8250_clear_fifos(up);
1303 	serial_in(up, UART_RX);
1304 	serial8250_clear_IER(up);
1305 
1306 out_unlock:
1307 	spin_unlock_irqrestore(&port->lock, flags);
1308 
1309 	/*
1310 	 * Check if the device is a Fintek F81216A
1311 	 */
1312 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1313 		fintek_8250_probe(up);
1314 
1315 	if (up->capabilities != old_capabilities) {
1316 		dev_warn(port->dev, "detected caps %08x should be %08x\n",
1317 			 old_capabilities, up->capabilities);
1318 	}
1319 out:
1320 	DEBUG_AUTOCONF("iir=%d ", scratch);
1321 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1322 }
1323 
autoconfig_irq(struct uart_8250_port * up)1324 static void autoconfig_irq(struct uart_8250_port *up)
1325 {
1326 	struct uart_port *port = &up->port;
1327 	unsigned char save_mcr, save_ier;
1328 	unsigned char save_ICP = 0;
1329 	unsigned int ICP = 0;
1330 	unsigned long irqs;
1331 	int irq;
1332 
1333 	if (port->flags & UPF_FOURPORT) {
1334 		ICP = (port->iobase & 0xfe0) | 0x1f;
1335 		save_ICP = inb_p(ICP);
1336 		outb_p(0x80, ICP);
1337 		inb_p(ICP);
1338 	}
1339 
1340 	if (uart_console(port))
1341 		console_lock();
1342 
1343 	/* forget possible initially masked and pending IRQ */
1344 	probe_irq_off(probe_irq_on());
1345 	save_mcr = serial8250_in_MCR(up);
1346 	/* Synchronize UART_IER access against the console. */
1347 	spin_lock_irq(&port->lock);
1348 	save_ier = serial_in(up, UART_IER);
1349 	spin_unlock_irq(&port->lock);
1350 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1351 
1352 	irqs = probe_irq_on();
1353 	serial8250_out_MCR(up, 0);
1354 	udelay(10);
1355 	if (port->flags & UPF_FOURPORT) {
1356 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1357 	} else {
1358 		serial8250_out_MCR(up,
1359 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1360 	}
1361 	/* Synchronize UART_IER access against the console. */
1362 	spin_lock_irq(&port->lock);
1363 	serial_out(up, UART_IER, UART_IER_ALL_INTR);
1364 	spin_unlock_irq(&port->lock);
1365 	serial_in(up, UART_LSR);
1366 	serial_in(up, UART_RX);
1367 	serial_in(up, UART_IIR);
1368 	serial_in(up, UART_MSR);
1369 	serial_out(up, UART_TX, 0xFF);
1370 	udelay(20);
1371 	irq = probe_irq_off(irqs);
1372 
1373 	serial8250_out_MCR(up, save_mcr);
1374 	/* Synchronize UART_IER access against the console. */
1375 	spin_lock_irq(&port->lock);
1376 	serial_out(up, UART_IER, save_ier);
1377 	spin_unlock_irq(&port->lock);
1378 
1379 	if (port->flags & UPF_FOURPORT)
1380 		outb_p(save_ICP, ICP);
1381 
1382 	if (uart_console(port))
1383 		console_unlock();
1384 
1385 	port->irq = (irq > 0) ? irq : 0;
1386 }
1387 
serial8250_stop_rx(struct uart_port * port)1388 static void serial8250_stop_rx(struct uart_port *port)
1389 {
1390 	struct uart_8250_port *up = up_to_u8250p(port);
1391 
1392 	/* Port locked to synchronize UART_IER access against the console. */
1393 	lockdep_assert_held_once(&port->lock);
1394 
1395 	serial8250_rpm_get(up);
1396 
1397 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1398 	up->port.read_status_mask &= ~UART_LSR_DR;
1399 	serial_port_out(port, UART_IER, up->ier);
1400 
1401 	serial8250_rpm_put(up);
1402 }
1403 
1404 /**
1405  * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1406  * @p: uart 8250 port
1407  *
1408  * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1409  */
serial8250_em485_stop_tx(struct uart_8250_port * p)1410 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1411 {
1412 	unsigned char mcr = serial8250_in_MCR(p);
1413 
1414 	/* Port locked to synchronize UART_IER access against the console. */
1415 	lockdep_assert_held_once(&p->port.lock);
1416 
1417 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1418 		mcr |= UART_MCR_RTS;
1419 	else
1420 		mcr &= ~UART_MCR_RTS;
1421 	serial8250_out_MCR(p, mcr);
1422 
1423 	/*
1424 	 * Empty the RX FIFO, we are not interested in anything
1425 	 * received during the half-duplex transmission.
1426 	 * Enable previously disabled RX interrupts.
1427 	 */
1428 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1429 		serial8250_clear_and_reinit_fifos(p);
1430 
1431 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1432 		serial_port_out(&p->port, UART_IER, p->ier);
1433 	}
1434 }
1435 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1436 
serial8250_em485_handle_stop_tx(struct hrtimer * t)1437 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1438 {
1439 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1440 			stop_tx_timer);
1441 	struct uart_8250_port *p = em485->port;
1442 	unsigned long flags;
1443 
1444 	serial8250_rpm_get(p);
1445 	spin_lock_irqsave(&p->port.lock, flags);
1446 	if (em485->active_timer == &em485->stop_tx_timer) {
1447 		p->rs485_stop_tx(p);
1448 		em485->active_timer = NULL;
1449 		em485->tx_stopped = true;
1450 	}
1451 	spin_unlock_irqrestore(&p->port.lock, flags);
1452 	serial8250_rpm_put(p);
1453 
1454 	return HRTIMER_NORESTART;
1455 }
1456 
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)1457 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1458 {
1459 	hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1460 }
1461 
__stop_tx_rs485(struct uart_8250_port * p,u64 stop_delay)1462 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1463 {
1464 	struct uart_8250_em485 *em485 = p->em485;
1465 
1466 	/* Port locked to synchronize UART_IER access against the console. */
1467 	lockdep_assert_held_once(&p->port.lock);
1468 
1469 	stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1470 
1471 	/*
1472 	 * rs485_stop_tx() is going to set RTS according to config
1473 	 * AND flush RX FIFO if required.
1474 	 */
1475 	if (stop_delay > 0) {
1476 		em485->active_timer = &em485->stop_tx_timer;
1477 		hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1478 	} else {
1479 		p->rs485_stop_tx(p);
1480 		em485->active_timer = NULL;
1481 		em485->tx_stopped = true;
1482 	}
1483 }
1484 
__stop_tx(struct uart_8250_port * p)1485 static inline void __stop_tx(struct uart_8250_port *p)
1486 {
1487 	struct uart_8250_em485 *em485 = p->em485;
1488 
1489 	if (em485) {
1490 		u16 lsr = serial_lsr_in(p);
1491 		u64 stop_delay = 0;
1492 
1493 		if (!(lsr & UART_LSR_THRE))
1494 			return;
1495 		/*
1496 		 * To provide required timing and allow FIFO transfer,
1497 		 * __stop_tx_rs485() must be called only when both FIFO and
1498 		 * shift register are empty. The device driver should either
1499 		 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1500 		 * enlarge stop_tx_timer by the tx time of one frame to cover
1501 		 * for emptying of the shift register.
1502 		 */
1503 		if (!(lsr & UART_LSR_TEMT)) {
1504 			if (!(p->capabilities & UART_CAP_NOTEMT))
1505 				return;
1506 			/*
1507 			 * RTS might get deasserted too early with the normal
1508 			 * frame timing formula. It seems to suggest THRE might
1509 			 * get asserted already during tx of the stop bit
1510 			 * rather than after it is fully sent.
1511 			 * Roughly estimate 1 extra bit here with / 7.
1512 			 */
1513 			stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1514 		}
1515 
1516 		__stop_tx_rs485(p, stop_delay);
1517 	}
1518 
1519 	if (serial8250_clear_THRI(p))
1520 		serial8250_rpm_put_tx(p);
1521 }
1522 
serial8250_stop_tx(struct uart_port * port)1523 static void serial8250_stop_tx(struct uart_port *port)
1524 {
1525 	struct uart_8250_port *up = up_to_u8250p(port);
1526 
1527 	serial8250_rpm_get(up);
1528 	__stop_tx(up);
1529 
1530 	/*
1531 	 * We really want to stop the transmitter from sending.
1532 	 */
1533 	if (port->type == PORT_16C950) {
1534 		up->acr |= UART_ACR_TXDIS;
1535 		serial_icr_write(up, UART_ACR, up->acr);
1536 	}
1537 	serial8250_rpm_put(up);
1538 }
1539 
__start_tx(struct uart_port * port)1540 static inline void __start_tx(struct uart_port *port)
1541 {
1542 	struct uart_8250_port *up = up_to_u8250p(port);
1543 
1544 	if (up->dma && !up->dma->tx_dma(up))
1545 		return;
1546 
1547 	if (serial8250_set_THRI(up)) {
1548 		if (up->bugs & UART_BUG_TXEN) {
1549 			u16 lsr = serial_lsr_in(up);
1550 
1551 			if (lsr & UART_LSR_THRE)
1552 				serial8250_tx_chars(up);
1553 		}
1554 	}
1555 
1556 	/*
1557 	 * Re-enable the transmitter if we disabled it.
1558 	 */
1559 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1560 		up->acr &= ~UART_ACR_TXDIS;
1561 		serial_icr_write(up, UART_ACR, up->acr);
1562 	}
1563 }
1564 
1565 /**
1566  * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1567  * @up: uart 8250 port
1568  *
1569  * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1570  * Assumes that setting the RTS bit in the MCR register means RTS is high.
1571  * (Some chips use inverse semantics.)  Further assumes that reception is
1572  * stoppable by disabling the UART_IER_RDI interrupt.  (Some chips set the
1573  * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1574  */
serial8250_em485_start_tx(struct uart_8250_port * up)1575 void serial8250_em485_start_tx(struct uart_8250_port *up)
1576 {
1577 	unsigned char mcr = serial8250_in_MCR(up);
1578 
1579 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1580 		serial8250_stop_rx(&up->port);
1581 
1582 	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1583 		mcr |= UART_MCR_RTS;
1584 	else
1585 		mcr &= ~UART_MCR_RTS;
1586 	serial8250_out_MCR(up, mcr);
1587 }
1588 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1589 
1590 /* Returns false, if start_tx_timer was setup to defer TX start */
start_tx_rs485(struct uart_port * port)1591 static bool start_tx_rs485(struct uart_port *port)
1592 {
1593 	struct uart_8250_port *up = up_to_u8250p(port);
1594 	struct uart_8250_em485 *em485 = up->em485;
1595 
1596 	/*
1597 	 * While serial8250_em485_handle_stop_tx() is a noop if
1598 	 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1599 	 * the timer is still armed and triggers only after the current bunch of
1600 	 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1601 	 * So cancel the timer. There is still a theoretical race condition if
1602 	 * the timer is already running and only comes around to check for
1603 	 * em485->active_timer when &em485->stop_tx_timer is armed again.
1604 	 */
1605 	if (em485->active_timer == &em485->stop_tx_timer)
1606 		hrtimer_try_to_cancel(&em485->stop_tx_timer);
1607 
1608 	em485->active_timer = NULL;
1609 
1610 	if (em485->tx_stopped) {
1611 		em485->tx_stopped = false;
1612 
1613 		up->rs485_start_tx(up);
1614 
1615 		if (up->port.rs485.delay_rts_before_send > 0) {
1616 			em485->active_timer = &em485->start_tx_timer;
1617 			start_hrtimer_ms(&em485->start_tx_timer,
1618 					 up->port.rs485.delay_rts_before_send);
1619 			return false;
1620 		}
1621 	}
1622 
1623 	return true;
1624 }
1625 
serial8250_em485_handle_start_tx(struct hrtimer * t)1626 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1627 {
1628 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1629 			start_tx_timer);
1630 	struct uart_8250_port *p = em485->port;
1631 	unsigned long flags;
1632 
1633 	spin_lock_irqsave(&p->port.lock, flags);
1634 	if (em485->active_timer == &em485->start_tx_timer) {
1635 		__start_tx(&p->port);
1636 		em485->active_timer = NULL;
1637 	}
1638 	spin_unlock_irqrestore(&p->port.lock, flags);
1639 
1640 	return HRTIMER_NORESTART;
1641 }
1642 
serial8250_start_tx(struct uart_port * port)1643 static void serial8250_start_tx(struct uart_port *port)
1644 {
1645 	struct uart_8250_port *up = up_to_u8250p(port);
1646 	struct uart_8250_em485 *em485 = up->em485;
1647 
1648 	/* Port locked to synchronize UART_IER access against the console. */
1649 	lockdep_assert_held_once(&port->lock);
1650 
1651 	if (!port->x_char && uart_circ_empty(&port->state->xmit))
1652 		return;
1653 
1654 	serial8250_rpm_get_tx(up);
1655 
1656 	if (em485) {
1657 		if ((em485->active_timer == &em485->start_tx_timer) ||
1658 		    !start_tx_rs485(port))
1659 			return;
1660 	}
1661 	__start_tx(port);
1662 }
1663 
serial8250_throttle(struct uart_port * port)1664 static void serial8250_throttle(struct uart_port *port)
1665 {
1666 	port->throttle(port);
1667 }
1668 
serial8250_unthrottle(struct uart_port * port)1669 static void serial8250_unthrottle(struct uart_port *port)
1670 {
1671 	port->unthrottle(port);
1672 }
1673 
serial8250_disable_ms(struct uart_port * port)1674 static void serial8250_disable_ms(struct uart_port *port)
1675 {
1676 	struct uart_8250_port *up = up_to_u8250p(port);
1677 
1678 	/* Port locked to synchronize UART_IER access against the console. */
1679 	lockdep_assert_held_once(&port->lock);
1680 
1681 	/* no MSR capabilities */
1682 	if (up->bugs & UART_BUG_NOMSR)
1683 		return;
1684 
1685 	mctrl_gpio_disable_ms(up->gpios);
1686 
1687 	up->ier &= ~UART_IER_MSI;
1688 	serial_port_out(port, UART_IER, up->ier);
1689 }
1690 
serial8250_enable_ms(struct uart_port * port)1691 static void serial8250_enable_ms(struct uart_port *port)
1692 {
1693 	struct uart_8250_port *up = up_to_u8250p(port);
1694 
1695 	/* Port locked to synchronize UART_IER access against the console. */
1696 	lockdep_assert_held_once(&port->lock);
1697 
1698 	/* no MSR capabilities */
1699 	if (up->bugs & UART_BUG_NOMSR)
1700 		return;
1701 
1702 	mctrl_gpio_enable_ms(up->gpios);
1703 
1704 	up->ier |= UART_IER_MSI;
1705 
1706 	serial8250_rpm_get(up);
1707 	serial_port_out(port, UART_IER, up->ier);
1708 	serial8250_rpm_put(up);
1709 }
1710 
serial8250_read_char(struct uart_8250_port * up,u16 lsr)1711 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1712 {
1713 	struct uart_port *port = &up->port;
1714 	u8 ch, flag = TTY_NORMAL;
1715 
1716 	if (likely(lsr & UART_LSR_DR))
1717 		ch = serial_in(up, UART_RX);
1718 	else
1719 		/*
1720 		 * Intel 82571 has a Serial Over Lan device that will
1721 		 * set UART_LSR_BI without setting UART_LSR_DR when
1722 		 * it receives a break. To avoid reading from the
1723 		 * receive buffer without UART_LSR_DR bit set, we
1724 		 * just force the read character to be 0
1725 		 */
1726 		ch = 0;
1727 
1728 	port->icount.rx++;
1729 
1730 	lsr |= up->lsr_saved_flags;
1731 	up->lsr_saved_flags = 0;
1732 
1733 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1734 		if (lsr & UART_LSR_BI) {
1735 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1736 			port->icount.brk++;
1737 			/*
1738 			 * We do the SysRQ and SAK checking
1739 			 * here because otherwise the break
1740 			 * may get masked by ignore_status_mask
1741 			 * or read_status_mask.
1742 			 */
1743 			if (uart_handle_break(port))
1744 				return;
1745 		} else if (lsr & UART_LSR_PE)
1746 			port->icount.parity++;
1747 		else if (lsr & UART_LSR_FE)
1748 			port->icount.frame++;
1749 		if (lsr & UART_LSR_OE)
1750 			port->icount.overrun++;
1751 
1752 		/*
1753 		 * Mask off conditions which should be ignored.
1754 		 */
1755 		lsr &= port->read_status_mask;
1756 
1757 		if (lsr & UART_LSR_BI) {
1758 			dev_dbg(port->dev, "handling break\n");
1759 			flag = TTY_BREAK;
1760 		} else if (lsr & UART_LSR_PE)
1761 			flag = TTY_PARITY;
1762 		else if (lsr & UART_LSR_FE)
1763 			flag = TTY_FRAME;
1764 	}
1765 	if (uart_prepare_sysrq_char(port, ch))
1766 		return;
1767 
1768 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1769 }
1770 EXPORT_SYMBOL_GPL(serial8250_read_char);
1771 
1772 /*
1773  * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1774  *
1775  * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1776  * (such as THRE) because the LSR value might come from an already consumed
1777  * character.
1778  */
serial8250_rx_chars(struct uart_8250_port * up,u16 lsr)1779 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1780 {
1781 	struct uart_port *port = &up->port;
1782 	int max_count = 256;
1783 
1784 	do {
1785 		serial8250_read_char(up, lsr);
1786 		if (--max_count == 0)
1787 			break;
1788 		lsr = serial_in(up, UART_LSR);
1789 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1790 
1791 	tty_flip_buffer_push(&port->state->port);
1792 	return lsr;
1793 }
1794 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1795 
serial8250_tx_chars(struct uart_8250_port * up)1796 void serial8250_tx_chars(struct uart_8250_port *up)
1797 {
1798 	struct uart_port *port = &up->port;
1799 	struct circ_buf *xmit = &port->state->xmit;
1800 	int count;
1801 
1802 	if (port->x_char) {
1803 		uart_xchar_out(port, UART_TX);
1804 		return;
1805 	}
1806 	if (uart_tx_stopped(port)) {
1807 		serial8250_stop_tx(port);
1808 		return;
1809 	}
1810 	if (uart_circ_empty(xmit)) {
1811 		__stop_tx(up);
1812 		return;
1813 	}
1814 
1815 	count = up->tx_loadsz;
1816 	do {
1817 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1818 		if (up->bugs & UART_BUG_TXRACE) {
1819 			/*
1820 			 * The Aspeed BMC virtual UARTs have a bug where data
1821 			 * may get stuck in the BMC's Tx FIFO from bursts of
1822 			 * writes on the APB interface.
1823 			 *
1824 			 * Delay back-to-back writes by a read cycle to avoid
1825 			 * stalling the VUART. Read a register that won't have
1826 			 * side-effects and discard the result.
1827 			 */
1828 			serial_in(up, UART_SCR);
1829 		}
1830 		uart_xmit_advance(port, 1);
1831 		if (uart_circ_empty(xmit))
1832 			break;
1833 		if ((up->capabilities & UART_CAP_HFIFO) &&
1834 		    !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1835 			break;
1836 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1837 		if ((up->capabilities & UART_CAP_MINI) &&
1838 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1839 			break;
1840 	} while (--count > 0);
1841 
1842 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1843 		uart_write_wakeup(port);
1844 
1845 	/*
1846 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1847 	 * HW can go idle. So we get here once again with empty FIFO and disable
1848 	 * the interrupt and RPM in __stop_tx()
1849 	 */
1850 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1851 		__stop_tx(up);
1852 }
1853 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1854 
1855 /* Caller holds uart port lock */
serial8250_modem_status(struct uart_8250_port * up)1856 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1857 {
1858 	struct uart_port *port = &up->port;
1859 	unsigned int status = serial_in(up, UART_MSR);
1860 
1861 	status |= up->msr_saved_flags;
1862 	up->msr_saved_flags = 0;
1863 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1864 	    port->state != NULL) {
1865 		if (status & UART_MSR_TERI)
1866 			port->icount.rng++;
1867 		if (status & UART_MSR_DDSR)
1868 			port->icount.dsr++;
1869 		if (status & UART_MSR_DDCD)
1870 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1871 		if (status & UART_MSR_DCTS)
1872 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1873 
1874 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1875 	}
1876 
1877 	return status;
1878 }
1879 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1880 
handle_rx_dma(struct uart_8250_port * up,unsigned int iir)1881 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1882 {
1883 	switch (iir & 0x3f) {
1884 	case UART_IIR_THRI:
1885 		/*
1886 		 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1887 		 * because it's impossible to do an informed decision about
1888 		 * that with IIR_THRI.
1889 		 *
1890 		 * This also fixes one known DMA Rx corruption issue where
1891 		 * DR is asserted but DMA Rx only gets a corrupted zero byte
1892 		 * (too early DR?).
1893 		 */
1894 		return false;
1895 	case UART_IIR_RDI:
1896 		if (!up->dma->rx_running)
1897 			break;
1898 		fallthrough;
1899 	case UART_IIR_RLSI:
1900 	case UART_IIR_RX_TIMEOUT:
1901 		serial8250_rx_dma_flush(up);
1902 		return true;
1903 	}
1904 	return up->dma->rx_dma(up);
1905 }
1906 
1907 /*
1908  * This handles the interrupt from one port.
1909  */
serial8250_handle_irq(struct uart_port * port,unsigned int iir)1910 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1911 {
1912 	struct uart_8250_port *up = up_to_u8250p(port);
1913 	struct tty_port *tport = &port->state->port;
1914 	bool skip_rx = false;
1915 	unsigned long flags;
1916 	u16 status;
1917 
1918 	if (iir & UART_IIR_NO_INT)
1919 		return 0;
1920 
1921 	spin_lock_irqsave(&port->lock, flags);
1922 
1923 	status = serial_lsr_in(up);
1924 
1925 	/*
1926 	 * If port is stopped and there are no error conditions in the
1927 	 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1928 	 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1929 	 * control when FIFO occupancy reaches preset threshold, thus
1930 	 * halting RX. This only works when auto HW flow control is
1931 	 * available.
1932 	 */
1933 	if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1934 	    (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1935 	    !(port->read_status_mask & UART_LSR_DR))
1936 		skip_rx = true;
1937 
1938 	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1939 		struct irq_data *d;
1940 
1941 		d = irq_get_irq_data(port->irq);
1942 		if (d && irqd_is_wakeup_set(d))
1943 			pm_wakeup_event(tport->tty->dev, 0);
1944 		if (!up->dma || handle_rx_dma(up, iir))
1945 			status = serial8250_rx_chars(up, status);
1946 	}
1947 	serial8250_modem_status(up);
1948 	if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1949 		if (!up->dma || up->dma->tx_err)
1950 			serial8250_tx_chars(up);
1951 		else if (!up->dma->tx_running)
1952 			__stop_tx(up);
1953 	}
1954 
1955 	uart_unlock_and_check_sysrq_irqrestore(port, flags);
1956 
1957 	return 1;
1958 }
1959 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1960 
serial8250_default_handle_irq(struct uart_port * port)1961 static int serial8250_default_handle_irq(struct uart_port *port)
1962 {
1963 	struct uart_8250_port *up = up_to_u8250p(port);
1964 	unsigned int iir;
1965 	int ret;
1966 
1967 	serial8250_rpm_get(up);
1968 
1969 	iir = serial_port_in(port, UART_IIR);
1970 	ret = serial8250_handle_irq(port, iir);
1971 
1972 	serial8250_rpm_put(up);
1973 	return ret;
1974 }
1975 
1976 /*
1977  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1978  * have a programmable TX threshold that triggers the THRE interrupt in
1979  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1980  * has space available. Load it up with tx_loadsz bytes.
1981  */
serial8250_tx_threshold_handle_irq(struct uart_port * port)1982 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1983 {
1984 	unsigned long flags;
1985 	unsigned int iir = serial_port_in(port, UART_IIR);
1986 
1987 	/* TX Threshold IRQ triggered so load up FIFO */
1988 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1989 		struct uart_8250_port *up = up_to_u8250p(port);
1990 
1991 		spin_lock_irqsave(&port->lock, flags);
1992 		serial8250_tx_chars(up);
1993 		spin_unlock_irqrestore(&port->lock, flags);
1994 	}
1995 
1996 	iir = serial_port_in(port, UART_IIR);
1997 	return serial8250_handle_irq(port, iir);
1998 }
1999 
serial8250_tx_empty(struct uart_port * port)2000 static unsigned int serial8250_tx_empty(struct uart_port *port)
2001 {
2002 	struct uart_8250_port *up = up_to_u8250p(port);
2003 	unsigned int result = 0;
2004 	unsigned long flags;
2005 
2006 	serial8250_rpm_get(up);
2007 
2008 	spin_lock_irqsave(&port->lock, flags);
2009 	if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
2010 		result = TIOCSER_TEMT;
2011 	spin_unlock_irqrestore(&port->lock, flags);
2012 
2013 	serial8250_rpm_put(up);
2014 
2015 	return result;
2016 }
2017 
serial8250_do_get_mctrl(struct uart_port * port)2018 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2019 {
2020 	struct uart_8250_port *up = up_to_u8250p(port);
2021 	unsigned int status;
2022 	unsigned int val;
2023 
2024 	serial8250_rpm_get(up);
2025 	status = serial8250_modem_status(up);
2026 	serial8250_rpm_put(up);
2027 
2028 	val = serial8250_MSR_to_TIOCM(status);
2029 	if (up->gpios)
2030 		return mctrl_gpio_get(up->gpios, &val);
2031 
2032 	return val;
2033 }
2034 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2035 
serial8250_get_mctrl(struct uart_port * port)2036 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2037 {
2038 	if (port->get_mctrl)
2039 		return port->get_mctrl(port);
2040 	return serial8250_do_get_mctrl(port);
2041 }
2042 
serial8250_do_set_mctrl(struct uart_port * port,unsigned int mctrl)2043 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2044 {
2045 	struct uart_8250_port *up = up_to_u8250p(port);
2046 	unsigned char mcr;
2047 
2048 	mcr = serial8250_TIOCM_to_MCR(mctrl);
2049 
2050 	mcr |= up->mcr;
2051 
2052 	serial8250_out_MCR(up, mcr);
2053 }
2054 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2055 
serial8250_set_mctrl(struct uart_port * port,unsigned int mctrl)2056 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2057 {
2058 	if (port->rs485.flags & SER_RS485_ENABLED)
2059 		return;
2060 
2061 	if (port->set_mctrl)
2062 		port->set_mctrl(port, mctrl);
2063 	else
2064 		serial8250_do_set_mctrl(port, mctrl);
2065 }
2066 
serial8250_break_ctl(struct uart_port * port,int break_state)2067 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2068 {
2069 	struct uart_8250_port *up = up_to_u8250p(port);
2070 	unsigned long flags;
2071 
2072 	serial8250_rpm_get(up);
2073 	spin_lock_irqsave(&port->lock, flags);
2074 	if (break_state == -1)
2075 		up->lcr |= UART_LCR_SBC;
2076 	else
2077 		up->lcr &= ~UART_LCR_SBC;
2078 	serial_port_out(port, UART_LCR, up->lcr);
2079 	spin_unlock_irqrestore(&port->lock, flags);
2080 	serial8250_rpm_put(up);
2081 }
2082 
wait_for_lsr(struct uart_8250_port * up,int bits)2083 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2084 {
2085 	unsigned int status, tmout = 10000;
2086 
2087 	/* Wait up to 10ms for the character(s) to be sent. */
2088 	for (;;) {
2089 		status = serial_lsr_in(up);
2090 
2091 		if ((status & bits) == bits)
2092 			break;
2093 		if (--tmout == 0)
2094 			break;
2095 		udelay(1);
2096 		touch_nmi_watchdog();
2097 	}
2098 }
2099 
2100 /*
2101  *	Wait for transmitter & holding register to empty
2102  */
wait_for_xmitr(struct uart_8250_port * up,int bits)2103 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2104 {
2105 	unsigned int tmout;
2106 
2107 	wait_for_lsr(up, bits);
2108 
2109 	/* Wait up to 1s for flow control if necessary */
2110 	if (up->port.flags & UPF_CONS_FLOW) {
2111 		for (tmout = 1000000; tmout; tmout--) {
2112 			unsigned int msr = serial_in(up, UART_MSR);
2113 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2114 			if (msr & UART_MSR_CTS)
2115 				break;
2116 			udelay(1);
2117 			touch_nmi_watchdog();
2118 		}
2119 	}
2120 }
2121 
2122 #ifdef CONFIG_CONSOLE_POLL
2123 /*
2124  * Console polling routines for writing and reading from the uart while
2125  * in an interrupt or debug context.
2126  */
2127 
serial8250_get_poll_char(struct uart_port * port)2128 static int serial8250_get_poll_char(struct uart_port *port)
2129 {
2130 	struct uart_8250_port *up = up_to_u8250p(port);
2131 	int status;
2132 	u16 lsr;
2133 
2134 	serial8250_rpm_get(up);
2135 
2136 	lsr = serial_port_in(port, UART_LSR);
2137 
2138 	if (!(lsr & UART_LSR_DR)) {
2139 		status = NO_POLL_CHAR;
2140 		goto out;
2141 	}
2142 
2143 	status = serial_port_in(port, UART_RX);
2144 out:
2145 	serial8250_rpm_put(up);
2146 	return status;
2147 }
2148 
2149 
serial8250_put_poll_char(struct uart_port * port,unsigned char c)2150 static void serial8250_put_poll_char(struct uart_port *port,
2151 			 unsigned char c)
2152 {
2153 	unsigned int ier;
2154 	struct uart_8250_port *up = up_to_u8250p(port);
2155 
2156 	/*
2157 	 * Normally the port is locked to synchronize UART_IER access
2158 	 * against the console. However, this function is only used by
2159 	 * KDB/KGDB, where it may not be possible to acquire the port
2160 	 * lock because all other CPUs are quiesced. The quiescence
2161 	 * should allow safe lockless usage here.
2162 	 */
2163 
2164 	serial8250_rpm_get(up);
2165 	/*
2166 	 *	First save the IER then disable the interrupts
2167 	 */
2168 	ier = serial_port_in(port, UART_IER);
2169 	serial8250_clear_IER(up);
2170 
2171 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2172 	/*
2173 	 *	Send the character out.
2174 	 */
2175 	serial_port_out(port, UART_TX, c);
2176 
2177 	/*
2178 	 *	Finally, wait for transmitter to become empty
2179 	 *	and restore the IER
2180 	 */
2181 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2182 	serial_port_out(port, UART_IER, ier);
2183 	serial8250_rpm_put(up);
2184 }
2185 
2186 #endif /* CONFIG_CONSOLE_POLL */
2187 
serial8250_do_startup(struct uart_port * port)2188 int serial8250_do_startup(struct uart_port *port)
2189 {
2190 	struct uart_8250_port *up = up_to_u8250p(port);
2191 	unsigned long flags;
2192 	unsigned char iir;
2193 	int retval;
2194 	u16 lsr;
2195 
2196 	if (!port->fifosize)
2197 		port->fifosize = uart_config[port->type].fifo_size;
2198 	if (!up->tx_loadsz)
2199 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2200 	if (!up->capabilities)
2201 		up->capabilities = uart_config[port->type].flags;
2202 	up->mcr = 0;
2203 
2204 	if (port->iotype != up->cur_iotype)
2205 		set_io_from_upio(port);
2206 
2207 	serial8250_rpm_get(up);
2208 	if (port->type == PORT_16C950) {
2209 		/*
2210 		 * Wake up and initialize UART
2211 		 *
2212 		 * Synchronize UART_IER access against the console.
2213 		 */
2214 		spin_lock_irqsave(&port->lock, flags);
2215 		up->acr = 0;
2216 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2217 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2218 		serial_port_out(port, UART_IER, 0);
2219 		serial_port_out(port, UART_LCR, 0);
2220 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2221 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2222 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2223 		serial_port_out(port, UART_LCR, 0);
2224 		spin_unlock_irqrestore(&port->lock, flags);
2225 	}
2226 
2227 	if (port->type == PORT_DA830) {
2228 		/*
2229 		 * Reset the port
2230 		 *
2231 		 * Synchronize UART_IER access against the console.
2232 		 */
2233 		spin_lock_irqsave(&port->lock, flags);
2234 		serial_port_out(port, UART_IER, 0);
2235 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2236 		spin_unlock_irqrestore(&port->lock, flags);
2237 		mdelay(10);
2238 
2239 		/* Enable Tx, Rx and free run mode */
2240 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2241 				UART_DA830_PWREMU_MGMT_UTRST |
2242 				UART_DA830_PWREMU_MGMT_URRST |
2243 				UART_DA830_PWREMU_MGMT_FREE);
2244 	}
2245 
2246 	if (port->type == PORT_NPCM) {
2247 		/*
2248 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2249 		 * register). Enable it, and set TIOC (timeout interrupt
2250 		 * comparator) to be 0x20 for correct operation.
2251 		 */
2252 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2253 	}
2254 
2255 #ifdef CONFIG_SERIAL_8250_RSA
2256 	/*
2257 	 * If this is an RSA port, see if we can kick it up to the
2258 	 * higher speed clock.
2259 	 */
2260 	enable_rsa(up);
2261 #endif
2262 
2263 	/*
2264 	 * Clear the FIFO buffers and disable them.
2265 	 * (they will be reenabled in set_termios())
2266 	 */
2267 	serial8250_clear_fifos(up);
2268 
2269 	/*
2270 	 * Clear the interrupt registers.
2271 	 */
2272 	serial_port_in(port, UART_LSR);
2273 	serial_port_in(port, UART_RX);
2274 	serial_port_in(port, UART_IIR);
2275 	serial_port_in(port, UART_MSR);
2276 
2277 	/*
2278 	 * At this point, there's no way the LSR could still be 0xff;
2279 	 * if it is, then bail out, because there's likely no UART
2280 	 * here.
2281 	 */
2282 	if (!(port->flags & UPF_BUGGY_UART) &&
2283 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2284 		dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2285 		retval = -ENODEV;
2286 		goto out;
2287 	}
2288 
2289 	/*
2290 	 * For a XR16C850, we need to set the trigger levels
2291 	 */
2292 	if (port->type == PORT_16850) {
2293 		unsigned char fctr;
2294 
2295 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2296 
2297 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2298 		serial_port_out(port, UART_FCTR,
2299 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2300 		serial_port_out(port, UART_TRG, UART_TRG_96);
2301 		serial_port_out(port, UART_FCTR,
2302 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2303 		serial_port_out(port, UART_TRG, UART_TRG_96);
2304 
2305 		serial_port_out(port, UART_LCR, 0);
2306 	}
2307 
2308 	/*
2309 	 * For the Altera 16550 variants, set TX threshold trigger level.
2310 	 */
2311 	if (((port->type == PORT_ALTR_16550_F32) ||
2312 	     (port->type == PORT_ALTR_16550_F64) ||
2313 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2314 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2315 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2316 			dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2317 		} else {
2318 			serial_port_out(port, UART_ALTR_AFR,
2319 					UART_ALTR_EN_TXFIFO_LW);
2320 			serial_port_out(port, UART_ALTR_TX_LOW,
2321 					port->fifosize - up->tx_loadsz);
2322 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2323 		}
2324 	}
2325 
2326 	/* Check if we need to have shared IRQs */
2327 	if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2328 		up->port.irqflags |= IRQF_SHARED;
2329 
2330 	retval = up->ops->setup_irq(up);
2331 	if (retval)
2332 		goto out;
2333 
2334 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2335 		unsigned char iir1;
2336 
2337 		if (port->irqflags & IRQF_SHARED)
2338 			disable_irq_nosync(port->irq);
2339 
2340 		/*
2341 		 * Test for UARTs that do not reassert THRE when the
2342 		 * transmitter is idle and the interrupt has already
2343 		 * been cleared.  Real 16550s should always reassert
2344 		 * this interrupt whenever the transmitter is idle and
2345 		 * the interrupt is enabled.  Delays are necessary to
2346 		 * allow register changes to become visible.
2347 		 *
2348 		 * Synchronize UART_IER access against the console.
2349 		 */
2350 		spin_lock_irqsave(&port->lock, flags);
2351 
2352 		wait_for_xmitr(up, UART_LSR_THRE);
2353 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2354 		udelay(1); /* allow THRE to set */
2355 		iir1 = serial_port_in(port, UART_IIR);
2356 		serial_port_out(port, UART_IER, 0);
2357 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2358 		udelay(1); /* allow a working UART time to re-assert THRE */
2359 		iir = serial_port_in(port, UART_IIR);
2360 		serial_port_out(port, UART_IER, 0);
2361 
2362 		spin_unlock_irqrestore(&port->lock, flags);
2363 
2364 		if (port->irqflags & IRQF_SHARED)
2365 			enable_irq(port->irq);
2366 
2367 		/*
2368 		 * If the interrupt is not reasserted, or we otherwise
2369 		 * don't trust the iir, setup a timer to kick the UART
2370 		 * on a regular basis.
2371 		 */
2372 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2373 		    up->port.flags & UPF_BUG_THRE) {
2374 			up->bugs |= UART_BUG_THRE;
2375 		}
2376 	}
2377 
2378 	up->ops->setup_timer(up);
2379 
2380 	/*
2381 	 * Now, initialize the UART
2382 	 */
2383 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2384 
2385 	spin_lock_irqsave(&port->lock, flags);
2386 	if (up->port.flags & UPF_FOURPORT) {
2387 		if (!up->port.irq)
2388 			up->port.mctrl |= TIOCM_OUT1;
2389 	} else
2390 		/*
2391 		 * Most PC uarts need OUT2 raised to enable interrupts.
2392 		 */
2393 		if (port->irq)
2394 			up->port.mctrl |= TIOCM_OUT2;
2395 
2396 	serial8250_set_mctrl(port, port->mctrl);
2397 
2398 	/*
2399 	 * Serial over Lan (SoL) hack:
2400 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2401 	 * used for Serial Over Lan.  Those chips take a longer time than a
2402 	 * normal serial device to signalize that a transmission data was
2403 	 * queued. Due to that, the above test generally fails. One solution
2404 	 * would be to delay the reading of iir. However, this is not
2405 	 * reliable, since the timeout is variable. So, let's just don't
2406 	 * test if we receive TX irq.  This way, we'll never enable
2407 	 * UART_BUG_TXEN.
2408 	 */
2409 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2410 		goto dont_test_tx_en;
2411 
2412 	/*
2413 	 * Do a quick test to see if we receive an interrupt when we enable
2414 	 * the TX irq.
2415 	 */
2416 	serial_port_out(port, UART_IER, UART_IER_THRI);
2417 	lsr = serial_port_in(port, UART_LSR);
2418 	iir = serial_port_in(port, UART_IIR);
2419 	serial_port_out(port, UART_IER, 0);
2420 
2421 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2422 		if (!(up->bugs & UART_BUG_TXEN)) {
2423 			up->bugs |= UART_BUG_TXEN;
2424 			dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2425 		}
2426 	} else {
2427 		up->bugs &= ~UART_BUG_TXEN;
2428 	}
2429 
2430 dont_test_tx_en:
2431 	spin_unlock_irqrestore(&port->lock, flags);
2432 
2433 	/*
2434 	 * Clear the interrupt registers again for luck, and clear the
2435 	 * saved flags to avoid getting false values from polling
2436 	 * routines or the previous session.
2437 	 */
2438 	serial_port_in(port, UART_LSR);
2439 	serial_port_in(port, UART_RX);
2440 	serial_port_in(port, UART_IIR);
2441 	serial_port_in(port, UART_MSR);
2442 	up->lsr_saved_flags = 0;
2443 	up->msr_saved_flags = 0;
2444 
2445 	/*
2446 	 * Request DMA channels for both RX and TX.
2447 	 */
2448 	if (up->dma) {
2449 		const char *msg = NULL;
2450 
2451 		if (uart_console(port))
2452 			msg = "forbid DMA for kernel console";
2453 		else if (serial8250_request_dma(up))
2454 			msg = "failed to request DMA";
2455 		if (msg) {
2456 			dev_warn_ratelimited(port->dev, "%s\n", msg);
2457 			up->dma = NULL;
2458 		}
2459 	}
2460 
2461 	/*
2462 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2463 	 * enable until after the FIFOs are enabled; otherwise, an already-
2464 	 * active sender can swamp the interrupt handler with "too much work".
2465 	 */
2466 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2467 
2468 	if (port->flags & UPF_FOURPORT) {
2469 		unsigned int icp;
2470 		/*
2471 		 * Enable interrupts on the AST Fourport board
2472 		 */
2473 		icp = (port->iobase & 0xfe0) | 0x01f;
2474 		outb_p(0x80, icp);
2475 		inb_p(icp);
2476 	}
2477 	retval = 0;
2478 out:
2479 	serial8250_rpm_put(up);
2480 	return retval;
2481 }
2482 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2483 
serial8250_startup(struct uart_port * port)2484 static int serial8250_startup(struct uart_port *port)
2485 {
2486 	if (port->startup)
2487 		return port->startup(port);
2488 	return serial8250_do_startup(port);
2489 }
2490 
serial8250_do_shutdown(struct uart_port * port)2491 void serial8250_do_shutdown(struct uart_port *port)
2492 {
2493 	struct uart_8250_port *up = up_to_u8250p(port);
2494 	unsigned long flags;
2495 
2496 	serial8250_rpm_get(up);
2497 	/*
2498 	 * Disable interrupts from this port
2499 	 *
2500 	 * Synchronize UART_IER access against the console.
2501 	 */
2502 	spin_lock_irqsave(&port->lock, flags);
2503 	up->ier = 0;
2504 	serial_port_out(port, UART_IER, 0);
2505 	spin_unlock_irqrestore(&port->lock, flags);
2506 
2507 	synchronize_irq(port->irq);
2508 
2509 	if (up->dma)
2510 		serial8250_release_dma(up);
2511 
2512 	spin_lock_irqsave(&port->lock, flags);
2513 	if (port->flags & UPF_FOURPORT) {
2514 		/* reset interrupts on the AST Fourport board */
2515 		inb((port->iobase & 0xfe0) | 0x1f);
2516 		port->mctrl |= TIOCM_OUT1;
2517 	} else
2518 		port->mctrl &= ~TIOCM_OUT2;
2519 
2520 	serial8250_set_mctrl(port, port->mctrl);
2521 	spin_unlock_irqrestore(&port->lock, flags);
2522 
2523 	/*
2524 	 * Disable break condition and FIFOs
2525 	 */
2526 	serial_port_out(port, UART_LCR,
2527 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2528 	serial8250_clear_fifos(up);
2529 
2530 #ifdef CONFIG_SERIAL_8250_RSA
2531 	/*
2532 	 * Reset the RSA board back to 115kbps compat mode.
2533 	 */
2534 	disable_rsa(up);
2535 #endif
2536 
2537 	/*
2538 	 * Read data port to reset things, and then unlink from
2539 	 * the IRQ chain.
2540 	 */
2541 	serial_port_in(port, UART_RX);
2542 	serial8250_rpm_put(up);
2543 
2544 	up->ops->release_irq(up);
2545 }
2546 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2547 
serial8250_shutdown(struct uart_port * port)2548 static void serial8250_shutdown(struct uart_port *port)
2549 {
2550 	if (port->shutdown)
2551 		port->shutdown(port);
2552 	else
2553 		serial8250_do_shutdown(port);
2554 }
2555 
2556 /* Nuvoton NPCM UARTs have a custom divisor calculation */
npcm_get_divisor(struct uart_8250_port * up,unsigned int baud)2557 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2558 		unsigned int baud)
2559 {
2560 	struct uart_port *port = &up->port;
2561 
2562 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2563 }
2564 
serial8250_do_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)2565 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2566 					      unsigned int baud,
2567 					      unsigned int *frac)
2568 {
2569 	upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2570 	struct uart_8250_port *up = up_to_u8250p(port);
2571 	unsigned int quot;
2572 
2573 	/*
2574 	 * Handle magic divisors for baud rates above baud_base on SMSC
2575 	 * Super I/O chips.  We clamp custom rates from clk/6 and clk/12
2576 	 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively.  These
2577 	 * magic divisors actually reprogram the baud rate generator's
2578 	 * reference clock derived from chips's 14.318MHz clock input.
2579 	 *
2580 	 * Documentation claims that with these magic divisors the base
2581 	 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2582 	 * for the extra baud rates of 460800bps and 230400bps rather
2583 	 * than the usual base frequency of 1.8462MHz.  However empirical
2584 	 * evidence contradicts that.
2585 	 *
2586 	 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2587 	 * effectively used as a clock prescaler selection bit for the
2588 	 * base frequency of 7.3728MHz, always used.  If set to 0, then
2589 	 * the base frequency is divided by 4 for use by the Baud Rate
2590 	 * Generator, for the usual arrangement where the value of 1 of
2591 	 * the divisor produces the baud rate of 115200bps.  Conversely,
2592 	 * if set to 1 and high-speed operation has been enabled with the
2593 	 * Serial Port Mode Register in the Device Configuration Space,
2594 	 * then the base frequency is supplied directly to the Baud Rate
2595 	 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2596 	 * 0x8004, etc. the respective baud rates produced are 460800bps,
2597 	 * 230400bps, 153600bps, 115200bps, etc.
2598 	 *
2599 	 * In all cases only low 15 bits of the divisor are used to divide
2600 	 * the baud base and therefore 32767 is the maximum divisor value
2601 	 * possible, even though documentation says that the programmable
2602 	 * Baud Rate Generator is capable of dividing the internal PLL
2603 	 * clock by any divisor from 1 to 65535.
2604 	 */
2605 	if (magic_multiplier && baud >= port->uartclk / 6)
2606 		quot = 0x8001;
2607 	else if (magic_multiplier && baud >= port->uartclk / 12)
2608 		quot = 0x8002;
2609 	else if (up->port.type == PORT_NPCM)
2610 		quot = npcm_get_divisor(up, baud);
2611 	else
2612 		quot = uart_get_divisor(port, baud);
2613 
2614 	/*
2615 	 * Oxford Semi 952 rev B workaround
2616 	 */
2617 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2618 		quot++;
2619 
2620 	return quot;
2621 }
2622 
serial8250_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)2623 static unsigned int serial8250_get_divisor(struct uart_port *port,
2624 					   unsigned int baud,
2625 					   unsigned int *frac)
2626 {
2627 	if (port->get_divisor)
2628 		return port->get_divisor(port, baud, frac);
2629 
2630 	return serial8250_do_get_divisor(port, baud, frac);
2631 }
2632 
serial8250_compute_lcr(struct uart_8250_port * up,tcflag_t c_cflag)2633 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2634 					    tcflag_t c_cflag)
2635 {
2636 	unsigned char cval;
2637 
2638 	cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2639 
2640 	if (c_cflag & CSTOPB)
2641 		cval |= UART_LCR_STOP;
2642 	if (c_cflag & PARENB)
2643 		cval |= UART_LCR_PARITY;
2644 	if (!(c_cflag & PARODD))
2645 		cval |= UART_LCR_EPAR;
2646 	if (c_cflag & CMSPAR)
2647 		cval |= UART_LCR_SPAR;
2648 
2649 	return cval;
2650 }
2651 
serial8250_do_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)2652 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2653 			       unsigned int quot, unsigned int quot_frac)
2654 {
2655 	struct uart_8250_port *up = up_to_u8250p(port);
2656 
2657 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2658 	if (is_omap1510_8250(up)) {
2659 		if (baud == 115200) {
2660 			quot = 1;
2661 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2662 		} else
2663 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2664 	}
2665 
2666 	/*
2667 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2668 	 * otherwise just set DLAB
2669 	 */
2670 	if (up->capabilities & UART_NATSEMI)
2671 		serial_port_out(port, UART_LCR, 0xe0);
2672 	else
2673 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2674 
2675 	serial_dl_write(up, quot);
2676 }
2677 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2678 
serial8250_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)2679 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2680 				   unsigned int quot, unsigned int quot_frac)
2681 {
2682 	if (port->set_divisor)
2683 		port->set_divisor(port, baud, quot, quot_frac);
2684 	else
2685 		serial8250_do_set_divisor(port, baud, quot, quot_frac);
2686 }
2687 
serial8250_get_baud_rate(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2688 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2689 					     struct ktermios *termios,
2690 					     const struct ktermios *old)
2691 {
2692 	unsigned int tolerance = port->uartclk / 100;
2693 	unsigned int min;
2694 	unsigned int max;
2695 
2696 	/*
2697 	 * Handle magic divisors for baud rates above baud_base on SMSC
2698 	 * Super I/O chips.  Enable custom rates of clk/4 and clk/8, but
2699 	 * disable divisor values beyond 32767, which are unavailable.
2700 	 */
2701 	if (port->flags & UPF_MAGIC_MULTIPLIER) {
2702 		min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2703 		max = (port->uartclk + tolerance) / 4;
2704 	} else {
2705 		min = port->uartclk / 16 / UART_DIV_MAX;
2706 		max = (port->uartclk + tolerance) / 16;
2707 	}
2708 
2709 	/*
2710 	 * Ask the core to calculate the divisor for us.
2711 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2712 	 * slower than nominal still match standard baud rates without
2713 	 * causing transmission errors.
2714 	 */
2715 	return uart_get_baud_rate(port, termios, old, min, max);
2716 }
2717 
2718 /*
2719  * Note in order to avoid the tty port mutex deadlock don't use the next method
2720  * within the uart port callbacks. Primarily it's supposed to be utilized to
2721  * handle a sudden reference clock rate change.
2722  */
serial8250_update_uartclk(struct uart_port * port,unsigned int uartclk)2723 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2724 {
2725 	struct uart_8250_port *up = up_to_u8250p(port);
2726 	struct tty_port *tport = &port->state->port;
2727 	unsigned int baud, quot, frac = 0;
2728 	struct ktermios *termios;
2729 	struct tty_struct *tty;
2730 	unsigned long flags;
2731 
2732 	tty = tty_port_tty_get(tport);
2733 	if (!tty) {
2734 		mutex_lock(&tport->mutex);
2735 		port->uartclk = uartclk;
2736 		mutex_unlock(&tport->mutex);
2737 		return;
2738 	}
2739 
2740 	down_write(&tty->termios_rwsem);
2741 	mutex_lock(&tport->mutex);
2742 
2743 	if (port->uartclk == uartclk)
2744 		goto out_unlock;
2745 
2746 	port->uartclk = uartclk;
2747 
2748 	if (!tty_port_initialized(tport))
2749 		goto out_unlock;
2750 
2751 	termios = &tty->termios;
2752 
2753 	baud = serial8250_get_baud_rate(port, termios, NULL);
2754 	quot = serial8250_get_divisor(port, baud, &frac);
2755 
2756 	serial8250_rpm_get(up);
2757 	spin_lock_irqsave(&port->lock, flags);
2758 
2759 	uart_update_timeout(port, termios->c_cflag, baud);
2760 
2761 	serial8250_set_divisor(port, baud, quot, frac);
2762 	serial_port_out(port, UART_LCR, up->lcr);
2763 
2764 	spin_unlock_irqrestore(&port->lock, flags);
2765 	serial8250_rpm_put(up);
2766 
2767 out_unlock:
2768 	mutex_unlock(&tport->mutex);
2769 	up_write(&tty->termios_rwsem);
2770 	tty_kref_put(tty);
2771 }
2772 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2773 
2774 void
serial8250_do_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2775 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2776 		          const struct ktermios *old)
2777 {
2778 	struct uart_8250_port *up = up_to_u8250p(port);
2779 	unsigned char cval;
2780 	unsigned long flags;
2781 	unsigned int baud, quot, frac = 0;
2782 
2783 	if (up->capabilities & UART_CAP_MINI) {
2784 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2785 		if ((termios->c_cflag & CSIZE) == CS5 ||
2786 		    (termios->c_cflag & CSIZE) == CS6)
2787 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2788 	}
2789 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2790 
2791 	baud = serial8250_get_baud_rate(port, termios, old);
2792 	quot = serial8250_get_divisor(port, baud, &frac);
2793 
2794 	/*
2795 	 * Ok, we're now changing the port state.  Do it with
2796 	 * interrupts disabled.
2797 	 *
2798 	 * Synchronize UART_IER access against the console.
2799 	 */
2800 	serial8250_rpm_get(up);
2801 	spin_lock_irqsave(&port->lock, flags);
2802 
2803 	up->lcr = cval;					/* Save computed LCR */
2804 
2805 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2806 		if (baud < 2400 && !up->dma) {
2807 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2808 			up->fcr |= UART_FCR_TRIGGER_1;
2809 		}
2810 	}
2811 
2812 	/*
2813 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2814 	 * deasserted when the receive FIFO contains more characters than
2815 	 * the trigger, or the MCR RTS bit is cleared.
2816 	 */
2817 	if (up->capabilities & UART_CAP_AFE) {
2818 		up->mcr &= ~UART_MCR_AFE;
2819 		if (termios->c_cflag & CRTSCTS)
2820 			up->mcr |= UART_MCR_AFE;
2821 	}
2822 
2823 	/*
2824 	 * Update the per-port timeout.
2825 	 */
2826 	uart_update_timeout(port, termios->c_cflag, baud);
2827 
2828 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2829 	if (termios->c_iflag & INPCK)
2830 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2831 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2832 		port->read_status_mask |= UART_LSR_BI;
2833 
2834 	/*
2835 	 * Characters to ignore
2836 	 */
2837 	port->ignore_status_mask = 0;
2838 	if (termios->c_iflag & IGNPAR)
2839 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2840 	if (termios->c_iflag & IGNBRK) {
2841 		port->ignore_status_mask |= UART_LSR_BI;
2842 		/*
2843 		 * If we're ignoring parity and break indicators,
2844 		 * ignore overruns too (for real raw support).
2845 		 */
2846 		if (termios->c_iflag & IGNPAR)
2847 			port->ignore_status_mask |= UART_LSR_OE;
2848 	}
2849 
2850 	/*
2851 	 * ignore all characters if CREAD is not set
2852 	 */
2853 	if ((termios->c_cflag & CREAD) == 0)
2854 		port->ignore_status_mask |= UART_LSR_DR;
2855 
2856 	/*
2857 	 * CTS flow control flag and modem status interrupts
2858 	 */
2859 	up->ier &= ~UART_IER_MSI;
2860 	if (!(up->bugs & UART_BUG_NOMSR) &&
2861 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2862 		up->ier |= UART_IER_MSI;
2863 	if (up->capabilities & UART_CAP_UUE)
2864 		up->ier |= UART_IER_UUE;
2865 	if (up->capabilities & UART_CAP_RTOIE)
2866 		up->ier |= UART_IER_RTOIE;
2867 
2868 	serial_port_out(port, UART_IER, up->ier);
2869 
2870 	if (up->capabilities & UART_CAP_EFR) {
2871 		unsigned char efr = 0;
2872 		/*
2873 		 * TI16C752/Startech hardware flow control.  FIXME:
2874 		 * - TI16C752 requires control thresholds to be set.
2875 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2876 		 */
2877 		if (termios->c_cflag & CRTSCTS)
2878 			efr |= UART_EFR_CTS;
2879 
2880 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2881 		if (port->flags & UPF_EXAR_EFR)
2882 			serial_port_out(port, UART_XR_EFR, efr);
2883 		else
2884 			serial_port_out(port, UART_EFR, efr);
2885 	}
2886 
2887 	serial8250_set_divisor(port, baud, quot, frac);
2888 
2889 	/*
2890 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2891 	 * is written without DLAB set, this mode will be disabled.
2892 	 */
2893 	if (port->type == PORT_16750)
2894 		serial_port_out(port, UART_FCR, up->fcr);
2895 
2896 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2897 	if (port->type != PORT_16750) {
2898 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2899 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2900 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2901 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2902 	}
2903 	serial8250_set_mctrl(port, port->mctrl);
2904 	spin_unlock_irqrestore(&port->lock, flags);
2905 	serial8250_rpm_put(up);
2906 
2907 	/* Don't rewrite B0 */
2908 	if (tty_termios_baud_rate(termios))
2909 		tty_termios_encode_baud_rate(termios, baud, baud);
2910 }
2911 EXPORT_SYMBOL(serial8250_do_set_termios);
2912 
2913 static void
serial8250_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2914 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2915 		       const struct ktermios *old)
2916 {
2917 	if (port->set_termios)
2918 		port->set_termios(port, termios, old);
2919 	else
2920 		serial8250_do_set_termios(port, termios, old);
2921 }
2922 
serial8250_do_set_ldisc(struct uart_port * port,struct ktermios * termios)2923 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2924 {
2925 	if (termios->c_line == N_PPS) {
2926 		port->flags |= UPF_HARDPPS_CD;
2927 		spin_lock_irq(&port->lock);
2928 		serial8250_enable_ms(port);
2929 		spin_unlock_irq(&port->lock);
2930 	} else {
2931 		port->flags &= ~UPF_HARDPPS_CD;
2932 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2933 			spin_lock_irq(&port->lock);
2934 			serial8250_disable_ms(port);
2935 			spin_unlock_irq(&port->lock);
2936 		}
2937 	}
2938 }
2939 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2940 
2941 static void
serial8250_set_ldisc(struct uart_port * port,struct ktermios * termios)2942 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2943 {
2944 	if (port->set_ldisc)
2945 		port->set_ldisc(port, termios);
2946 	else
2947 		serial8250_do_set_ldisc(port, termios);
2948 }
2949 
serial8250_do_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2950 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2951 		      unsigned int oldstate)
2952 {
2953 	struct uart_8250_port *p = up_to_u8250p(port);
2954 
2955 	serial8250_set_sleep(p, state != 0);
2956 }
2957 EXPORT_SYMBOL(serial8250_do_pm);
2958 
2959 static void
serial8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2960 serial8250_pm(struct uart_port *port, unsigned int state,
2961 	      unsigned int oldstate)
2962 {
2963 	if (port->pm)
2964 		port->pm(port, state, oldstate);
2965 	else
2966 		serial8250_do_pm(port, state, oldstate);
2967 }
2968 
serial8250_port_size(struct uart_8250_port * pt)2969 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2970 {
2971 	if (pt->port.mapsize)
2972 		return pt->port.mapsize;
2973 	if (is_omap1_8250(pt))
2974 		return 0x16 << pt->port.regshift;
2975 
2976 	return 8 << pt->port.regshift;
2977 }
2978 
2979 /*
2980  * Resource handling.
2981  */
serial8250_request_std_resource(struct uart_8250_port * up)2982 static int serial8250_request_std_resource(struct uart_8250_port *up)
2983 {
2984 	unsigned int size = serial8250_port_size(up);
2985 	struct uart_port *port = &up->port;
2986 	int ret = 0;
2987 
2988 	switch (port->iotype) {
2989 	case UPIO_AU:
2990 	case UPIO_TSI:
2991 	case UPIO_MEM32:
2992 	case UPIO_MEM32BE:
2993 	case UPIO_MEM16:
2994 	case UPIO_MEM:
2995 		if (!port->mapbase) {
2996 			ret = -EINVAL;
2997 			break;
2998 		}
2999 
3000 		if (!request_mem_region(port->mapbase, size, "serial")) {
3001 			ret = -EBUSY;
3002 			break;
3003 		}
3004 
3005 		if (port->flags & UPF_IOREMAP) {
3006 			port->membase = ioremap(port->mapbase, size);
3007 			if (!port->membase) {
3008 				release_mem_region(port->mapbase, size);
3009 				ret = -ENOMEM;
3010 			}
3011 		}
3012 		break;
3013 
3014 	case UPIO_HUB6:
3015 	case UPIO_PORT:
3016 		if (!request_region(port->iobase, size, "serial"))
3017 			ret = -EBUSY;
3018 		break;
3019 	}
3020 	return ret;
3021 }
3022 
serial8250_release_std_resource(struct uart_8250_port * up)3023 static void serial8250_release_std_resource(struct uart_8250_port *up)
3024 {
3025 	unsigned int size = serial8250_port_size(up);
3026 	struct uart_port *port = &up->port;
3027 
3028 	switch (port->iotype) {
3029 	case UPIO_AU:
3030 	case UPIO_TSI:
3031 	case UPIO_MEM32:
3032 	case UPIO_MEM32BE:
3033 	case UPIO_MEM16:
3034 	case UPIO_MEM:
3035 		if (!port->mapbase)
3036 			break;
3037 
3038 		if (port->flags & UPF_IOREMAP) {
3039 			iounmap(port->membase);
3040 			port->membase = NULL;
3041 		}
3042 
3043 		release_mem_region(port->mapbase, size);
3044 		break;
3045 
3046 	case UPIO_HUB6:
3047 	case UPIO_PORT:
3048 		release_region(port->iobase, size);
3049 		break;
3050 	}
3051 }
3052 
serial8250_release_port(struct uart_port * port)3053 static void serial8250_release_port(struct uart_port *port)
3054 {
3055 	struct uart_8250_port *up = up_to_u8250p(port);
3056 
3057 	serial8250_release_std_resource(up);
3058 }
3059 
serial8250_request_port(struct uart_port * port)3060 static int serial8250_request_port(struct uart_port *port)
3061 {
3062 	struct uart_8250_port *up = up_to_u8250p(port);
3063 
3064 	return serial8250_request_std_resource(up);
3065 }
3066 
fcr_get_rxtrig_bytes(struct uart_8250_port * up)3067 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3068 {
3069 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3070 	unsigned char bytes;
3071 
3072 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3073 
3074 	return bytes ? bytes : -EOPNOTSUPP;
3075 }
3076 
bytes_to_fcr_rxtrig(struct uart_8250_port * up,unsigned char bytes)3077 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3078 {
3079 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3080 	int i;
3081 
3082 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3083 		return -EOPNOTSUPP;
3084 
3085 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3086 		if (bytes < conf_type->rxtrig_bytes[i])
3087 			/* Use the nearest lower value */
3088 			return (--i) << UART_FCR_R_TRIG_SHIFT;
3089 	}
3090 
3091 	return UART_FCR_R_TRIG_11;
3092 }
3093 
do_get_rxtrig(struct tty_port * port)3094 static int do_get_rxtrig(struct tty_port *port)
3095 {
3096 	struct uart_state *state = container_of(port, struct uart_state, port);
3097 	struct uart_port *uport = state->uart_port;
3098 	struct uart_8250_port *up = up_to_u8250p(uport);
3099 
3100 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3101 		return -EINVAL;
3102 
3103 	return fcr_get_rxtrig_bytes(up);
3104 }
3105 
do_serial8250_get_rxtrig(struct tty_port * port)3106 static int do_serial8250_get_rxtrig(struct tty_port *port)
3107 {
3108 	int rxtrig_bytes;
3109 
3110 	mutex_lock(&port->mutex);
3111 	rxtrig_bytes = do_get_rxtrig(port);
3112 	mutex_unlock(&port->mutex);
3113 
3114 	return rxtrig_bytes;
3115 }
3116 
rx_trig_bytes_show(struct device * dev,struct device_attribute * attr,char * buf)3117 static ssize_t rx_trig_bytes_show(struct device *dev,
3118 	struct device_attribute *attr, char *buf)
3119 {
3120 	struct tty_port *port = dev_get_drvdata(dev);
3121 	int rxtrig_bytes;
3122 
3123 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
3124 	if (rxtrig_bytes < 0)
3125 		return rxtrig_bytes;
3126 
3127 	return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3128 }
3129 
do_set_rxtrig(struct tty_port * port,unsigned char bytes)3130 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3131 {
3132 	struct uart_state *state = container_of(port, struct uart_state, port);
3133 	struct uart_port *uport = state->uart_port;
3134 	struct uart_8250_port *up = up_to_u8250p(uport);
3135 	int rxtrig;
3136 
3137 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3138 		return -EINVAL;
3139 
3140 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3141 	if (rxtrig < 0)
3142 		return rxtrig;
3143 
3144 	serial8250_clear_fifos(up);
3145 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3146 	up->fcr |= (unsigned char)rxtrig;
3147 	serial_out(up, UART_FCR, up->fcr);
3148 	return 0;
3149 }
3150 
do_serial8250_set_rxtrig(struct tty_port * port,unsigned char bytes)3151 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3152 {
3153 	int ret;
3154 
3155 	mutex_lock(&port->mutex);
3156 	ret = do_set_rxtrig(port, bytes);
3157 	mutex_unlock(&port->mutex);
3158 
3159 	return ret;
3160 }
3161 
rx_trig_bytes_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3162 static ssize_t rx_trig_bytes_store(struct device *dev,
3163 	struct device_attribute *attr, const char *buf, size_t count)
3164 {
3165 	struct tty_port *port = dev_get_drvdata(dev);
3166 	unsigned char bytes;
3167 	int ret;
3168 
3169 	if (!count)
3170 		return -EINVAL;
3171 
3172 	ret = kstrtou8(buf, 10, &bytes);
3173 	if (ret < 0)
3174 		return ret;
3175 
3176 	ret = do_serial8250_set_rxtrig(port, bytes);
3177 	if (ret < 0)
3178 		return ret;
3179 
3180 	return count;
3181 }
3182 
3183 static DEVICE_ATTR_RW(rx_trig_bytes);
3184 
3185 static struct attribute *serial8250_dev_attrs[] = {
3186 	&dev_attr_rx_trig_bytes.attr,
3187 	NULL
3188 };
3189 
3190 static struct attribute_group serial8250_dev_attr_group = {
3191 	.attrs = serial8250_dev_attrs,
3192 };
3193 
register_dev_spec_attr_grp(struct uart_8250_port * up)3194 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3195 {
3196 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3197 
3198 	if (conf_type->rxtrig_bytes[0])
3199 		up->port.attr_group = &serial8250_dev_attr_group;
3200 }
3201 
serial8250_config_port(struct uart_port * port,int flags)3202 static void serial8250_config_port(struct uart_port *port, int flags)
3203 {
3204 	struct uart_8250_port *up = up_to_u8250p(port);
3205 	int ret;
3206 
3207 	/*
3208 	 * Find the region that we can probe for.  This in turn
3209 	 * tells us whether we can probe for the type of port.
3210 	 */
3211 	ret = serial8250_request_std_resource(up);
3212 	if (ret < 0)
3213 		return;
3214 
3215 	if (port->iotype != up->cur_iotype)
3216 		set_io_from_upio(port);
3217 
3218 	if (flags & UART_CONFIG_TYPE)
3219 		autoconfig(up);
3220 
3221 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3222 	if (port->type == PORT_TEGRA)
3223 		up->bugs |= UART_BUG_NOMSR;
3224 
3225 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3226 		autoconfig_irq(up);
3227 
3228 	if (port->type == PORT_UNKNOWN)
3229 		serial8250_release_std_resource(up);
3230 
3231 	register_dev_spec_attr_grp(up);
3232 	up->fcr = uart_config[up->port.type].fcr;
3233 }
3234 
3235 static int
serial8250_verify_port(struct uart_port * port,struct serial_struct * ser)3236 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3237 {
3238 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3239 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3240 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3241 	    ser->type == PORT_STARTECH)
3242 		return -EINVAL;
3243 	return 0;
3244 }
3245 
serial8250_type(struct uart_port * port)3246 static const char *serial8250_type(struct uart_port *port)
3247 {
3248 	int type = port->type;
3249 
3250 	if (type >= ARRAY_SIZE(uart_config))
3251 		type = 0;
3252 	return uart_config[type].name;
3253 }
3254 
3255 static const struct uart_ops serial8250_pops = {
3256 	.tx_empty	= serial8250_tx_empty,
3257 	.set_mctrl	= serial8250_set_mctrl,
3258 	.get_mctrl	= serial8250_get_mctrl,
3259 	.stop_tx	= serial8250_stop_tx,
3260 	.start_tx	= serial8250_start_tx,
3261 	.throttle	= serial8250_throttle,
3262 	.unthrottle	= serial8250_unthrottle,
3263 	.stop_rx	= serial8250_stop_rx,
3264 	.enable_ms	= serial8250_enable_ms,
3265 	.break_ctl	= serial8250_break_ctl,
3266 	.startup	= serial8250_startup,
3267 	.shutdown	= serial8250_shutdown,
3268 	.set_termios	= serial8250_set_termios,
3269 	.set_ldisc	= serial8250_set_ldisc,
3270 	.pm		= serial8250_pm,
3271 	.type		= serial8250_type,
3272 	.release_port	= serial8250_release_port,
3273 	.request_port	= serial8250_request_port,
3274 	.config_port	= serial8250_config_port,
3275 	.verify_port	= serial8250_verify_port,
3276 #ifdef CONFIG_CONSOLE_POLL
3277 	.poll_get_char = serial8250_get_poll_char,
3278 	.poll_put_char = serial8250_put_poll_char,
3279 #endif
3280 };
3281 
serial8250_init_port(struct uart_8250_port * up)3282 void serial8250_init_port(struct uart_8250_port *up)
3283 {
3284 	struct uart_port *port = &up->port;
3285 
3286 	spin_lock_init(&port->lock);
3287 	port->ctrl_id = 0;
3288 	port->pm = NULL;
3289 	port->ops = &serial8250_pops;
3290 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3291 
3292 	up->cur_iotype = 0xFF;
3293 }
3294 EXPORT_SYMBOL_GPL(serial8250_init_port);
3295 
serial8250_set_defaults(struct uart_8250_port * up)3296 void serial8250_set_defaults(struct uart_8250_port *up)
3297 {
3298 	struct uart_port *port = &up->port;
3299 
3300 	if (up->port.flags & UPF_FIXED_TYPE) {
3301 		unsigned int type = up->port.type;
3302 
3303 		if (!up->port.fifosize)
3304 			up->port.fifosize = uart_config[type].fifo_size;
3305 		if (!up->tx_loadsz)
3306 			up->tx_loadsz = uart_config[type].tx_loadsz;
3307 		if (!up->capabilities)
3308 			up->capabilities = uart_config[type].flags;
3309 	}
3310 
3311 	set_io_from_upio(port);
3312 
3313 	/* default dma handlers */
3314 	if (up->dma) {
3315 		if (!up->dma->tx_dma)
3316 			up->dma->tx_dma = serial8250_tx_dma;
3317 		if (!up->dma->rx_dma)
3318 			up->dma->rx_dma = serial8250_rx_dma;
3319 	}
3320 }
3321 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3322 
3323 #ifdef CONFIG_SERIAL_8250_CONSOLE
3324 
serial8250_console_putchar(struct uart_port * port,unsigned char ch)3325 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3326 {
3327 	struct uart_8250_port *up = up_to_u8250p(port);
3328 
3329 	wait_for_xmitr(up, UART_LSR_THRE);
3330 	serial_port_out(port, UART_TX, ch);
3331 }
3332 
3333 /*
3334  *	Restore serial console when h/w power-off detected
3335  */
serial8250_console_restore(struct uart_8250_port * up)3336 static void serial8250_console_restore(struct uart_8250_port *up)
3337 {
3338 	struct uart_port *port = &up->port;
3339 	struct ktermios termios;
3340 	unsigned int baud, quot, frac = 0;
3341 
3342 	termios.c_cflag = port->cons->cflag;
3343 	termios.c_ispeed = port->cons->ispeed;
3344 	termios.c_ospeed = port->cons->ospeed;
3345 	if (port->state->port.tty && termios.c_cflag == 0) {
3346 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3347 		termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3348 		termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3349 	}
3350 
3351 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3352 	quot = serial8250_get_divisor(port, baud, &frac);
3353 
3354 	serial8250_set_divisor(port, baud, quot, frac);
3355 	serial_port_out(port, UART_LCR, up->lcr);
3356 	serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3357 }
3358 
3359 /*
3360  * Print a string to the serial port using the device FIFO
3361  *
3362  * It sends fifosize bytes and then waits for the fifo
3363  * to get empty.
3364  */
serial8250_console_fifo_write(struct uart_8250_port * up,const char * s,unsigned int count)3365 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3366 					  const char *s, unsigned int count)
3367 {
3368 	int i;
3369 	const char *end = s + count;
3370 	unsigned int fifosize = up->tx_loadsz;
3371 	bool cr_sent = false;
3372 
3373 	while (s != end) {
3374 		wait_for_lsr(up, UART_LSR_THRE);
3375 
3376 		for (i = 0; i < fifosize && s != end; ++i) {
3377 			if (*s == '\n' && !cr_sent) {
3378 				serial_out(up, UART_TX, '\r');
3379 				cr_sent = true;
3380 			} else {
3381 				serial_out(up, UART_TX, *s++);
3382 				cr_sent = false;
3383 			}
3384 		}
3385 	}
3386 }
3387 
3388 /*
3389  *	Print a string to the serial port trying not to disturb
3390  *	any possible real use of the port...
3391  *
3392  *	The console_lock must be held when we get here.
3393  *
3394  *	Doing runtime PM is really a bad idea for the kernel console.
3395  *	Thus, we assume the function is called when device is powered up.
3396  */
serial8250_console_write(struct uart_8250_port * up,const char * s,unsigned int count)3397 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3398 			      unsigned int count)
3399 {
3400 	struct uart_8250_em485 *em485 = up->em485;
3401 	struct uart_port *port = &up->port;
3402 	unsigned long flags;
3403 	unsigned int ier, use_fifo;
3404 	int locked = 1;
3405 
3406 	touch_nmi_watchdog();
3407 
3408 	if (oops_in_progress)
3409 		locked = spin_trylock_irqsave(&port->lock, flags);
3410 	else
3411 		spin_lock_irqsave(&port->lock, flags);
3412 
3413 	/*
3414 	 *	First save the IER then disable the interrupts
3415 	 */
3416 	ier = serial_port_in(port, UART_IER);
3417 	serial8250_clear_IER(up);
3418 
3419 	/* check scratch reg to see if port powered off during system sleep */
3420 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3421 		serial8250_console_restore(up);
3422 		up->canary = 0;
3423 	}
3424 
3425 	if (em485) {
3426 		if (em485->tx_stopped)
3427 			up->rs485_start_tx(up);
3428 		mdelay(port->rs485.delay_rts_before_send);
3429 	}
3430 
3431 	use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3432 		/*
3433 		 * BCM283x requires to check the fifo
3434 		 * after each byte.
3435 		 */
3436 		!(up->capabilities & UART_CAP_MINI) &&
3437 		/*
3438 		 * tx_loadsz contains the transmit fifo size
3439 		 */
3440 		up->tx_loadsz > 1 &&
3441 		(up->fcr & UART_FCR_ENABLE_FIFO) &&
3442 		port->state &&
3443 		test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3444 		/*
3445 		 * After we put a data in the fifo, the controller will send
3446 		 * it regardless of the CTS state. Therefore, only use fifo
3447 		 * if we don't use control flow.
3448 		 */
3449 		!(up->port.flags & UPF_CONS_FLOW);
3450 
3451 	if (likely(use_fifo))
3452 		serial8250_console_fifo_write(up, s, count);
3453 	else
3454 		uart_console_write(port, s, count, serial8250_console_putchar);
3455 
3456 	/*
3457 	 *	Finally, wait for transmitter to become empty
3458 	 *	and restore the IER
3459 	 */
3460 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3461 
3462 	if (em485) {
3463 		mdelay(port->rs485.delay_rts_after_send);
3464 		if (em485->tx_stopped)
3465 			up->rs485_stop_tx(up);
3466 	}
3467 
3468 	serial_port_out(port, UART_IER, ier);
3469 
3470 	/*
3471 	 *	The receive handling will happen properly because the
3472 	 *	receive ready bit will still be set; it is not cleared
3473 	 *	on read.  However, modem control will not, we must
3474 	 *	call it if we have saved something in the saved flags
3475 	 *	while processing with interrupts off.
3476 	 */
3477 	if (up->msr_saved_flags)
3478 		serial8250_modem_status(up);
3479 
3480 	if (locked)
3481 		spin_unlock_irqrestore(&port->lock, flags);
3482 }
3483 
probe_baud(struct uart_port * port)3484 static unsigned int probe_baud(struct uart_port *port)
3485 {
3486 	unsigned char lcr, dll, dlm;
3487 	unsigned int quot;
3488 
3489 	lcr = serial_port_in(port, UART_LCR);
3490 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3491 	dll = serial_port_in(port, UART_DLL);
3492 	dlm = serial_port_in(port, UART_DLM);
3493 	serial_port_out(port, UART_LCR, lcr);
3494 
3495 	quot = (dlm << 8) | dll;
3496 	return (port->uartclk / 16) / quot;
3497 }
3498 
serial8250_console_setup(struct uart_port * port,char * options,bool probe)3499 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3500 {
3501 	int baud = 9600;
3502 	int bits = 8;
3503 	int parity = 'n';
3504 	int flow = 'n';
3505 	int ret;
3506 
3507 	if (!port->iobase && !port->membase)
3508 		return -ENODEV;
3509 
3510 	if (options)
3511 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3512 	else if (probe)
3513 		baud = probe_baud(port);
3514 
3515 	ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3516 	if (ret)
3517 		return ret;
3518 
3519 	if (port->dev)
3520 		pm_runtime_get_sync(port->dev);
3521 
3522 	return 0;
3523 }
3524 
serial8250_console_exit(struct uart_port * port)3525 int serial8250_console_exit(struct uart_port *port)
3526 {
3527 	if (port->dev)
3528 		pm_runtime_put_sync(port->dev);
3529 
3530 	return 0;
3531 }
3532 
3533 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3534 
3535 MODULE_LICENSE("GPL");
3536