1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31
32 #include "sdhci.h"
33
34 #define DRIVER_NAME "sdhci"
35
36 #define DBG(f, x...) \
37 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38
39 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41 #define SDHCI_USE_LEDS_CLASS
42 #endif
43
44 #define MAX_TUNING_LOOP 40
45
46 static unsigned int debug_quirks = 0;
47 static unsigned int debug_quirks2;
48
49 static void sdhci_finish_data(struct sdhci_host *);
50
51 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55
56 #ifdef CONFIG_PM_RUNTIME
57 static int sdhci_runtime_pm_get(struct sdhci_host *host);
58 static int sdhci_runtime_pm_put(struct sdhci_host *host);
59 #else
sdhci_runtime_pm_get(struct sdhci_host * host)60 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61 {
62 return 0;
63 }
sdhci_runtime_pm_put(struct sdhci_host * host)64 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65 {
66 return 0;
67 }
68 #endif
69
sdhci_dumpregs(struct sdhci_host * host)70 static void sdhci_dumpregs(struct sdhci_host *host)
71 {
72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
73 mmc_hostname(host->mmc));
74
75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
103 sdhci_readl(host, SDHCI_CAPABILITIES),
104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
106 sdhci_readw(host, SDHCI_COMMAND),
107 sdhci_readl(host, SDHCI_MAX_CURRENT));
108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
110
111 if (host->flags & SDHCI_USE_ADMA)
112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
116 pr_debug(DRIVER_NAME ": ===========================================\n");
117 }
118
119 /*****************************************************************************\
120 * *
121 * Low level functions *
122 * *
123 \*****************************************************************************/
124
sdhci_clear_set_irqs(struct sdhci_host * host,u32 clear,u32 set)125 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126 {
127 u32 ier;
128
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130 ier &= ~clear;
131 ier |= set;
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134 }
135
sdhci_unmask_irqs(struct sdhci_host * host,u32 irqs)136 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137 {
138 sdhci_clear_set_irqs(host, 0, irqs);
139 }
140
sdhci_mask_irqs(struct sdhci_host * host,u32 irqs)141 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142 {
143 sdhci_clear_set_irqs(host, irqs, 0);
144 }
145
sdhci_set_card_detection(struct sdhci_host * host,bool enable)146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147 {
148 u32 present, irqs;
149
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
152 return;
153
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
158 if (enable)
159 sdhci_unmask_irqs(host, irqs);
160 else
161 sdhci_mask_irqs(host, irqs);
162 }
163
sdhci_enable_card_detection(struct sdhci_host * host)164 static void sdhci_enable_card_detection(struct sdhci_host *host)
165 {
166 sdhci_set_card_detection(host, true);
167 }
168
sdhci_disable_card_detection(struct sdhci_host * host)169 static void sdhci_disable_card_detection(struct sdhci_host *host)
170 {
171 sdhci_set_card_detection(host, false);
172 }
173
sdhci_reset(struct sdhci_host * host,u8 mask)174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
175 {
176 unsigned long timeout;
177 u32 uninitialized_var(ier);
178
179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
181 SDHCI_CARD_PRESENT))
182 return;
183 }
184
185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
190
191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
192
193 if (mask & SDHCI_RESET_ALL)
194 host->clock = 0;
195
196 /* Wait max 100 ms */
197 timeout = 100;
198
199 /* hw clears the bit when it's done */
200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
201 if (timeout == 0) {
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 timeout--;
208 mdelay(1);
209 }
210
211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
213
214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
216
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
220 }
221 }
222
223 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
sdhci_init(struct sdhci_host * host,int soft)225 static void sdhci_init(struct sdhci_host *host, int soft)
226 {
227 if (soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229 else
230 sdhci_reset(host, SDHCI_RESET_ALL);
231
232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
237
238 if (soft) {
239 /* force clock reconfiguration */
240 host->clock = 0;
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
242 }
243 }
244
sdhci_reinit(struct sdhci_host * host)245 static void sdhci_reinit(struct sdhci_host *host)
246 {
247 sdhci_init(host, 0);
248 sdhci_enable_card_detection(host);
249 }
250
sdhci_activate_led(struct sdhci_host * host)251 static void sdhci_activate_led(struct sdhci_host *host)
252 {
253 u8 ctrl;
254
255 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
256 ctrl |= SDHCI_CTRL_LED;
257 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
258 }
259
sdhci_deactivate_led(struct sdhci_host * host)260 static void sdhci_deactivate_led(struct sdhci_host *host)
261 {
262 u8 ctrl;
263
264 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
265 ctrl &= ~SDHCI_CTRL_LED;
266 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
267 }
268
269 #ifdef SDHCI_USE_LEDS_CLASS
sdhci_led_control(struct led_classdev * led,enum led_brightness brightness)270 static void sdhci_led_control(struct led_classdev *led,
271 enum led_brightness brightness)
272 {
273 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
274 unsigned long flags;
275
276 spin_lock_irqsave(&host->lock, flags);
277
278 if (host->runtime_suspended)
279 goto out;
280
281 if (brightness == LED_OFF)
282 sdhci_deactivate_led(host);
283 else
284 sdhci_activate_led(host);
285 out:
286 spin_unlock_irqrestore(&host->lock, flags);
287 }
288 #endif
289
290 /*****************************************************************************\
291 * *
292 * Core functions *
293 * *
294 \*****************************************************************************/
295
sdhci_read_block_pio(struct sdhci_host * host)296 static void sdhci_read_block_pio(struct sdhci_host *host)
297 {
298 unsigned long flags;
299 size_t blksize, len, chunk;
300 u32 uninitialized_var(scratch);
301 u8 *buf;
302
303 DBG("PIO reading\n");
304
305 blksize = host->data->blksz;
306 chunk = 0;
307
308 local_irq_save(flags);
309
310 while (blksize) {
311 if (!sg_miter_next(&host->sg_miter))
312 BUG();
313
314 len = min(host->sg_miter.length, blksize);
315
316 blksize -= len;
317 host->sg_miter.consumed = len;
318
319 buf = host->sg_miter.addr;
320
321 while (len) {
322 if (chunk == 0) {
323 scratch = sdhci_readl(host, SDHCI_BUFFER);
324 chunk = 4;
325 }
326
327 *buf = scratch & 0xFF;
328
329 buf++;
330 scratch >>= 8;
331 chunk--;
332 len--;
333 }
334 }
335
336 sg_miter_stop(&host->sg_miter);
337
338 local_irq_restore(flags);
339 }
340
sdhci_write_block_pio(struct sdhci_host * host)341 static void sdhci_write_block_pio(struct sdhci_host *host)
342 {
343 unsigned long flags;
344 size_t blksize, len, chunk;
345 u32 scratch;
346 u8 *buf;
347
348 DBG("PIO writing\n");
349
350 blksize = host->data->blksz;
351 chunk = 0;
352 scratch = 0;
353
354 local_irq_save(flags);
355
356 while (blksize) {
357 if (!sg_miter_next(&host->sg_miter))
358 BUG();
359
360 len = min(host->sg_miter.length, blksize);
361
362 blksize -= len;
363 host->sg_miter.consumed = len;
364
365 buf = host->sg_miter.addr;
366
367 while (len) {
368 scratch |= (u32)*buf << (chunk * 8);
369
370 buf++;
371 chunk++;
372 len--;
373
374 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
375 sdhci_writel(host, scratch, SDHCI_BUFFER);
376 chunk = 0;
377 scratch = 0;
378 }
379 }
380 }
381
382 sg_miter_stop(&host->sg_miter);
383
384 local_irq_restore(flags);
385 }
386
sdhci_transfer_pio(struct sdhci_host * host)387 static void sdhci_transfer_pio(struct sdhci_host *host)
388 {
389 u32 mask;
390
391 BUG_ON(!host->data);
392
393 if (host->blocks == 0)
394 return;
395
396 if (host->data->flags & MMC_DATA_READ)
397 mask = SDHCI_DATA_AVAILABLE;
398 else
399 mask = SDHCI_SPACE_AVAILABLE;
400
401 /*
402 * Some controllers (JMicron JMB38x) mess up the buffer bits
403 * for transfers < 4 bytes. As long as it is just one block,
404 * we can ignore the bits.
405 */
406 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
407 (host->data->blocks == 1))
408 mask = ~0;
409
410 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
411 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
412 udelay(100);
413
414 if (host->data->flags & MMC_DATA_READ)
415 sdhci_read_block_pio(host);
416 else
417 sdhci_write_block_pio(host);
418
419 host->blocks--;
420 if (host->blocks == 0)
421 break;
422 }
423
424 DBG("PIO transfer complete.\n");
425 }
426
sdhci_kmap_atomic(struct scatterlist * sg,unsigned long * flags)427 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
428 {
429 local_irq_save(*flags);
430 return kmap_atomic(sg_page(sg)) + sg->offset;
431 }
432
sdhci_kunmap_atomic(void * buffer,unsigned long * flags)433 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
434 {
435 kunmap_atomic(buffer);
436 local_irq_restore(*flags);
437 }
438
sdhci_set_adma_desc(u8 * desc,u32 addr,int len,unsigned cmd)439 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
440 {
441 __le32 *dataddr = (__le32 __force *)(desc + 4);
442 __le16 *cmdlen = (__le16 __force *)desc;
443
444 /* SDHCI specification says ADMA descriptors should be 4 byte
445 * aligned, so using 16 or 32bit operations should be safe. */
446
447 cmdlen[0] = cpu_to_le16(cmd);
448 cmdlen[1] = cpu_to_le16(len);
449
450 dataddr[0] = cpu_to_le32(addr);
451 }
452
sdhci_adma_table_pre(struct sdhci_host * host,struct mmc_data * data)453 static int sdhci_adma_table_pre(struct sdhci_host *host,
454 struct mmc_data *data)
455 {
456 int direction;
457
458 u8 *desc;
459 u8 *align;
460 dma_addr_t addr;
461 dma_addr_t align_addr;
462 int len, offset;
463
464 struct scatterlist *sg;
465 int i;
466 char *buffer;
467 unsigned long flags;
468
469 /*
470 * The spec does not specify endianness of descriptor table.
471 * We currently guess that it is LE.
472 */
473
474 if (data->flags & MMC_DATA_READ)
475 direction = DMA_FROM_DEVICE;
476 else
477 direction = DMA_TO_DEVICE;
478
479 /*
480 * The ADMA descriptor table is mapped further down as we
481 * need to fill it with data first.
482 */
483
484 host->align_addr = dma_map_single(mmc_dev(host->mmc),
485 host->align_buffer, 128 * 4, direction);
486 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
487 goto fail;
488 BUG_ON(host->align_addr & 0x3);
489
490 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
491 data->sg, data->sg_len, direction);
492 if (host->sg_count == 0)
493 goto unmap_align;
494
495 desc = host->adma_desc;
496 align = host->align_buffer;
497
498 align_addr = host->align_addr;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 addr = sg_dma_address(sg);
502 len = sg_dma_len(sg);
503
504 /*
505 * The SDHCI specification states that ADMA
506 * addresses must be 32-bit aligned. If they
507 * aren't, then we use a bounce buffer for
508 * the (up to three) bytes that screw up the
509 * alignment.
510 */
511 offset = (4 - (addr & 0x3)) & 0x3;
512 if (offset) {
513 if (data->flags & MMC_DATA_WRITE) {
514 buffer = sdhci_kmap_atomic(sg, &flags);
515 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
516 memcpy(align, buffer, offset);
517 sdhci_kunmap_atomic(buffer, &flags);
518 }
519
520 /* tran, valid */
521 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
522
523 BUG_ON(offset > 65536);
524
525 align += 4;
526 align_addr += 4;
527
528 desc += 8;
529
530 addr += offset;
531 len -= offset;
532 }
533
534 BUG_ON(len > 65536);
535
536 /* tran, valid */
537 sdhci_set_adma_desc(desc, addr, len, 0x21);
538 desc += 8;
539
540 /*
541 * If this triggers then we have a calculation bug
542 * somewhere. :/
543 */
544 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
545 }
546
547 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
548 /*
549 * Mark the last descriptor as the terminating descriptor
550 */
551 if (desc != host->adma_desc) {
552 desc -= 8;
553 desc[0] |= 0x2; /* end */
554 }
555 } else {
556 /*
557 * Add a terminating entry.
558 */
559
560 /* nop, end, valid */
561 sdhci_set_adma_desc(desc, 0, 0, 0x3);
562 }
563
564 /*
565 * Resync align buffer as we might have changed it.
566 */
567 if (data->flags & MMC_DATA_WRITE) {
568 dma_sync_single_for_device(mmc_dev(host->mmc),
569 host->align_addr, 128 * 4, direction);
570 }
571
572 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
573 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
574 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
575 goto unmap_entries;
576 BUG_ON(host->adma_addr & 0x3);
577
578 return 0;
579
580 unmap_entries:
581 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
582 data->sg_len, direction);
583 unmap_align:
584 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585 128 * 4, direction);
586 fail:
587 return -EINVAL;
588 }
589
sdhci_adma_table_post(struct sdhci_host * host,struct mmc_data * data)590 static void sdhci_adma_table_post(struct sdhci_host *host,
591 struct mmc_data *data)
592 {
593 int direction;
594
595 struct scatterlist *sg;
596 int i, size;
597 u8 *align;
598 char *buffer;
599 unsigned long flags;
600
601 if (data->flags & MMC_DATA_READ)
602 direction = DMA_FROM_DEVICE;
603 else
604 direction = DMA_TO_DEVICE;
605
606 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
607 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
608
609 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
610 128 * 4, direction);
611
612 if (data->flags & MMC_DATA_READ) {
613 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
614 data->sg_len, direction);
615
616 align = host->align_buffer;
617
618 for_each_sg(data->sg, sg, host->sg_count, i) {
619 if (sg_dma_address(sg) & 0x3) {
620 size = 4 - (sg_dma_address(sg) & 0x3);
621
622 buffer = sdhci_kmap_atomic(sg, &flags);
623 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
624 memcpy(buffer, align, size);
625 sdhci_kunmap_atomic(buffer, &flags);
626
627 align += 4;
628 }
629 }
630 }
631
632 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
633 data->sg_len, direction);
634 }
635
sdhci_calc_timeout(struct sdhci_host * host,struct mmc_command * cmd)636 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
637 {
638 u8 count;
639 struct mmc_data *data = cmd->data;
640 unsigned target_timeout, current_timeout;
641
642 /*
643 * If the host controller provides us with an incorrect timeout
644 * value, just skip the check and use 0xE. The hardware may take
645 * longer to time out, but that's much better than having a too-short
646 * timeout value.
647 */
648 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
649 return 0xE;
650
651 /* Unspecified timeout, assume max */
652 if (!data && !cmd->cmd_timeout_ms)
653 return 0xE;
654
655 /* timeout in us */
656 if (!data)
657 target_timeout = cmd->cmd_timeout_ms * 1000;
658 else {
659 target_timeout = data->timeout_ns / 1000;
660 if (host->clock)
661 target_timeout += data->timeout_clks / host->clock;
662 }
663
664 /*
665 * Figure out needed cycles.
666 * We do this in steps in order to fit inside a 32 bit int.
667 * The first step is the minimum timeout, which will have a
668 * minimum resolution of 6 bits:
669 * (1) 2^13*1000 > 2^22,
670 * (2) host->timeout_clk < 2^16
671 * =>
672 * (1) / (2) > 2^6
673 */
674 count = 0;
675 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
676 while (current_timeout < target_timeout) {
677 count++;
678 current_timeout <<= 1;
679 if (count >= 0xF)
680 break;
681 }
682
683 if (count >= 0xF) {
684 pr_warning("%s: Too large timeout requested for CMD%d!\n",
685 mmc_hostname(host->mmc), cmd->opcode);
686 count = 0xE;
687 }
688
689 return count;
690 }
691
sdhci_set_transfer_irqs(struct sdhci_host * host)692 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
693 {
694 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
695 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
696
697 if (host->flags & SDHCI_REQ_USE_DMA)
698 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
699 else
700 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
701 }
702
sdhci_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)703 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
704 {
705 u8 count;
706 u8 ctrl;
707 struct mmc_data *data = cmd->data;
708 int ret;
709
710 WARN_ON(host->data);
711
712 if (data || (cmd->flags & MMC_RSP_BUSY)) {
713 count = sdhci_calc_timeout(host, cmd);
714 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
715 }
716
717 if (!data)
718 return;
719
720 /* Sanity checks */
721 BUG_ON(data->blksz * data->blocks > 524288);
722 BUG_ON(data->blksz > host->mmc->max_blk_size);
723 BUG_ON(data->blocks > 65535);
724
725 host->data = data;
726 host->data_early = 0;
727 host->data->bytes_xfered = 0;
728
729 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
730 host->flags |= SDHCI_REQ_USE_DMA;
731
732 /*
733 * FIXME: This doesn't account for merging when mapping the
734 * scatterlist.
735 */
736 if (host->flags & SDHCI_REQ_USE_DMA) {
737 int broken, i;
738 struct scatterlist *sg;
739
740 broken = 0;
741 if (host->flags & SDHCI_USE_ADMA) {
742 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
743 broken = 1;
744 } else {
745 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
746 broken = 1;
747 }
748
749 if (unlikely(broken)) {
750 for_each_sg(data->sg, sg, data->sg_len, i) {
751 if (sg->length & 0x3) {
752 DBG("Reverting to PIO because of "
753 "transfer size (%d)\n",
754 sg->length);
755 host->flags &= ~SDHCI_REQ_USE_DMA;
756 break;
757 }
758 }
759 }
760 }
761
762 /*
763 * The assumption here being that alignment is the same after
764 * translation to device address space.
765 */
766 if (host->flags & SDHCI_REQ_USE_DMA) {
767 int broken, i;
768 struct scatterlist *sg;
769
770 broken = 0;
771 if (host->flags & SDHCI_USE_ADMA) {
772 /*
773 * As we use 3 byte chunks to work around
774 * alignment problems, we need to check this
775 * quirk.
776 */
777 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 broken = 1;
779 } else {
780 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
781 broken = 1;
782 }
783
784 if (unlikely(broken)) {
785 for_each_sg(data->sg, sg, data->sg_len, i) {
786 if (sg->offset & 0x3) {
787 DBG("Reverting to PIO because of "
788 "bad alignment\n");
789 host->flags &= ~SDHCI_REQ_USE_DMA;
790 break;
791 }
792 }
793 }
794 }
795
796 if (host->flags & SDHCI_REQ_USE_DMA) {
797 if (host->flags & SDHCI_USE_ADMA) {
798 ret = sdhci_adma_table_pre(host, data);
799 if (ret) {
800 /*
801 * This only happens when someone fed
802 * us an invalid request.
803 */
804 WARN_ON(1);
805 host->flags &= ~SDHCI_REQ_USE_DMA;
806 } else {
807 sdhci_writel(host, host->adma_addr,
808 SDHCI_ADMA_ADDRESS);
809 }
810 } else {
811 int sg_cnt;
812
813 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
814 data->sg, data->sg_len,
815 (data->flags & MMC_DATA_READ) ?
816 DMA_FROM_DEVICE :
817 DMA_TO_DEVICE);
818 if (sg_cnt == 0) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 WARN_ON(sg_cnt != 1);
827 sdhci_writel(host, sg_dma_address(data->sg),
828 SDHCI_DMA_ADDRESS);
829 }
830 }
831 }
832
833 /*
834 * Always adjust the DMA selection as some controllers
835 * (e.g. JMicron) can't do PIO properly when the selection
836 * is ADMA.
837 */
838 if (host->version >= SDHCI_SPEC_200) {
839 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
840 ctrl &= ~SDHCI_CTRL_DMA_MASK;
841 if ((host->flags & SDHCI_REQ_USE_DMA) &&
842 (host->flags & SDHCI_USE_ADMA))
843 ctrl |= SDHCI_CTRL_ADMA32;
844 else
845 ctrl |= SDHCI_CTRL_SDMA;
846 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
847 }
848
849 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
850 int flags;
851
852 flags = SG_MITER_ATOMIC;
853 if (host->data->flags & MMC_DATA_READ)
854 flags |= SG_MITER_TO_SG;
855 else
856 flags |= SG_MITER_FROM_SG;
857 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
858 host->blocks = data->blocks;
859 }
860
861 sdhci_set_transfer_irqs(host);
862
863 /* Set the DMA boundary value and block size */
864 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
865 data->blksz), SDHCI_BLOCK_SIZE);
866 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
867 }
868
sdhci_set_transfer_mode(struct sdhci_host * host,struct mmc_command * cmd)869 static void sdhci_set_transfer_mode(struct sdhci_host *host,
870 struct mmc_command *cmd)
871 {
872 u16 mode;
873 struct mmc_data *data = cmd->data;
874
875 if (data == NULL)
876 return;
877
878 WARN_ON(!host->data);
879
880 mode = SDHCI_TRNS_BLK_CNT_EN;
881 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
882 mode |= SDHCI_TRNS_MULTI;
883 /*
884 * If we are sending CMD23, CMD12 never gets sent
885 * on successful completion (so no Auto-CMD12).
886 */
887 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
888 mode |= SDHCI_TRNS_AUTO_CMD12;
889 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
890 mode |= SDHCI_TRNS_AUTO_CMD23;
891 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
892 }
893 }
894
895 if (data->flags & MMC_DATA_READ)
896 mode |= SDHCI_TRNS_READ;
897 if (host->flags & SDHCI_REQ_USE_DMA)
898 mode |= SDHCI_TRNS_DMA;
899
900 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
901 }
902
sdhci_finish_data(struct sdhci_host * host)903 static void sdhci_finish_data(struct sdhci_host *host)
904 {
905 struct mmc_data *data;
906
907 BUG_ON(!host->data);
908
909 data = host->data;
910 host->data = NULL;
911
912 if (host->flags & SDHCI_REQ_USE_DMA) {
913 if (host->flags & SDHCI_USE_ADMA)
914 sdhci_adma_table_post(host, data);
915 else {
916 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
917 data->sg_len, (data->flags & MMC_DATA_READ) ?
918 DMA_FROM_DEVICE : DMA_TO_DEVICE);
919 }
920 }
921
922 /*
923 * The specification states that the block count register must
924 * be updated, but it does not specify at what point in the
925 * data flow. That makes the register entirely useless to read
926 * back so we have to assume that nothing made it to the card
927 * in the event of an error.
928 */
929 if (data->error)
930 data->bytes_xfered = 0;
931 else
932 data->bytes_xfered = data->blksz * data->blocks;
933
934 /*
935 * Need to send CMD12 if -
936 * a) open-ended multiblock transfer (no CMD23)
937 * b) error in multiblock transfer
938 */
939 if (data->stop &&
940 (data->error ||
941 !host->mrq->sbc)) {
942
943 /*
944 * The controller needs a reset of internal state machines
945 * upon error conditions.
946 */
947 if (data->error) {
948 sdhci_reset(host, SDHCI_RESET_CMD);
949 sdhci_reset(host, SDHCI_RESET_DATA);
950 }
951
952 sdhci_send_command(host, data->stop);
953 } else
954 tasklet_schedule(&host->finish_tasklet);
955 }
956
sdhci_send_command(struct sdhci_host * host,struct mmc_command * cmd)957 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
958 {
959 int flags;
960 u32 mask;
961 unsigned long timeout;
962
963 WARN_ON(host->cmd);
964
965 /* Wait max 10 ms */
966 timeout = 10;
967
968 mask = SDHCI_CMD_INHIBIT;
969 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
970 mask |= SDHCI_DATA_INHIBIT;
971
972 /* We shouldn't wait for data inihibit for stop commands, even
973 though they might use busy signaling */
974 if (host->mrq->data && (cmd == host->mrq->data->stop))
975 mask &= ~SDHCI_DATA_INHIBIT;
976
977 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
978 if (timeout == 0) {
979 pr_err("%s: Controller never released "
980 "inhibit bit(s).\n", mmc_hostname(host->mmc));
981 sdhci_dumpregs(host);
982 cmd->error = -EIO;
983 tasklet_schedule(&host->finish_tasklet);
984 return;
985 }
986 timeout--;
987 mdelay(1);
988 }
989
990 mod_timer(&host->timer, jiffies + 10 * HZ);
991
992 host->cmd = cmd;
993
994 sdhci_prepare_data(host, cmd);
995
996 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
997
998 sdhci_set_transfer_mode(host, cmd);
999
1000 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1001 pr_err("%s: Unsupported response type!\n",
1002 mmc_hostname(host->mmc));
1003 cmd->error = -EINVAL;
1004 tasklet_schedule(&host->finish_tasklet);
1005 return;
1006 }
1007
1008 if (!(cmd->flags & MMC_RSP_PRESENT))
1009 flags = SDHCI_CMD_RESP_NONE;
1010 else if (cmd->flags & MMC_RSP_136)
1011 flags = SDHCI_CMD_RESP_LONG;
1012 else if (cmd->flags & MMC_RSP_BUSY)
1013 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1014 else
1015 flags = SDHCI_CMD_RESP_SHORT;
1016
1017 if (cmd->flags & MMC_RSP_CRC)
1018 flags |= SDHCI_CMD_CRC;
1019 if (cmd->flags & MMC_RSP_OPCODE)
1020 flags |= SDHCI_CMD_INDEX;
1021
1022 /* CMD19 is special in that the Data Present Select should be set */
1023 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1024 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1025 flags |= SDHCI_CMD_DATA;
1026
1027 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1028 }
1029
sdhci_finish_command(struct sdhci_host * host)1030 static void sdhci_finish_command(struct sdhci_host *host)
1031 {
1032 int i;
1033
1034 BUG_ON(host->cmd == NULL);
1035
1036 if (host->cmd->flags & MMC_RSP_PRESENT) {
1037 if (host->cmd->flags & MMC_RSP_136) {
1038 /* CRC is stripped so we need to do some shifting. */
1039 for (i = 0;i < 4;i++) {
1040 host->cmd->resp[i] = sdhci_readl(host,
1041 SDHCI_RESPONSE + (3-i)*4) << 8;
1042 if (i != 3)
1043 host->cmd->resp[i] |=
1044 sdhci_readb(host,
1045 SDHCI_RESPONSE + (3-i)*4-1);
1046 }
1047 } else {
1048 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1049 }
1050 }
1051
1052 host->cmd->error = 0;
1053
1054 /* Finished CMD23, now send actual command. */
1055 if (host->cmd == host->mrq->sbc) {
1056 host->cmd = NULL;
1057 sdhci_send_command(host, host->mrq->cmd);
1058 } else {
1059
1060 /* Processed actual command. */
1061 if (host->data && host->data_early)
1062 sdhci_finish_data(host);
1063
1064 if (!host->cmd->data)
1065 tasklet_schedule(&host->finish_tasklet);
1066
1067 host->cmd = NULL;
1068 }
1069 }
1070
sdhci_set_clock(struct sdhci_host * host,unsigned int clock)1071 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1072 {
1073 int div = 0; /* Initialized for compiler warning */
1074 int real_div = div, clk_mul = 1;
1075 u16 clk = 0;
1076 unsigned long timeout;
1077
1078 if (clock && clock == host->clock)
1079 return;
1080
1081 host->mmc->actual_clock = 0;
1082
1083 if (host->ops->set_clock) {
1084 host->ops->set_clock(host, clock);
1085 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1086 return;
1087 }
1088
1089 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1090
1091 if (clock == 0)
1092 goto out;
1093
1094 if (host->version >= SDHCI_SPEC_300) {
1095 /*
1096 * Check if the Host Controller supports Programmable Clock
1097 * Mode.
1098 */
1099 if (host->clk_mul) {
1100 u16 ctrl;
1101
1102 /*
1103 * We need to figure out whether the Host Driver needs
1104 * to select Programmable Clock Mode, or the value can
1105 * be set automatically by the Host Controller based on
1106 * the Preset Value registers.
1107 */
1108 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1109 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1110 for (div = 1; div <= 1024; div++) {
1111 if (((host->max_clk * host->clk_mul) /
1112 div) <= clock)
1113 break;
1114 }
1115 /*
1116 * Set Programmable Clock Mode in the Clock
1117 * Control register.
1118 */
1119 clk = SDHCI_PROG_CLOCK_MODE;
1120 real_div = div;
1121 clk_mul = host->clk_mul;
1122 div--;
1123 }
1124 } else {
1125 /* Version 3.00 divisors must be a multiple of 2. */
1126 if (host->max_clk <= clock)
1127 div = 1;
1128 else {
1129 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1130 div += 2) {
1131 if ((host->max_clk / div) <= clock)
1132 break;
1133 }
1134 }
1135 real_div = div;
1136 div >>= 1;
1137 }
1138 } else {
1139 /* Version 2.00 divisors must be a power of 2. */
1140 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1141 if ((host->max_clk / div) <= clock)
1142 break;
1143 }
1144 real_div = div;
1145 div >>= 1;
1146 }
1147
1148 if (real_div)
1149 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1150
1151 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1152 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1153 << SDHCI_DIVIDER_HI_SHIFT;
1154 clk |= SDHCI_CLOCK_INT_EN;
1155 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1156
1157 /* Wait max 20 ms */
1158 timeout = 20;
1159 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1160 & SDHCI_CLOCK_INT_STABLE)) {
1161 if (timeout == 0) {
1162 pr_err("%s: Internal clock never "
1163 "stabilised.\n", mmc_hostname(host->mmc));
1164 sdhci_dumpregs(host);
1165 return;
1166 }
1167 timeout--;
1168 mdelay(1);
1169 }
1170
1171 clk |= SDHCI_CLOCK_CARD_EN;
1172 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1173
1174 out:
1175 host->clock = clock;
1176 }
1177
sdhci_set_power(struct sdhci_host * host,unsigned short power)1178 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1179 {
1180 u8 pwr = 0;
1181
1182 if (power != (unsigned short)-1) {
1183 switch (1 << power) {
1184 case MMC_VDD_165_195:
1185 pwr = SDHCI_POWER_180;
1186 break;
1187 case MMC_VDD_29_30:
1188 case MMC_VDD_30_31:
1189 pwr = SDHCI_POWER_300;
1190 break;
1191 case MMC_VDD_32_33:
1192 case MMC_VDD_33_34:
1193 pwr = SDHCI_POWER_330;
1194 break;
1195 default:
1196 BUG();
1197 }
1198 }
1199
1200 if (host->pwr == pwr)
1201 return -1;
1202
1203 host->pwr = pwr;
1204
1205 if (pwr == 0) {
1206 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1207 return 0;
1208 }
1209
1210 /*
1211 * Spec says that we should clear the power reg before setting
1212 * a new value. Some controllers don't seem to like this though.
1213 */
1214 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1215 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1216
1217 /*
1218 * At least the Marvell CaFe chip gets confused if we set the voltage
1219 * and set turn on power at the same time, so set the voltage first.
1220 */
1221 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1222 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1223
1224 pwr |= SDHCI_POWER_ON;
1225
1226 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1227
1228 /*
1229 * Some controllers need an extra 10ms delay of 10ms before they
1230 * can apply clock after applying power
1231 */
1232 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1233 mdelay(10);
1234
1235 return power;
1236 }
1237
1238 /*****************************************************************************\
1239 * *
1240 * MMC callbacks *
1241 * *
1242 \*****************************************************************************/
1243
sdhci_request(struct mmc_host * mmc,struct mmc_request * mrq)1244 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245 {
1246 struct sdhci_host *host;
1247 bool present;
1248 unsigned long flags;
1249 u32 tuning_opcode;
1250
1251 host = mmc_priv(mmc);
1252
1253 sdhci_runtime_pm_get(host);
1254
1255 spin_lock_irqsave(&host->lock, flags);
1256
1257 WARN_ON(host->mrq != NULL);
1258
1259 #ifndef SDHCI_USE_LEDS_CLASS
1260 sdhci_activate_led(host);
1261 #endif
1262
1263 /*
1264 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1265 * requests if Auto-CMD12 is enabled.
1266 */
1267 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1268 if (mrq->stop) {
1269 mrq->data->stop = NULL;
1270 mrq->stop = NULL;
1271 }
1272 }
1273
1274 host->mrq = mrq;
1275
1276 /* If polling, assume that the card is always present. */
1277 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1278 present = true;
1279 else
1280 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1281 SDHCI_CARD_PRESENT;
1282
1283 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1284 host->mrq->cmd->error = -ENOMEDIUM;
1285 tasklet_schedule(&host->finish_tasklet);
1286 } else {
1287 u32 present_state;
1288
1289 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1290 /*
1291 * Check if the re-tuning timer has already expired and there
1292 * is no on-going data transfer. If so, we need to execute
1293 * tuning procedure before sending command.
1294 */
1295 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1296 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1297 if (mmc->card) {
1298 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1299 tuning_opcode =
1300 mmc->card->type == MMC_TYPE_MMC ?
1301 MMC_SEND_TUNING_BLOCK_HS200 :
1302 MMC_SEND_TUNING_BLOCK;
1303 spin_unlock_irqrestore(&host->lock, flags);
1304 sdhci_execute_tuning(mmc, tuning_opcode);
1305 spin_lock_irqsave(&host->lock, flags);
1306
1307 /* Restore original mmc_request structure */
1308 host->mrq = mrq;
1309 }
1310 }
1311
1312 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1313 sdhci_send_command(host, mrq->sbc);
1314 else
1315 sdhci_send_command(host, mrq->cmd);
1316 }
1317
1318 mmiowb();
1319 spin_unlock_irqrestore(&host->lock, flags);
1320 }
1321
sdhci_do_set_ios(struct sdhci_host * host,struct mmc_ios * ios)1322 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1323 {
1324 unsigned long flags;
1325 int vdd_bit = -1;
1326 u8 ctrl;
1327
1328 spin_lock_irqsave(&host->lock, flags);
1329
1330 if (host->flags & SDHCI_DEVICE_DEAD) {
1331 spin_unlock_irqrestore(&host->lock, flags);
1332 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1333 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1334 return;
1335 }
1336
1337 /*
1338 * Reset the chip on each power off.
1339 * Should clear out any weird states.
1340 */
1341 if (ios->power_mode == MMC_POWER_OFF) {
1342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1343 sdhci_reinit(host);
1344 }
1345
1346 sdhci_set_clock(host, ios->clock);
1347
1348 if (ios->power_mode == MMC_POWER_OFF)
1349 vdd_bit = sdhci_set_power(host, -1);
1350 else
1351 vdd_bit = sdhci_set_power(host, ios->vdd);
1352
1353 if (host->vmmc && vdd_bit != -1) {
1354 spin_unlock_irqrestore(&host->lock, flags);
1355 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1356 spin_lock_irqsave(&host->lock, flags);
1357 }
1358
1359 if (host->ops->platform_send_init_74_clocks)
1360 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1361
1362 /*
1363 * If your platform has 8-bit width support but is not a v3 controller,
1364 * or if it requires special setup code, you should implement that in
1365 * platform_8bit_width().
1366 */
1367 if (host->ops->platform_8bit_width)
1368 host->ops->platform_8bit_width(host, ios->bus_width);
1369 else {
1370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1371 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1372 ctrl &= ~SDHCI_CTRL_4BITBUS;
1373 if (host->version >= SDHCI_SPEC_300)
1374 ctrl |= SDHCI_CTRL_8BITBUS;
1375 } else {
1376 if (host->version >= SDHCI_SPEC_300)
1377 ctrl &= ~SDHCI_CTRL_8BITBUS;
1378 if (ios->bus_width == MMC_BUS_WIDTH_4)
1379 ctrl |= SDHCI_CTRL_4BITBUS;
1380 else
1381 ctrl &= ~SDHCI_CTRL_4BITBUS;
1382 }
1383 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1384 }
1385
1386 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1387
1388 if ((ios->timing == MMC_TIMING_SD_HS ||
1389 ios->timing == MMC_TIMING_MMC_HS)
1390 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1391 ctrl |= SDHCI_CTRL_HISPD;
1392 else
1393 ctrl &= ~SDHCI_CTRL_HISPD;
1394
1395 if (host->version >= SDHCI_SPEC_300) {
1396 u16 clk, ctrl_2;
1397 unsigned int clock;
1398
1399 /* In case of UHS-I modes, set High Speed Enable */
1400 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1401 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1402 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1403 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1404 (ios->timing == MMC_TIMING_UHS_SDR25))
1405 ctrl |= SDHCI_CTRL_HISPD;
1406
1407 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1408 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1409 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1410 /*
1411 * We only need to set Driver Strength if the
1412 * preset value enable is not set.
1413 */
1414 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1415 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1416 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1417 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1418 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1419
1420 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1421 } else {
1422 /*
1423 * According to SDHC Spec v3.00, if the Preset Value
1424 * Enable in the Host Control 2 register is set, we
1425 * need to reset SD Clock Enable before changing High
1426 * Speed Enable to avoid generating clock gliches.
1427 */
1428
1429 /* Reset SD Clock Enable */
1430 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1431 clk &= ~SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433
1434 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1435
1436 /* Re-enable SD Clock */
1437 clock = host->clock;
1438 host->clock = 0;
1439 sdhci_set_clock(host, clock);
1440 }
1441
1442
1443 /* Reset SD Clock Enable */
1444 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1445 clk &= ~SDHCI_CLOCK_CARD_EN;
1446 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1447
1448 if (host->ops->set_uhs_signaling)
1449 host->ops->set_uhs_signaling(host, ios->timing);
1450 else {
1451 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1452 /* Select Bus Speed Mode for host */
1453 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1454 if (ios->timing == MMC_TIMING_MMC_HS200)
1455 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1456 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1457 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1458 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1459 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1460 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1461 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1462 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1463 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1464 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1465 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1466 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1467 }
1468
1469 /* Re-enable SD Clock */
1470 clock = host->clock;
1471 host->clock = 0;
1472 sdhci_set_clock(host, clock);
1473 } else
1474 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1475
1476 /*
1477 * Some (ENE) controllers go apeshit on some ios operation,
1478 * signalling timeout and CRC errors even on CMD0. Resetting
1479 * it on each ios seems to solve the problem.
1480 */
1481 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1482 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1483
1484 mmiowb();
1485 spin_unlock_irqrestore(&host->lock, flags);
1486 }
1487
sdhci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1488 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1489 {
1490 struct sdhci_host *host = mmc_priv(mmc);
1491
1492 sdhci_runtime_pm_get(host);
1493 sdhci_do_set_ios(host, ios);
1494 sdhci_runtime_pm_put(host);
1495 }
1496
sdhci_check_ro(struct sdhci_host * host)1497 static int sdhci_check_ro(struct sdhci_host *host)
1498 {
1499 unsigned long flags;
1500 int is_readonly;
1501
1502 spin_lock_irqsave(&host->lock, flags);
1503
1504 if (host->flags & SDHCI_DEVICE_DEAD)
1505 is_readonly = 0;
1506 else if (host->ops->get_ro)
1507 is_readonly = host->ops->get_ro(host);
1508 else
1509 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1510 & SDHCI_WRITE_PROTECT);
1511
1512 spin_unlock_irqrestore(&host->lock, flags);
1513
1514 /* This quirk needs to be replaced by a callback-function later */
1515 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1516 !is_readonly : is_readonly;
1517 }
1518
1519 #define SAMPLE_COUNT 5
1520
sdhci_do_get_ro(struct sdhci_host * host)1521 static int sdhci_do_get_ro(struct sdhci_host *host)
1522 {
1523 int i, ro_count;
1524
1525 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1526 return sdhci_check_ro(host);
1527
1528 ro_count = 0;
1529 for (i = 0; i < SAMPLE_COUNT; i++) {
1530 if (sdhci_check_ro(host)) {
1531 if (++ro_count > SAMPLE_COUNT / 2)
1532 return 1;
1533 }
1534 msleep(30);
1535 }
1536 return 0;
1537 }
1538
sdhci_hw_reset(struct mmc_host * mmc)1539 static void sdhci_hw_reset(struct mmc_host *mmc)
1540 {
1541 struct sdhci_host *host = mmc_priv(mmc);
1542
1543 if (host->ops && host->ops->hw_reset)
1544 host->ops->hw_reset(host);
1545 }
1546
sdhci_get_ro(struct mmc_host * mmc)1547 static int sdhci_get_ro(struct mmc_host *mmc)
1548 {
1549 struct sdhci_host *host = mmc_priv(mmc);
1550 int ret;
1551
1552 sdhci_runtime_pm_get(host);
1553 ret = sdhci_do_get_ro(host);
1554 sdhci_runtime_pm_put(host);
1555 return ret;
1556 }
1557
sdhci_enable_sdio_irq_nolock(struct sdhci_host * host,int enable)1558 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1559 {
1560 if (host->flags & SDHCI_DEVICE_DEAD)
1561 goto out;
1562
1563 if (enable)
1564 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1565 else
1566 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1567
1568 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1569 if (host->runtime_suspended)
1570 goto out;
1571
1572 if (enable)
1573 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1574 else
1575 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1576 out:
1577 mmiowb();
1578 }
1579
sdhci_enable_sdio_irq(struct mmc_host * mmc,int enable)1580 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1581 {
1582 struct sdhci_host *host = mmc_priv(mmc);
1583 unsigned long flags;
1584
1585 spin_lock_irqsave(&host->lock, flags);
1586 sdhci_enable_sdio_irq_nolock(host, enable);
1587 spin_unlock_irqrestore(&host->lock, flags);
1588 }
1589
sdhci_do_start_signal_voltage_switch(struct sdhci_host * host,struct mmc_ios * ios)1590 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1591 struct mmc_ios *ios)
1592 {
1593 u8 pwr;
1594 u16 clk, ctrl;
1595 u32 present_state;
1596
1597 /*
1598 * Signal Voltage Switching is only applicable for Host Controllers
1599 * v3.00 and above.
1600 */
1601 if (host->version < SDHCI_SPEC_300)
1602 return 0;
1603
1604 /*
1605 * We first check whether the request is to set signalling voltage
1606 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1607 */
1608 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1609 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1610 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1611 ctrl &= ~SDHCI_CTRL_VDD_180;
1612 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1613
1614 /* Wait for 5ms */
1615 usleep_range(5000, 5500);
1616
1617 /* 3.3V regulator output should be stable within 5 ms */
1618 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1619 if (!(ctrl & SDHCI_CTRL_VDD_180))
1620 return 0;
1621 else {
1622 pr_info(DRIVER_NAME ": Switching to 3.3V "
1623 "signalling voltage failed\n");
1624 return -EIO;
1625 }
1626 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1627 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1628 /* Stop SDCLK */
1629 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1630 clk &= ~SDHCI_CLOCK_CARD_EN;
1631 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1632
1633 /* Check whether DAT[3:0] is 0000 */
1634 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1635 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1636 SDHCI_DATA_LVL_SHIFT)) {
1637 /*
1638 * Enable 1.8V Signal Enable in the Host Control2
1639 * register
1640 */
1641 ctrl |= SDHCI_CTRL_VDD_180;
1642 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1643
1644 /* Wait for 5ms */
1645 usleep_range(5000, 5500);
1646
1647 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1648 if (ctrl & SDHCI_CTRL_VDD_180) {
1649 /* Provide SDCLK again and wait for 1ms*/
1650 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1651 clk |= SDHCI_CLOCK_CARD_EN;
1652 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1653 usleep_range(1000, 1500);
1654
1655 /*
1656 * If DAT[3:0] level is 1111b, then the card
1657 * was successfully switched to 1.8V signaling.
1658 */
1659 present_state = sdhci_readl(host,
1660 SDHCI_PRESENT_STATE);
1661 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1662 SDHCI_DATA_LVL_MASK)
1663 return 0;
1664 }
1665 }
1666
1667 /*
1668 * If we are here, that means the switch to 1.8V signaling
1669 * failed. We power cycle the card, and retry initialization
1670 * sequence by setting S18R to 0.
1671 */
1672 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1673 pwr &= ~SDHCI_POWER_ON;
1674 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1675
1676 /* Wait for 1ms as per the spec */
1677 usleep_range(1000, 1500);
1678 pwr |= SDHCI_POWER_ON;
1679 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1680
1681 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1682 "voltage failed, retrying with S18R set to 0\n");
1683 return -EAGAIN;
1684 } else
1685 /* No signal voltage switch required */
1686 return 0;
1687 }
1688
sdhci_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1689 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1690 struct mmc_ios *ios)
1691 {
1692 struct sdhci_host *host = mmc_priv(mmc);
1693 int err;
1694
1695 if (host->version < SDHCI_SPEC_300)
1696 return 0;
1697 sdhci_runtime_pm_get(host);
1698 err = sdhci_do_start_signal_voltage_switch(host, ios);
1699 sdhci_runtime_pm_put(host);
1700 return err;
1701 }
1702
sdhci_execute_tuning(struct mmc_host * mmc,u32 opcode)1703 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1704 {
1705 struct sdhci_host *host;
1706 u16 ctrl;
1707 u32 ier;
1708 int tuning_loop_counter = MAX_TUNING_LOOP;
1709 unsigned long timeout;
1710 int err = 0;
1711 bool requires_tuning_nonuhs = false;
1712
1713 host = mmc_priv(mmc);
1714
1715 sdhci_runtime_pm_get(host);
1716 disable_irq(host->irq);
1717 spin_lock(&host->lock);
1718
1719 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1720
1721 /*
1722 * The Host Controller needs tuning only in case of SDR104 mode
1723 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1724 * Capabilities register.
1725 * If the Host Controller supports the HS200 mode then the
1726 * tuning function has to be executed.
1727 */
1728 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1729 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1730 host->flags & SDHCI_HS200_NEEDS_TUNING))
1731 requires_tuning_nonuhs = true;
1732
1733 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1734 requires_tuning_nonuhs)
1735 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1736 else {
1737 spin_unlock(&host->lock);
1738 enable_irq(host->irq);
1739 sdhci_runtime_pm_put(host);
1740 return 0;
1741 }
1742
1743 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1744
1745 /*
1746 * As per the Host Controller spec v3.00, tuning command
1747 * generates Buffer Read Ready interrupt, so enable that.
1748 *
1749 * Note: The spec clearly says that when tuning sequence
1750 * is being performed, the controller does not generate
1751 * interrupts other than Buffer Read Ready interrupt. But
1752 * to make sure we don't hit a controller bug, we _only_
1753 * enable Buffer Read Ready interrupt here.
1754 */
1755 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1756 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1757
1758 /*
1759 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1760 * of loops reaches 40 times or a timeout of 150ms occurs.
1761 */
1762 timeout = 150;
1763 do {
1764 struct mmc_command cmd = {0};
1765 struct mmc_request mrq = {NULL};
1766
1767 if (!tuning_loop_counter && !timeout)
1768 break;
1769
1770 cmd.opcode = opcode;
1771 cmd.arg = 0;
1772 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1773 cmd.retries = 0;
1774 cmd.data = NULL;
1775 cmd.error = 0;
1776
1777 mrq.cmd = &cmd;
1778 host->mrq = &mrq;
1779
1780 /*
1781 * In response to CMD19, the card sends 64 bytes of tuning
1782 * block to the Host Controller. So we set the block size
1783 * to 64 here.
1784 */
1785 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1786 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1787 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1788 SDHCI_BLOCK_SIZE);
1789 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1790 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1791 SDHCI_BLOCK_SIZE);
1792 } else {
1793 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1794 SDHCI_BLOCK_SIZE);
1795 }
1796
1797 /*
1798 * The tuning block is sent by the card to the host controller.
1799 * So we set the TRNS_READ bit in the Transfer Mode register.
1800 * This also takes care of setting DMA Enable and Multi Block
1801 * Select in the same register to 0.
1802 */
1803 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1804
1805 sdhci_send_command(host, &cmd);
1806
1807 host->cmd = NULL;
1808 host->mrq = NULL;
1809
1810 spin_unlock(&host->lock);
1811 enable_irq(host->irq);
1812
1813 /* Wait for Buffer Read Ready interrupt */
1814 wait_event_interruptible_timeout(host->buf_ready_int,
1815 (host->tuning_done == 1),
1816 msecs_to_jiffies(50));
1817 disable_irq(host->irq);
1818 spin_lock(&host->lock);
1819
1820 if (!host->tuning_done) {
1821 pr_info(DRIVER_NAME ": Timeout waiting for "
1822 "Buffer Read Ready interrupt during tuning "
1823 "procedure, falling back to fixed sampling "
1824 "clock\n");
1825 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1826 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1827 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1828 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1829
1830 err = -EIO;
1831 goto out;
1832 }
1833
1834 host->tuning_done = 0;
1835
1836 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1837 tuning_loop_counter--;
1838 timeout--;
1839 mdelay(1);
1840 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1841
1842 /*
1843 * The Host Driver has exhausted the maximum number of loops allowed,
1844 * so use fixed sampling frequency.
1845 */
1846 if (!tuning_loop_counter || !timeout) {
1847 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1848 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1849 } else {
1850 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1851 pr_info(DRIVER_NAME ": Tuning procedure"
1852 " failed, falling back to fixed sampling"
1853 " clock\n");
1854 err = -EIO;
1855 }
1856 }
1857
1858 out:
1859 /*
1860 * If this is the very first time we are here, we start the retuning
1861 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1862 * flag won't be set, we check this condition before actually starting
1863 * the timer.
1864 */
1865 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1866 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1867 mod_timer(&host->tuning_timer, jiffies +
1868 host->tuning_count * HZ);
1869 /* Tuning mode 1 limits the maximum data length to 4MB */
1870 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1871 } else {
1872 host->flags &= ~SDHCI_NEEDS_RETUNING;
1873 /* Reload the new initial value for timer */
1874 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1875 mod_timer(&host->tuning_timer, jiffies +
1876 host->tuning_count * HZ);
1877 }
1878
1879 /*
1880 * In case tuning fails, host controllers which support re-tuning can
1881 * try tuning again at a later time, when the re-tuning timer expires.
1882 * So for these controllers, we return 0. Since there might be other
1883 * controllers who do not have this capability, we return error for
1884 * them.
1885 */
1886 if (err && host->tuning_count &&
1887 host->tuning_mode == SDHCI_TUNING_MODE_1)
1888 err = 0;
1889
1890 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1891 spin_unlock(&host->lock);
1892 enable_irq(host->irq);
1893 sdhci_runtime_pm_put(host);
1894
1895 return err;
1896 }
1897
sdhci_do_enable_preset_value(struct sdhci_host * host,bool enable)1898 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1899 {
1900 u16 ctrl;
1901 unsigned long flags;
1902
1903 /* Host Controller v3.00 defines preset value registers */
1904 if (host->version < SDHCI_SPEC_300)
1905 return;
1906
1907 spin_lock_irqsave(&host->lock, flags);
1908
1909 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1910
1911 /*
1912 * We only enable or disable Preset Value if they are not already
1913 * enabled or disabled respectively. Otherwise, we bail out.
1914 */
1915 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1916 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1917 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1918 host->flags |= SDHCI_PV_ENABLED;
1919 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1920 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1921 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1922 host->flags &= ~SDHCI_PV_ENABLED;
1923 }
1924
1925 spin_unlock_irqrestore(&host->lock, flags);
1926 }
1927
sdhci_enable_preset_value(struct mmc_host * mmc,bool enable)1928 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1929 {
1930 struct sdhci_host *host = mmc_priv(mmc);
1931
1932 sdhci_runtime_pm_get(host);
1933 sdhci_do_enable_preset_value(host, enable);
1934 sdhci_runtime_pm_put(host);
1935 }
1936
1937 static const struct mmc_host_ops sdhci_ops = {
1938 .request = sdhci_request,
1939 .set_ios = sdhci_set_ios,
1940 .get_ro = sdhci_get_ro,
1941 .hw_reset = sdhci_hw_reset,
1942 .enable_sdio_irq = sdhci_enable_sdio_irq,
1943 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1944 .execute_tuning = sdhci_execute_tuning,
1945 .enable_preset_value = sdhci_enable_preset_value,
1946 };
1947
1948 /*****************************************************************************\
1949 * *
1950 * Tasklets *
1951 * *
1952 \*****************************************************************************/
1953
sdhci_tasklet_card(unsigned long param)1954 static void sdhci_tasklet_card(unsigned long param)
1955 {
1956 struct sdhci_host *host;
1957 unsigned long flags;
1958
1959 host = (struct sdhci_host*)param;
1960
1961 spin_lock_irqsave(&host->lock, flags);
1962
1963 /* Check host->mrq first in case we are runtime suspended */
1964 if (host->mrq &&
1965 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1966 pr_err("%s: Card removed during transfer!\n",
1967 mmc_hostname(host->mmc));
1968 pr_err("%s: Resetting controller.\n",
1969 mmc_hostname(host->mmc));
1970
1971 sdhci_reset(host, SDHCI_RESET_CMD);
1972 sdhci_reset(host, SDHCI_RESET_DATA);
1973
1974 host->mrq->cmd->error = -ENOMEDIUM;
1975 tasklet_schedule(&host->finish_tasklet);
1976 }
1977
1978 spin_unlock_irqrestore(&host->lock, flags);
1979
1980 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1981 }
1982
sdhci_tasklet_finish(unsigned long param)1983 static void sdhci_tasklet_finish(unsigned long param)
1984 {
1985 struct sdhci_host *host;
1986 unsigned long flags;
1987 struct mmc_request *mrq;
1988
1989 host = (struct sdhci_host*)param;
1990
1991 spin_lock_irqsave(&host->lock, flags);
1992
1993 /*
1994 * If this tasklet gets rescheduled while running, it will
1995 * be run again afterwards but without any active request.
1996 */
1997 if (!host->mrq) {
1998 spin_unlock_irqrestore(&host->lock, flags);
1999 return;
2000 }
2001
2002 del_timer(&host->timer);
2003
2004 mrq = host->mrq;
2005
2006 /*
2007 * The controller needs a reset of internal state machines
2008 * upon error conditions.
2009 */
2010 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2011 ((mrq->cmd && mrq->cmd->error) ||
2012 (mrq->data && (mrq->data->error ||
2013 (mrq->data->stop && mrq->data->stop->error))) ||
2014 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2015
2016 /* Some controllers need this kick or reset won't work here */
2017 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2018 unsigned int clock;
2019
2020 /* This is to force an update */
2021 clock = host->clock;
2022 host->clock = 0;
2023 sdhci_set_clock(host, clock);
2024 }
2025
2026 /* Spec says we should do both at the same time, but Ricoh
2027 controllers do not like that. */
2028 sdhci_reset(host, SDHCI_RESET_CMD);
2029 sdhci_reset(host, SDHCI_RESET_DATA);
2030 }
2031
2032 host->mrq = NULL;
2033 host->cmd = NULL;
2034 host->data = NULL;
2035
2036 #ifndef SDHCI_USE_LEDS_CLASS
2037 sdhci_deactivate_led(host);
2038 #endif
2039
2040 mmiowb();
2041 spin_unlock_irqrestore(&host->lock, flags);
2042
2043 mmc_request_done(host->mmc, mrq);
2044 sdhci_runtime_pm_put(host);
2045 }
2046
sdhci_timeout_timer(unsigned long data)2047 static void sdhci_timeout_timer(unsigned long data)
2048 {
2049 struct sdhci_host *host;
2050 unsigned long flags;
2051
2052 host = (struct sdhci_host*)data;
2053
2054 spin_lock_irqsave(&host->lock, flags);
2055
2056 if (host->mrq) {
2057 pr_err("%s: Timeout waiting for hardware "
2058 "interrupt.\n", mmc_hostname(host->mmc));
2059 sdhci_dumpregs(host);
2060
2061 if (host->data) {
2062 host->data->error = -ETIMEDOUT;
2063 sdhci_finish_data(host);
2064 } else {
2065 if (host->cmd)
2066 host->cmd->error = -ETIMEDOUT;
2067 else
2068 host->mrq->cmd->error = -ETIMEDOUT;
2069
2070 tasklet_schedule(&host->finish_tasklet);
2071 }
2072 }
2073
2074 mmiowb();
2075 spin_unlock_irqrestore(&host->lock, flags);
2076 }
2077
sdhci_tuning_timer(unsigned long data)2078 static void sdhci_tuning_timer(unsigned long data)
2079 {
2080 struct sdhci_host *host;
2081 unsigned long flags;
2082
2083 host = (struct sdhci_host *)data;
2084
2085 spin_lock_irqsave(&host->lock, flags);
2086
2087 host->flags |= SDHCI_NEEDS_RETUNING;
2088
2089 spin_unlock_irqrestore(&host->lock, flags);
2090 }
2091
2092 /*****************************************************************************\
2093 * *
2094 * Interrupt handling *
2095 * *
2096 \*****************************************************************************/
2097
sdhci_cmd_irq(struct sdhci_host * host,u32 intmask)2098 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2099 {
2100 BUG_ON(intmask == 0);
2101
2102 if (!host->cmd) {
2103 pr_err("%s: Got command interrupt 0x%08x even "
2104 "though no command operation was in progress.\n",
2105 mmc_hostname(host->mmc), (unsigned)intmask);
2106 sdhci_dumpregs(host);
2107 return;
2108 }
2109
2110 if (intmask & SDHCI_INT_TIMEOUT)
2111 host->cmd->error = -ETIMEDOUT;
2112 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2113 SDHCI_INT_INDEX))
2114 host->cmd->error = -EILSEQ;
2115
2116 if (host->cmd->error) {
2117 tasklet_schedule(&host->finish_tasklet);
2118 return;
2119 }
2120
2121 /*
2122 * The host can send and interrupt when the busy state has
2123 * ended, allowing us to wait without wasting CPU cycles.
2124 * Unfortunately this is overloaded on the "data complete"
2125 * interrupt, so we need to take some care when handling
2126 * it.
2127 *
2128 * Note: The 1.0 specification is a bit ambiguous about this
2129 * feature so there might be some problems with older
2130 * controllers.
2131 */
2132 if (host->cmd->flags & MMC_RSP_BUSY) {
2133 if (host->cmd->data)
2134 DBG("Cannot wait for busy signal when also "
2135 "doing a data transfer");
2136 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2137 return;
2138
2139 /* The controller does not support the end-of-busy IRQ,
2140 * fall through and take the SDHCI_INT_RESPONSE */
2141 }
2142
2143 if (intmask & SDHCI_INT_RESPONSE)
2144 sdhci_finish_command(host);
2145 }
2146
2147 #ifdef CONFIG_MMC_DEBUG
sdhci_show_adma_error(struct sdhci_host * host)2148 static void sdhci_show_adma_error(struct sdhci_host *host)
2149 {
2150 const char *name = mmc_hostname(host->mmc);
2151 u8 *desc = host->adma_desc;
2152 __le32 *dma;
2153 __le16 *len;
2154 u8 attr;
2155
2156 sdhci_dumpregs(host);
2157
2158 while (true) {
2159 dma = (__le32 *)(desc + 4);
2160 len = (__le16 *)(desc + 2);
2161 attr = *desc;
2162
2163 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2164 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2165
2166 desc += 8;
2167
2168 if (attr & 2)
2169 break;
2170 }
2171 }
2172 #else
sdhci_show_adma_error(struct sdhci_host * host)2173 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2174 #endif
2175
sdhci_data_irq(struct sdhci_host * host,u32 intmask)2176 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2177 {
2178 u32 command;
2179 BUG_ON(intmask == 0);
2180
2181 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2182 if (intmask & SDHCI_INT_DATA_AVAIL) {
2183 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2184 if (command == MMC_SEND_TUNING_BLOCK ||
2185 command == MMC_SEND_TUNING_BLOCK_HS200) {
2186 host->tuning_done = 1;
2187 wake_up(&host->buf_ready_int);
2188 return;
2189 }
2190 }
2191
2192 if (!host->data) {
2193 /*
2194 * The "data complete" interrupt is also used to
2195 * indicate that a busy state has ended. See comment
2196 * above in sdhci_cmd_irq().
2197 */
2198 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2199 if (intmask & SDHCI_INT_DATA_END) {
2200 sdhci_finish_command(host);
2201 return;
2202 }
2203 }
2204
2205 pr_err("%s: Got data interrupt 0x%08x even "
2206 "though no data operation was in progress.\n",
2207 mmc_hostname(host->mmc), (unsigned)intmask);
2208 sdhci_dumpregs(host);
2209
2210 return;
2211 }
2212
2213 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2214 host->data->error = -ETIMEDOUT;
2215 else if (intmask & SDHCI_INT_DATA_END_BIT)
2216 host->data->error = -EILSEQ;
2217 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2218 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2219 != MMC_BUS_TEST_R)
2220 host->data->error = -EILSEQ;
2221 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2222 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2223 sdhci_show_adma_error(host);
2224 host->data->error = -EIO;
2225 }
2226
2227 if (host->data->error)
2228 sdhci_finish_data(host);
2229 else {
2230 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2231 sdhci_transfer_pio(host);
2232
2233 /*
2234 * We currently don't do anything fancy with DMA
2235 * boundaries, but as we can't disable the feature
2236 * we need to at least restart the transfer.
2237 *
2238 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2239 * should return a valid address to continue from, but as
2240 * some controllers are faulty, don't trust them.
2241 */
2242 if (intmask & SDHCI_INT_DMA_END) {
2243 u32 dmastart, dmanow;
2244 dmastart = sg_dma_address(host->data->sg);
2245 dmanow = dmastart + host->data->bytes_xfered;
2246 /*
2247 * Force update to the next DMA block boundary.
2248 */
2249 dmanow = (dmanow &
2250 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2251 SDHCI_DEFAULT_BOUNDARY_SIZE;
2252 host->data->bytes_xfered = dmanow - dmastart;
2253 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2254 " next 0x%08x\n",
2255 mmc_hostname(host->mmc), dmastart,
2256 host->data->bytes_xfered, dmanow);
2257 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2258 }
2259
2260 if (intmask & SDHCI_INT_DATA_END) {
2261 if (host->cmd) {
2262 /*
2263 * Data managed to finish before the
2264 * command completed. Make sure we do
2265 * things in the proper order.
2266 */
2267 host->data_early = 1;
2268 } else {
2269 sdhci_finish_data(host);
2270 }
2271 }
2272 }
2273 }
2274
sdhci_irq(int irq,void * dev_id)2275 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2276 {
2277 irqreturn_t result;
2278 struct sdhci_host *host = dev_id;
2279 u32 intmask, unexpected = 0;
2280 int cardint = 0, max_loops = 16;
2281
2282 spin_lock(&host->lock);
2283
2284 if (host->runtime_suspended) {
2285 spin_unlock(&host->lock);
2286 pr_warning("%s: got irq while runtime suspended\n",
2287 mmc_hostname(host->mmc));
2288 return IRQ_HANDLED;
2289 }
2290
2291 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2292
2293 if (!intmask || intmask == 0xffffffff) {
2294 result = IRQ_NONE;
2295 goto out;
2296 }
2297
2298 again:
2299 DBG("*** %s got interrupt: 0x%08x\n",
2300 mmc_hostname(host->mmc), intmask);
2301
2302 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2303 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2304 SDHCI_CARD_PRESENT;
2305
2306 /*
2307 * There is a observation on i.mx esdhc. INSERT bit will be
2308 * immediately set again when it gets cleared, if a card is
2309 * inserted. We have to mask the irq to prevent interrupt
2310 * storm which will freeze the system. And the REMOVE gets
2311 * the same situation.
2312 *
2313 * More testing are needed here to ensure it works for other
2314 * platforms though.
2315 */
2316 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2317 SDHCI_INT_CARD_REMOVE);
2318 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2319 SDHCI_INT_CARD_INSERT);
2320
2321 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2322 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2323 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2324 tasklet_schedule(&host->card_tasklet);
2325 }
2326
2327 if (intmask & SDHCI_INT_CMD_MASK) {
2328 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2329 SDHCI_INT_STATUS);
2330 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2331 }
2332
2333 if (intmask & SDHCI_INT_DATA_MASK) {
2334 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2335 SDHCI_INT_STATUS);
2336 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2337 }
2338
2339 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2340
2341 intmask &= ~SDHCI_INT_ERROR;
2342
2343 if (intmask & SDHCI_INT_BUS_POWER) {
2344 pr_err("%s: Card is consuming too much power!\n",
2345 mmc_hostname(host->mmc));
2346 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2347 }
2348
2349 intmask &= ~SDHCI_INT_BUS_POWER;
2350
2351 if (intmask & SDHCI_INT_CARD_INT)
2352 cardint = 1;
2353
2354 intmask &= ~SDHCI_INT_CARD_INT;
2355
2356 if (intmask) {
2357 unexpected |= intmask;
2358 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2359 }
2360
2361 result = IRQ_HANDLED;
2362
2363 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2364 if (intmask && --max_loops)
2365 goto again;
2366 out:
2367 spin_unlock(&host->lock);
2368
2369 if (unexpected) {
2370 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2371 mmc_hostname(host->mmc), unexpected);
2372 sdhci_dumpregs(host);
2373 }
2374 /*
2375 * We have to delay this as it calls back into the driver.
2376 */
2377 if (cardint)
2378 mmc_signal_sdio_irq(host->mmc);
2379
2380 return result;
2381 }
2382
2383 /*****************************************************************************\
2384 * *
2385 * Suspend/resume *
2386 * *
2387 \*****************************************************************************/
2388
2389 #ifdef CONFIG_PM
2390
sdhci_suspend_host(struct sdhci_host * host)2391 int sdhci_suspend_host(struct sdhci_host *host)
2392 {
2393 int ret;
2394 bool has_tuning_timer;
2395
2396 if (host->ops->platform_suspend)
2397 host->ops->platform_suspend(host);
2398
2399 sdhci_disable_card_detection(host);
2400
2401 /* Disable tuning since we are suspending */
2402 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2403 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2404 if (has_tuning_timer) {
2405 del_timer_sync(&host->tuning_timer);
2406 host->flags &= ~SDHCI_NEEDS_RETUNING;
2407 }
2408
2409 ret = mmc_suspend_host(host->mmc);
2410 if (ret) {
2411 if (has_tuning_timer) {
2412 host->flags |= SDHCI_NEEDS_RETUNING;
2413 mod_timer(&host->tuning_timer, jiffies +
2414 host->tuning_count * HZ);
2415 }
2416
2417 sdhci_enable_card_detection(host);
2418
2419 return ret;
2420 }
2421
2422 free_irq(host->irq, host);
2423
2424 return ret;
2425 }
2426
2427 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2428
sdhci_resume_host(struct sdhci_host * host)2429 int sdhci_resume_host(struct sdhci_host *host)
2430 {
2431 int ret;
2432
2433 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2434 if (host->ops->enable_dma)
2435 host->ops->enable_dma(host);
2436 }
2437
2438 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2439 mmc_hostname(host->mmc), host);
2440 if (ret)
2441 return ret;
2442
2443 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2444 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2445 /* Card keeps power but host controller does not */
2446 sdhci_init(host, 0);
2447 host->pwr = 0;
2448 host->clock = 0;
2449 sdhci_do_set_ios(host, &host->mmc->ios);
2450 } else {
2451 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2452 mmiowb();
2453 }
2454
2455 ret = mmc_resume_host(host->mmc);
2456 sdhci_enable_card_detection(host);
2457
2458 if (host->ops->platform_resume)
2459 host->ops->platform_resume(host);
2460
2461 /* Set the re-tuning expiration flag */
2462 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2463 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2464 host->flags |= SDHCI_NEEDS_RETUNING;
2465
2466 return ret;
2467 }
2468
2469 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2470
sdhci_enable_irq_wakeups(struct sdhci_host * host)2471 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2472 {
2473 u8 val;
2474 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2475 val |= SDHCI_WAKE_ON_INT;
2476 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2477 }
2478
2479 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2480
2481 #endif /* CONFIG_PM */
2482
2483 #ifdef CONFIG_PM_RUNTIME
2484
sdhci_runtime_pm_get(struct sdhci_host * host)2485 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2486 {
2487 return pm_runtime_get_sync(host->mmc->parent);
2488 }
2489
sdhci_runtime_pm_put(struct sdhci_host * host)2490 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2491 {
2492 pm_runtime_mark_last_busy(host->mmc->parent);
2493 return pm_runtime_put_autosuspend(host->mmc->parent);
2494 }
2495
sdhci_runtime_suspend_host(struct sdhci_host * host)2496 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2497 {
2498 unsigned long flags;
2499 int ret = 0;
2500
2501 /* Disable tuning since we are suspending */
2502 if (host->version >= SDHCI_SPEC_300 &&
2503 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2504 del_timer_sync(&host->tuning_timer);
2505 host->flags &= ~SDHCI_NEEDS_RETUNING;
2506 }
2507
2508 spin_lock_irqsave(&host->lock, flags);
2509 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2510 spin_unlock_irqrestore(&host->lock, flags);
2511
2512 synchronize_irq(host->irq);
2513
2514 spin_lock_irqsave(&host->lock, flags);
2515 host->runtime_suspended = true;
2516 spin_unlock_irqrestore(&host->lock, flags);
2517
2518 return ret;
2519 }
2520 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2521
sdhci_runtime_resume_host(struct sdhci_host * host)2522 int sdhci_runtime_resume_host(struct sdhci_host *host)
2523 {
2524 unsigned long flags;
2525 int ret = 0, host_flags = host->flags;
2526
2527 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2528 if (host->ops->enable_dma)
2529 host->ops->enable_dma(host);
2530 }
2531
2532 sdhci_init(host, 0);
2533
2534 /* Force clock and power re-program */
2535 host->pwr = 0;
2536 host->clock = 0;
2537 sdhci_do_set_ios(host, &host->mmc->ios);
2538
2539 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2540 if (host_flags & SDHCI_PV_ENABLED)
2541 sdhci_do_enable_preset_value(host, true);
2542
2543 /* Set the re-tuning expiration flag */
2544 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2545 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2546 host->flags |= SDHCI_NEEDS_RETUNING;
2547
2548 spin_lock_irqsave(&host->lock, flags);
2549
2550 host->runtime_suspended = false;
2551
2552 /* Enable SDIO IRQ */
2553 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2554 sdhci_enable_sdio_irq_nolock(host, true);
2555
2556 /* Enable Card Detection */
2557 sdhci_enable_card_detection(host);
2558
2559 spin_unlock_irqrestore(&host->lock, flags);
2560
2561 return ret;
2562 }
2563 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2564
2565 #endif
2566
2567 /*****************************************************************************\
2568 * *
2569 * Device allocation/registration *
2570 * *
2571 \*****************************************************************************/
2572
sdhci_alloc_host(struct device * dev,size_t priv_size)2573 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2574 size_t priv_size)
2575 {
2576 struct mmc_host *mmc;
2577 struct sdhci_host *host;
2578
2579 WARN_ON(dev == NULL);
2580
2581 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2582 if (!mmc)
2583 return ERR_PTR(-ENOMEM);
2584
2585 host = mmc_priv(mmc);
2586 host->mmc = mmc;
2587
2588 return host;
2589 }
2590
2591 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2592
sdhci_add_host(struct sdhci_host * host)2593 int sdhci_add_host(struct sdhci_host *host)
2594 {
2595 struct mmc_host *mmc;
2596 u32 caps[2];
2597 u32 max_current_caps;
2598 unsigned int ocr_avail;
2599 int ret;
2600
2601 WARN_ON(host == NULL);
2602 if (host == NULL)
2603 return -EINVAL;
2604
2605 mmc = host->mmc;
2606
2607 if (debug_quirks)
2608 host->quirks = debug_quirks;
2609 if (debug_quirks2)
2610 host->quirks2 = debug_quirks2;
2611
2612 sdhci_reset(host, SDHCI_RESET_ALL);
2613
2614 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2615 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2616 >> SDHCI_SPEC_VER_SHIFT;
2617 if (host->version > SDHCI_SPEC_300) {
2618 pr_err("%s: Unknown controller version (%d). "
2619 "You may experience problems.\n", mmc_hostname(mmc),
2620 host->version);
2621 }
2622
2623 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2624 sdhci_readl(host, SDHCI_CAPABILITIES);
2625
2626 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2627 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2628
2629 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2630 host->flags |= SDHCI_USE_SDMA;
2631 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2632 DBG("Controller doesn't have SDMA capability\n");
2633 else
2634 host->flags |= SDHCI_USE_SDMA;
2635
2636 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2637 (host->flags & SDHCI_USE_SDMA)) {
2638 DBG("Disabling DMA as it is marked broken\n");
2639 host->flags &= ~SDHCI_USE_SDMA;
2640 }
2641
2642 if ((host->version >= SDHCI_SPEC_200) &&
2643 (caps[0] & SDHCI_CAN_DO_ADMA2))
2644 host->flags |= SDHCI_USE_ADMA;
2645
2646 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2647 (host->flags & SDHCI_USE_ADMA)) {
2648 DBG("Disabling ADMA as it is marked broken\n");
2649 host->flags &= ~SDHCI_USE_ADMA;
2650 }
2651
2652 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2653 if (host->ops->enable_dma) {
2654 if (host->ops->enable_dma(host)) {
2655 pr_warning("%s: No suitable DMA "
2656 "available. Falling back to PIO.\n",
2657 mmc_hostname(mmc));
2658 host->flags &=
2659 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2660 }
2661 }
2662 }
2663
2664 if (host->flags & SDHCI_USE_ADMA) {
2665 /*
2666 * We need to allocate descriptors for all sg entries
2667 * (128) and potentially one alignment transfer for
2668 * each of those entries.
2669 */
2670 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2671 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2672 if (!host->adma_desc || !host->align_buffer) {
2673 kfree(host->adma_desc);
2674 kfree(host->align_buffer);
2675 pr_warning("%s: Unable to allocate ADMA "
2676 "buffers. Falling back to standard DMA.\n",
2677 mmc_hostname(mmc));
2678 host->flags &= ~SDHCI_USE_ADMA;
2679 }
2680 }
2681
2682 /*
2683 * If we use DMA, then it's up to the caller to set the DMA
2684 * mask, but PIO does not need the hw shim so we set a new
2685 * mask here in that case.
2686 */
2687 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2688 host->dma_mask = DMA_BIT_MASK(64);
2689 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2690 }
2691
2692 if (host->version >= SDHCI_SPEC_300)
2693 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2694 >> SDHCI_CLOCK_BASE_SHIFT;
2695 else
2696 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2697 >> SDHCI_CLOCK_BASE_SHIFT;
2698
2699 host->max_clk *= 1000000;
2700 if (host->max_clk == 0 || host->quirks &
2701 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2702 if (!host->ops->get_max_clock) {
2703 pr_err("%s: Hardware doesn't specify base clock "
2704 "frequency.\n", mmc_hostname(mmc));
2705 return -ENODEV;
2706 }
2707 host->max_clk = host->ops->get_max_clock(host);
2708 }
2709
2710 /*
2711 * In case of Host Controller v3.00, find out whether clock
2712 * multiplier is supported.
2713 */
2714 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2715 SDHCI_CLOCK_MUL_SHIFT;
2716
2717 /*
2718 * In case the value in Clock Multiplier is 0, then programmable
2719 * clock mode is not supported, otherwise the actual clock
2720 * multiplier is one more than the value of Clock Multiplier
2721 * in the Capabilities Register.
2722 */
2723 if (host->clk_mul)
2724 host->clk_mul += 1;
2725
2726 /*
2727 * Set host parameters.
2728 */
2729 mmc->ops = &sdhci_ops;
2730 mmc->f_max = host->max_clk;
2731 if (host->ops->get_min_clock)
2732 mmc->f_min = host->ops->get_min_clock(host);
2733 else if (host->version >= SDHCI_SPEC_300) {
2734 if (host->clk_mul) {
2735 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2736 mmc->f_max = host->max_clk * host->clk_mul;
2737 } else
2738 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2739 } else
2740 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2741
2742 host->timeout_clk =
2743 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2744 if (host->timeout_clk == 0) {
2745 if (host->ops->get_timeout_clock) {
2746 host->timeout_clk = host->ops->get_timeout_clock(host);
2747 } else if (!(host->quirks &
2748 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2749 pr_err("%s: Hardware doesn't specify timeout clock "
2750 "frequency.\n", mmc_hostname(mmc));
2751 return -ENODEV;
2752 }
2753 }
2754 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2755 host->timeout_clk *= 1000;
2756
2757 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2758 host->timeout_clk = mmc->f_max / 1000;
2759
2760 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2761
2762 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2763
2764 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2765 host->flags |= SDHCI_AUTO_CMD12;
2766
2767 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2768 if ((host->version >= SDHCI_SPEC_300) &&
2769 ((host->flags & SDHCI_USE_ADMA) ||
2770 !(host->flags & SDHCI_USE_SDMA))) {
2771 host->flags |= SDHCI_AUTO_CMD23;
2772 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2773 } else {
2774 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2775 }
2776
2777 /*
2778 * A controller may support 8-bit width, but the board itself
2779 * might not have the pins brought out. Boards that support
2780 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2781 * their platform code before calling sdhci_add_host(), and we
2782 * won't assume 8-bit width for hosts without that CAP.
2783 */
2784 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2785 mmc->caps |= MMC_CAP_4_BIT_DATA;
2786
2787 if (caps[0] & SDHCI_CAN_DO_HISPD)
2788 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2789
2790 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2791 mmc_card_is_removable(mmc))
2792 mmc->caps |= MMC_CAP_NEEDS_POLL;
2793
2794 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2795 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2796 SDHCI_SUPPORT_DDR50))
2797 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2798
2799 /* SDR104 supports also implies SDR50 support */
2800 if (caps[1] & SDHCI_SUPPORT_SDR104)
2801 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2802 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2803 mmc->caps |= MMC_CAP_UHS_SDR50;
2804
2805 if (caps[1] & SDHCI_SUPPORT_DDR50)
2806 mmc->caps |= MMC_CAP_UHS_DDR50;
2807
2808 /* Does the host need tuning for SDR50? */
2809 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2810 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2811
2812 /* Does the host need tuning for HS200? */
2813 if (mmc->caps2 & MMC_CAP2_HS200)
2814 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2815
2816 /* Driver Type(s) (A, C, D) supported by the host */
2817 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2818 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2819 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2820 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2821 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2822 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2823
2824 /*
2825 * If Power Off Notify capability is enabled by the host,
2826 * set notify to short power off notify timeout value.
2827 */
2828 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2829 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2830 else
2831 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2832
2833 /* Initial value for re-tuning timer count */
2834 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2835 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2836
2837 /*
2838 * In case Re-tuning Timer is not disabled, the actual value of
2839 * re-tuning timer will be 2 ^ (n - 1).
2840 */
2841 if (host->tuning_count)
2842 host->tuning_count = 1 << (host->tuning_count - 1);
2843
2844 /* Re-tuning mode supported by the Host Controller */
2845 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2846 SDHCI_RETUNING_MODE_SHIFT;
2847
2848 ocr_avail = 0;
2849 /*
2850 * According to SD Host Controller spec v3.00, if the Host System
2851 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2852 * the value is meaningful only if Voltage Support in the Capabilities
2853 * register is set. The actual current value is 4 times the register
2854 * value.
2855 */
2856 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2857
2858 if (caps[0] & SDHCI_CAN_VDD_330) {
2859 int max_current_330;
2860
2861 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2862
2863 max_current_330 = ((max_current_caps &
2864 SDHCI_MAX_CURRENT_330_MASK) >>
2865 SDHCI_MAX_CURRENT_330_SHIFT) *
2866 SDHCI_MAX_CURRENT_MULTIPLIER;
2867
2868 if (max_current_330 > 150)
2869 mmc->caps |= MMC_CAP_SET_XPC_330;
2870 }
2871 if (caps[0] & SDHCI_CAN_VDD_300) {
2872 int max_current_300;
2873
2874 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2875
2876 max_current_300 = ((max_current_caps &
2877 SDHCI_MAX_CURRENT_300_MASK) >>
2878 SDHCI_MAX_CURRENT_300_SHIFT) *
2879 SDHCI_MAX_CURRENT_MULTIPLIER;
2880
2881 if (max_current_300 > 150)
2882 mmc->caps |= MMC_CAP_SET_XPC_300;
2883 }
2884 if (caps[0] & SDHCI_CAN_VDD_180) {
2885 int max_current_180;
2886
2887 ocr_avail |= MMC_VDD_165_195;
2888
2889 max_current_180 = ((max_current_caps &
2890 SDHCI_MAX_CURRENT_180_MASK) >>
2891 SDHCI_MAX_CURRENT_180_SHIFT) *
2892 SDHCI_MAX_CURRENT_MULTIPLIER;
2893
2894 if (max_current_180 > 150)
2895 mmc->caps |= MMC_CAP_SET_XPC_180;
2896
2897 /* Maximum current capabilities of the host at 1.8V */
2898 if (max_current_180 >= 800)
2899 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2900 else if (max_current_180 >= 600)
2901 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2902 else if (max_current_180 >= 400)
2903 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2904 else
2905 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2906 }
2907
2908 mmc->ocr_avail = ocr_avail;
2909 mmc->ocr_avail_sdio = ocr_avail;
2910 if (host->ocr_avail_sdio)
2911 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2912 mmc->ocr_avail_sd = ocr_avail;
2913 if (host->ocr_avail_sd)
2914 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2915 else /* normal SD controllers don't support 1.8V */
2916 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2917 mmc->ocr_avail_mmc = ocr_avail;
2918 if (host->ocr_avail_mmc)
2919 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2920
2921 if (mmc->ocr_avail == 0) {
2922 pr_err("%s: Hardware doesn't report any "
2923 "support voltages.\n", mmc_hostname(mmc));
2924 return -ENODEV;
2925 }
2926
2927 spin_lock_init(&host->lock);
2928
2929 /*
2930 * Maximum number of segments. Depends on if the hardware
2931 * can do scatter/gather or not.
2932 */
2933 if (host->flags & SDHCI_USE_ADMA)
2934 mmc->max_segs = 128;
2935 else if (host->flags & SDHCI_USE_SDMA)
2936 mmc->max_segs = 1;
2937 else /* PIO */
2938 mmc->max_segs = 128;
2939
2940 /*
2941 * Maximum number of sectors in one transfer. Limited by DMA boundary
2942 * size (512KiB).
2943 */
2944 mmc->max_req_size = 524288;
2945
2946 /*
2947 * Maximum segment size. Could be one segment with the maximum number
2948 * of bytes. When doing hardware scatter/gather, each entry cannot
2949 * be larger than 64 KiB though.
2950 */
2951 if (host->flags & SDHCI_USE_ADMA) {
2952 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2953 mmc->max_seg_size = 65535;
2954 else
2955 mmc->max_seg_size = 65536;
2956 } else {
2957 mmc->max_seg_size = mmc->max_req_size;
2958 }
2959
2960 /*
2961 * Maximum block size. This varies from controller to controller and
2962 * is specified in the capabilities register.
2963 */
2964 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2965 mmc->max_blk_size = 2;
2966 } else {
2967 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2968 SDHCI_MAX_BLOCK_SHIFT;
2969 if (mmc->max_blk_size >= 3) {
2970 pr_warning("%s: Invalid maximum block size, "
2971 "assuming 512 bytes\n", mmc_hostname(mmc));
2972 mmc->max_blk_size = 0;
2973 }
2974 }
2975
2976 mmc->max_blk_size = 512 << mmc->max_blk_size;
2977
2978 /*
2979 * Maximum block count.
2980 */
2981 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2982
2983 /*
2984 * Init tasklets.
2985 */
2986 tasklet_init(&host->card_tasklet,
2987 sdhci_tasklet_card, (unsigned long)host);
2988 tasklet_init(&host->finish_tasklet,
2989 sdhci_tasklet_finish, (unsigned long)host);
2990
2991 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2992
2993 if (host->version >= SDHCI_SPEC_300) {
2994 init_waitqueue_head(&host->buf_ready_int);
2995
2996 /* Initialize re-tuning timer */
2997 init_timer(&host->tuning_timer);
2998 host->tuning_timer.data = (unsigned long)host;
2999 host->tuning_timer.function = sdhci_tuning_timer;
3000 }
3001
3002 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3003 mmc_hostname(mmc), host);
3004 if (ret)
3005 goto untasklet;
3006
3007 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3008 if (IS_ERR(host->vmmc)) {
3009 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3010 host->vmmc = NULL;
3011 }
3012
3013 sdhci_init(host, 0);
3014
3015 #ifdef CONFIG_MMC_DEBUG
3016 sdhci_dumpregs(host);
3017 #endif
3018
3019 #ifdef SDHCI_USE_LEDS_CLASS
3020 snprintf(host->led_name, sizeof(host->led_name),
3021 "%s::", mmc_hostname(mmc));
3022 host->led.name = host->led_name;
3023 host->led.brightness = LED_OFF;
3024 host->led.default_trigger = mmc_hostname(mmc);
3025 host->led.brightness_set = sdhci_led_control;
3026
3027 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3028 if (ret)
3029 goto reset;
3030 #endif
3031
3032 mmiowb();
3033
3034 mmc_add_host(mmc);
3035
3036 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3037 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3038 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3039 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3040
3041 sdhci_enable_card_detection(host);
3042
3043 return 0;
3044
3045 #ifdef SDHCI_USE_LEDS_CLASS
3046 reset:
3047 sdhci_reset(host, SDHCI_RESET_ALL);
3048 free_irq(host->irq, host);
3049 #endif
3050 untasklet:
3051 tasklet_kill(&host->card_tasklet);
3052 tasklet_kill(&host->finish_tasklet);
3053
3054 return ret;
3055 }
3056
3057 EXPORT_SYMBOL_GPL(sdhci_add_host);
3058
sdhci_remove_host(struct sdhci_host * host,int dead)3059 void sdhci_remove_host(struct sdhci_host *host, int dead)
3060 {
3061 unsigned long flags;
3062
3063 if (dead) {
3064 spin_lock_irqsave(&host->lock, flags);
3065
3066 host->flags |= SDHCI_DEVICE_DEAD;
3067
3068 if (host->mrq) {
3069 pr_err("%s: Controller removed during "
3070 " transfer!\n", mmc_hostname(host->mmc));
3071
3072 host->mrq->cmd->error = -ENOMEDIUM;
3073 tasklet_schedule(&host->finish_tasklet);
3074 }
3075
3076 spin_unlock_irqrestore(&host->lock, flags);
3077 }
3078
3079 sdhci_disable_card_detection(host);
3080
3081 mmc_remove_host(host->mmc);
3082
3083 #ifdef SDHCI_USE_LEDS_CLASS
3084 led_classdev_unregister(&host->led);
3085 #endif
3086
3087 if (!dead)
3088 sdhci_reset(host, SDHCI_RESET_ALL);
3089
3090 free_irq(host->irq, host);
3091
3092 del_timer_sync(&host->timer);
3093 if (host->version >= SDHCI_SPEC_300)
3094 del_timer_sync(&host->tuning_timer);
3095
3096 tasklet_kill(&host->card_tasklet);
3097 tasklet_kill(&host->finish_tasklet);
3098
3099 if (host->vmmc)
3100 regulator_put(host->vmmc);
3101
3102 kfree(host->adma_desc);
3103 kfree(host->align_buffer);
3104
3105 host->adma_desc = NULL;
3106 host->align_buffer = NULL;
3107 }
3108
3109 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3110
sdhci_free_host(struct sdhci_host * host)3111 void sdhci_free_host(struct sdhci_host *host)
3112 {
3113 mmc_free_host(host->mmc);
3114 }
3115
3116 EXPORT_SYMBOL_GPL(sdhci_free_host);
3117
3118 /*****************************************************************************\
3119 * *
3120 * Driver init/exit *
3121 * *
3122 \*****************************************************************************/
3123
sdhci_drv_init(void)3124 static int __init sdhci_drv_init(void)
3125 {
3126 pr_info(DRIVER_NAME
3127 ": Secure Digital Host Controller Interface driver\n");
3128 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3129
3130 return 0;
3131 }
3132
sdhci_drv_exit(void)3133 static void __exit sdhci_drv_exit(void)
3134 {
3135 }
3136
3137 module_init(sdhci_drv_init);
3138 module_exit(sdhci_drv_exit);
3139
3140 module_param(debug_quirks, uint, 0444);
3141 module_param(debug_quirks2, uint, 0444);
3142
3143 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3144 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3145 MODULE_LICENSE("GPL");
3146
3147 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3148 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3149