1 /*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Header file for Host Controller registers and I/O accessors.
5 *
6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
12 */
13 #ifndef __SDHCI_HW_H
14 #define __SDHCI_HW_H
15
16 #include <linux/scatterlist.h>
17 #include <linux/compiler.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20
21 #include <linux/mmc/sdhci.h>
22
23 /*
24 * Controller registers
25 */
26
27 #define SDHCI_DMA_ADDRESS 0x00
28 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
29
30 #define SDHCI_BLOCK_SIZE 0x04
31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
32
33 #define SDHCI_BLOCK_COUNT 0x06
34
35 #define SDHCI_ARGUMENT 0x08
36
37 #define SDHCI_TRANSFER_MODE 0x0C
38 #define SDHCI_TRNS_DMA 0x01
39 #define SDHCI_TRNS_BLK_CNT_EN 0x02
40 #define SDHCI_TRNS_AUTO_CMD12 0x04
41 #define SDHCI_TRNS_AUTO_CMD23 0x08
42 #define SDHCI_TRNS_READ 0x10
43 #define SDHCI_TRNS_MULTI 0x20
44
45 #define SDHCI_COMMAND 0x0E
46 #define SDHCI_CMD_RESP_MASK 0x03
47 #define SDHCI_CMD_CRC 0x08
48 #define SDHCI_CMD_INDEX 0x10
49 #define SDHCI_CMD_DATA 0x20
50 #define SDHCI_CMD_ABORTCMD 0xC0
51
52 #define SDHCI_CMD_RESP_NONE 0x00
53 #define SDHCI_CMD_RESP_LONG 0x01
54 #define SDHCI_CMD_RESP_SHORT 0x02
55 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
56
57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
59
60 #define SDHCI_RESPONSE 0x10
61
62 #define SDHCI_BUFFER 0x20
63
64 #define SDHCI_PRESENT_STATE 0x24
65 #define SDHCI_CMD_INHIBIT 0x00000001
66 #define SDHCI_DATA_INHIBIT 0x00000002
67 #define SDHCI_DOING_WRITE 0x00000100
68 #define SDHCI_DOING_READ 0x00000200
69 #define SDHCI_SPACE_AVAILABLE 0x00000400
70 #define SDHCI_DATA_AVAILABLE 0x00000800
71 #define SDHCI_CARD_PRESENT 0x00010000
72 #define SDHCI_WRITE_PROTECT 0x00080000
73 #define SDHCI_DATA_LVL_MASK 0x00F00000
74 #define SDHCI_DATA_LVL_SHIFT 20
75
76 #define SDHCI_HOST_CONTROL 0x28
77 #define SDHCI_CTRL_LED 0x01
78 #define SDHCI_CTRL_4BITBUS 0x02
79 #define SDHCI_CTRL_HISPD 0x04
80 #define SDHCI_CTRL_DMA_MASK 0x18
81 #define SDHCI_CTRL_SDMA 0x00
82 #define SDHCI_CTRL_ADMA1 0x08
83 #define SDHCI_CTRL_ADMA32 0x10
84 #define SDHCI_CTRL_ADMA64 0x18
85 #define SDHCI_CTRL_8BITBUS 0x20
86
87 #define SDHCI_POWER_CONTROL 0x29
88 #define SDHCI_POWER_ON 0x01
89 #define SDHCI_POWER_180 0x0A
90 #define SDHCI_POWER_300 0x0C
91 #define SDHCI_POWER_330 0x0E
92
93 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
94
95 #define SDHCI_WAKE_UP_CONTROL 0x2B
96 #define SDHCI_WAKE_ON_INT 0x01
97 #define SDHCI_WAKE_ON_INSERT 0x02
98 #define SDHCI_WAKE_ON_REMOVE 0x04
99
100 #define SDHCI_CLOCK_CONTROL 0x2C
101 #define SDHCI_DIVIDER_SHIFT 8
102 #define SDHCI_DIVIDER_HI_SHIFT 6
103 #define SDHCI_DIV_MASK 0xFF
104 #define SDHCI_DIV_MASK_LEN 8
105 #define SDHCI_DIV_HI_MASK 0x300
106 #define SDHCI_PROG_CLOCK_MODE 0x0020
107 #define SDHCI_CLOCK_CARD_EN 0x0004
108 #define SDHCI_CLOCK_INT_STABLE 0x0002
109 #define SDHCI_CLOCK_INT_EN 0x0001
110
111 #define SDHCI_TIMEOUT_CONTROL 0x2E
112
113 #define SDHCI_SOFTWARE_RESET 0x2F
114 #define SDHCI_RESET_ALL 0x01
115 #define SDHCI_RESET_CMD 0x02
116 #define SDHCI_RESET_DATA 0x04
117
118 #define SDHCI_INT_STATUS 0x30
119 #define SDHCI_INT_ENABLE 0x34
120 #define SDHCI_SIGNAL_ENABLE 0x38
121 #define SDHCI_INT_RESPONSE 0x00000001
122 #define SDHCI_INT_DATA_END 0x00000002
123 #define SDHCI_INT_DMA_END 0x00000008
124 #define SDHCI_INT_SPACE_AVAIL 0x00000010
125 #define SDHCI_INT_DATA_AVAIL 0x00000020
126 #define SDHCI_INT_CARD_INSERT 0x00000040
127 #define SDHCI_INT_CARD_REMOVE 0x00000080
128 #define SDHCI_INT_CARD_INT 0x00000100
129 #define SDHCI_INT_ERROR 0x00008000
130 #define SDHCI_INT_TIMEOUT 0x00010000
131 #define SDHCI_INT_CRC 0x00020000
132 #define SDHCI_INT_END_BIT 0x00040000
133 #define SDHCI_INT_INDEX 0x00080000
134 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
135 #define SDHCI_INT_DATA_CRC 0x00200000
136 #define SDHCI_INT_DATA_END_BIT 0x00400000
137 #define SDHCI_INT_BUS_POWER 0x00800000
138 #define SDHCI_INT_ACMD12ERR 0x01000000
139 #define SDHCI_INT_ADMA_ERROR 0x02000000
140
141 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
142 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
143
144 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
145 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
146 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
147 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
148 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
149 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
150 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
151
152 #define SDHCI_ACMD12_ERR 0x3C
153
154 #define SDHCI_HOST_CONTROL2 0x3E
155 #define SDHCI_CTRL_UHS_MASK 0x0007
156 #define SDHCI_CTRL_UHS_SDR12 0x0000
157 #define SDHCI_CTRL_UHS_SDR25 0x0001
158 #define SDHCI_CTRL_UHS_SDR50 0x0002
159 #define SDHCI_CTRL_UHS_SDR104 0x0003
160 #define SDHCI_CTRL_UHS_DDR50 0x0004
161 #define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */
162 #define SDHCI_CTRL_VDD_180 0x0008
163 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
164 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
165 #define SDHCI_CTRL_DRV_TYPE_A 0x0010
166 #define SDHCI_CTRL_DRV_TYPE_C 0x0020
167 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
168 #define SDHCI_CTRL_EXEC_TUNING 0x0040
169 #define SDHCI_CTRL_TUNED_CLK 0x0080
170 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
171
172 #define SDHCI_CAPABILITIES 0x40
173 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
174 #define SDHCI_TIMEOUT_CLK_SHIFT 0
175 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
176 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
177 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
178 #define SDHCI_CLOCK_BASE_SHIFT 8
179 #define SDHCI_MAX_BLOCK_MASK 0x00030000
180 #define SDHCI_MAX_BLOCK_SHIFT 16
181 #define SDHCI_CAN_DO_8BIT 0x00040000
182 #define SDHCI_CAN_DO_ADMA2 0x00080000
183 #define SDHCI_CAN_DO_ADMA1 0x00100000
184 #define SDHCI_CAN_DO_HISPD 0x00200000
185 #define SDHCI_CAN_DO_SDMA 0x00400000
186 #define SDHCI_CAN_VDD_330 0x01000000
187 #define SDHCI_CAN_VDD_300 0x02000000
188 #define SDHCI_CAN_VDD_180 0x04000000
189 #define SDHCI_CAN_64BIT 0x10000000
190
191 #define SDHCI_SUPPORT_SDR50 0x00000001
192 #define SDHCI_SUPPORT_SDR104 0x00000002
193 #define SDHCI_SUPPORT_DDR50 0x00000004
194 #define SDHCI_DRIVER_TYPE_A 0x00000010
195 #define SDHCI_DRIVER_TYPE_C 0x00000020
196 #define SDHCI_DRIVER_TYPE_D 0x00000040
197 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
198 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
199 #define SDHCI_USE_SDR50_TUNING 0x00002000
200 #define SDHCI_RETUNING_MODE_MASK 0x0000C000
201 #define SDHCI_RETUNING_MODE_SHIFT 14
202 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
203 #define SDHCI_CLOCK_MUL_SHIFT 16
204
205 #define SDHCI_CAPABILITIES_1 0x44
206
207 #define SDHCI_MAX_CURRENT 0x48
208 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
209 #define SDHCI_MAX_CURRENT_330_SHIFT 0
210 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
211 #define SDHCI_MAX_CURRENT_300_SHIFT 8
212 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
213 #define SDHCI_MAX_CURRENT_180_SHIFT 16
214 #define SDHCI_MAX_CURRENT_MULTIPLIER 4
215
216 /* 4C-4F reserved for more max current */
217
218 #define SDHCI_SET_ACMD12_ERROR 0x50
219 #define SDHCI_SET_INT_ERROR 0x52
220
221 #define SDHCI_ADMA_ERROR 0x54
222
223 /* 55-57 reserved */
224
225 #define SDHCI_ADMA_ADDRESS 0x58
226
227 /* 60-FB reserved */
228
229 #define SDHCI_SLOT_INT_STATUS 0xFC
230
231 #define SDHCI_HOST_VERSION 0xFE
232 #define SDHCI_VENDOR_VER_MASK 0xFF00
233 #define SDHCI_VENDOR_VER_SHIFT 8
234 #define SDHCI_SPEC_VER_MASK 0x00FF
235 #define SDHCI_SPEC_VER_SHIFT 0
236 #define SDHCI_SPEC_100 0
237 #define SDHCI_SPEC_200 1
238 #define SDHCI_SPEC_300 2
239
240 /*
241 * End of controller registers.
242 */
243
244 #define SDHCI_MAX_DIV_SPEC_200 256
245 #define SDHCI_MAX_DIV_SPEC_300 2046
246
247 /*
248 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
249 */
250 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
251 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
252
253 struct sdhci_ops {
254 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
255 u32 (*read_l)(struct sdhci_host *host, int reg);
256 u16 (*read_w)(struct sdhci_host *host, int reg);
257 u8 (*read_b)(struct sdhci_host *host, int reg);
258 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
259 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
260 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
261 #endif
262
263 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
264
265 int (*enable_dma)(struct sdhci_host *host);
266 unsigned int (*get_max_clock)(struct sdhci_host *host);
267 unsigned int (*get_min_clock)(struct sdhci_host *host);
268 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
269 int (*platform_8bit_width)(struct sdhci_host *host,
270 int width);
271 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
272 u8 power_mode);
273 unsigned int (*get_ro)(struct sdhci_host *host);
274 void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
275 void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
276 int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
277 void (*hw_reset)(struct sdhci_host *host);
278 void (*platform_suspend)(struct sdhci_host *host);
279 void (*platform_resume)(struct sdhci_host *host);
280 };
281
282 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
283
sdhci_writel(struct sdhci_host * host,u32 val,int reg)284 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
285 {
286 if (unlikely(host->ops->write_l))
287 host->ops->write_l(host, val, reg);
288 else
289 writel(val, host->ioaddr + reg);
290 }
291
sdhci_writew(struct sdhci_host * host,u16 val,int reg)292 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
293 {
294 if (unlikely(host->ops->write_w))
295 host->ops->write_w(host, val, reg);
296 else
297 writew(val, host->ioaddr + reg);
298 }
299
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)300 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
301 {
302 if (unlikely(host->ops->write_b))
303 host->ops->write_b(host, val, reg);
304 else
305 writeb(val, host->ioaddr + reg);
306 }
307
sdhci_readl(struct sdhci_host * host,int reg)308 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
309 {
310 if (unlikely(host->ops->read_l))
311 return host->ops->read_l(host, reg);
312 else
313 return readl(host->ioaddr + reg);
314 }
315
sdhci_readw(struct sdhci_host * host,int reg)316 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
317 {
318 if (unlikely(host->ops->read_w))
319 return host->ops->read_w(host, reg);
320 else
321 return readw(host->ioaddr + reg);
322 }
323
sdhci_readb(struct sdhci_host * host,int reg)324 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
325 {
326 if (unlikely(host->ops->read_b))
327 return host->ops->read_b(host, reg);
328 else
329 return readb(host->ioaddr + reg);
330 }
331
332 #else
333
sdhci_writel(struct sdhci_host * host,u32 val,int reg)334 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
335 {
336 writel(val, host->ioaddr + reg);
337 }
338
sdhci_writew(struct sdhci_host * host,u16 val,int reg)339 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
340 {
341 writew(val, host->ioaddr + reg);
342 }
343
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)344 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
345 {
346 writeb(val, host->ioaddr + reg);
347 }
348
sdhci_readl(struct sdhci_host * host,int reg)349 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
350 {
351 return readl(host->ioaddr + reg);
352 }
353
sdhci_readw(struct sdhci_host * host,int reg)354 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
355 {
356 return readw(host->ioaddr + reg);
357 }
358
sdhci_readb(struct sdhci_host * host,int reg)359 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
360 {
361 return readb(host->ioaddr + reg);
362 }
363
364 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
365
366 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
367 size_t priv_size);
368 extern void sdhci_free_host(struct sdhci_host *host);
369
sdhci_priv(struct sdhci_host * host)370 static inline void *sdhci_priv(struct sdhci_host *host)
371 {
372 return (void *)host->private;
373 }
374
375 extern void sdhci_card_detect(struct sdhci_host *host);
376 extern int sdhci_add_host(struct sdhci_host *host);
377 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
378
379 #ifdef CONFIG_PM
380 extern int sdhci_suspend_host(struct sdhci_host *host);
381 extern int sdhci_resume_host(struct sdhci_host *host);
382 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
383 #endif
384
385 #ifdef CONFIG_PM_RUNTIME
386 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
387 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
388 #endif
389
390 #endif /* __SDHCI_HW_H */
391