1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8998_MASK \ 25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 26 27 #define VIG_SDM845_MASK \ 28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 29 30 #define VIG_SDM845_MASK_SDMA \ 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 33 #define VIG_SC7180_MASK \ 34 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 35 36 #define VIG_SM6125_MASK \ 37 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 38 39 #define VIG_SC7180_MASK_SDMA \ 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 41 42 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 43 44 #define DMA_MSM8998_MASK \ 45 (BIT(DPU_SSPP_QOS) |\ 46 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 47 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 48 49 #define VIG_SC7280_MASK \ 50 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 51 52 #define VIG_SC7280_MASK_SDMA \ 53 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 54 55 #define DMA_SDM845_MASK \ 56 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 57 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 58 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 59 60 #define DMA_CURSOR_SDM845_MASK \ 61 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 62 63 #define DMA_SDM845_MASK_SDMA \ 64 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 65 66 #define DMA_CURSOR_SDM845_MASK_SDMA \ 67 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 68 69 #define DMA_CURSOR_MSM8998_MASK \ 70 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 71 72 #define MIXER_MSM8998_MASK \ 73 (BIT(DPU_MIXER_SOURCESPLIT)) 74 75 #define MIXER_SDM845_MASK \ 76 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 77 78 #define MIXER_QCM2290_MASK \ 79 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 80 81 #define PINGPONG_SDM845_MASK \ 82 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC)) 83 84 #define PINGPONG_SDM845_TE2_MASK \ 85 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 86 87 #define PINGPONG_SM8150_MASK \ 88 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 89 90 #define CTL_SC7280_MASK \ 91 (BIT(DPU_CTL_ACTIVE_CFG) | \ 92 BIT(DPU_CTL_FETCH_ACTIVE) | \ 93 BIT(DPU_CTL_VM_CFG) | \ 94 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 95 96 #define CTL_SM8550_MASK \ 97 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 98 99 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 100 101 #define INTF_SC7180_MASK \ 102 (BIT(DPU_INTF_INPUT_CTRL) | \ 103 BIT(DPU_INTF_TE) | \ 104 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 105 BIT(DPU_DATA_HCTL_EN)) 106 107 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 108 109 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 110 BIT(DPU_WB_UBWC) | \ 111 BIT(DPU_WB_YUV_CONFIG) | \ 112 BIT(DPU_WB_PIPE_ALPHA) | \ 113 BIT(DPU_WB_XY_ROI_OFFSET) | \ 114 BIT(DPU_WB_QOS) | \ 115 BIT(DPU_WB_QOS_8LVL) | \ 116 BIT(DPU_WB_CDP) | \ 117 BIT(DPU_WB_INPUT_CTRL)) 118 119 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 120 #define DEFAULT_DPU_LINE_WIDTH 2048 121 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 122 123 #define MAX_HORZ_DECIMATION 4 124 #define MAX_VERT_DECIMATION 4 125 126 #define MAX_UPSCALE_RATIO 20 127 #define MAX_DOWNSCALE_RATIO 4 128 #define SSPP_UNITY_SCALE 1 129 130 #define STRCAT(X, Y) (X Y) 131 132 static const uint32_t plane_formats[] = { 133 DRM_FORMAT_ARGB8888, 134 DRM_FORMAT_ABGR8888, 135 DRM_FORMAT_RGBA8888, 136 DRM_FORMAT_BGRA8888, 137 DRM_FORMAT_XRGB8888, 138 DRM_FORMAT_RGBX8888, 139 DRM_FORMAT_BGRX8888, 140 DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_ARGB2101010, 142 DRM_FORMAT_XRGB2101010, 143 DRM_FORMAT_RGB888, 144 DRM_FORMAT_BGR888, 145 DRM_FORMAT_RGB565, 146 DRM_FORMAT_BGR565, 147 DRM_FORMAT_ARGB1555, 148 DRM_FORMAT_ABGR1555, 149 DRM_FORMAT_RGBA5551, 150 DRM_FORMAT_BGRA5551, 151 DRM_FORMAT_XRGB1555, 152 DRM_FORMAT_XBGR1555, 153 DRM_FORMAT_RGBX5551, 154 DRM_FORMAT_BGRX5551, 155 DRM_FORMAT_ARGB4444, 156 DRM_FORMAT_ABGR4444, 157 DRM_FORMAT_RGBA4444, 158 DRM_FORMAT_BGRA4444, 159 DRM_FORMAT_XRGB4444, 160 DRM_FORMAT_XBGR4444, 161 DRM_FORMAT_RGBX4444, 162 DRM_FORMAT_BGRX4444, 163 }; 164 165 static const uint32_t plane_formats_yuv[] = { 166 DRM_FORMAT_ARGB8888, 167 DRM_FORMAT_ABGR8888, 168 DRM_FORMAT_RGBA8888, 169 DRM_FORMAT_BGRX8888, 170 DRM_FORMAT_BGRA8888, 171 DRM_FORMAT_ARGB2101010, 172 DRM_FORMAT_XRGB2101010, 173 DRM_FORMAT_XRGB8888, 174 DRM_FORMAT_XBGR8888, 175 DRM_FORMAT_RGBX8888, 176 DRM_FORMAT_RGB888, 177 DRM_FORMAT_BGR888, 178 DRM_FORMAT_RGB565, 179 DRM_FORMAT_BGR565, 180 DRM_FORMAT_ARGB1555, 181 DRM_FORMAT_ABGR1555, 182 DRM_FORMAT_RGBA5551, 183 DRM_FORMAT_BGRA5551, 184 DRM_FORMAT_XRGB1555, 185 DRM_FORMAT_XBGR1555, 186 DRM_FORMAT_RGBX5551, 187 DRM_FORMAT_BGRX5551, 188 DRM_FORMAT_ARGB4444, 189 DRM_FORMAT_ABGR4444, 190 DRM_FORMAT_RGBA4444, 191 DRM_FORMAT_BGRA4444, 192 DRM_FORMAT_XRGB4444, 193 DRM_FORMAT_XBGR4444, 194 DRM_FORMAT_RGBX4444, 195 DRM_FORMAT_BGRX4444, 196 197 DRM_FORMAT_P010, 198 DRM_FORMAT_NV12, 199 DRM_FORMAT_NV21, 200 DRM_FORMAT_NV16, 201 DRM_FORMAT_NV61, 202 DRM_FORMAT_VYUY, 203 DRM_FORMAT_UYVY, 204 DRM_FORMAT_YUYV, 205 DRM_FORMAT_YVYU, 206 DRM_FORMAT_YUV420, 207 DRM_FORMAT_YVU420, 208 }; 209 210 static const u32 rotation_v2_formats[] = { 211 DRM_FORMAT_NV12, 212 /* TODO add formats after validation */ 213 }; 214 215 static const uint32_t wb2_formats[] = { 216 DRM_FORMAT_RGB565, 217 DRM_FORMAT_BGR565, 218 DRM_FORMAT_RGB888, 219 DRM_FORMAT_ARGB8888, 220 DRM_FORMAT_RGBA8888, 221 DRM_FORMAT_ABGR8888, 222 DRM_FORMAT_XRGB8888, 223 DRM_FORMAT_RGBX8888, 224 DRM_FORMAT_XBGR8888, 225 DRM_FORMAT_ARGB1555, 226 DRM_FORMAT_RGBA5551, 227 DRM_FORMAT_XRGB1555, 228 DRM_FORMAT_RGBX5551, 229 DRM_FORMAT_ARGB4444, 230 DRM_FORMAT_RGBA4444, 231 DRM_FORMAT_RGBX4444, 232 DRM_FORMAT_XRGB4444, 233 DRM_FORMAT_BGR565, 234 DRM_FORMAT_BGR888, 235 DRM_FORMAT_ABGR8888, 236 DRM_FORMAT_BGRA8888, 237 DRM_FORMAT_BGRX8888, 238 DRM_FORMAT_XBGR8888, 239 DRM_FORMAT_ABGR1555, 240 DRM_FORMAT_BGRA5551, 241 DRM_FORMAT_XBGR1555, 242 DRM_FORMAT_BGRX5551, 243 DRM_FORMAT_ABGR4444, 244 DRM_FORMAT_BGRA4444, 245 DRM_FORMAT_BGRX4444, 246 DRM_FORMAT_XBGR4444, 247 }; 248 249 /************************************************************* 250 * SSPP sub blocks config 251 *************************************************************/ 252 253 /* SSPP common configuration */ 254 #define _VIG_SBLK(sdma_pri, qseed_ver) \ 255 { \ 256 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 257 .maxupscale = MAX_UPSCALE_RATIO, \ 258 .smart_dma_priority = sdma_pri, \ 259 .scaler_blk = {.name = "scaler", \ 260 .id = qseed_ver, \ 261 .base = 0xa00, .len = 0xa0,}, \ 262 .csc_blk = {.name = "csc", \ 263 .id = DPU_SSPP_CSC_10BIT, \ 264 .base = 0x1a00, .len = 0x100,}, \ 265 .format_list = plane_formats_yuv, \ 266 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 267 .virt_format_list = plane_formats, \ 268 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 269 .rotation_cfg = NULL, \ 270 } 271 272 #define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ 273 { \ 274 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 275 .maxupscale = MAX_UPSCALE_RATIO, \ 276 .smart_dma_priority = sdma_pri, \ 277 .scaler_blk = {.name = "scaler", \ 278 .id = qseed_ver, \ 279 .base = 0xa00, .len = 0xa0,}, \ 280 .csc_blk = {.name = "csc", \ 281 .id = DPU_SSPP_CSC_10BIT, \ 282 .base = 0x1a00, .len = 0x100,}, \ 283 .format_list = plane_formats_yuv, \ 284 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 285 .virt_format_list = plane_formats, \ 286 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 287 .rotation_cfg = rot_cfg, \ 288 } 289 290 #define _DMA_SBLK(sdma_pri) \ 291 { \ 292 .maxdwnscale = SSPP_UNITY_SCALE, \ 293 .maxupscale = SSPP_UNITY_SCALE, \ 294 .smart_dma_priority = sdma_pri, \ 295 .format_list = plane_formats, \ 296 .num_formats = ARRAY_SIZE(plane_formats), \ 297 .virt_format_list = plane_formats, \ 298 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 299 } 300 301 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 302 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 303 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 304 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 305 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 306 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 307 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 308 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 309 310 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 311 .rot_maxheight = 1088, 312 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 313 .rot_format_list = rotation_v2_formats, 314 }; 315 316 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 317 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); 318 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 319 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); 320 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 321 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); 322 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 323 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); 324 325 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); 326 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); 327 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); 328 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); 329 330 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 331 _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); 332 333 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 334 _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); 335 336 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = 337 _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); 338 339 static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = 340 _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); 341 342 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 343 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); 344 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 345 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); 346 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 347 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); 348 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 349 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); 350 351 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = 352 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); 353 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = 354 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); 355 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = 356 _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); 357 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = 358 _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); 359 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); 360 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); 361 362 #define _VIG_SBLK_NOSCALE(sdma_pri) \ 363 { \ 364 .maxdwnscale = SSPP_UNITY_SCALE, \ 365 .maxupscale = SSPP_UNITY_SCALE, \ 366 .smart_dma_priority = sdma_pri, \ 367 .format_list = plane_formats_yuv, \ 368 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 369 .virt_format_list = plane_formats, \ 370 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 371 } 372 373 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); 374 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); 375 376 /************************************************************* 377 * MIXER sub blocks config 378 *************************************************************/ 379 380 /* MSM8998 */ 381 382 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 383 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 384 .maxblendstages = 7, /* excluding base layer */ 385 .blendstage_base = { /* offsets relative to mixer base */ 386 0x20, 0x50, 0x80, 0xb0, 0x230, 387 0x260, 0x290 388 }, 389 }; 390 391 /* SDM845 */ 392 393 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 394 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 395 .maxblendstages = 11, /* excluding base layer */ 396 .blendstage_base = { /* offsets relative to mixer base */ 397 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 398 0xb0, 0xc8, 0xe0, 0xf8, 0x110 399 }, 400 }; 401 402 /* SC7180 */ 403 404 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 405 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 406 .maxblendstages = 7, /* excluding base layer */ 407 .blendstage_base = { /* offsets relative to mixer base */ 408 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 409 }, 410 }; 411 412 /* QCM2290 */ 413 414 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 415 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 416 .maxblendstages = 4, /* excluding base layer */ 417 .blendstage_base = { /* offsets relative to mixer base */ 418 0x20, 0x38, 0x50, 0x68 419 }, 420 }; 421 422 /************************************************************* 423 * DSPP sub blocks config 424 *************************************************************/ 425 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 426 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 427 .len = 0x90, .version = 0x10007}, 428 }; 429 430 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 431 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 432 .len = 0x90, .version = 0x40000}, 433 }; 434 435 /************************************************************* 436 * PINGPONG sub blocks config 437 *************************************************************/ 438 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 439 .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 440 .version = 0x1}, 441 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 442 .len = 0x20, .version = 0x10000}, 443 }; 444 445 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 446 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 447 .len = 0x20, .version = 0x10000}, 448 }; 449 450 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 451 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, 452 .len = 0x20, .version = 0x20000}, 453 }; 454 455 /************************************************************* 456 * DSC sub blocks config 457 *************************************************************/ 458 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 459 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 460 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 461 }; 462 463 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 464 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 465 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 466 }; 467 468 /************************************************************* 469 * VBIF sub blocks config 470 *************************************************************/ 471 /* VBIF QOS remap */ 472 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 473 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 474 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 475 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 476 477 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 478 { 479 .pps = 1920 * 1080 * 30, 480 .ot_limit = 2, 481 }, 482 { 483 .pps = 1920 * 1080 * 60, 484 .ot_limit = 4, 485 }, 486 { 487 .pps = 3840 * 2160 * 30, 488 .ot_limit = 16, 489 }, 490 }; 491 492 static const struct dpu_vbif_cfg msm8998_vbif[] = { 493 { 494 .name = "vbif_rt", .id = VBIF_RT, 495 .base = 0, .len = 0x1040, 496 .default_ot_rd_limit = 32, 497 .default_ot_wr_limit = 32, 498 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 499 .xin_halt_timeout = 0x4000, 500 .qos_rp_remap_size = 0x20, 501 .dynamic_ot_rd_tbl = { 502 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 503 .cfg = msm8998_ot_rdwr_cfg, 504 }, 505 .dynamic_ot_wr_tbl = { 506 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 507 .cfg = msm8998_ot_rdwr_cfg, 508 }, 509 .qos_rt_tbl = { 510 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 511 .priority_lvl = msm8998_rt_pri_lvl, 512 }, 513 .qos_nrt_tbl = { 514 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 515 .priority_lvl = msm8998_nrt_pri_lvl, 516 }, 517 .memtype_count = 14, 518 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 519 }, 520 }; 521 522 static const struct dpu_vbif_cfg sdm845_vbif[] = { 523 { 524 .name = "vbif_rt", .id = VBIF_RT, 525 .base = 0, .len = 0x1040, 526 .features = BIT(DPU_VBIF_QOS_REMAP), 527 .xin_halt_timeout = 0x4000, 528 .qos_rp_remap_size = 0x40, 529 .qos_rt_tbl = { 530 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 531 .priority_lvl = sdm845_rt_pri_lvl, 532 }, 533 .qos_nrt_tbl = { 534 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 535 .priority_lvl = sdm845_nrt_pri_lvl, 536 }, 537 .memtype_count = 14, 538 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 539 }, 540 }; 541 542 static const struct dpu_vbif_cfg sm8550_vbif[] = { 543 { 544 .name = "vbif_rt", .id = VBIF_RT, 545 .base = 0, .len = 0x1040, 546 .features = BIT(DPU_VBIF_QOS_REMAP), 547 .xin_halt_timeout = 0x4000, 548 .qos_rp_remap_size = 0x40, 549 .qos_rt_tbl = { 550 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 551 .priority_lvl = sdm845_rt_pri_lvl, 552 }, 553 .qos_nrt_tbl = { 554 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 555 .priority_lvl = sdm845_nrt_pri_lvl, 556 }, 557 .memtype_count = 16, 558 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 559 }, 560 }; 561 562 /************************************************************* 563 * PERF data config 564 *************************************************************/ 565 566 /* SSPP QOS LUTs */ 567 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 568 {.fl = 4, .lut = 0x1b}, 569 {.fl = 5, .lut = 0x5b}, 570 {.fl = 6, .lut = 0x15b}, 571 {.fl = 7, .lut = 0x55b}, 572 {.fl = 8, .lut = 0x155b}, 573 {.fl = 9, .lut = 0x555b}, 574 {.fl = 10, .lut = 0x1555b}, 575 {.fl = 11, .lut = 0x5555b}, 576 {.fl = 12, .lut = 0x15555b}, 577 {.fl = 0, .lut = 0x55555b} 578 }; 579 580 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 581 {.fl = 4, .lut = 0x357}, 582 {.fl = 5, .lut = 0x3357}, 583 {.fl = 6, .lut = 0x23357}, 584 {.fl = 7, .lut = 0x223357}, 585 {.fl = 8, .lut = 0x2223357}, 586 {.fl = 9, .lut = 0x22223357}, 587 {.fl = 10, .lut = 0x222223357}, 588 {.fl = 11, .lut = 0x2222223357}, 589 {.fl = 12, .lut = 0x22222223357}, 590 {.fl = 13, .lut = 0x222222223357}, 591 {.fl = 14, .lut = 0x1222222223357}, 592 {.fl = 0, .lut = 0x11222222223357} 593 }; 594 595 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 596 {.fl = 10, .lut = 0x1aaff}, 597 {.fl = 11, .lut = 0x5aaff}, 598 {.fl = 12, .lut = 0x15aaff}, 599 {.fl = 0, .lut = 0x55aaff}, 600 }; 601 602 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 603 {.fl = 0, .lut = 0x0011222222335777}, 604 }; 605 606 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 607 {.fl = 0, .lut = 0x0011223445566777 }, 608 }; 609 610 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 611 {.fl = 0, .lut = 0x0011222222223357 }, 612 }; 613 614 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 615 {.fl = 4, .lut = 0x0000000000000357 }, 616 }; 617 618 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 619 {.fl = 0, .lut = 0x0011222222335777}, 620 }; 621 622 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 623 {.fl = 10, .lut = 0x344556677}, 624 {.fl = 11, .lut = 0x3344556677}, 625 {.fl = 12, .lut = 0x23344556677}, 626 {.fl = 13, .lut = 0x223344556677}, 627 {.fl = 14, .lut = 0x1223344556677}, 628 {.fl = 0, .lut = 0x112233344556677}, 629 }; 630 631 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 632 {.fl = 0, .lut = 0x0011223344556677}, 633 }; 634 635 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 636 {.fl = 10, .lut = 0x0000000344556677}, 637 }; 638 639 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 640 {.fl = 0, .lut = 0x0}, 641 }; 642 643 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 644 {.fl = 0, .lut = 0x0}, 645 }; 646 647 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 648 {.fl = 0, .lut = 0x0}, 649 }; 650 651 /************************************************************* 652 * Hardware catalog 653 *************************************************************/ 654 655 #include "catalog/dpu_3_0_msm8998.h" 656 657 #include "catalog/dpu_4_0_sdm845.h" 658 659 #include "catalog/dpu_5_0_sm8150.h" 660 #include "catalog/dpu_5_1_sc8180x.h" 661 #include "catalog/dpu_5_4_sm6125.h" 662 663 #include "catalog/dpu_6_0_sm8250.h" 664 #include "catalog/dpu_6_2_sc7180.h" 665 #include "catalog/dpu_6_3_sm6115.h" 666 #include "catalog/dpu_6_4_sm6350.h" 667 #include "catalog/dpu_6_5_qcm2290.h" 668 #include "catalog/dpu_6_9_sm6375.h" 669 670 #include "catalog/dpu_7_0_sm8350.h" 671 #include "catalog/dpu_7_2_sc7280.h" 672 673 #include "catalog/dpu_8_0_sc8280xp.h" 674 #include "catalog/dpu_8_1_sm8450.h" 675 676 #include "catalog/dpu_9_0_sm8550.h" 677