1 /*
2 ** System Bus Adapter (SBA) I/O MMU manager
3 **
4 ** (c) Copyright 2000 Grant Grundler
5 ** (c) Copyright 2000 Hewlett-Packard Company
6 **
7 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
8 **
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
13 **
14 **
15 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
16 ** J5000/J7000/N-class/L-class machines and their successors.
17 **
18 ** FIXME: add DMA hint support programming in both sba and lba modules.
19 */
20
21 #include <linux/config.h>
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27
28 #include <linux/mm.h>
29 #include <linux/string.h>
30 #undef PCI_DEBUG /* for ASSERT */
31 #include <linux/pci.h>
32 #undef PCI_DEBUG
33
34 #include <asm/byteorder.h>
35 #include <asm/io.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
37
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
39 #include <asm/gsc.h> /* FIXME: for gsc_read/gsc_write */
40
41 #include <linux/proc_fs.h>
42 #include <asm/runway.h> /* for proc_runway_root */
43 #include <asm/pdc.h> /* for PDC_MODEL_* */
44
45 #define MODULE_NAME "SBA"
46
47 /*
48 ** The number of debug flags is a clue - this code is fragile.
49 ** Don't even think about messing with it unless you have
50 ** plenty of 710's to sacrifice to the computer gods. :^)
51 */
52 #undef DEBUG_SBA_INIT
53 #undef DEBUG_SBA_RUN
54 #undef DEBUG_SBA_RUN_SG
55 #undef DEBUG_SBA_RESOURCE
56 #undef ASSERT_PDIR_SANITY
57 #undef DEBUG_LARGE_SG_ENTRIES
58 #undef DEBUG_DMB_TRAP
59
60 #define SBA_INLINE __inline__
61
62 #ifdef DEBUG_SBA_INIT
63 #define DBG_INIT(x...) printk(x)
64 #else
65 #define DBG_INIT(x...)
66 #endif
67
68 #ifdef DEBUG_SBA_RUN
69 #define DBG_RUN(x...) printk(x)
70 #else
71 #define DBG_RUN(x...)
72 #endif
73
74 #ifdef DEBUG_SBA_RUN_SG
75 #define DBG_RUN_SG(x...) printk(x)
76 #else
77 #define DBG_RUN_SG(x...)
78 #endif
79
80
81 #ifdef DEBUG_SBA_RESOURCE
82 #define DBG_RES(x...) printk(x)
83 #else
84 #define DBG_RES(x...)
85 #endif
86
87 /*
88 ** The number of pdir entries to "free" before issueing
89 ** a read to PCOM register to flush out PCOM writes.
90 ** Interacts with allocation granularity (ie 4 or 8 entries
91 ** allocated and free'd/purged at a time might make this
92 ** less interesting).
93 */
94 #define DELAYED_RESOURCE_CNT 16
95
96 #define DEFAULT_DMA_HINT_REG 0
97
98 #define ASTRO_RUNWAY_PORT 0x582
99 #define ASTRO_ROPES_PORT 0x780
100
101 #define IKE_MERCED_PORT 0x803
102 #define IKE_ROPES_PORT 0x781
103
104 #define REO_MERCED_PORT 0x804
105 #define REO_ROPES_PORT 0x782
106
107 #define REOG_MERCED_PORT 0x805
108 #define REOG_ROPES_PORT 0x783
109
110 #define SBA_FUNC_ID 0x0000 /* function id */
111 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
112
113 #define IS_ASTRO(id) \
114 (((id)->hversion == ASTRO_RUNWAY_PORT) || ((id)->hversion == ASTRO_ROPES_PORT))
115
116 #define IS_IKE(id) \
117 (((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
118
119 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
120
121 #define ASTRO_IOC_OFFSET 0x20000
122 /* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
123 #define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
124
125 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
126 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
127 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
128 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
129 #define IOC_CTRL_RM (1 << 8) /* Real Mode */
130 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
131
132 #define MAX_IOC 2 /* per Ike. Astro only has 1 */
133
134
135 /*
136 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
137 ** Firmware programs this stuff. Don't touch it.
138 */
139 #define IOS_DIST_BASE 0x390
140 #define IOS_DIST_MASK 0x398
141 #define IOS_DIST_ROUTE 0x3A0
142
143 #define IOS_DIRECT_BASE 0x3C0
144 #define IOS_DIRECT_MASK 0x3C8
145 #define IOS_DIRECT_ROUTE 0x3D0
146
147 /*
148 ** Offsets into I/O TLB (Function 2 and 3 on Ike)
149 */
150 #define ROPE0_CTL 0x200 /* "regbus pci0" */
151 #define ROPE1_CTL 0x208
152 #define ROPE2_CTL 0x210
153 #define ROPE3_CTL 0x218
154 #define ROPE4_CTL 0x220
155 #define ROPE5_CTL 0x228
156 #define ROPE6_CTL 0x230
157 #define ROPE7_CTL 0x238
158
159 #define HF_ENABLE 0x40
160
161
162 #define IOC_IBASE 0x300 /* IO TLB */
163 #define IOC_IMASK 0x308
164 #define IOC_PCOM 0x310
165 #define IOC_TCNFG 0x318
166 #define IOC_PDIR_BASE 0x320
167
168 #define IOC_IOVA_SPACE_BASE 0 /* IOVA ranges start at 0 */
169
170 /*
171 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
172 ** It's safer (avoid memory corruption) to keep DMA page mappings
173 ** equivalently sized to VM PAGE_SIZE.
174 **
175 ** We really can't avoid generating a new mapping for each
176 ** page since the Virtual Coherence Index has to be generated
177 ** and updated for each page.
178 **
179 ** IOVP_SIZE could only be greater than PAGE_SIZE if we are
180 ** confident the drivers really only touch the next physical
181 ** page iff that driver instance owns it.
182 */
183 #define IOVP_SIZE PAGE_SIZE
184 #define IOVP_SHIFT PAGE_SHIFT
185 #define IOVP_MASK PAGE_MASK
186
187 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
188 #define SBA_PERF_MASK1 0x718
189 #define SBA_PERF_MASK2 0x730
190
191
192 /*
193 ** Offsets into PCI Performance Counters (functions 12 and 13)
194 ** Controlled by PERF registers in function 2 & 3 respectively.
195 */
196 #define SBA_PERF_CNT1 0x200
197 #define SBA_PERF_CNT2 0x208
198 #define SBA_PERF_CNT3 0x210
199
200
201 struct ioc {
202 unsigned long ioc_hpa; /* I/O MMU base address */
203 char *res_map; /* resource map, bit == pdir entry */
204 u64 *pdir_base; /* physical base address */
205
206 unsigned long *res_hint; /* next avail IOVP - circular search */
207 spinlock_t res_lock;
208 unsigned long hint_mask_pdir; /* bits used for DMA hints */
209 unsigned int res_bitshift; /* from the LEFT! */
210 unsigned int res_size; /* size of resource map in bytes */
211 unsigned int hint_shift_pdir;
212 #if DELAYED_RESOURCE_CNT > 0
213 int saved_cnt;
214 struct sba_dma_pair {
215 dma_addr_t iova;
216 size_t size;
217 } saved[DELAYED_RESOURCE_CNT];
218 #endif
219
220 #ifdef CONFIG_PROC_FS
221 #define SBA_SEARCH_SAMPLE 0x100
222 unsigned long avg_search[SBA_SEARCH_SAMPLE];
223 unsigned long avg_idx; /* current index into avg_search */
224 unsigned long used_pages;
225 unsigned long msingle_calls;
226 unsigned long msingle_pages;
227 unsigned long msg_calls;
228 unsigned long msg_pages;
229 unsigned long usingle_calls;
230 unsigned long usingle_pages;
231 unsigned long usg_calls;
232 unsigned long usg_pages;
233 #endif
234
235 /* STUFF We don't need in performance path */
236 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
237 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
238 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
239 };
240
241 struct sba_device {
242 struct sba_device *next; /* list of SBA's in system */
243 struct parisc_device *dev; /* dev found in bus walk */
244 struct parisc_device_id *iodc; /* data about dev from firmware */
245 const char *name;
246 unsigned long sba_hpa; /* base address */
247 spinlock_t sba_lock;
248 unsigned int flags; /* state/functionality enabled */
249 unsigned int hw_rev; /* HW revision of chip */
250
251 unsigned int num_ioc; /* number of on-board IOC's */
252 struct ioc ioc[MAX_IOC];
253 };
254
255
256 static struct sba_device *sba_list;
257
258 static unsigned long ioc_needs_fdc = 0;
259
260 /* Ratio of Host MEM to IOV Space size */
261 static unsigned long sba_mem_ratio = 8;
262
263 /* global count of IOMMUs in the system */
264 static unsigned int global_ioc_cnt = 0;
265
266 /* PA8700 (Piranha 2.2) bug workaround */
267 static unsigned long piranha_bad_128k = 0;
268
269 /* Looks nice and keeps the compiler happy */
270 #define SBA_DEV(d) ((struct sba_device *) (d))
271
272
273 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
274
275
276 /************************************
277 ** SBA register read and write support
278 **
279 ** BE WARNED: register writes are posted.
280 ** (ie follow writes which must reach HW with a read)
281 **
282 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
283 */
284 #define READ_REG32(addr) le32_to_cpu(__raw_readl(addr))
285 #define READ_REG64(addr) le64_to_cpu(__raw_readq(addr))
286 #define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
287 #define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
288
289 #ifdef __LP64__
290 #define READ_REG(addr) READ_REG64(addr)
291 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
292 #else
293 #define READ_REG(addr) READ_REG32(addr)
294 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
295 #endif
296
297 #ifdef DEBUG_SBA_INIT
298
299 /* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
300
301 /**
302 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
303 * @hpa: base address of the sba
304 *
305 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
306 * IO Adapter (aka Bus Converter).
307 */
308 static void
sba_dump_ranges(unsigned long hpa)309 sba_dump_ranges(unsigned long hpa)
310 {
311 DBG_INIT("SBA at 0x%lx\n", hpa);
312 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
313 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
314 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
315 DBG_INIT("\n");
316 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
317 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
318 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
319 }
320
321 /**
322 * sba_dump_tlb - debugging only - print IOMMU operating parameters
323 * @hpa: base address of the IOMMU
324 *
325 * Print the size/location of the IO MMU PDIR.
326 */
327 static void
sba_dump_tlb(unsigned long hpa)328 sba_dump_tlb(unsigned long hpa)
329 {
330 DBG_INIT("IO TLB at 0x%lx\n", hpa);
331 DBG_INIT("IOC_IBASE : %Lx\n", READ_REG64(hpa+IOC_IBASE));
332 DBG_INIT("IOC_IMASK : %Lx\n", READ_REG64(hpa+IOC_IMASK));
333 DBG_INIT("IOC_TCNFG : %Lx\n", READ_REG64(hpa+IOC_TCNFG));
334 DBG_INIT("IOC_PDIR_BASE: %Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
335 DBG_INIT("\n");
336 }
337 #endif
338
339
340 #ifdef ASSERT_PDIR_SANITY
341
342 /**
343 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
344 * @ioc: IO MMU structure which owns the pdir we are interested in.
345 * @msg: text to print ont the output line.
346 * @pide: pdir index.
347 *
348 * Print one entry of the IO MMU PDIR in human readable form.
349 */
350 static void
sba_dump_pdir_entry(struct ioc * ioc,char * msg,uint pide)351 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
352 {
353 /* start printing from lowest pde in rval */
354 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
355 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
356 uint rcnt;
357
358 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
359 msg,
360 rptr, pide & (BITS_PER_LONG - 1), *rptr);
361
362 rcnt = 0;
363 while (rcnt < BITS_PER_LONG) {
364 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
365 (rcnt == (pide & (BITS_PER_LONG - 1)))
366 ? " -->" : " ",
367 rcnt, ptr, *ptr );
368 rcnt++;
369 ptr++;
370 }
371 printk(KERN_DEBUG "%s", msg);
372 }
373
374
375 /**
376 * sba_check_pdir - debugging only - consistency checker
377 * @ioc: IO MMU structure which owns the pdir we are interested in.
378 * @msg: text to print ont the output line.
379 *
380 * Verify the resource map and pdir state is consistent
381 */
382 static int
sba_check_pdir(struct ioc * ioc,char * msg)383 sba_check_pdir(struct ioc *ioc, char *msg)
384 {
385 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
386 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
387 u64 *pptr = ioc->pdir_base; /* pdir ptr */
388 uint pide = 0;
389
390 while (rptr < rptr_end) {
391 u32 rval = *rptr;
392 int rcnt = 32; /* number of bits we might check */
393
394 while (rcnt) {
395 /* Get last byte and highest bit from that */
396 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
397 if ((rval ^ pde) & 0x80000000)
398 {
399 /*
400 ** BUMMER! -- res_map != pdir --
401 ** Dump rval and matching pdir entries
402 */
403 sba_dump_pdir_entry(ioc, msg, pide);
404 return(1);
405 }
406 rcnt--;
407 rval <<= 1; /* try the next bit */
408 pptr++;
409 pide++;
410 }
411 rptr++; /* look at next word of res_map */
412 }
413 /* It'd be nice if we always got here :^) */
414 return 0;
415 }
416
417
418 /**
419 * sba_dump_sg - debugging only - print Scatter-Gather list
420 * @ioc: IO MMU structure which owns the pdir we are interested in.
421 * @startsg: head of the SG list
422 * @nents: number of entries in SG list
423 *
424 * print the SG list so we can verify it's correct by hand.
425 */
426 static void
sba_dump_sg(struct ioc * ioc,struct scatterlist * startsg,int nents)427 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
428 {
429 while (nents-- > 0) {
430 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
431 nents,
432 (unsigned long) sg_dma_address(startsg),
433 sg_dma_len(startsg),
434 sg_virt_addr(startsg), startsg->length);
435 startsg++;
436 }
437 }
438
439 #endif /* ASSERT_PDIR_SANITY */
440
441
442
443
444 /**************************************************************
445 *
446 * I/O Pdir Resource Management
447 *
448 * Bits set in the resource map are in use.
449 * Each bit can represent a number of pages.
450 * LSbs represent lower addresses (IOVA's).
451 *
452 ***************************************************************/
453 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
454
455 /* Convert from IOVP to IOVA and vice versa. */
456 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset) | ((hint_reg)<<(ioc->hint_shift_pdir)))
457 #define SBA_IOVP(ioc,iova) ((iova) & ioc->hint_mask_pdir)
458
459 /* FIXME : review these macros to verify correctness and usage */
460 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
461 #define MKIOVP(dma_hint,pide) (dma_addr_t)((long)(dma_hint) | ((long)(pide) << IOVP_SHIFT))
462 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
463
464 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
465 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
466
467
468 /**
469 * sba_search_bitmap - find free space in IO PDIR resource bitmap
470 * @ioc: IO MMU structure which owns the pdir we are interested in.
471 * @bits_wanted: number of entries we need.
472 *
473 * Find consecutive free bits in resource bitmap.
474 * Each bit represents one entry in the IO Pdir.
475 * Cool perf optimization: search for log2(size) bits at a time.
476 */
477 static SBA_INLINE unsigned long
sba_search_bitmap(struct ioc * ioc,unsigned long bits_wanted)478 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
479 {
480 unsigned long *res_ptr = ioc->res_hint;
481 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
482 unsigned long pide = ~0UL;
483
484 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
485 ASSERT(res_ptr < res_end);
486 if (bits_wanted > (BITS_PER_LONG/2)) {
487 /* Search word at a time - no mask needed */
488 for(; res_ptr < res_end; ++res_ptr) {
489 if (*res_ptr == 0) {
490 *res_ptr = RESMAP_MASK(bits_wanted);
491 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
492 pide <<= 3; /* convert to bit address */
493 break;
494 }
495 }
496 /* point to the next word on next pass */
497 res_ptr++;
498 ioc->res_bitshift = 0;
499 } else {
500 /*
501 ** Search the resource bit map on well-aligned values.
502 ** "o" is the alignment.
503 ** We need the alignment to invalidate I/O TLB using
504 ** SBA HW features in the unmap path.
505 */
506 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
507 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
508 unsigned long mask;
509
510 if (bitshiftcnt >= BITS_PER_LONG) {
511 bitshiftcnt = 0;
512 res_ptr++;
513 }
514 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
515
516 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
517 while(res_ptr < res_end)
518 {
519 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
520 ASSERT(0 != mask);
521 if(0 == ((*res_ptr) & mask)) {
522 *res_ptr |= mask; /* mark resources busy! */
523 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
524 pide <<= 3; /* convert to bit address */
525 pide += bitshiftcnt;
526 break;
527 }
528 mask >>= o;
529 bitshiftcnt += o;
530 if (0 == mask) {
531 mask = RESMAP_MASK(bits_wanted);
532 bitshiftcnt=0;
533 res_ptr++;
534 }
535 }
536 /* look in the same word on the next pass */
537 ioc->res_bitshift = bitshiftcnt + bits_wanted;
538 }
539
540 /* wrapped ? */
541 if (res_end <= res_ptr) {
542 ioc->res_hint = (unsigned long *) ioc->res_map;
543 ioc->res_bitshift = 0;
544 } else {
545 ioc->res_hint = res_ptr;
546 }
547 return (pide);
548 }
549
550
551 /**
552 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
553 * @ioc: IO MMU structure which owns the pdir we are interested in.
554 * @size: number of bytes to create a mapping for
555 *
556 * Given a size, find consecutive unmarked and then mark those bits in the
557 * resource bit map.
558 */
559 static int
sba_alloc_range(struct ioc * ioc,size_t size)560 sba_alloc_range(struct ioc *ioc, size_t size)
561 {
562 unsigned int pages_needed = size >> IOVP_SHIFT;
563 #ifdef CONFIG_PROC_FS
564 unsigned long cr_start = mfctl(16);
565 #endif
566 unsigned long pide;
567
568 ASSERT(pages_needed);
569 ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE);
570 ASSERT(pages_needed <= BITS_PER_LONG);
571 ASSERT(0 == (size & ~IOVP_MASK));
572
573 /*
574 ** "seek and ye shall find"...praying never hurts either...
575 ** ggg sacrifices another 710 to the computer gods.
576 */
577
578 pide = sba_search_bitmap(ioc, pages_needed);
579 if (pide >= (ioc->res_size << 3)) {
580 pide = sba_search_bitmap(ioc, pages_needed);
581 if (pide >= (ioc->res_size << 3))
582 panic(__FILE__ ": I/O MMU @ %lx is out of mapping resources\n", ioc->ioc_hpa);
583 }
584
585 #ifdef ASSERT_PDIR_SANITY
586 /* verify the first enable bit is clear */
587 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
588 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
589 }
590 #endif
591
592 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
593 __FUNCTION__, size, pages_needed, pide,
594 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
595 ioc->res_bitshift );
596
597 #ifdef CONFIG_PROC_FS
598 {
599 unsigned long cr_end = mfctl(16);
600 unsigned long tmp = cr_end - cr_start;
601 /* check for roll over */
602 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
603 }
604 ioc->avg_search[ioc->avg_idx++] = cr_start;
605 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
606
607 ioc->used_pages += pages_needed;
608 #endif
609
610 return (pide);
611 }
612
613
614 /**
615 * sba_free_range - unmark bits in IO PDIR resource bitmap
616 * @ioc: IO MMU structure which owns the pdir we are interested in.
617 * @iova: IO virtual address which was previously allocated.
618 * @size: number of bytes to create a mapping for
619 *
620 * clear bits in the ioc's resource map
621 */
622 static SBA_INLINE void
sba_free_range(struct ioc * ioc,dma_addr_t iova,size_t size)623 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
624 {
625 unsigned long iovp = SBA_IOVP(ioc, iova);
626 unsigned int pide = PDIR_INDEX(iovp);
627 unsigned int ridx = pide >> 3; /* convert bit to byte address */
628 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
629
630 int bits_not_wanted = size >> IOVP_SHIFT;
631
632 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
633 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
634
635 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
636 __FUNCTION__, (uint) iova, size,
637 bits_not_wanted, m, pide, res_ptr, *res_ptr);
638
639 #ifdef CONFIG_PROC_FS
640 ioc->used_pages -= bits_not_wanted;
641 #endif
642
643 ASSERT(m != 0);
644 ASSERT(bits_not_wanted);
645 ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE);
646 ASSERT(bits_not_wanted <= BITS_PER_LONG);
647 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
648 *res_ptr &= ~m;
649 }
650
651
652 /**************************************************************
653 *
654 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
655 *
656 ***************************************************************/
657
658 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
659
660
661 typedef unsigned long space_t;
662 #define KERNEL_SPACE 0
663
664 /**
665 * sba_io_pdir_entry - fill in one IO PDIR entry
666 * @pdir_ptr: pointer to IO PDIR entry
667 * @sid: process Space ID
668 * @vba: Virtual CPU address of buffer to map
669 *
670 * SBA Mapping Routine
671 *
672 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
673 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
674 * pdir_ptr (arg0). Each IO Pdir entry consists of 8 bytes as
675 * shown below (MSB == bit 0):
676 *
677 * 0 19 51 55 63
678 * +-+---------------------+----------------------------------+----+--------+
679 * |V| U | PPN[43:12] | U | VI |
680 * +-+---------------------+----------------------------------+----+--------+
681 *
682 * V == Valid Bit
683 * U == Unused
684 * PPN == Physical Page Number
685 * VI == Virtual Index (aka Coherent Index)
686 *
687 * The physical address fields are filled with the results of the LPA
688 * instruction. The virtual index field is filled with the results of
689 * of the LCI (Load Coherence Index) instruction. The 8 bits used for
690 * the virtual index are bits 12:19 of the value returned by LCI.
691 *
692 * We need to pre-swap the bytes since PCX-W is Big Endian.
693 */
694
695
696 void SBA_INLINE
sba_io_pdir_entry(u64 * pdir_ptr,space_t sid,unsigned long vba)697 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba)
698 {
699 u64 pa; /* physical address */
700 register unsigned ci; /* coherent index */
701
702 /* We currently only support kernel addresses.
703 * fdc instr below will need to reload sr1 with KERNEL_SPACE
704 * once we try to support direct DMA to user space.
705 */
706 ASSERT(sid == KERNEL_SPACE);
707
708 pa = virt_to_phys(vba);
709 pa &= ~4095ULL; /* clear out offset bits */
710
711 mtsp(sid,1);
712 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
713 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
714
715 pa |= 0x8000000000000000ULL; /* set "valid" bit */
716 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
717
718 /*
719 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
720 * (bit #61, big endian), we have to flush and sync every time
721 * IO-PDIR is changed in Ike/Astro.
722 */
723 if (ioc_needs_fdc) {
724 asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
725 }
726 }
727
728
729 /**
730 * sba_mark_invalid - invalidate one or more IO PDIR entries
731 * @ioc: IO MMU structure which owns the pdir we are interested in.
732 * @iova: IO Virtual Address mapped earlier
733 * @byte_cnt: number of bytes this mapping covers.
734 *
735 * Marking the IO PDIR entry(ies) as Invalid and invalidate
736 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
737 * is to purge stale entries in the IO TLB when unmapping entries.
738 *
739 * The PCOM register supports purging of multiple pages, with a minium
740 * of 1 page and a maximum of 2GB. Hardware requires the address be
741 * aligned to the size of the range being purged. The size of the range
742 * must be a power of 2. The "Cool perf optimization" in the
743 * allocation routine helps keep that true.
744 */
745 static SBA_INLINE void
sba_mark_invalid(struct ioc * ioc,dma_addr_t iova,size_t byte_cnt)746 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
747 {
748 u32 iovp = (u32) SBA_IOVP(ioc,iova);
749
750 /* Even though this is a big-endian machine, the entries
751 ** in the iopdir are little endian. That's why we clear the byte
752 ** at +7 instead of at +0.
753 */
754 int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
755
756 /* Must be non-zero and rounded up */
757 ASSERT(byte_cnt > 0);
758 ASSERT(0 == (byte_cnt & ~IOVP_MASK));
759
760 #ifdef ASSERT_PDIR_SANITY
761 /* Assert first pdir entry is set */
762 if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
763 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
764 }
765 #endif
766
767 if (byte_cnt <= IOVP_SIZE)
768 {
769 ASSERT( off < ioc->pdir_size);
770
771 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
772
773 /*
774 ** clear I/O PDIR entry "valid" bit
775 ** Do NOT clear the rest - save it for debugging.
776 ** We should only clear bits that have previously
777 ** been enabled.
778 */
779 ((u8 *)(ioc->pdir_base))[off] = 0;
780 } else {
781 u32 t = get_order(byte_cnt) + PAGE_SHIFT;
782
783 iovp |= t;
784 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
785
786 do {
787 /* verify this pdir entry is enabled */
788 ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80));
789 /* clear I/O Pdir entry "valid" bit first */
790 ((u8 *)(ioc->pdir_base))[off] = 0;
791 off += sizeof(u64);
792 byte_cnt -= IOVP_SIZE;
793 } while (byte_cnt > 0);
794 }
795
796 WRITE_REG(iovp, ioc->ioc_hpa+IOC_PCOM);
797 }
798
799 /**
800 * sba_dma_supported - PCI driver can query DMA support
801 * @dev: instance of PCI owned by the driver that's asking
802 * @mask: number of address bits this PCI device can handle
803 *
804 * See Documentation/DMA-mapping.txt
805 */
806 static int
sba_dma_supported(struct pci_dev * dev,u64 mask)807 sba_dma_supported( struct pci_dev *dev, u64 mask)
808 {
809 if (dev == NULL) {
810 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
811 BUG();
812 return(0);
813 }
814
815 /* only support 32-bit PCI devices - no DAC support (yet) */
816 return((int) (mask == 0xffffffffUL));
817 }
818
819
820 /**
821 * sba_map_single - map one buffer and return IOVA for DMA
822 * @dev: instance of PCI owned by the driver that's asking.
823 * @addr: driver buffer to map.
824 * @size: number of bytes to map in driver buffer.
825 * @direction: R/W or both.
826 *
827 * See Documentation/DMA-mapping.txt
828 */
829 static dma_addr_t
sba_map_single(struct pci_dev * dev,void * addr,size_t size,int direction)830 sba_map_single(struct pci_dev *dev, void *addr, size_t size, int direction)
831 {
832 struct ioc *ioc;
833 unsigned long flags;
834 dma_addr_t iovp;
835 dma_addr_t offset;
836 u64 *pdir_start;
837 int pide;
838
839 ASSERT(size > 0);
840 ASSERT(size <= DMA_CHUNK_SIZE);
841
842 ASSERT(dev->sysdata);
843 ioc = GET_IOC(dev);
844 ASSERT(ioc);
845
846 /* save offset bits */
847 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
848
849 /* round up to nearest IOVP_SIZE */
850 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
851
852 spin_lock_irqsave(&ioc->res_lock, flags);
853 #ifdef ASSERT_PDIR_SANITY
854 sba_check_pdir(ioc,"Check before sba_map_single()");
855 #endif
856
857 #ifdef CONFIG_PROC_FS
858 ioc->msingle_calls++;
859 ioc->msingle_pages += size >> IOVP_SHIFT;
860 #endif
861 pide = sba_alloc_range(ioc, size);
862 iovp = (dma_addr_t) pide << IOVP_SHIFT;
863
864 DBG_RUN("%s() 0x%p -> 0x%lx",
865 __FUNCTION__, addr, (long) iovp | offset);
866
867 pdir_start = &(ioc->pdir_base[pide]);
868
869 while (size > 0) {
870 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
871 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr);
872
873 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
874 pdir_start,
875 (u8) (((u8 *) pdir_start)[7]),
876 (u8) (((u8 *) pdir_start)[6]),
877 (u8) (((u8 *) pdir_start)[5]),
878 (u8) (((u8 *) pdir_start)[4]),
879 (u8) (((u8 *) pdir_start)[3]),
880 (u8) (((u8 *) pdir_start)[2]),
881 (u8) (((u8 *) pdir_start)[1]),
882 (u8) (((u8 *) pdir_start)[0])
883 );
884
885 addr += IOVP_SIZE;
886 size -= IOVP_SIZE;
887 pdir_start++;
888 }
889 /* form complete address */
890 #ifdef ASSERT_PDIR_SANITY
891 sba_check_pdir(ioc,"Check after sba_map_single()");
892 #endif
893 spin_unlock_irqrestore(&ioc->res_lock, flags);
894 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
895 }
896
897
898 /**
899 * sba_unmap_single - unmap one IOVA and free resources
900 * @dev: instance of PCI owned by the driver that's asking.
901 * @iova: IOVA of driver buffer previously mapped.
902 * @size: number of bytes mapped in driver buffer.
903 * @direction: R/W or both.
904 *
905 * See Documentation/DMA-mapping.txt
906 */
907 static void
sba_unmap_single(struct pci_dev * dev,dma_addr_t iova,size_t size,int direction)908 sba_unmap_single(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction)
909 {
910 struct ioc *ioc;
911 #if DELAYED_RESOURCE_CNT > 0
912 struct sba_dma_pair *d;
913 #endif
914 unsigned long flags;
915 dma_addr_t offset;
916
917 ASSERT(dev->sysdata);
918 ioc = GET_IOC(dev);
919 ASSERT(ioc);
920
921 offset = iova & ~IOVP_MASK;
922
923 DBG_RUN("%s() iovp 0x%lx/%x\n",
924 __FUNCTION__, (long) iova, size);
925
926 iova ^= offset; /* clear offset bits */
927 size += offset;
928 size = ROUNDUP(size, IOVP_SIZE);
929
930 spin_lock_irqsave(&ioc->res_lock, flags);
931
932 #ifdef CONFIG_PROC_FS
933 ioc->usingle_calls++;
934 ioc->usingle_pages += size >> IOVP_SHIFT;
935 #endif
936
937 #if DELAYED_RESOURCE_CNT > 0
938 d = &(ioc->saved[ioc->saved_cnt]);
939 d->iova = iova;
940 d->size = size;
941 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
942 int cnt = ioc->saved_cnt;
943 while (cnt--) {
944 sba_mark_invalid(ioc, d->iova, d->size);
945 sba_free_range(ioc, d->iova, d->size);
946 d--;
947 }
948 ioc->saved_cnt = 0;
949 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
950 }
951 #else /* DELAYED_RESOURCE_CNT == 0 */
952 sba_mark_invalid(ioc, iova, size);
953 sba_free_range(ioc, iova, size);
954 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
955 #endif /* DELAYED_RESOURCE_CNT == 0 */
956 spin_unlock_irqrestore(&ioc->res_lock, flags);
957
958 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
959 ** For Astro based systems this isn't a big deal WRT performance.
960 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
961 ** we don't need the syncdma. The issue here is I/O MMU cachelines
962 ** are *not* coherent in all cases. May be hwrev dependent.
963 ** Need to investigate more.
964 asm volatile("syncdma");
965 */
966 }
967
968
969 /**
970 * sba_alloc_consistent - allocate/map shared mem for DMA
971 * @hwdev: instance of PCI owned by the driver that's asking.
972 * @size: number of bytes mapped in driver buffer.
973 * @dma_handle: IOVA of new buffer.
974 *
975 * See Documentation/DMA-mapping.txt
976 */
977 static void *
sba_alloc_consistent(struct pci_dev * hwdev,size_t size,dma_addr_t * dma_handle)978 sba_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
979 {
980 void *ret;
981
982 if (!hwdev) {
983 /* only support PCI */
984 *dma_handle = 0;
985 return 0;
986 }
987
988 ret = (void *) __get_free_pages(GFP_ATOMIC, get_order(size));
989
990 if (ret) {
991 memset(ret, 0, size);
992 *dma_handle = sba_map_single(hwdev, ret, size, 0);
993 }
994
995 return ret;
996 }
997
998
999 /**
1000 * sba_free_consistent - free/unmap shared mem for DMA
1001 * @hwdev: instance of PCI owned by the driver that's asking.
1002 * @size: number of bytes mapped in driver buffer.
1003 * @vaddr: virtual address IOVA of "consistent" buffer.
1004 * @dma_handler: IO virtual address of "consistent" buffer.
1005 *
1006 * See Documentation/DMA-mapping.txt
1007 */
1008 static void
sba_free_consistent(struct pci_dev * hwdev,size_t size,void * vaddr,dma_addr_t dma_handle)1009 sba_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
1010 {
1011 sba_unmap_single(hwdev, dma_handle, size, 0);
1012 free_pages((unsigned long) vaddr, get_order(size));
1013 }
1014
1015
1016 /*
1017 ** Since 0 is a valid pdir_base index value, can't use that
1018 ** to determine if a value is valid or not. Use a flag to indicate
1019 ** the SG list entry contains a valid pdir index.
1020 */
1021 #define PIDE_FLAG 0x80000000UL
1022
1023 #ifdef DEBUG_LARGE_SG_ENTRIES
1024 int dump_run_sg = 0;
1025 #endif
1026
1027
1028 /**
1029 * sba_fill_pdir - write allocated SG entries into IO PDIR
1030 * @ioc: IO MMU structure which owns the pdir we are interested in.
1031 * @startsg: list of IOVA/size pairs
1032 * @nents: number of entries in startsg list
1033 *
1034 * Take preprocessed SG list and write corresponding entries
1035 * in the IO PDIR.
1036 */
1037
1038 static SBA_INLINE int
sba_fill_pdir(struct ioc * ioc,struct scatterlist * startsg,int nents)1039 sba_fill_pdir(
1040 struct ioc *ioc,
1041 struct scatterlist *startsg,
1042 int nents)
1043 {
1044 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
1045 int n_mappings = 0;
1046 u64 *pdirp = 0;
1047 unsigned long dma_offset = 0;
1048
1049 dma_sg--;
1050 while (nents-- > 0) {
1051 int cnt = sg_dma_len(startsg);
1052 sg_dma_len(startsg) = 0;
1053
1054 #ifdef DEBUG_LARGE_SG_ENTRIES
1055 if (dump_run_sg)
1056 printk(KERN_DEBUG " %2d : %08lx/%05x %p/%05x\n",
1057 nents,
1058 (unsigned long) sg_dma_address(startsg), cnt,
1059 sg_virt_addr(startsg), startsg->length
1060 );
1061 #else
1062 DBG_RUN_SG(" %d : %08lx/%05x %p/%05x\n",
1063 nents,
1064 (unsigned long) sg_dma_address(startsg), cnt,
1065 sg_virt_addr(startsg), startsg->length
1066 );
1067 #endif
1068 /*
1069 ** Look for the start of a new DMA stream
1070 */
1071 if (sg_dma_address(startsg) & PIDE_FLAG) {
1072 u32 pide = sg_dma_address(startsg) & ~PIDE_FLAG;
1073 dma_offset = (unsigned long) pide & ~IOVP_MASK;
1074 sg_dma_address(startsg) = 0;
1075 dma_sg++;
1076 sg_dma_address(dma_sg) = pide;
1077 pdirp = &(ioc->pdir_base[pide >> IOVP_SHIFT]);
1078 n_mappings++;
1079 }
1080
1081 /*
1082 ** Look for a VCONTIG chunk
1083 */
1084 if (cnt) {
1085 unsigned long vaddr = (unsigned long) sg_virt_addr(startsg);
1086 ASSERT(pdirp);
1087
1088 /* Since multiple Vcontig blocks could make up
1089 ** one DMA stream, *add* cnt to dma_len.
1090 */
1091 sg_dma_len(dma_sg) += cnt;
1092 cnt += dma_offset;
1093 dma_offset=0; /* only want offset on first chunk */
1094 cnt = ROUNDUP(cnt, IOVP_SIZE);
1095 #ifdef CONFIG_PROC_FS
1096 ioc->msg_pages += cnt >> IOVP_SHIFT;
1097 #endif
1098 do {
1099 sba_io_pdir_entry(pdirp, KERNEL_SPACE, vaddr);
1100 vaddr += IOVP_SIZE;
1101 cnt -= IOVP_SIZE;
1102 pdirp++;
1103 } while (cnt > 0);
1104 }
1105 startsg++;
1106 }
1107 #ifdef DEBUG_LARGE_SG_ENTRIES
1108 dump_run_sg = 0;
1109 #endif
1110 return(n_mappings);
1111 }
1112
1113
1114 /*
1115 ** Two address ranges are DMA contiguous *iff* "end of prev" and
1116 ** "start of next" are both on a page boundry.
1117 **
1118 ** (shift left is a quick trick to mask off upper bits)
1119 */
1120 #define DMA_CONTIG(__X, __Y) \
1121 (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - PAGE_SHIFT)) == 0UL)
1122
1123
1124 /**
1125 * sba_coalesce_chunks - preprocess the SG list
1126 * @ioc: IO MMU structure which owns the pdir we are interested in.
1127 * @startsg: list of IOVA/size pairs
1128 * @nents: number of entries in startsg list
1129 *
1130 * First pass is to walk the SG list and determine where the breaks are
1131 * in the DMA stream. Allocates PDIR entries but does not fill them.
1132 * Returns the number of DMA chunks.
1133 *
1134 * Doing the fill seperate from the coalescing/allocation keeps the
1135 * code simpler. Future enhancement could make one pass through
1136 * the sglist do both.
1137 */
1138 static SBA_INLINE int
sba_coalesce_chunks(struct ioc * ioc,struct scatterlist * startsg,int nents)1139 sba_coalesce_chunks( struct ioc *ioc,
1140 struct scatterlist *startsg,
1141 int nents)
1142 {
1143 struct scatterlist *vcontig_sg; /* VCONTIG chunk head */
1144 unsigned long vcontig_len; /* len of VCONTIG chunk */
1145 unsigned long vcontig_end;
1146 struct scatterlist *dma_sg; /* next DMA stream head */
1147 unsigned long dma_offset, dma_len; /* start/len of DMA stream */
1148 int n_mappings = 0;
1149
1150 while (nents > 0) {
1151 unsigned long vaddr = (unsigned long) sg_virt_addr(startsg);
1152
1153 /*
1154 ** Prepare for first/next DMA stream
1155 */
1156 dma_sg = vcontig_sg = startsg;
1157 dma_len = vcontig_len = vcontig_end = startsg->length;
1158 vcontig_end += vaddr;
1159 dma_offset = vaddr & ~IOVP_MASK;
1160
1161 /* PARANOID: clear entries */
1162 sg_dma_address(startsg) = 0;
1163 sg_dma_len(startsg) = 0;
1164
1165 /*
1166 ** This loop terminates one iteration "early" since
1167 ** it's always looking one "ahead".
1168 */
1169 while (--nents > 0) {
1170 unsigned long vaddr; /* tmp */
1171
1172 startsg++;
1173
1174 /* PARANOID: clear entries */
1175 sg_dma_address(startsg) = 0;
1176 sg_dma_len(startsg) = 0;
1177
1178 /* catch brokenness in SCSI layer */
1179 ASSERT(startsg->length <= DMA_CHUNK_SIZE);
1180
1181 /*
1182 ** First make sure current dma stream won't
1183 ** exceed DMA_CHUNK_SIZE if we coalesce the
1184 ** next entry.
1185 */
1186 if (((dma_len + dma_offset + startsg->length + ~IOVP_MASK) & IOVP_MASK) > DMA_CHUNK_SIZE)
1187 break;
1188
1189 /*
1190 ** Then look for virtually contiguous blocks.
1191 ** PARISC needs to associate a virtual address
1192 ** with each IO address mapped. The CPU cache is
1193 ** virtually tagged and the IOMMU uses part
1194 ** of the virtual address to participate in
1195 ** CPU cache coherency.
1196 **
1197 ** append the next transaction?
1198 */
1199 vaddr = (unsigned long) sg_virt_addr(startsg);
1200 if (vcontig_end == vaddr)
1201 {
1202 vcontig_len += startsg->length;
1203 vcontig_end += startsg->length;
1204 dma_len += startsg->length;
1205 continue;
1206 }
1207
1208 #ifdef DEBUG_LARGE_SG_ENTRIES
1209 dump_run_sg = (vcontig_len > IOVP_SIZE);
1210 #endif
1211
1212 /*
1213 ** Not virtually contigous.
1214 ** Terminate prev chunk.
1215 ** Start a new chunk.
1216 **
1217 ** Once we start a new VCONTIG chunk, dma_offset
1218 ** can't change. And we need the offset from the first
1219 ** chunk - not the last one. Ergo Successive chunks
1220 ** must start on page boundaries and dove tail
1221 ** with it's predecessor.
1222 */
1223 sg_dma_len(vcontig_sg) = vcontig_len;
1224
1225 vcontig_sg = startsg;
1226 vcontig_len = startsg->length;
1227
1228 /*
1229 ** 3) do the entries end/start on page boundaries?
1230 ** Don't update vcontig_end until we've checked.
1231 */
1232 if (DMA_CONTIG(vcontig_end, vaddr))
1233 {
1234 vcontig_end = vcontig_len + vaddr;
1235 dma_len += vcontig_len;
1236 continue;
1237 } else {
1238 break;
1239 }
1240 }
1241
1242 /*
1243 ** End of DMA Stream
1244 ** Terminate last VCONTIG block.
1245 ** Allocate space for DMA stream.
1246 */
1247 sg_dma_len(vcontig_sg) = vcontig_len;
1248 dma_len = (dma_len + dma_offset + ~IOVP_MASK) & IOVP_MASK;
1249 ASSERT(dma_len <= DMA_CHUNK_SIZE);
1250 sg_dma_address(dma_sg) =
1251 PIDE_FLAG
1252 | (sba_alloc_range(ioc, dma_len) << IOVP_SHIFT)
1253 | dma_offset;
1254 n_mappings++;
1255 }
1256
1257 return n_mappings;
1258 }
1259
1260
1261 /**
1262 * sba_map_sg - map Scatter/Gather list
1263 * @dev: instance of PCI owned by the driver that's asking.
1264 * @sglist: array of buffer/length pairs
1265 * @nents: number of entries in list
1266 * @direction: R/W or both.
1267 *
1268 * See Documentation/DMA-mapping.txt
1269 */
1270 static int
sba_map_sg(struct pci_dev * dev,struct scatterlist * sglist,int nents,int direction)1271 sba_map_sg(struct pci_dev *dev, struct scatterlist *sglist, int nents, int direction)
1272 {
1273 struct ioc *ioc;
1274 int coalesced, filled = 0;
1275 unsigned long flags;
1276
1277 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1278
1279 ASSERT(dev->sysdata);
1280 ioc = GET_IOC(dev);
1281 ASSERT(ioc);
1282
1283 /* Fast path single entry scatterlists. */
1284 if (nents == 1) {
1285 sg_dma_address(sglist) = sba_map_single(dev,
1286 sg_virt_addr(sglist),
1287 sglist->length, direction);
1288 sg_dma_len(sglist) = sglist->length;
1289 return 1;
1290 }
1291
1292 spin_lock_irqsave(&ioc->res_lock, flags);
1293
1294 #ifdef ASSERT_PDIR_SANITY
1295 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1296 {
1297 sba_dump_sg(ioc, sglist, nents);
1298 panic("Check before sba_map_sg()");
1299 }
1300 #endif
1301
1302 #ifdef CONFIG_PROC_FS
1303 ioc->msg_calls++;
1304 #endif
1305
1306 /*
1307 ** First coalesce the chunks and allocate I/O pdir space
1308 **
1309 ** If this is one DMA stream, we can properly map using the
1310 ** correct virtual address associated with each DMA page.
1311 ** w/o this association, we wouldn't have coherent DMA!
1312 ** Access to the virtual address is what forces a two pass algorithm.
1313 */
1314 coalesced = sba_coalesce_chunks(ioc, sglist, nents);
1315
1316 /*
1317 ** Program the I/O Pdir
1318 **
1319 ** map the virtual addresses to the I/O Pdir
1320 ** o dma_address will contain the pdir index
1321 ** o dma_len will contain the number of bytes to map
1322 ** o address contains the virtual address.
1323 */
1324 filled = sba_fill_pdir(ioc, sglist, nents);
1325
1326 #ifdef ASSERT_PDIR_SANITY
1327 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1328 {
1329 sba_dump_sg(ioc, sglist, nents);
1330 panic("Check after sba_map_sg()\n");
1331 }
1332 #endif
1333
1334 spin_unlock_irqrestore(&ioc->res_lock, flags);
1335
1336 ASSERT(coalesced == filled);
1337 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1338
1339 return filled;
1340 }
1341
1342
1343 /**
1344 * sba_unmap_sg - unmap Scatter/Gather list
1345 * @dev: instance of PCI owned by the driver that's asking.
1346 * @sglist: array of buffer/length pairs
1347 * @nents: number of entries in list
1348 * @direction: R/W or both.
1349 *
1350 * See Documentation/DMA-mapping.txt
1351 */
1352 static void
sba_unmap_sg(struct pci_dev * dev,struct scatterlist * sglist,int nents,int direction)1353 sba_unmap_sg(struct pci_dev *dev, struct scatterlist *sglist, int nents, int direction)
1354 {
1355 struct ioc *ioc;
1356 #ifdef ASSERT_PDIR_SANITY
1357 unsigned long flags;
1358 #endif
1359
1360 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1361 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1362
1363 ASSERT(dev->sysdata);
1364 ioc = GET_IOC(dev);
1365 ASSERT(ioc);
1366
1367 #ifdef CONFIG_PROC_FS
1368 ioc->usg_calls++;
1369 #endif
1370
1371 #ifdef ASSERT_PDIR_SANITY
1372 spin_lock_irqsave(&ioc->res_lock, flags);
1373 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1374 spin_unlock_irqrestore(&ioc->res_lock, flags);
1375 #endif
1376
1377 while (sg_dma_len(sglist) && nents--) {
1378
1379 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1380 #ifdef CONFIG_PROC_FS
1381 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1382 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1383 #endif
1384 ++sglist;
1385 }
1386
1387 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1388
1389 #ifdef ASSERT_PDIR_SANITY
1390 spin_lock_irqsave(&ioc->res_lock, flags);
1391 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1392 spin_unlock_irqrestore(&ioc->res_lock, flags);
1393 #endif
1394
1395 }
1396
1397 static struct pci_dma_ops sba_ops = {
1398 sba_dma_supported,
1399 sba_alloc_consistent, /* allocate cacheable host mem */
1400 sba_free_consistent, /* release cacheable host mem */
1401 sba_map_single,
1402 sba_unmap_single,
1403 sba_map_sg,
1404 sba_unmap_sg,
1405 NULL, /* dma_sync_single */
1406 NULL /* dma_sync_sg */
1407 };
1408
1409
1410 /**************************************************************************
1411 **
1412 ** SBA PAT PDC support
1413 **
1414 ** o call pdc_pat_cell_module()
1415 ** o store ranges in PCI "resource" structures
1416 **
1417 **************************************************************************/
1418
1419 static void
sba_get_pat_resources(struct sba_device * sba_dev)1420 sba_get_pat_resources(struct sba_device *sba_dev)
1421 {
1422 #if 0
1423 /*
1424 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1425 ** PAT PDC to program the SBA/LBA directed range registers...this
1426 ** burden may fall on the LBA code since it directly supports the
1427 ** PCI subsystem. It's not clear yet. - ggg
1428 */
1429 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1430 FIXME : ???
1431 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1432 Tells where the dvi bits are located in the address.
1433 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1434 FIXME : ???
1435 #endif
1436 }
1437
1438
1439 /**************************************************************
1440 *
1441 * Initialization and claim
1442 *
1443 ***************************************************************/
1444 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1445 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1446 static void *
sba_alloc_pdir(unsigned int pdir_size)1447 sba_alloc_pdir(unsigned int pdir_size)
1448 {
1449 unsigned long pdir_base;
1450 unsigned long pdir_order = get_order(pdir_size);
1451
1452 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1453 if (NULL == (void *) pdir_base)
1454 panic("sba_ioc_init() could not allocate I/O Page Table\n");
1455
1456 /* If this is not PA8700 (PCX-W2)
1457 ** OR newer than ver 2.2
1458 ** OR in a system that doesn't need VINDEX bits from SBA,
1459 **
1460 ** then we aren't exposed to the HW bug.
1461 */
1462 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1463 || (boot_cpu_data.pdc.versions > 0x202)
1464 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1465 return (void *) pdir_base;
1466
1467 /*
1468 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1469 *
1470 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1471 * Ike/Astro can cause silent data corruption. This is only
1472 * a problem if the I/O PDIR is located in memory such that
1473 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1474 *
1475 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1476 * right physical address, we can either avoid (IOPDIR <= 1MB)
1477 * or minimize (2MB IO Pdir) the problem if we restrict the
1478 * IO Pdir to a maximum size of 2MB-128K (1902K).
1479 *
1480 * Because we always allocate 2^N sized IO pdirs, either of the
1481 * "bad" regions will be the last 128K if at all. That's easy
1482 * to test for.
1483 *
1484 */
1485 if (pdir_order <= (19-12)) {
1486 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1487 /* allocate a new one on 512k alignment */
1488 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1489 /* release original */
1490 free_pages(pdir_base, pdir_order);
1491
1492 pdir_base = new_pdir;
1493
1494 /* release excess */
1495 while (pdir_order < (19-12)) {
1496 new_pdir += pdir_size;
1497 free_pages(new_pdir, pdir_order);
1498 pdir_order +=1;
1499 pdir_size <<=1;
1500 }
1501 }
1502 } else {
1503 /*
1504 ** 1MB or 2MB Pdir
1505 ** Needs to be aligned on an "odd" 1MB boundary.
1506 */
1507 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1508
1509 /* release original */
1510 free_pages( pdir_base, pdir_order);
1511
1512 /* release first 1MB */
1513 free_pages(new_pdir, 20-12);
1514
1515 pdir_base = new_pdir + 1024*1024;
1516
1517 if (pdir_order > (20-12)) {
1518 /*
1519 ** 2MB Pdir.
1520 **
1521 ** Flag tells init_bitmap() to mark bad 128k as used
1522 ** and to reduce the size by 128k.
1523 */
1524 piranha_bad_128k = 1;
1525
1526 new_pdir += 3*1024*1024;
1527 /* release last 1MB */
1528 free_pages(new_pdir, 20-12);
1529
1530 /* release unusable 128KB */
1531 free_pages(new_pdir - 128*1024 , 17-12);
1532
1533 pdir_size -= 128*1024;
1534 }
1535 }
1536
1537 memset((void *) pdir_base, 0, pdir_size);
1538 return (void *) pdir_base;
1539 }
1540
1541
1542 static void
sba_ioc_init(struct parisc_device * sba,struct ioc * ioc,int ioc_num)1543 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1544 {
1545 /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
1546 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1547
1548 u32 iova_space_size, iova_space_mask;
1549 int pdir_size, iov_order;
1550 unsigned long physmem;
1551 struct parisc_device *lba;
1552
1553 /*
1554 ** Determine IOVA Space size from memory size.
1555 **
1556 ** Ideally, PCI drivers would register the maximum number
1557 ** of DMA they can have outstanding for each device they
1558 ** own. Next best thing would be to guess how much DMA
1559 ** can be outstanding based on PCI Class/sub-class. Both
1560 ** methods still require some "extra" to support PCI
1561 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1562 **
1563 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1564 ** for DMA hints - ergo only 30 bits max.
1565 */
1566
1567 physmem = num_physpages << PAGE_SHIFT;
1568 iova_space_size = (u32) (physmem/(sba_mem_ratio*global_ioc_cnt));
1569
1570 /* limit IOVA space size to 1MB-1GB */
1571 if (iova_space_size < 1024*1024) {
1572 iova_space_size = 1024*1024;
1573 }
1574 #ifdef __LP64__
1575 else if (iova_space_size > 512*1024*1024) {
1576 iova_space_size = 512*1024*1024;
1577 }
1578 #endif
1579
1580 /*
1581 ** iova space must be log2() in size.
1582 ** thus, pdir/res_map will also be log2().
1583 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1584 */
1585 iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT));
1586 ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */
1587 ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */
1588 iova_space_size = 1 << (iov_order + IOVP_SHIFT);
1589
1590 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1591
1592 ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */
1593
1594 /* Verify it's a power of two */
1595 ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT));
1596
1597 DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n",
1598 __FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
1599 iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
1600
1601 /* FIXME : DMA HINTs not used */
1602 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1603 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1604
1605 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1606
1607 DBG_INIT("%s() pdir %p size %x hint_shift_pdir %x hint_mask_pdir %lx\n",
1608 __FUNCTION__, ioc->pdir_base, pdir_size,
1609 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1610
1611 ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
1612 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1613
1614 /* build IMASK for IOC and Elroy */
1615 iova_space_mask = 0xffffffff;
1616 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1617
1618 /*
1619 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1620 ** ibase=0, imask=0xFE000000, size=0x2000000.
1621 */
1622 ioc->ibase = IOC_IOVA_SPACE_BASE | 1; /* bit 0 == enable bit */
1623 ioc->imask = iova_space_mask; /* save it */
1624
1625 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1626 __FUNCTION__, ioc->ibase, ioc->imask);
1627
1628 /*
1629 ** FIXME: Hint registers are programmed with default hint
1630 ** values during boot, so hints should be sane even if we
1631 ** can't reprogram them the way drivers want.
1632 */
1633
1634 /*
1635 ** setup Elroy IBASE/IMASK registers as well.
1636 */
1637 for (lba = sba->child; lba; lba = lba->sibling) {
1638 int rope_num = (lba->hpa >> 13) & 0xf;
1639 if (rope_num >> 3 == ioc_num)
1640 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1641 }
1642
1643 /*
1644 ** Program the IOC's ibase and enable IOVA translation
1645 */
1646 WRITE_REG(ioc->ibase, ioc->ioc_hpa+IOC_IBASE);
1647 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1648
1649 /* Set I/O PDIR Page size to 4K */
1650 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1651
1652 /*
1653 ** Clear I/O TLB of any possible entries.
1654 ** (Yes. This is a bit paranoid...but so what)
1655 */
1656 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1657
1658 DBG_INIT("%s() DONE\n", __FUNCTION__);
1659 }
1660
1661
1662
1663 /**************************************************************************
1664 **
1665 ** SBA initialization code (HW and SW)
1666 **
1667 ** o identify SBA chip itself
1668 ** o initialize SBA chip modes (HardFail)
1669 ** o initialize SBA chip modes (HardFail)
1670 ** o FIXME: initialize DMA hints for reasonable defaults
1671 **
1672 **************************************************************************/
1673
1674 static void
sba_hw_init(struct sba_device * sba_dev)1675 sba_hw_init(struct sba_device *sba_dev)
1676 {
1677 int i;
1678 int num_ioc;
1679 u64 ioc_ctl;
1680
1681 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1682 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1683 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1684 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1685 ioc_ctl |= IOC_CTRL_TC; /* Astro: firmware enables this */
1686
1687 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1688
1689 #ifdef DEBUG_SBA_INIT
1690 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1691 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1692 #endif
1693
1694 if (IS_ASTRO(sba_dev->iodc)) {
1695 /* PAT_PDC (L-class) also reports the same goofy base */
1696 sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
1697 num_ioc = 1;
1698 } else {
1699 sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
1700 num_ioc = 2;
1701 }
1702
1703 sba_dev->num_ioc = num_ioc;
1704 for (i = 0; i < num_ioc; i++) {
1705 sba_dev->ioc[i].ioc_hpa += sba_dev->sba_hpa + IKE_IOC_OFFSET(i);
1706
1707 /*
1708 ** Make sure the box crashes if we get any errors on a rope.
1709 */
1710 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
1711 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
1712 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
1713 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
1714 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
1715 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
1716 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
1717 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1718
1719 /* flush out the writes */
1720 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1721
1722 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1723 }
1724 }
1725
1726 static void
sba_common_init(struct sba_device * sba_dev)1727 sba_common_init(struct sba_device *sba_dev)
1728 {
1729 int i;
1730
1731 /* add this one to the head of the list (order doesn't matter)
1732 ** This will be useful for debugging - especially if we get coredumps
1733 */
1734 sba_dev->next = sba_list;
1735 sba_list = sba_dev;
1736
1737 for(i=0; i< sba_dev->num_ioc; i++) {
1738 int res_size;
1739 #ifdef DEBUG_DMB_TRAP
1740 extern void iterate_pages(unsigned long , unsigned long ,
1741 void (*)(pte_t * , unsigned long),
1742 unsigned long );
1743 void set_data_memory_break(pte_t * , unsigned long);
1744 #endif
1745 /* resource map size dictated by pdir_size */
1746 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1747
1748 /* Second part of PIRANHA BUG */
1749 if (piranha_bad_128k) {
1750 res_size -= (128*1024)/sizeof(u64);
1751 }
1752
1753 res_size >>= 3; /* convert bit count to byte count */
1754 DBG_INIT("%s() res_size 0x%x\n",
1755 __FUNCTION__, res_size);
1756
1757 sba_dev->ioc[i].res_size = res_size;
1758 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1759
1760 #ifdef DEBUG_DMB_TRAP
1761 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1762 set_data_memory_break, 0);
1763 #endif
1764
1765 if (NULL == sba_dev->ioc[i].res_map)
1766 {
1767 panic(__FILE__ ":%s() could not allocate resource map\n", __FUNCTION__ );
1768 }
1769
1770 memset(sba_dev->ioc[i].res_map, 0, res_size);
1771 /* next available IOVP - circular search */
1772 sba_dev->ioc[i].res_hint = (unsigned long *)
1773 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1774
1775 #ifdef ASSERT_PDIR_SANITY
1776 /* Mark first bit busy - ie no IOVA 0 */
1777 sba_dev->ioc[i].res_map[0] = 0x80;
1778 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1779 #endif
1780
1781 /* Third (and last) part of PIRANHA BUG */
1782 if (piranha_bad_128k) {
1783 /* region from +1408K to +1536 is un-usable. */
1784
1785 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1786 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1787 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1788 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1789
1790 /* mark that part of the io pdir busy */
1791 while (p_start < p_end)
1792 *p_start++ = -1;
1793
1794 }
1795
1796 #ifdef DEBUG_DMB_TRAP
1797 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1798 set_data_memory_break, 0);
1799 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1800 set_data_memory_break, 0);
1801 #endif
1802
1803 DBG_INIT("%s() %d res_map %x %p\n",
1804 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1805 }
1806
1807 sba_dev->sba_lock = SPIN_LOCK_UNLOCKED;
1808 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1809
1810 #ifdef DEBUG_SBA_INIT
1811 /*
1812 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1813 * (bit #61, big endian), we have to flush and sync every time
1814 * IO-PDIR is changed in Ike/Astro.
1815 */
1816 if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
1817 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1818 } else {
1819 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1820 }
1821 #endif
1822 }
1823
1824 #ifdef CONFIG_PROC_FS
sba_proc_info(char * buf,char ** start,off_t offset,int len)1825 static int sba_proc_info(char *buf, char **start, off_t offset, int len)
1826 {
1827 struct sba_device *sba_dev = sba_list;
1828 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1829 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1830 unsigned long i = 0, avg = 0, min, max;
1831
1832 sprintf(buf, "%s rev %d.%d\n",
1833 sba_dev->name,
1834 (sba_dev->hw_rev & 0x7) + 1,
1835 (sba_dev->hw_rev & 0x18) >> 3
1836 );
1837 sprintf(buf, "%sIO PDIR size : %d bytes (%d entries)\n",
1838 buf,
1839 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1840 total_pages);
1841
1842 sprintf(buf, "%sIO PDIR entries : %ld free %ld used (%d%%)\n", buf,
1843 total_pages - ioc->used_pages, ioc->used_pages,
1844 (int) (ioc->used_pages * 100 / total_pages));
1845
1846 sprintf(buf, "%sResource bitmap : %d bytes (%d pages)\n",
1847 buf, ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1848
1849 min = max = ioc->avg_search[0];
1850 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1851 avg += ioc->avg_search[i];
1852 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1853 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1854 }
1855 avg /= SBA_SEARCH_SAMPLE;
1856 sprintf(buf, "%s Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1857 buf, min, avg, max);
1858
1859 sprintf(buf, "%spci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1860 buf, ioc->msingle_calls, ioc->msingle_pages,
1861 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1862
1863 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1864 min = ioc->usingle_calls;
1865 max = ioc->usingle_pages - ioc->usg_pages;
1866 sprintf(buf, "%spci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1867 buf, min, max,
1868 (int) ((max * 1000)/min));
1869
1870 sprintf(buf, "%spci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1871 buf, ioc->msg_calls, ioc->msg_pages,
1872 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1873
1874 sprintf(buf, "%spci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1875 buf, ioc->usg_calls, ioc->usg_pages,
1876 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1877
1878 return strlen(buf);
1879 }
1880
1881 #if 0
1882 /* XXX too much output - exceeds 4k limit and needs to be re-written */
1883 static int
1884 sba_resource_map(char *buf, char **start, off_t offset, int len)
1885 {
1886 struct sba_device *sba_dev = sba_list;
1887 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Mutli-IOC suppoer! */
1888 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
1889 int i;
1890
1891 buf[0] = '\0';
1892 for(i = 0; i < (ioc->res_size / sizeof(unsigned int)); ++i, ++res_ptr) {
1893 if ((i & 7) == 0)
1894 strcat(buf,"\n ");
1895 sprintf(buf, "%s %08x", buf, *res_ptr);
1896 }
1897 strcat(buf, "\n");
1898
1899 return strlen(buf);
1900 }
1901 #endif /* 0 */
1902 #endif /* CONFIG_PROC_FS */
1903
1904 static struct parisc_device_id sba_tbl[] = {
1905 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1906 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1907 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1908 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1909 /* These two entries commented out because we don't find them in a
1910 * buswalk yet. If/when we do, they would cause us to think we had
1911 * many more SBAs then we really do.
1912 * { HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
1913 * { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
1914 */
1915 { 0, }
1916 };
1917
1918 int sba_driver_callback(struct parisc_device *);
1919
1920 static struct parisc_driver sba_driver = {
1921 name: MODULE_NAME,
1922 id_table: sba_tbl,
1923 probe: sba_driver_callback,
1924 };
1925
1926 /*
1927 ** Determine if lba should claim this chip (return 0) or not (return 1).
1928 ** If so, initialize the chip and tell other partners in crime they
1929 ** have work to do.
1930 */
1931 int
sba_driver_callback(struct parisc_device * dev)1932 sba_driver_callback(struct parisc_device *dev)
1933 {
1934 struct sba_device *sba_dev;
1935 u32 func_class;
1936 int i;
1937 char *version;
1938
1939 #ifdef DEBUG_SBA_INIT
1940 sba_dump_ranges(dev->hpa);
1941 #endif
1942
1943 /* Read HW Rev First */
1944 func_class = READ_REG(dev->hpa + SBA_FCLASS);
1945
1946 if (IS_ASTRO(&dev->id)) {
1947 unsigned long fclass;
1948 static char astro_rev[]="Astro ?.?";
1949
1950 /* Astro is broken...Read HW Rev First */
1951 fclass = READ_REG(dev->hpa);
1952
1953 astro_rev[6] = '1' + (char) (fclass & 0x7);
1954 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1955 version = astro_rev;
1956
1957 } else if (IS_IKE(&dev->id)) {
1958 static char ike_rev[]="Ike rev ?";
1959
1960 ike_rev[8] = '0' + (char) (func_class & 0xff);
1961 version = ike_rev;
1962 } else {
1963 static char reo_rev[]="REO rev ?";
1964
1965 reo_rev[8] = '0' + (char) (func_class & 0xff);
1966 version = reo_rev;
1967 }
1968
1969 if (!global_ioc_cnt) {
1970 global_ioc_cnt = count_parisc_driver(&sba_driver);
1971
1972 /* Only Astro has one IOC per SBA */
1973 if (!IS_ASTRO(&dev->id))
1974 global_ioc_cnt *= 2;
1975 }
1976
1977 printk(KERN_INFO "%s found %s at 0x%lx\n",
1978 MODULE_NAME, version, dev->hpa);
1979
1980 #ifdef DEBUG_SBA_INIT
1981 sba_dump_tlb(dev->hpa);
1982 #endif
1983
1984 sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
1985 if (NULL == sba_dev) {
1986 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1987 return(1);
1988 }
1989
1990 dev->sysdata = (void *) sba_dev;
1991 memset(sba_dev, 0, sizeof(struct sba_device));
1992
1993 for(i=0; i<MAX_IOC; i++)
1994 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1995
1996 sba_dev->dev = dev;
1997 sba_dev->hw_rev = func_class;
1998 sba_dev->iodc = &dev->id;
1999 sba_dev->name = dev->name;
2000 sba_dev->sba_hpa = dev->hpa; /* faster access */
2001
2002 sba_get_pat_resources(sba_dev);
2003 sba_hw_init(sba_dev);
2004 sba_common_init(sba_dev);
2005
2006 hppa_dma_ops = &sba_ops;
2007
2008 #ifdef CONFIG_PROC_FS
2009 if (IS_ASTRO(&dev->id)) {
2010 create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
2011 } else if (IS_IKE(&dev->id)) {
2012 create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
2013 } else {
2014 create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
2015 }
2016 #if 0
2017 create_proc_info_entry("bitmap", 0, proc_runway_root, sba_resource_map);
2018 #endif
2019 #endif
2020 return 0;
2021 }
2022
2023 /*
2024 ** One time initialization to let the world know the SBA was found.
2025 ** This is the only routine which is NOT static.
2026 ** Must be called exactly once before pci_init().
2027 */
sba_init(void)2028 void __init sba_init(void)
2029 {
2030 register_parisc_driver(&sba_driver);
2031 }
2032
2033
2034 /**
2035 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2036 * @dev: The parisc device.
2037 *
2038 * This function searches through the registerd IOMMU's and returns the
2039 * appropriate IOMMU data for the given parisc PCI controller.
2040 */
sba_get_iommu(struct parisc_device * pci_hba)2041 void * sba_get_iommu(struct parisc_device *pci_hba)
2042 {
2043 struct sba_device *sba = (struct sba_device *) pci_hba->parent->sysdata;
2044 char t = pci_hba->parent->id.hw_type;
2045 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2046
2047 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
2048 BUG();
2049
2050 return &(sba->ioc[iocnum]);
2051 }
2052