1 /*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/linkage.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
27
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/ptrace.h>
32
33 #include <asm/sibyte/sb1250_regs.h>
34 #include <asm/sibyte/sb1250_int.h>
35 #include <asm/sibyte/sb1250_uart.h>
36 #include <asm/sibyte/sb1250_scd.h>
37 #include <asm/sibyte/sb1250.h>
38 #include <asm/sibyte/64bit.h>
39
40 /*
41 * These are the routines that handle all the low level interrupt stuff.
42 * Actions handled here are: initialization of the interrupt map, requesting of
43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
44 * for interrupt lines
45 */
46
47
48 #define shutdown_sb1250_irq disable_sb1250_irq
49 static void end_sb1250_irq(unsigned int irq);
50 static void enable_sb1250_irq(unsigned int irq);
51 static void disable_sb1250_irq(unsigned int irq);
52 static unsigned int startup_sb1250_irq(unsigned int irq);
53 static void ack_sb1250_irq(unsigned int irq);
54 #ifdef CONFIG_SMP
55 static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
56 #endif
57
58 #ifdef CONFIG_SIBYTE_HAS_LDT
59 extern unsigned long ldt_eoi_space;
60 #endif
61
62 #ifdef CONFIG_KGDB
63 #include <asm/gdb-stub.h>
64 extern void breakpoint(void);
65 static int kgdb_irq;
66 #ifdef CONFIG_GDB_CONSOLE
67 extern void register_gdb_console(void);
68 #endif
69
70 /* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
71 static int kgdb_flag = 1;
nokgdb(char * str)72 static int __init nokgdb(char *str)
73 {
74 kgdb_flag = 0;
75 return 1;
76 }
77 __setup("nokgdb", nokgdb);
78
79 /* Default to UART1 */
80 int kgdb_port = 1;
81 #ifdef CONFIG_SIBYTE_SB1250_DUART
82 extern char sb1250_duart_present[];
83 #endif
84 #endif
85
86 static struct hw_interrupt_type sb1250_irq_type = {
87 "SB1250-IMR",
88 startup_sb1250_irq,
89 shutdown_sb1250_irq,
90 enable_sb1250_irq,
91 disable_sb1250_irq,
92 ack_sb1250_irq,
93 end_sb1250_irq,
94 #ifdef CONFIG_SMP
95 sb1250_set_affinity
96 #else
97 NULL
98 #endif
99 };
100
101 /* Store the CPU id (not the logical number) */
102 int sb1250_irq_owner[SB1250_NR_IRQS];
103
104 spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED;
105
sb1250_mask_irq(int cpu,int irq)106 void sb1250_mask_irq(int cpu, int irq)
107 {
108 unsigned long flags;
109 u64 cur_ints;
110
111 spin_lock_irqsave(&sb1250_imr_lock, flags);
112 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
113 cur_ints |= (((u64) 1) << irq);
114 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
115 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
116 }
117
sb1250_unmask_irq(int cpu,int irq)118 void sb1250_unmask_irq(int cpu, int irq)
119 {
120 unsigned long flags;
121 u64 cur_ints;
122
123 spin_lock_irqsave(&sb1250_imr_lock, flags);
124 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
125 cur_ints &= ~(((u64) 1) << irq);
126 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
127 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
128 }
129
130 #ifdef CONFIG_SMP
sb1250_set_affinity(unsigned int irq,unsigned long mask)131 static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
132 {
133 int i = 0, old_cpu, cpu, int_on;
134 u64 cur_ints;
135 irq_desc_t *desc = irq_desc + irq;
136 unsigned long flags;
137
138 while (mask) {
139 if (mask & 1) {
140 mask >>= 1;
141 break;
142 }
143 mask >>= 1;
144 i++;
145 }
146
147 if (mask) {
148 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
149 return;
150 }
151
152 /* Convert logical CPU to physical CPU */
153 cpu = cpu_logical_map(i);
154
155 /* Protect against other affinity changers and IMR manipulation */
156 spin_lock_irqsave(&desc->lock, flags);
157 spin_lock(&sb1250_imr_lock);
158
159 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
160 old_cpu = sb1250_irq_owner[irq];
161 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK);
162 int_on = !(cur_ints & (((u64) 1) << irq));
163 if (int_on) {
164 /* If it was on, mask it */
165 cur_ints |= (((u64) 1) << irq);
166 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK);
167 }
168 sb1250_irq_owner[irq] = cpu;
169 if (int_on) {
170 /* unmask for the new CPU */
171 cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
172 cur_ints &= ~(((u64) 1) << irq);
173 __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
174 }
175 spin_unlock(&sb1250_imr_lock);
176 spin_unlock_irqrestore(&desc->lock, flags);
177 }
178 #endif
179
180
181 /* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
182 extern void sb1250_irq_handler(void);
183
184 /*****************************************************************************/
185
startup_sb1250_irq(unsigned int irq)186 static unsigned int startup_sb1250_irq(unsigned int irq)
187 {
188 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
189
190 return 0; /* never anything pending */
191 }
192
193
disable_sb1250_irq(unsigned int irq)194 static void disable_sb1250_irq(unsigned int irq)
195 {
196 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
197 }
198
enable_sb1250_irq(unsigned int irq)199 static void enable_sb1250_irq(unsigned int irq)
200 {
201 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
202 }
203
204
ack_sb1250_irq(unsigned int irq)205 static void ack_sb1250_irq(unsigned int irq)
206 {
207 #ifdef CONFIG_SIBYTE_HAS_LDT
208 u64 pending;
209
210 /*
211 * If the interrupt was an HT interrupt, now is the time to
212 * clear it. NOTE: we assume the HT bridge was set up to
213 * deliver the interrupts to all CPUs (which makes affinity
214 * changing easier for us)
215 */
216 pending = in64(KSEG1 + A_IMR_REGISTER(sb1250_irq_owner[irq],
217 R_IMR_LDT_INTERRUPT));
218 pending &= ((u64)1 << (irq));
219 if (pending) {
220 int i;
221 for (i=0; i<smp_num_cpus; i++) {
222 /*
223 * Clear for all CPUs so an affinity switch
224 * doesn't find an old status
225 */
226 out64(pending,
227 KSEG1+A_IMR_REGISTER(cpu_logical_map(i),
228 R_IMR_LDT_INTERRUPT_CLR));
229 }
230
231 /*
232 * Generate EOI. For Pass 1 parts, EOI is a nop. For
233 * Pass 2, the LDT world may be edge-triggered, but
234 * this EOI shouldn't hurt. If they are
235 * level-sensitive, the EOI is required.
236 */
237 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
238 }
239 #endif
240 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
241 }
242
243
end_sb1250_irq(unsigned int irq)244 static void end_sb1250_irq(unsigned int irq)
245 {
246 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
247 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
248 }
249 }
250
251
init_sb1250_irqs(void)252 void __init init_sb1250_irqs(void)
253 {
254 int i;
255
256 for (i = 0; i < NR_IRQS; i++) {
257 irq_desc[i].status = IRQ_DISABLED;
258 irq_desc[i].action = 0;
259 irq_desc[i].depth = 1;
260 if (i < SB1250_NR_IRQS) {
261 irq_desc[i].handler = &sb1250_irq_type;
262 sb1250_irq_owner[i] = 0;
263 } else {
264 irq_desc[i].handler = &no_irq_type;
265 }
266 }
267 }
268
269
sb1250_dummy_handler(int irq,void * dev_id,struct pt_regs * regs)270 static void sb1250_dummy_handler(int irq, void *dev_id, struct pt_regs *regs)
271 {
272 }
273
274 static struct irqaction sb1250_dummy_action = {
275 .handler = sb1250_dummy_handler,
276 .flags = 0,
277 .mask = 0,
278 .name = "sb1250-private",
279 .next = NULL,
280 .dev_id = 0
281 };
282
sb1250_steal_irq(int irq)283 int sb1250_steal_irq(int irq)
284 {
285 irq_desc_t *desc = irq_desc + irq;
286 unsigned long flags;
287 int retval = 0;
288
289 if (irq >= SB1250_NR_IRQS)
290 return -EINVAL;
291
292 spin_lock_irqsave(&desc->lock,flags);
293 /* Don't allow sharing at all for these */
294 if (desc->action != NULL)
295 retval = -EBUSY;
296 else {
297 desc->action = &sb1250_dummy_action;
298 desc->depth = 0;
299 }
300 spin_unlock_irqrestore(&desc->lock,flags);
301 return 0;
302 }
303
304 /*
305 * init_IRQ is called early in the boot sequence from init/main.c. It
306 * is responsible for setting up the interrupt mapper and installing the
307 * handler that will be responsible for dispatching interrupts to the
308 * "right" place.
309 */
310 /*
311 * For now, map all interrupts to IP[2]. We could save
312 * some cycles by parceling out system interrupts to different
313 * IP lines, but keep it simple for bringup. We'll also direct
314 * all interrupts to a single CPU; we should probably route
315 * PCI and LDT to one cpu and everything else to the other
316 * to balance the load a bit.
317 *
318 * On the second cpu, everything is set to IP5, which is
319 * ignored, EXCEPT the mailbox interrupt. That one is
320 * set to IP[2] so it is handled. This is needed so we
321 * can do cross-cpu function calls, as requred by SMP
322 */
323
324 #define IMR_IP2_VAL K_INT_MAP_I0
325 #define IMR_IP3_VAL K_INT_MAP_I1
326 #define IMR_IP4_VAL K_INT_MAP_I2
327 #define IMR_IP5_VAL K_INT_MAP_I3
328 #define IMR_IP6_VAL K_INT_MAP_I4
329
init_IRQ(void)330 void __init init_IRQ(void)
331 {
332
333 unsigned int i;
334 u64 tmp;
335 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
336 STATUSF_IP1 | STATUSF_IP0;
337
338 /* Default everything to IP2 */
339 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
340 out64(IMR_IP2_VAL,
341 KSEG1 + A_IMR_REGISTER(0,
342 R_IMR_INTERRUPT_MAP_BASE) +
343 (i << 3));
344 out64(IMR_IP2_VAL,
345 KSEG1 + A_IMR_REGISTER(1,
346 R_IMR_INTERRUPT_MAP_BASE) +
347 (i << 3));
348 }
349
350 init_sb1250_irqs();
351
352 /*
353 * Map the high 16 bits of the mailbox registers to IP[3], for
354 * inter-cpu messages
355 */
356 /* Was I1 */
357 out64(IMR_IP3_VAL, KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
358 (K_INT_MBOX_0 << 3));
359 out64(IMR_IP3_VAL, KSEG1 + A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
360 (K_INT_MBOX_0 << 3));
361
362 /* Clear the mailboxes. The firmware may leave them dirty */
363 out64(0xffffffffffffffff,
364 KSEG1 + A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU));
365 out64(0xffffffffffffffff,
366 KSEG1 + A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU));
367
368 /* Mask everything except the mailbox registers for both cpus */
369 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
370 out64(tmp, KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK));
371 out64(tmp, KSEG1 + A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK));
372
373 sb1250_steal_irq(K_INT_MBOX_0);
374
375 /*
376 * Note that the timer interrupts are also mapped, but this is
377 * done in sb1250_time_init(). Also, the profiling driver
378 * does its own management of IP7.
379 */
380
381 #ifdef CONFIG_KGDB
382 imask |= STATUSF_IP6;
383 #endif
384 /* Enable necessary IPs, disable the rest */
385 change_c0_status(ST0_IM, imask);
386 set_except_vector(0, sb1250_irq_handler);
387
388 #ifdef CONFIG_KGDB
389 if (kgdb_flag) {
390 kgdb_irq = K_INT_UART_0 + kgdb_port;
391
392 #ifdef CONFIG_SIBYTE_SB1250_DUART
393 sb1250_duart_present[kgdb_port] = 0;
394 #endif
395 /* Setup uart 1 settings, mapper */
396 out64(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
397
398 sb1250_steal_irq(kgdb_irq);
399 out64(IMR_IP6_VAL,
400 IO_SPACE_BASE + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
401 (kgdb_irq<<3));
402 sb1250_unmask_irq(0, kgdb_irq);
403
404 #ifdef CONFIG_GDB_CONSOLE
405 register_gdb_console();
406 #endif
407 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
408 set_debug_traps();
409 breakpoint();
410 }
411 #endif
412 }
413
414 #ifdef CONFIG_KGDB
415
416 #include <linux/delay.h>
417
418 #define duart_out(reg, val) csr_out32(val, KSEG1 + A_DUART_CHANREG(kgdb_port,reg))
419 #define duart_in(reg) csr_in32(KSEG1 + A_DUART_CHANREG(kgdb_port,reg))
420
sb1250_kgdb_interrupt(struct pt_regs * regs)421 void sb1250_kgdb_interrupt(struct pt_regs *regs)
422 {
423 /*
424 * Clear break-change status (allow some time for the remote
425 * host to stop the break, since we would see another
426 * interrupt on the end-of-break too)
427 */
428 kstat.irqs[smp_processor_id()][kgdb_irq]++;
429 mdelay(500);
430 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
431 M_DUART_RX_EN | M_DUART_TX_EN);
432 set_async_breakpoint(®s->cp0_epc);
433 }
434
435 #endif /* CONFIG_KGDB */
436