1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/kernel_stat.h>
33 #include <linux/module.h>
34 #include <linux/signal.h>
35 #include <linux/sched.h>
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/timex.h>
40 #include <linux/slab.h>
41 #include <linux/random.h>
42 #include <linux/delay.h>
43
44 #include <asm/bitops.h>
45 #include <asm/bootinfo.h>
46 #include <asm/io.h>
47 #include <asm/mipsregs.h>
48 #include <asm/system.h>
49 #include <asm/au1000.h>
50 #ifdef CONFIG_MIPS_PB1000
51 #include <asm/pb1000.h>
52 #endif
53
54 #undef DEBUG_IRQ
55 #ifdef DEBUG_IRQ
56 /* note: prints function name for you */
57 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
58 #else
59 #define DPRINTK(fmt, args...)
60 #endif
61
62 #define EXT_INTC0_REQ0 2 /* IP 2 */
63 #define EXT_INTC0_REQ1 3 /* IP 3 */
64 #define EXT_INTC1_REQ0 4 /* IP 4 */
65 #define EXT_INTC1_REQ1 5 /* IP 5 */
66 #define MIPS_TIMER_IP 7 /* IP 7 */
67
68 #ifdef CONFIG_KGDB
69 extern void breakpoint(void);
70 #endif
71
72 extern asmlinkage void au1000_IRQ(void);
73 extern void set_debug_traps(void);
74 extern irq_cpustat_t irq_stat [NR_CPUS];
75 unsigned int local_bh_count[NR_CPUS];
76 unsigned int local_irq_count[NR_CPUS];
77
78 static void setup_local_irq(unsigned int irq, int type, int int_req);
79 static unsigned int startup_irq(unsigned int irq);
80 static void end_irq(unsigned int irq_nr);
81 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
82 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
83 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
84 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
85 inline void local_enable_irq(unsigned int irq_nr);
86 inline void local_disable_irq(unsigned int irq_nr);
87
88 extern void __init init_generic_irq(void);
89 void (*board_init_irq)(void);
90
91 #ifdef CONFIG_PM
92 extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
93 #endif
94
95 static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED;
96
97
startup_irq(unsigned int irq_nr)98 static unsigned int startup_irq(unsigned int irq_nr)
99 {
100 local_enable_irq(irq_nr);
101 return 0;
102 }
103
104
shutdown_irq(unsigned int irq_nr)105 static void shutdown_irq(unsigned int irq_nr)
106 {
107 local_disable_irq(irq_nr);
108 return;
109 }
110
111
local_enable_irq(unsigned int irq_nr)112 inline void local_enable_irq(unsigned int irq_nr)
113 {
114 if (irq_nr > AU1000_LAST_INTC0_INT) {
115 au_writel(1<<(irq_nr-32), IC1_MASKSET);
116 au_writel(1<<(irq_nr-32), IC1_WAKESET);
117 }
118 else {
119 au_writel(1<<irq_nr, IC0_MASKSET);
120 au_writel(1<<irq_nr, IC0_WAKESET);
121 }
122 au_sync();
123 }
124
125
local_disable_irq(unsigned int irq_nr)126 inline void local_disable_irq(unsigned int irq_nr)
127 {
128 if (irq_nr > AU1000_LAST_INTC0_INT) {
129 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
130 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
131 }
132 else {
133 au_writel(1<<irq_nr, IC0_MASKCLR);
134 au_writel(1<<irq_nr, IC0_WAKECLR);
135 }
136 au_sync();
137 }
138
139
mask_and_ack_rise_edge_irq(unsigned int irq_nr)140 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
141 {
142 if (irq_nr > AU1000_LAST_INTC0_INT) {
143 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
144 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
145 }
146 else {
147 au_writel(1<<irq_nr, IC0_RISINGCLR);
148 au_writel(1<<irq_nr, IC0_MASKCLR);
149 }
150 au_sync();
151 }
152
153
mask_and_ack_fall_edge_irq(unsigned int irq_nr)154 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
155 {
156 if (irq_nr > AU1000_LAST_INTC0_INT) {
157 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
158 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
159 }
160 else {
161 au_writel(1<<irq_nr, IC0_FALLINGCLR);
162 au_writel(1<<irq_nr, IC0_MASKCLR);
163 }
164 au_sync();
165 }
166
167
mask_and_ack_either_edge_irq(unsigned int irq_nr)168 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
169 {
170 /* This may assume that we don't get interrupts from
171 * both edges at once, or if we do, that we don't care.
172 */
173 if (irq_nr > AU1000_LAST_INTC0_INT) {
174 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
175 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
176 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
177 }
178 else {
179 au_writel(1<<irq_nr, IC0_FALLINGCLR);
180 au_writel(1<<irq_nr, IC0_RISINGCLR);
181 au_writel(1<<irq_nr, IC0_MASKCLR);
182 }
183 au_sync();
184 }
185
186
mask_and_ack_level_irq(unsigned int irq_nr)187 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
188 {
189
190 local_disable_irq(irq_nr);
191 au_sync();
192 #if defined(CONFIG_MIPS_PB1000)
193 if (irq_nr == AU1000_GPIO_15) {
194 au_writel(0x8000, PB1000_MDR); /* ack int */
195 au_sync();
196 }
197 #endif
198 return;
199 }
200
201
end_irq(unsigned int irq_nr)202 static void end_irq(unsigned int irq_nr)
203 {
204 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
205 local_enable_irq(irq_nr);
206 }
207 #if defined(CONFIG_MIPS_PB1000)
208 if (irq_nr == AU1000_GPIO_15) {
209 au_writel(0x4000, PB1000_MDR); /* enable int */
210 au_sync();
211 }
212 #endif
213 }
214
save_local_and_disable(int controller)215 unsigned long save_local_and_disable(int controller)
216 {
217 int i;
218 unsigned long flags, mask;
219
220 spin_lock_irqsave(&irq_lock, flags);
221 if (controller) {
222 mask = au_readl(IC1_MASKSET);
223 for (i=32; i<64; i++) {
224 local_disable_irq(i);
225 }
226 }
227 else {
228 mask = au_readl(IC0_MASKSET);
229 for (i=0; i<32; i++) {
230 local_disable_irq(i);
231 }
232 }
233 spin_unlock_irqrestore(&irq_lock, flags);
234
235 return mask;
236 }
237
restore_local_and_enable(int controller,unsigned long mask)238 void restore_local_and_enable(int controller, unsigned long mask)
239 {
240 int i;
241 unsigned long flags, new_mask;
242
243 spin_lock_irqsave(&irq_lock, flags);
244 for (i=0; i<32; i++) {
245 if (mask & (1<<i)) {
246 if (controller)
247 local_enable_irq(i+32);
248 else
249 local_enable_irq(i);
250 }
251 }
252 if (controller)
253 new_mask = au_readl(IC1_MASKSET);
254 else
255 new_mask = au_readl(IC0_MASKSET);
256
257 spin_unlock_irqrestore(&irq_lock, flags);
258 }
259
260
261 static struct hw_interrupt_type rise_edge_irq_type = {
262 "Au1000 Rise Edge",
263 startup_irq,
264 shutdown_irq,
265 local_enable_irq,
266 local_disable_irq,
267 mask_and_ack_rise_edge_irq,
268 end_irq,
269 NULL
270 };
271
272 static struct hw_interrupt_type fall_edge_irq_type = {
273 "Au1000 Fall Edge",
274 startup_irq,
275 shutdown_irq,
276 local_enable_irq,
277 local_disable_irq,
278 mask_and_ack_fall_edge_irq,
279 end_irq,
280 NULL
281 };
282
283 static struct hw_interrupt_type either_edge_irq_type = {
284 "Au1000 Rise or Fall Edge",
285 startup_irq,
286 shutdown_irq,
287 local_enable_irq,
288 local_disable_irq,
289 mask_and_ack_either_edge_irq,
290 end_irq,
291 NULL
292 };
293
294 static struct hw_interrupt_type level_irq_type = {
295 "Au1000 Level",
296 startup_irq,
297 shutdown_irq,
298 local_enable_irq,
299 local_disable_irq,
300 mask_and_ack_level_irq,
301 end_irq,
302 NULL
303 };
304
305 #ifdef CONFIG_PM
startup_match20_interrupt(void)306 void startup_match20_interrupt(void)
307 {
308 local_enable_irq(AU1000_TOY_MATCH2_INT);
309 }
310 #endif
311
setup_local_irq(unsigned int irq_nr,int type,int int_req)312 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
313 {
314 if (irq_nr > AU1000_MAX_INTR) return;
315 /* Config2[n], Config1[n], Config0[n] */
316 if (irq_nr > AU1000_LAST_INTC0_INT) {
317 switch (type) {
318 case INTC_INT_RISE_EDGE: /* 0:0:1 */
319 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
320 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
321 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
322 irq_desc[irq_nr].handler = &rise_edge_irq_type;
323 break;
324 case INTC_INT_FALL_EDGE: /* 0:1:0 */
325 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
326 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
327 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
328 irq_desc[irq_nr].handler = &fall_edge_irq_type;
329 break;
330 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
331 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
332 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
333 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
334 irq_desc[irq_nr].handler = &either_edge_irq_type;
335 break;
336 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
337 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
338 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
339 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
340 irq_desc[irq_nr].handler = &level_irq_type;
341 break;
342 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
343 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
344 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
345 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
346 irq_desc[irq_nr].handler = &level_irq_type;
347 break;
348 case INTC_INT_DISABLED: /* 0:0:0 */
349 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
350 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
351 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
352 break;
353 default: /* disable the interrupt */
354 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
355 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
356 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
357 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
358 return;
359 }
360 if (int_req) /* assign to interrupt request 1 */
361 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
362 else /* assign to interrupt request 0 */
363 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
364 au_writel(1<<(irq_nr-32), IC1_SRCSET);
365 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
366 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
367 }
368 else {
369 switch (type) {
370 case INTC_INT_RISE_EDGE: /* 0:0:1 */
371 au_writel(1<<irq_nr, IC0_CFG2CLR);
372 au_writel(1<<irq_nr, IC0_CFG1CLR);
373 au_writel(1<<irq_nr, IC0_CFG0SET);
374 irq_desc[irq_nr].handler = &rise_edge_irq_type;
375 break;
376 case INTC_INT_FALL_EDGE: /* 0:1:0 */
377 au_writel(1<<irq_nr, IC0_CFG2CLR);
378 au_writel(1<<irq_nr, IC0_CFG1SET);
379 au_writel(1<<irq_nr, IC0_CFG0CLR);
380 irq_desc[irq_nr].handler = &fall_edge_irq_type;
381 break;
382 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
383 au_writel(1<<irq_nr, IC0_CFG2CLR);
384 au_writel(1<<irq_nr, IC0_CFG1SET);
385 au_writel(1<<irq_nr, IC0_CFG0SET);
386 irq_desc[irq_nr].handler = &either_edge_irq_type;
387 break;
388 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
389 au_writel(1<<irq_nr, IC0_CFG2SET);
390 au_writel(1<<irq_nr, IC0_CFG1CLR);
391 au_writel(1<<irq_nr, IC0_CFG0SET);
392 irq_desc[irq_nr].handler = &level_irq_type;
393 break;
394 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
395 au_writel(1<<irq_nr, IC0_CFG2SET);
396 au_writel(1<<irq_nr, IC0_CFG1SET);
397 au_writel(1<<irq_nr, IC0_CFG0CLR);
398 irq_desc[irq_nr].handler = &level_irq_type;
399 break;
400 case INTC_INT_DISABLED: /* 0:0:0 */
401 au_writel(1<<irq_nr, IC0_CFG0CLR);
402 au_writel(1<<irq_nr, IC0_CFG1CLR);
403 au_writel(1<<irq_nr, IC0_CFG2CLR);
404 break;
405 default: /* disable the interrupt */
406 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
407 au_writel(1<<irq_nr, IC0_CFG0CLR);
408 au_writel(1<<irq_nr, IC0_CFG1CLR);
409 au_writel(1<<irq_nr, IC0_CFG2CLR);
410 return;
411 }
412 if (int_req) /* assign to interrupt request 1 */
413 au_writel(1<<irq_nr, IC0_ASSIGNCLR);
414 else /* assign to interrupt request 0 */
415 au_writel(1<<irq_nr, IC0_ASSIGNSET);
416 au_writel(1<<irq_nr, IC0_SRCSET);
417 au_writel(1<<irq_nr, IC0_MASKCLR);
418 au_writel(1<<irq_nr, IC0_WAKECLR);
419 }
420 au_sync();
421 }
422
423
init_IRQ(void)424 void __init init_IRQ(void)
425 {
426 int i;
427 unsigned long cp0_status;
428 au1xxx_irq_map_t *imp;
429 extern au1xxx_irq_map_t au1xxx_irq_map[];
430 extern au1xxx_irq_map_t au1xxx_ic0_map[];
431 extern int au1xxx_nr_irqs;
432 extern int au1xxx_ic0_nr_irqs;
433
434 cp0_status = read_c0_status();
435 memset(irq_desc, 0, sizeof(irq_desc));
436 set_except_vector(0, au1000_IRQ);
437
438 init_generic_irq();
439
440 /* Initialize interrupt controllers to a safe state.
441 */
442 au_writel(0xffffffff, IC0_CFG0CLR);
443 au_writel(0xffffffff, IC0_CFG1CLR);
444 au_writel(0xffffffff, IC0_CFG2CLR);
445 au_writel(0xffffffff, IC0_MASKCLR);
446 au_writel(0xffffffff, IC0_ASSIGNSET);
447 au_writel(0xffffffff, IC0_WAKECLR);
448 au_writel(0xffffffff, IC0_SRCSET);
449 au_writel(0xffffffff, IC0_FALLINGCLR);
450 au_writel(0xffffffff, IC0_RISINGCLR);
451 au_writel(0x00000000, IC0_TESTBIT);
452
453 au_writel(0xffffffff, IC1_CFG0CLR);
454 au_writel(0xffffffff, IC1_CFG1CLR);
455 au_writel(0xffffffff, IC1_CFG2CLR);
456 au_writel(0xffffffff, IC1_MASKCLR);
457 au_writel(0xffffffff, IC1_ASSIGNSET);
458 au_writel(0xffffffff, IC1_WAKECLR);
459 au_writel(0xffffffff, IC1_SRCSET);
460 au_writel(0xffffffff, IC1_FALLINGCLR);
461 au_writel(0xffffffff, IC1_RISINGCLR);
462 au_writel(0x00000000, IC1_TESTBIT);
463
464 /* Initialize IC0, which is fixed per processor.
465 */
466 imp = au1xxx_ic0_map;
467 for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
468 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
469 imp++;
470 }
471
472 /* Now set up the irq mapping for the board.
473 */
474 imp = au1xxx_irq_map;
475 for (i=0; i<au1xxx_nr_irqs; i++) {
476 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
477 imp++;
478 }
479
480 set_c0_status(ALLINTS);
481
482 /* Board specific IRQ initialization.
483 */
484 if (board_init_irq)
485 (*board_init_irq)();
486
487 #ifdef CONFIG_KGDB
488 /* If local serial I/O used for debug port, enter kgdb at once */
489 puts("Waiting for kgdb to connect...");
490 set_debug_traps();
491 breakpoint();
492 #endif
493 }
494
495
496 /*
497 * Interrupts are nested. Even if an interrupt handler is registered
498 * as "fast", we might get another interrupt before we return from
499 * intcX_reqX_irqdispatch().
500 */
501
intc0_req0_irqdispatch(struct pt_regs * regs)502 void intc0_req0_irqdispatch(struct pt_regs *regs)
503 {
504 int irq = 0;
505 static unsigned long intc0_req0 = 0;
506
507 intc0_req0 |= au_readl(IC0_REQ0INT);
508
509 if (!intc0_req0) return;
510
511 /*
512 * Because of the tight timing of SETUP token to reply
513 * transactions, the USB devices-side packet complete
514 * interrupt needs the highest priority.
515 */
516 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
517 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
518 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
519 return;
520 }
521
522 irq = au_ffs(intc0_req0) - 1;
523 intc0_req0 &= ~(1<<irq);
524 do_IRQ(irq, regs);
525 }
526
527
intc0_req1_irqdispatch(struct pt_regs * regs)528 void intc0_req1_irqdispatch(struct pt_regs *regs)
529 {
530 int irq = 0;
531 static unsigned long intc0_req1 = 0;
532
533 intc0_req1 |= au_readl(IC0_REQ1INT);
534
535 if (!intc0_req1) return;
536
537 irq = au_ffs(intc0_req1) - 1;
538 intc0_req1 &= ~(1<<irq);
539 #ifdef CONFIG_PM
540 if (irq == AU1000_TOY_MATCH2_INT) {
541 mask_and_ack_rise_edge_irq(irq);
542 counter0_irq(irq, NULL, regs);
543 local_enable_irq(irq);
544 }
545 else
546 #endif
547 {
548 do_IRQ(irq, regs);
549 }
550 }
551
552
553 /*
554 * Interrupt Controller 1:
555 * interrupts 32 - 63
556 */
intc1_req0_irqdispatch(struct pt_regs * regs)557 void intc1_req0_irqdispatch(struct pt_regs *regs)
558 {
559 int irq = 0;
560 static unsigned long intc1_req0 = 0;
561
562 intc1_req0 |= au_readl(IC1_REQ0INT);
563
564 if (!intc1_req0) return;
565
566 irq = au_ffs(intc1_req0) - 1;
567 intc1_req0 &= ~(1<<irq);
568 irq += 32;
569 do_IRQ(irq, regs);
570 }
571
572
intc1_req1_irqdispatch(struct pt_regs * regs)573 void intc1_req1_irqdispatch(struct pt_regs *regs)
574 {
575 int irq = 0;
576 static unsigned long intc1_req1 = 0;
577
578 intc1_req1 |= au_readl(IC1_REQ1INT);
579
580 if (!intc1_req1) return;
581
582 irq = au_ffs(intc1_req1) - 1;
583 intc1_req1 &= ~(1<<irq);
584 irq += 32;
585 do_IRQ(irq, regs);
586 }
587
588 #ifdef CONFIG_PM
589
590 /* Save/restore the interrupt controller state.
591 * Called from the save/restore core registers as part of the
592 * au_sleep function in power.c.....maybe I should just pm_register()
593 * them instead?
594 */
595 static uint sleep_intctl_config0[2];
596 static uint sleep_intctl_config1[2];
597 static uint sleep_intctl_config2[2];
598 static uint sleep_intctl_src[2];
599 static uint sleep_intctl_assign[2];
600 static uint sleep_intctl_wake[2];
601 static uint sleep_intctl_mask[2];
602
603 void
save_au1xxx_intctl(void)604 save_au1xxx_intctl(void)
605 {
606 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
607 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
608 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
609 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
610 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
611 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
612 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
613
614 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
615 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
616 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
617 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
618 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
619 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
620 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
621 }
622
623 /* For most restore operations, we clear the entire register and
624 * then set the bits we found during the save.
625 */
626 void
restore_au1xxx_intctl(void)627 restore_au1xxx_intctl(void)
628 {
629 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
630
631 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
632 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
633 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
634 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
635 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
636 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
637 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
638 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
639 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
640 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
641 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
642 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
643 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
644 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
645 au_writel(0x00000000, IC0_TESTBIT); au_sync();
646
647 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
648
649 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
650 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
651 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
652 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
653 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
654 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
655 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
656 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
657 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
658 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
659 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
660 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
661 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
662 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
663 au_writel(0x00000000, IC1_TESTBIT); au_sync();
664
665 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
666
667 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
668 }
669 #endif /* CONFIG_PM */
670