1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Samsung S5P Multi Format Codec v 5.1
4  *
5  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
6  * Kamil Debski, <k.debski@samsung.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-event.h>
19 #include <linux/workqueue.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_reserved_mem.h>
23 #include <media/videobuf2-v4l2.h>
24 #include "s5p_mfc_common.h"
25 #include "s5p_mfc_ctrl.h"
26 #include "s5p_mfc_debug.h"
27 #include "s5p_mfc_dec.h"
28 #include "s5p_mfc_enc.h"
29 #include "s5p_mfc_intr.h"
30 #include "s5p_mfc_iommu.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_cmd.h"
33 #include "s5p_mfc_pm.h"
34 
35 #define S5P_MFC_DEC_NAME	"s5p-mfc-dec"
36 #define S5P_MFC_ENC_NAME	"s5p-mfc-enc"
37 
38 int mfc_debug_level;
39 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
41 
42 static char *mfc_mem_size;
43 module_param_named(mem, mfc_mem_size, charp, 0644);
44 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
45 
46 /* Helper functions for interrupt processing */
47 
48 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)49 void clear_work_bit(struct s5p_mfc_ctx *ctx)
50 {
51 	struct s5p_mfc_dev *dev = ctx->dev;
52 
53 	spin_lock(&dev->condlock);
54 	__clear_bit(ctx->num, &dev->ctx_work_bits);
55 	spin_unlock(&dev->condlock);
56 }
57 
58 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)59 void set_work_bit(struct s5p_mfc_ctx *ctx)
60 {
61 	struct s5p_mfc_dev *dev = ctx->dev;
62 
63 	spin_lock(&dev->condlock);
64 	__set_bit(ctx->num, &dev->ctx_work_bits);
65 	spin_unlock(&dev->condlock);
66 }
67 
68 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)69 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
70 {
71 	struct s5p_mfc_dev *dev = ctx->dev;
72 	unsigned long flags;
73 
74 	spin_lock_irqsave(&dev->condlock, flags);
75 	__clear_bit(ctx->num, &dev->ctx_work_bits);
76 	spin_unlock_irqrestore(&dev->condlock, flags);
77 }
78 
79 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)80 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
81 {
82 	struct s5p_mfc_dev *dev = ctx->dev;
83 	unsigned long flags;
84 
85 	spin_lock_irqsave(&dev->condlock, flags);
86 	__set_bit(ctx->num, &dev->ctx_work_bits);
87 	spin_unlock_irqrestore(&dev->condlock, flags);
88 }
89 
s5p_mfc_get_new_ctx(struct s5p_mfc_dev * dev)90 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
91 {
92 	unsigned long flags;
93 	int ctx;
94 
95 	spin_lock_irqsave(&dev->condlock, flags);
96 	ctx = dev->curr_ctx;
97 	do {
98 		ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
99 		if (ctx == dev->curr_ctx) {
100 			if (!test_bit(ctx, &dev->ctx_work_bits))
101 				ctx = -EAGAIN;
102 			break;
103 		}
104 	} while (!test_bit(ctx, &dev->ctx_work_bits));
105 	spin_unlock_irqrestore(&dev->condlock, flags);
106 
107 	return ctx;
108 }
109 
110 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)111 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
112 			unsigned int err)
113 {
114 	ctx->int_cond = 1;
115 	ctx->int_type = reason;
116 	ctx->int_err = err;
117 	wake_up(&ctx->queue);
118 }
119 
120 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)121 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
122 			unsigned int err)
123 {
124 	dev->int_cond = 1;
125 	dev->int_type = reason;
126 	dev->int_err = err;
127 	wake_up(&dev->queue);
128 }
129 
s5p_mfc_cleanup_queue(struct list_head * lh,struct vb2_queue * vq)130 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
131 {
132 	struct s5p_mfc_buf *b;
133 	int i;
134 
135 	while (!list_empty(lh)) {
136 		b = list_entry(lh->next, struct s5p_mfc_buf, list);
137 		for (i = 0; i < b->b->vb2_buf.num_planes; i++)
138 			vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
139 		vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
140 		list_del(&b->list);
141 	}
142 }
143 
s5p_mfc_watchdog(struct timer_list * t)144 static void s5p_mfc_watchdog(struct timer_list *t)
145 {
146 	struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
147 
148 	if (test_bit(0, &dev->hw_lock))
149 		atomic_inc(&dev->watchdog_cnt);
150 	if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
151 		/* This means that hw is busy and no interrupts were
152 		 * generated by hw for the Nth time of running this
153 		 * watchdog timer. This usually means a serious hw
154 		 * error. Now it is time to kill all instances and
155 		 * reset the MFC. */
156 		mfc_err("Time out during waiting for HW\n");
157 		schedule_work(&dev->watchdog_work);
158 	}
159 	dev->watchdog_timer.expires = jiffies +
160 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
161 	add_timer(&dev->watchdog_timer);
162 }
163 
s5p_mfc_watchdog_worker(struct work_struct * work)164 static void s5p_mfc_watchdog_worker(struct work_struct *work)
165 {
166 	struct s5p_mfc_dev *dev;
167 	struct s5p_mfc_ctx *ctx;
168 	unsigned long flags;
169 	int mutex_locked;
170 	int i, ret;
171 
172 	dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
173 
174 	mfc_err("Driver timeout error handling\n");
175 	/* Lock the mutex that protects open and release.
176 	 * This is necessary as they may load and unload firmware. */
177 	mutex_locked = mutex_trylock(&dev->mfc_mutex);
178 	if (!mutex_locked)
179 		mfc_err("Error: some instance may be closing/opening\n");
180 	spin_lock_irqsave(&dev->irqlock, flags);
181 
182 	s5p_mfc_clock_off();
183 
184 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
185 		ctx = dev->ctx[i];
186 		if (!ctx)
187 			continue;
188 		ctx->state = MFCINST_ERROR;
189 		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
190 		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
191 		clear_work_bit(ctx);
192 		wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
193 	}
194 	clear_bit(0, &dev->hw_lock);
195 	spin_unlock_irqrestore(&dev->irqlock, flags);
196 
197 	/* De-init MFC */
198 	s5p_mfc_deinit_hw(dev);
199 
200 	/* Double check if there is at least one instance running.
201 	 * If no instance is in memory than no firmware should be present */
202 	if (dev->num_inst > 0) {
203 		ret = s5p_mfc_load_firmware(dev);
204 		if (ret) {
205 			mfc_err("Failed to reload FW\n");
206 			goto unlock;
207 		}
208 		s5p_mfc_clock_on();
209 		ret = s5p_mfc_init_hw(dev);
210 		s5p_mfc_clock_off();
211 		if (ret)
212 			mfc_err("Failed to reinit FW\n");
213 	}
214 unlock:
215 	if (mutex_locked)
216 		mutex_unlock(&dev->mfc_mutex);
217 }
218 
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)219 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
220 {
221 	struct s5p_mfc_buf *dst_buf;
222 	struct s5p_mfc_dev *dev = ctx->dev;
223 
224 	ctx->state = MFCINST_FINISHED;
225 	ctx->sequence++;
226 	while (!list_empty(&ctx->dst_queue)) {
227 		dst_buf = list_entry(ctx->dst_queue.next,
228 				     struct s5p_mfc_buf, list);
229 		mfc_debug(2, "Cleaning up buffer: %d\n",
230 					  dst_buf->b->vb2_buf.index);
231 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
232 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
233 		list_del(&dst_buf->list);
234 		dst_buf->flags |= MFC_BUF_FLAG_EOS;
235 		ctx->dst_queue_cnt--;
236 		dst_buf->b->sequence = (ctx->sequence++);
237 
238 		if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
239 			s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
240 			dst_buf->b->field = V4L2_FIELD_NONE;
241 		else
242 			dst_buf->b->field = V4L2_FIELD_INTERLACED;
243 		dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
244 
245 		ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
246 		vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
247 	}
248 }
249 
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)250 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
251 {
252 	struct s5p_mfc_dev *dev = ctx->dev;
253 	struct s5p_mfc_buf *dst_buf, *src_buf;
254 	u32 dec_y_addr;
255 	unsigned int frame_type;
256 
257 	/* Make sure we actually have a new frame before continuing. */
258 	frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
259 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
260 		return;
261 	dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
262 
263 	/* Copy timestamp / timecode from decoded src to dst and set
264 	   appropriate flags. */
265 	src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
266 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
267 		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
268 
269 		if (addr == dec_y_addr) {
270 			dst_buf->b->timecode = src_buf->b->timecode;
271 			dst_buf->b->vb2_buf.timestamp =
272 						src_buf->b->vb2_buf.timestamp;
273 			dst_buf->b->flags &=
274 				~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
275 			dst_buf->b->flags |=
276 				src_buf->b->flags
277 				& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
278 			switch (frame_type) {
279 			case S5P_FIMV_DECODE_FRAME_I_FRAME:
280 				dst_buf->b->flags |=
281 						V4L2_BUF_FLAG_KEYFRAME;
282 				break;
283 			case S5P_FIMV_DECODE_FRAME_P_FRAME:
284 				dst_buf->b->flags |=
285 						V4L2_BUF_FLAG_PFRAME;
286 				break;
287 			case S5P_FIMV_DECODE_FRAME_B_FRAME:
288 				dst_buf->b->flags |=
289 						V4L2_BUF_FLAG_BFRAME;
290 				break;
291 			default:
292 				/* Don't know how to handle
293 				   S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
294 				mfc_debug(2, "Unexpected frame type: %d\n",
295 						frame_type);
296 			}
297 			break;
298 		}
299 	}
300 }
301 
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)302 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
303 {
304 	struct s5p_mfc_dev *dev = ctx->dev;
305 	struct s5p_mfc_buf  *dst_buf;
306 	u32 dspl_y_addr;
307 	unsigned int frame_type;
308 
309 	dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
310 	if (IS_MFCV6_PLUS(dev))
311 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
312 			get_disp_frame_type, ctx);
313 	else
314 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
315 			get_dec_frame_type, dev);
316 
317 	/* If frame is same as previous then skip and do not dequeue */
318 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
319 		if (!ctx->after_packed_pb)
320 			ctx->sequence++;
321 		ctx->after_packed_pb = 0;
322 		return;
323 	}
324 	ctx->sequence++;
325 	/* The MFC returns address of the buffer, now we have to
326 	 * check which videobuf does it correspond to */
327 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
328 		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
329 
330 		/* Check if this is the buffer we're looking for */
331 		if (addr == dspl_y_addr) {
332 			list_del(&dst_buf->list);
333 			ctx->dst_queue_cnt--;
334 			dst_buf->b->sequence = ctx->sequence;
335 			if (s5p_mfc_hw_call(dev->mfc_ops,
336 					get_pic_type_top, ctx) ==
337 				s5p_mfc_hw_call(dev->mfc_ops,
338 					get_pic_type_bot, ctx))
339 				dst_buf->b->field = V4L2_FIELD_NONE;
340 			else
341 				dst_buf->b->field =
342 							V4L2_FIELD_INTERLACED;
343 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
344 						ctx->luma_size);
345 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
346 						ctx->chroma_size);
347 			clear_bit(dst_buf->b->vb2_buf.index,
348 							&ctx->dec_dst_flag);
349 
350 			vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
351 				VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
352 
353 			break;
354 		}
355 	}
356 }
357 
358 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)359 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
360 					unsigned int reason, unsigned int err)
361 {
362 	struct s5p_mfc_dev *dev = ctx->dev;
363 	unsigned int dst_frame_status;
364 	unsigned int dec_frame_status;
365 	struct s5p_mfc_buf *src_buf;
366 	unsigned int res_change;
367 
368 	dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
369 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
370 	dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
371 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
372 	res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
373 				& S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
374 				>> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
375 	mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
376 	if (ctx->state == MFCINST_RES_CHANGE_INIT)
377 		ctx->state = MFCINST_RES_CHANGE_FLUSH;
378 	if (res_change == S5P_FIMV_RES_INCREASE ||
379 		res_change == S5P_FIMV_RES_DECREASE) {
380 		ctx->state = MFCINST_RES_CHANGE_INIT;
381 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
382 		wake_up_ctx(ctx, reason, err);
383 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
384 		s5p_mfc_clock_off();
385 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
386 		return;
387 	}
388 	if (ctx->dpb_flush_flag)
389 		ctx->dpb_flush_flag = 0;
390 
391 	/* All frames remaining in the buffer have been extracted  */
392 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
393 		if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
394 			static const struct v4l2_event ev_src_ch = {
395 				.type = V4L2_EVENT_SOURCE_CHANGE,
396 				.u.src_change.changes =
397 					V4L2_EVENT_SRC_CH_RESOLUTION,
398 			};
399 
400 			s5p_mfc_handle_frame_all_extracted(ctx);
401 			ctx->state = MFCINST_RES_CHANGE_END;
402 			v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
403 
404 			goto leave_handle_frame;
405 		} else {
406 			s5p_mfc_handle_frame_all_extracted(ctx);
407 		}
408 	}
409 
410 	if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
411 		s5p_mfc_handle_frame_copy_time(ctx);
412 
413 	/* A frame has been decoded and is in the buffer  */
414 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
415 	    dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
416 		s5p_mfc_handle_frame_new(ctx, err);
417 	} else {
418 		mfc_debug(2, "No frame decode\n");
419 	}
420 	/* Mark source buffer as complete */
421 	if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
422 		&& !list_empty(&ctx->src_queue)) {
423 		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
424 								list);
425 		ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
426 						get_consumed_stream, dev);
427 		if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
428 			ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
429 			ctx->consumed_stream + STUFF_BYTE <
430 			src_buf->b->vb2_buf.planes[0].bytesused) {
431 			/* Run MFC again on the same buffer */
432 			mfc_debug(2, "Running again the same buffer\n");
433 			ctx->after_packed_pb = 1;
434 		} else {
435 			mfc_debug(2, "MFC needs next buffer\n");
436 			ctx->consumed_stream = 0;
437 			if (src_buf->flags & MFC_BUF_FLAG_EOS)
438 				ctx->state = MFCINST_FINISHING;
439 			list_del(&src_buf->list);
440 			ctx->src_queue_cnt--;
441 			if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
442 				vb2_buffer_done(&src_buf->b->vb2_buf,
443 						VB2_BUF_STATE_ERROR);
444 			else
445 				vb2_buffer_done(&src_buf->b->vb2_buf,
446 						VB2_BUF_STATE_DONE);
447 		}
448 	}
449 leave_handle_frame:
450 	if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
451 				    || ctx->dst_queue_cnt < ctx->pb_count)
452 		clear_work_bit(ctx);
453 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
454 	wake_up_ctx(ctx, reason, err);
455 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
456 	s5p_mfc_clock_off();
457 	/* if suspending, wake up device and do not try_run again*/
458 	if (test_bit(0, &dev->enter_suspend))
459 		wake_up_dev(dev, reason, err);
460 	else
461 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
462 }
463 
464 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)465 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
466 		struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
467 {
468 	mfc_err("Interrupt Error: %08x\n", err);
469 
470 	if (ctx) {
471 		/* Error recovery is dependent on the state of context */
472 		switch (ctx->state) {
473 		case MFCINST_RES_CHANGE_INIT:
474 		case MFCINST_RES_CHANGE_FLUSH:
475 		case MFCINST_RES_CHANGE_END:
476 		case MFCINST_FINISHING:
477 		case MFCINST_FINISHED:
478 		case MFCINST_RUNNING:
479 			/* It is highly probable that an error occurred
480 			 * while decoding a frame */
481 			clear_work_bit(ctx);
482 			ctx->state = MFCINST_ERROR;
483 			/* Mark all dst buffers as having an error */
484 			s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
485 			/* Mark all src buffers as having an error */
486 			s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
487 			wake_up_ctx(ctx, reason, err);
488 			break;
489 		default:
490 			clear_work_bit(ctx);
491 			ctx->state = MFCINST_ERROR;
492 			wake_up_ctx(ctx, reason, err);
493 			break;
494 		}
495 	}
496 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
497 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
498 	s5p_mfc_clock_off();
499 	wake_up_dev(dev, reason, err);
500 }
501 
502 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)503 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
504 				 unsigned int reason, unsigned int err)
505 {
506 	struct s5p_mfc_dev *dev;
507 
508 	if (!ctx)
509 		return;
510 	dev = ctx->dev;
511 	if (ctx->c_ops->post_seq_start) {
512 		if (ctx->c_ops->post_seq_start(ctx))
513 			mfc_err("post_seq_start() failed\n");
514 	} else {
515 		ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
516 				dev);
517 		ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
518 				dev);
519 
520 		s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
521 
522 		ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
523 				dev);
524 		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
525 				dev);
526 		if (FW_HAS_E_MIN_SCRATCH_BUF(dev))
527 			ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
528 						get_min_scratch_buf_size, dev);
529 		if (ctx->img_width == 0 || ctx->img_height == 0)
530 			ctx->state = MFCINST_ERROR;
531 		else
532 			ctx->state = MFCINST_HEAD_PARSED;
533 
534 		if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
535 			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
536 				!list_empty(&ctx->src_queue)) {
537 			struct s5p_mfc_buf *src_buf;
538 			src_buf = list_entry(ctx->src_queue.next,
539 					struct s5p_mfc_buf, list);
540 			if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
541 						dev) <
542 					src_buf->b->vb2_buf.planes[0].bytesused)
543 				ctx->head_processed = 0;
544 			else
545 				ctx->head_processed = 1;
546 		} else {
547 			ctx->head_processed = 1;
548 		}
549 	}
550 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
551 	clear_work_bit(ctx);
552 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
553 	s5p_mfc_clock_off();
554 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
555 	wake_up_ctx(ctx, reason, err);
556 }
557 
558 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)559 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
560 				 unsigned int reason, unsigned int err)
561 {
562 	struct s5p_mfc_buf *src_buf;
563 	struct s5p_mfc_dev *dev;
564 
565 	if (!ctx)
566 		return;
567 	dev = ctx->dev;
568 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
569 	ctx->int_type = reason;
570 	ctx->int_err = err;
571 	ctx->int_cond = 1;
572 	clear_work_bit(ctx);
573 	if (err == 0) {
574 		ctx->state = MFCINST_RUNNING;
575 		if (!ctx->dpb_flush_flag && ctx->head_processed) {
576 			if (!list_empty(&ctx->src_queue)) {
577 				src_buf = list_entry(ctx->src_queue.next,
578 					     struct s5p_mfc_buf, list);
579 				list_del(&src_buf->list);
580 				ctx->src_queue_cnt--;
581 				vb2_buffer_done(&src_buf->b->vb2_buf,
582 						VB2_BUF_STATE_DONE);
583 			}
584 		} else {
585 			ctx->dpb_flush_flag = 0;
586 		}
587 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
588 
589 		s5p_mfc_clock_off();
590 
591 		wake_up(&ctx->queue);
592 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
593 	} else {
594 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
595 
596 		s5p_mfc_clock_off();
597 
598 		wake_up(&ctx->queue);
599 	}
600 }
601 
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx)602 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
603 {
604 	struct s5p_mfc_dev *dev = ctx->dev;
605 	struct s5p_mfc_buf *mb_entry;
606 
607 	mfc_debug(2, "Stream completed\n");
608 
609 	ctx->state = MFCINST_FINISHED;
610 
611 	if (!list_empty(&ctx->dst_queue)) {
612 		mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
613 									list);
614 		list_del(&mb_entry->list);
615 		ctx->dst_queue_cnt--;
616 		vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
617 		vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
618 	}
619 
620 	clear_work_bit(ctx);
621 
622 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
623 
624 	s5p_mfc_clock_off();
625 	wake_up(&ctx->queue);
626 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
627 }
628 
629 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)630 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
631 {
632 	struct s5p_mfc_dev *dev = priv;
633 	struct s5p_mfc_ctx *ctx;
634 	unsigned int reason;
635 	unsigned int err;
636 
637 	mfc_debug_enter();
638 	/* Reset the timeout watchdog */
639 	atomic_set(&dev->watchdog_cnt, 0);
640 	spin_lock(&dev->irqlock);
641 	ctx = dev->ctx[dev->curr_ctx];
642 	/* Get the reason of interrupt and the error code */
643 	reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
644 	err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
645 	mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
646 	switch (reason) {
647 	case S5P_MFC_R2H_CMD_ERR_RET:
648 		/* An error has occurred */
649 		if (ctx->state == MFCINST_RUNNING &&
650 			(s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
651 				dev->warn_start ||
652 				err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
653 				err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
654 				err == S5P_FIMV_ERR_TIMEOUT))
655 			s5p_mfc_handle_frame(ctx, reason, err);
656 		else
657 			s5p_mfc_handle_error(dev, ctx, reason, err);
658 		clear_bit(0, &dev->enter_suspend);
659 		break;
660 
661 	case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
662 	case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
663 	case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
664 		if (ctx->c_ops->post_frame_start) {
665 			if (ctx->c_ops->post_frame_start(ctx))
666 				mfc_err("post_frame_start() failed\n");
667 
668 			if (ctx->state == MFCINST_FINISHING &&
669 						list_empty(&ctx->ref_queue)) {
670 				s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
671 				s5p_mfc_handle_stream_complete(ctx);
672 				break;
673 			}
674 			s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
675 			WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
676 			s5p_mfc_clock_off();
677 			wake_up_ctx(ctx, reason, err);
678 			s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
679 		} else {
680 			s5p_mfc_handle_frame(ctx, reason, err);
681 		}
682 		break;
683 
684 	case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
685 		s5p_mfc_handle_seq_done(ctx, reason, err);
686 		break;
687 
688 	case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
689 		ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
690 		ctx->state = MFCINST_GOT_INST;
691 		goto irq_cleanup_hw;
692 
693 	case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
694 		ctx->inst_no = MFC_NO_INSTANCE_SET;
695 		ctx->state = MFCINST_FREE;
696 		goto irq_cleanup_hw;
697 
698 	case S5P_MFC_R2H_CMD_SYS_INIT_RET:
699 	case S5P_MFC_R2H_CMD_FW_STATUS_RET:
700 	case S5P_MFC_R2H_CMD_SLEEP_RET:
701 	case S5P_MFC_R2H_CMD_WAKEUP_RET:
702 		if (ctx)
703 			clear_work_bit(ctx);
704 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
705 		clear_bit(0, &dev->hw_lock);
706 		clear_bit(0, &dev->enter_suspend);
707 		wake_up_dev(dev, reason, err);
708 		break;
709 
710 	case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
711 		s5p_mfc_handle_init_buffers(ctx, reason, err);
712 		break;
713 
714 	case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
715 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
716 		ctx->int_type = reason;
717 		ctx->int_err = err;
718 		s5p_mfc_handle_stream_complete(ctx);
719 		break;
720 
721 	case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
722 		ctx->state = MFCINST_RUNNING;
723 		goto irq_cleanup_hw;
724 
725 	default:
726 		mfc_debug(2, "Unknown int reason\n");
727 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
728 	}
729 	spin_unlock(&dev->irqlock);
730 	mfc_debug_leave();
731 	return IRQ_HANDLED;
732 irq_cleanup_hw:
733 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
734 	ctx->int_type = reason;
735 	ctx->int_err = err;
736 	ctx->int_cond = 1;
737 	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
738 		mfc_err("Failed to unlock hw\n");
739 
740 	s5p_mfc_clock_off();
741 	clear_work_bit(ctx);
742 	wake_up(&ctx->queue);
743 
744 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
745 	spin_unlock(&dev->irqlock);
746 	mfc_debug(2, "Exit via irq_cleanup_hw\n");
747 	return IRQ_HANDLED;
748 }
749 
750 /* Open an MFC node */
s5p_mfc_open(struct file * file)751 static int s5p_mfc_open(struct file *file)
752 {
753 	struct video_device *vdev = video_devdata(file);
754 	struct s5p_mfc_dev *dev = video_drvdata(file);
755 	struct s5p_mfc_ctx *ctx = NULL;
756 	struct vb2_queue *q;
757 	int ret = 0;
758 
759 	mfc_debug_enter();
760 	if (mutex_lock_interruptible(&dev->mfc_mutex))
761 		return -ERESTARTSYS;
762 	dev->num_inst++;	/* It is guarded by mfc_mutex in vfd */
763 	/* Allocate memory for context */
764 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
765 	if (!ctx) {
766 		ret = -ENOMEM;
767 		goto err_alloc;
768 	}
769 	init_waitqueue_head(&ctx->queue);
770 	v4l2_fh_init(&ctx->fh, vdev);
771 	file->private_data = &ctx->fh;
772 	v4l2_fh_add(&ctx->fh);
773 	ctx->dev = dev;
774 	INIT_LIST_HEAD(&ctx->src_queue);
775 	INIT_LIST_HEAD(&ctx->dst_queue);
776 	ctx->src_queue_cnt = 0;
777 	ctx->dst_queue_cnt = 0;
778 	/* Get context number */
779 	ctx->num = 0;
780 	while (dev->ctx[ctx->num]) {
781 		ctx->num++;
782 		if (ctx->num >= MFC_NUM_CONTEXTS) {
783 			mfc_debug(2, "Too many open contexts\n");
784 			ret = -EBUSY;
785 			goto err_no_ctx;
786 		}
787 	}
788 	/* Mark context as idle */
789 	clear_work_bit_irqsave(ctx);
790 	dev->ctx[ctx->num] = ctx;
791 	if (vdev == dev->vfd_dec) {
792 		ctx->type = MFCINST_DECODER;
793 		ctx->c_ops = get_dec_codec_ops();
794 		s5p_mfc_dec_init(ctx);
795 		/* Setup ctrl handler */
796 		ret = s5p_mfc_dec_ctrls_setup(ctx);
797 		if (ret) {
798 			mfc_err("Failed to setup mfc controls\n");
799 			goto err_ctrls_setup;
800 		}
801 	} else if (vdev == dev->vfd_enc) {
802 		ctx->type = MFCINST_ENCODER;
803 		ctx->c_ops = get_enc_codec_ops();
804 		/* only for encoder */
805 		INIT_LIST_HEAD(&ctx->ref_queue);
806 		ctx->ref_queue_cnt = 0;
807 		s5p_mfc_enc_init(ctx);
808 		/* Setup ctrl handler */
809 		ret = s5p_mfc_enc_ctrls_setup(ctx);
810 		if (ret) {
811 			mfc_err("Failed to setup mfc controls\n");
812 			goto err_ctrls_setup;
813 		}
814 	} else {
815 		ret = -ENOENT;
816 		goto err_bad_node;
817 	}
818 	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
819 	ctx->inst_no = MFC_NO_INSTANCE_SET;
820 	/* Load firmware if this is the first instance */
821 	if (dev->num_inst == 1) {
822 		dev->watchdog_timer.expires = jiffies +
823 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
824 		add_timer(&dev->watchdog_timer);
825 		ret = s5p_mfc_power_on();
826 		if (ret < 0) {
827 			mfc_err("power on failed\n");
828 			goto err_pwr_enable;
829 		}
830 		s5p_mfc_clock_on();
831 		ret = s5p_mfc_load_firmware(dev);
832 		if (ret) {
833 			s5p_mfc_clock_off();
834 			goto err_load_fw;
835 		}
836 		/* Init the FW */
837 		ret = s5p_mfc_init_hw(dev);
838 		s5p_mfc_clock_off();
839 		if (ret)
840 			goto err_init_hw;
841 	}
842 	/* Init videobuf2 queue for CAPTURE */
843 	q = &ctx->vq_dst;
844 	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
845 	q->drv_priv = &ctx->fh;
846 	q->lock = &dev->mfc_mutex;
847 	if (vdev == dev->vfd_dec) {
848 		q->io_modes = VB2_MMAP;
849 		q->ops = get_dec_queue_ops();
850 	} else if (vdev == dev->vfd_enc) {
851 		q->io_modes = VB2_MMAP | VB2_USERPTR;
852 		q->ops = get_enc_queue_ops();
853 	} else {
854 		ret = -ENOENT;
855 		goto err_queue_init;
856 	}
857 	/*
858 	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
859 	 * faster allocation.
860 	 */
861 	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
862 	q->mem_ops = &vb2_dma_contig_memops;
863 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
864 	ret = vb2_queue_init(q);
865 	if (ret) {
866 		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
867 		goto err_queue_init;
868 	}
869 	/* Init videobuf2 queue for OUTPUT */
870 	q = &ctx->vq_src;
871 	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
872 	q->drv_priv = &ctx->fh;
873 	q->lock = &dev->mfc_mutex;
874 	if (vdev == dev->vfd_dec) {
875 		q->io_modes = VB2_MMAP;
876 		q->ops = get_dec_queue_ops();
877 	} else if (vdev == dev->vfd_enc) {
878 		q->io_modes = VB2_MMAP | VB2_USERPTR;
879 		q->ops = get_enc_queue_ops();
880 	} else {
881 		ret = -ENOENT;
882 		goto err_queue_init;
883 	}
884 	/* One way to indicate end-of-stream for MFC is to set the
885 	 * bytesused == 0. However by default videobuf2 handles bytesused
886 	 * equal to 0 as a special case and changes its value to the size
887 	 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
888 	 * will keep the value of bytesused intact.
889 	 */
890 	q->allow_zero_bytesused = 1;
891 
892 	/*
893 	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
894 	 * faster allocation.
895 	 */
896 	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
897 	q->mem_ops = &vb2_dma_contig_memops;
898 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
899 	ret = vb2_queue_init(q);
900 	if (ret) {
901 		mfc_err("Failed to initialize videobuf2 queue(output)\n");
902 		goto err_queue_init;
903 	}
904 	mutex_unlock(&dev->mfc_mutex);
905 	mfc_debug_leave();
906 	return ret;
907 	/* Deinit when failure occurred */
908 err_queue_init:
909 	if (dev->num_inst == 1)
910 		s5p_mfc_deinit_hw(dev);
911 err_init_hw:
912 err_load_fw:
913 err_pwr_enable:
914 	if (dev->num_inst == 1) {
915 		if (s5p_mfc_power_off() < 0)
916 			mfc_err("power off failed\n");
917 		del_timer_sync(&dev->watchdog_timer);
918 	}
919 err_ctrls_setup:
920 	s5p_mfc_dec_ctrls_delete(ctx);
921 err_bad_node:
922 	dev->ctx[ctx->num] = NULL;
923 err_no_ctx:
924 	v4l2_fh_del(&ctx->fh);
925 	v4l2_fh_exit(&ctx->fh);
926 	kfree(ctx);
927 err_alloc:
928 	dev->num_inst--;
929 	mutex_unlock(&dev->mfc_mutex);
930 	mfc_debug_leave();
931 	return ret;
932 }
933 
934 /* Release MFC context */
s5p_mfc_release(struct file * file)935 static int s5p_mfc_release(struct file *file)
936 {
937 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
938 	struct s5p_mfc_dev *dev = ctx->dev;
939 
940 	/* if dev is null, do cleanup that doesn't need dev */
941 	mfc_debug_enter();
942 	if (dev)
943 		mutex_lock(&dev->mfc_mutex);
944 	vb2_queue_release(&ctx->vq_src);
945 	vb2_queue_release(&ctx->vq_dst);
946 	if (dev) {
947 		s5p_mfc_clock_on();
948 
949 		/* Mark context as idle */
950 		clear_work_bit_irqsave(ctx);
951 		/*
952 		 * If instance was initialised and not yet freed,
953 		 * return instance and free resources
954 		*/
955 		if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
956 			mfc_debug(2, "Has to free instance\n");
957 			s5p_mfc_close_mfc_inst(dev, ctx);
958 		}
959 		/* hardware locking scheme */
960 		if (dev->curr_ctx == ctx->num)
961 			clear_bit(0, &dev->hw_lock);
962 		dev->num_inst--;
963 		if (dev->num_inst == 0) {
964 			mfc_debug(2, "Last instance\n");
965 			s5p_mfc_deinit_hw(dev);
966 			del_timer_sync(&dev->watchdog_timer);
967 			s5p_mfc_clock_off();
968 			if (s5p_mfc_power_off() < 0)
969 				mfc_err("Power off failed\n");
970 		} else {
971 			mfc_debug(2, "Shutting down clock\n");
972 			s5p_mfc_clock_off();
973 		}
974 	}
975 	if (dev)
976 		dev->ctx[ctx->num] = NULL;
977 	s5p_mfc_dec_ctrls_delete(ctx);
978 	v4l2_fh_del(&ctx->fh);
979 	/* vdev is gone if dev is null */
980 	if (dev)
981 		v4l2_fh_exit(&ctx->fh);
982 	kfree(ctx);
983 	mfc_debug_leave();
984 	if (dev)
985 		mutex_unlock(&dev->mfc_mutex);
986 
987 	return 0;
988 }
989 
990 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)991 static __poll_t s5p_mfc_poll(struct file *file,
992 				 struct poll_table_struct *wait)
993 {
994 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
995 	struct s5p_mfc_dev *dev = ctx->dev;
996 	struct vb2_queue *src_q, *dst_q;
997 	struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
998 	__poll_t rc = 0;
999 	unsigned long flags;
1000 
1001 	mutex_lock(&dev->mfc_mutex);
1002 	src_q = &ctx->vq_src;
1003 	dst_q = &ctx->vq_dst;
1004 	/*
1005 	 * There has to be at least one buffer queued on each queued_list, which
1006 	 * means either in driver already or waiting for driver to claim it
1007 	 * and start processing.
1008 	 */
1009 	if ((!src_q->streaming || list_empty(&src_q->queued_list))
1010 		&& (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1011 		rc = EPOLLERR;
1012 		goto end;
1013 	}
1014 	mutex_unlock(&dev->mfc_mutex);
1015 	poll_wait(file, &ctx->fh.wait, wait);
1016 	poll_wait(file, &src_q->done_wq, wait);
1017 	poll_wait(file, &dst_q->done_wq, wait);
1018 	mutex_lock(&dev->mfc_mutex);
1019 	if (v4l2_event_pending(&ctx->fh))
1020 		rc |= EPOLLPRI;
1021 	spin_lock_irqsave(&src_q->done_lock, flags);
1022 	if (!list_empty(&src_q->done_list))
1023 		src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1024 								done_entry);
1025 	if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1026 				|| src_vb->state == VB2_BUF_STATE_ERROR))
1027 		rc |= EPOLLOUT | EPOLLWRNORM;
1028 	spin_unlock_irqrestore(&src_q->done_lock, flags);
1029 	spin_lock_irqsave(&dst_q->done_lock, flags);
1030 	if (!list_empty(&dst_q->done_list))
1031 		dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1032 								done_entry);
1033 	if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1034 				|| dst_vb->state == VB2_BUF_STATE_ERROR))
1035 		rc |= EPOLLIN | EPOLLRDNORM;
1036 	spin_unlock_irqrestore(&dst_q->done_lock, flags);
1037 end:
1038 	mutex_unlock(&dev->mfc_mutex);
1039 	return rc;
1040 }
1041 
1042 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)1043 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1044 {
1045 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1046 	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1047 	int ret;
1048 
1049 	if (offset < DST_QUEUE_OFF_BASE) {
1050 		mfc_debug(2, "mmaping source\n");
1051 		ret = vb2_mmap(&ctx->vq_src, vma);
1052 	} else {		/* capture */
1053 		mfc_debug(2, "mmaping destination\n");
1054 		vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1055 		ret = vb2_mmap(&ctx->vq_dst, vma);
1056 	}
1057 	return ret;
1058 }
1059 
1060 /* v4l2 ops */
1061 static const struct v4l2_file_operations s5p_mfc_fops = {
1062 	.owner = THIS_MODULE,
1063 	.open = s5p_mfc_open,
1064 	.release = s5p_mfc_release,
1065 	.poll = s5p_mfc_poll,
1066 	.unlocked_ioctl = video_ioctl2,
1067 	.mmap = s5p_mfc_mmap,
1068 };
1069 
1070 /* DMA memory related helper functions */
s5p_mfc_memdev_release(struct device * dev)1071 static void s5p_mfc_memdev_release(struct device *dev)
1072 {
1073 	of_reserved_mem_device_release(dev);
1074 }
1075 
s5p_mfc_alloc_memdev(struct device * dev,const char * name,unsigned int idx)1076 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1077 					   const char *name, unsigned int idx)
1078 {
1079 	struct device *child;
1080 	int ret;
1081 
1082 	child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1083 	if (!child)
1084 		return NULL;
1085 
1086 	device_initialize(child);
1087 	dev_set_name(child, "%s:%s", dev_name(dev), name);
1088 	child->parent = dev;
1089 	child->coherent_dma_mask = dev->coherent_dma_mask;
1090 	child->dma_mask = dev->dma_mask;
1091 	child->release = s5p_mfc_memdev_release;
1092 	child->dma_parms = devm_kzalloc(dev, sizeof(*child->dma_parms),
1093 					GFP_KERNEL);
1094 	if (!child->dma_parms)
1095 		goto err;
1096 
1097 	/*
1098 	 * The memdevs are not proper OF platform devices, so in order for them
1099 	 * to be treated as valid DMA masters we need a bit of a hack to force
1100 	 * them to inherit the MFC node's DMA configuration.
1101 	 */
1102 	of_dma_configure(child, dev->of_node, true);
1103 
1104 	if (device_add(child) == 0) {
1105 		ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1106 							 idx);
1107 		if (ret == 0)
1108 			return child;
1109 		device_del(child);
1110 	}
1111 err:
1112 	put_device(child);
1113 	return NULL;
1114 }
1115 
s5p_mfc_configure_2port_memory(struct s5p_mfc_dev * mfc_dev)1116 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1117 {
1118 	struct device *dev = &mfc_dev->plat_dev->dev;
1119 	void *bank2_virt;
1120 	dma_addr_t bank2_dma_addr;
1121 	unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1122 	int ret;
1123 
1124 	/*
1125 	 * Create and initialize virtual devices for accessing
1126 	 * reserved memory regions.
1127 	 */
1128 	mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1129 							   BANK_L_CTX);
1130 	if (!mfc_dev->mem_dev[BANK_L_CTX])
1131 		return -ENODEV;
1132 	mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1133 							   BANK_R_CTX);
1134 	if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1135 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1136 		return -ENODEV;
1137 	}
1138 
1139 	/* Allocate memory for firmware and initialize both banks addresses */
1140 	ret = s5p_mfc_alloc_firmware(mfc_dev);
1141 	if (ret) {
1142 		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1143 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1144 		return ret;
1145 	}
1146 
1147 	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1148 
1149 	bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1150 				       align_size, &bank2_dma_addr, GFP_KERNEL);
1151 	if (!bank2_virt) {
1152 		mfc_err("Allocating bank2 base failed\n");
1153 		s5p_mfc_release_firmware(mfc_dev);
1154 		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1155 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1156 		return -ENOMEM;
1157 	}
1158 
1159 	/* Valid buffers passed to MFC encoder with LAST_FRAME command
1160 	 * should not have address of bank2 - MFC will treat it as a null frame.
1161 	 * To avoid such situation we set bank2 address below the pool address.
1162 	 */
1163 	mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1164 
1165 	dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1166 			  bank2_dma_addr);
1167 
1168 	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1169 					DMA_BIT_MASK(32));
1170 	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1171 					DMA_BIT_MASK(32));
1172 
1173 	return 0;
1174 }
1175 
s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev * mfc_dev)1176 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1177 {
1178 	device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1179 	device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1180 	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1181 	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1182 }
1183 
s5p_mfc_configure_common_memory(struct s5p_mfc_dev * mfc_dev)1184 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1185 {
1186 	struct device *dev = &mfc_dev->plat_dev->dev;
1187 	unsigned long mem_size = SZ_4M;
1188 
1189 	if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1190 		mem_size = SZ_8M;
1191 
1192 	if (mfc_mem_size)
1193 		mem_size = memparse(mfc_mem_size, NULL);
1194 
1195 	mfc_dev->mem_bitmap = bitmap_zalloc(mem_size >> PAGE_SHIFT, GFP_KERNEL);
1196 	if (!mfc_dev->mem_bitmap)
1197 		return -ENOMEM;
1198 
1199 	mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1200 					       &mfc_dev->mem_base, GFP_KERNEL);
1201 	if (!mfc_dev->mem_virt) {
1202 		bitmap_free(mfc_dev->mem_bitmap);
1203 		dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1204 			(mem_size / SZ_1M));
1205 		return -ENOMEM;
1206 	}
1207 	mfc_dev->mem_size = mem_size;
1208 	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1209 	mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1210 
1211 	/*
1212 	 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1213 	 * as used (to keep required base alignment) and adjust base address
1214 	 */
1215 	if (mfc_dev->mem_base == (dma_addr_t)0) {
1216 		unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1217 
1218 		bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1219 		mfc_dev->dma_base[BANK_L_CTX] += offset;
1220 		mfc_dev->dma_base[BANK_R_CTX] += offset;
1221 	}
1222 
1223 	/* Firmware allocation cannot fail in this case */
1224 	s5p_mfc_alloc_firmware(mfc_dev);
1225 
1226 	mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1227 	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1228 
1229 	dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1230 		 (mem_size / SZ_1M));
1231 
1232 	return 0;
1233 }
1234 
s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev * mfc_dev)1235 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1236 {
1237 	struct device *dev = &mfc_dev->plat_dev->dev;
1238 
1239 	dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1240 			  mfc_dev->mem_base);
1241 	bitmap_free(mfc_dev->mem_bitmap);
1242 	vb2_dma_contig_clear_max_seg_size(dev);
1243 }
1244 
s5p_mfc_configure_dma_memory(struct s5p_mfc_dev * mfc_dev)1245 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1246 {
1247 	struct device *dev = &mfc_dev->plat_dev->dev;
1248 
1249 	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1250 		return s5p_mfc_configure_common_memory(mfc_dev);
1251 	else
1252 		return s5p_mfc_configure_2port_memory(mfc_dev);
1253 }
1254 
s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev * mfc_dev)1255 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1256 {
1257 	struct device *dev = &mfc_dev->plat_dev->dev;
1258 
1259 	s5p_mfc_release_firmware(mfc_dev);
1260 	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1261 		s5p_mfc_unconfigure_common_memory(mfc_dev);
1262 	else
1263 		s5p_mfc_unconfigure_2port_memory(mfc_dev);
1264 }
1265 
1266 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1267 static int s5p_mfc_probe(struct platform_device *pdev)
1268 {
1269 	struct s5p_mfc_dev *dev;
1270 	struct video_device *vfd;
1271 	int ret;
1272 
1273 	pr_debug("%s++\n", __func__);
1274 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1275 	if (!dev)
1276 		return -ENOMEM;
1277 
1278 	spin_lock_init(&dev->irqlock);
1279 	spin_lock_init(&dev->condlock);
1280 	dev->plat_dev = pdev;
1281 	if (!dev->plat_dev) {
1282 		mfc_err("No platform data specified\n");
1283 		return -ENODEV;
1284 	}
1285 
1286 	dev->variant = of_device_get_match_data(&pdev->dev);
1287 	if (!dev->variant) {
1288 		dev_err(&pdev->dev, "Failed to get device MFC hardware variant information\n");
1289 		return -ENOENT;
1290 	}
1291 
1292 	dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
1293 	if (IS_ERR(dev->regs_base))
1294 		return PTR_ERR(dev->regs_base);
1295 
1296 	ret = platform_get_irq(pdev, 0);
1297 	if (ret < 0)
1298 		return ret;
1299 	dev->irq = ret;
1300 	ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1301 					0, pdev->name, dev);
1302 	if (ret) {
1303 		dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1304 		return ret;
1305 	}
1306 
1307 	ret = s5p_mfc_configure_dma_memory(dev);
1308 	if (ret < 0) {
1309 		dev_err(&pdev->dev, "failed to configure DMA memory\n");
1310 		return ret;
1311 	}
1312 
1313 	ret = s5p_mfc_init_pm(dev);
1314 	if (ret < 0) {
1315 		dev_err(&pdev->dev, "failed to get mfc clock source\n");
1316 		goto err_dma;
1317 	}
1318 
1319 	/*
1320 	 * Load fails if fs isn't mounted. Try loading anyway.
1321 	 * _open() will load it, it it fails now. Ignore failure.
1322 	 */
1323 	s5p_mfc_load_firmware(dev);
1324 
1325 	mutex_init(&dev->mfc_mutex);
1326 	init_waitqueue_head(&dev->queue);
1327 	dev->hw_lock = 0;
1328 	INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1329 	atomic_set(&dev->watchdog_cnt, 0);
1330 	timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1331 
1332 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1333 	if (ret)
1334 		goto err_v4l2_dev_reg;
1335 
1336 	/* decoder */
1337 	vfd = video_device_alloc();
1338 	if (!vfd) {
1339 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1340 		ret = -ENOMEM;
1341 		goto err_dec_alloc;
1342 	}
1343 	vfd->fops	= &s5p_mfc_fops;
1344 	vfd->ioctl_ops	= get_dec_v4l2_ioctl_ops();
1345 	vfd->release	= video_device_release;
1346 	vfd->lock	= &dev->mfc_mutex;
1347 	vfd->v4l2_dev	= &dev->v4l2_dev;
1348 	vfd->vfl_dir	= VFL_DIR_M2M;
1349 	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1350 	set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags);
1351 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1352 	dev->vfd_dec	= vfd;
1353 	video_set_drvdata(vfd, dev);
1354 
1355 	/* encoder */
1356 	vfd = video_device_alloc();
1357 	if (!vfd) {
1358 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1359 		ret = -ENOMEM;
1360 		goto err_enc_alloc;
1361 	}
1362 	vfd->fops	= &s5p_mfc_fops;
1363 	vfd->ioctl_ops	= get_enc_v4l2_ioctl_ops();
1364 	vfd->release	= video_device_release;
1365 	vfd->lock	= &dev->mfc_mutex;
1366 	vfd->v4l2_dev	= &dev->v4l2_dev;
1367 	vfd->vfl_dir	= VFL_DIR_M2M;
1368 	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1369 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1370 	dev->vfd_enc	= vfd;
1371 	video_set_drvdata(vfd, dev);
1372 	platform_set_drvdata(pdev, dev);
1373 
1374 	/* Initialize HW ops and commands based on MFC version */
1375 	s5p_mfc_init_hw_ops(dev);
1376 	s5p_mfc_init_hw_cmds(dev);
1377 	s5p_mfc_init_regs(dev);
1378 
1379 	/* Register decoder and encoder */
1380 	ret = video_register_device(dev->vfd_dec, VFL_TYPE_VIDEO, 0);
1381 	if (ret) {
1382 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1383 		goto err_dec_reg;
1384 	}
1385 	v4l2_info(&dev->v4l2_dev,
1386 		  "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1387 
1388 	ret = video_register_device(dev->vfd_enc, VFL_TYPE_VIDEO, 0);
1389 	if (ret) {
1390 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1391 		goto err_enc_reg;
1392 	}
1393 	v4l2_info(&dev->v4l2_dev,
1394 		  "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1395 
1396 	pr_debug("%s--\n", __func__);
1397 	return 0;
1398 
1399 /* Deinit MFC if probe had failed */
1400 err_enc_reg:
1401 	video_unregister_device(dev->vfd_dec);
1402 err_dec_reg:
1403 	video_device_release(dev->vfd_enc);
1404 err_enc_alloc:
1405 	video_device_release(dev->vfd_dec);
1406 err_dec_alloc:
1407 	v4l2_device_unregister(&dev->v4l2_dev);
1408 err_v4l2_dev_reg:
1409 	s5p_mfc_final_pm(dev);
1410 err_dma:
1411 	s5p_mfc_unconfigure_dma_memory(dev);
1412 
1413 	pr_debug("%s-- with error\n", __func__);
1414 	return ret;
1415 
1416 }
1417 
1418 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1419 static int s5p_mfc_remove(struct platform_device *pdev)
1420 {
1421 	struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1422 	struct s5p_mfc_ctx *ctx;
1423 	int i;
1424 
1425 	v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1426 
1427 	/*
1428 	 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1429 	 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1430 	 * after s5p_mfc_remove() is run during unbind.
1431 	*/
1432 	mutex_lock(&dev->mfc_mutex);
1433 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1434 		ctx = dev->ctx[i];
1435 		if (!ctx)
1436 			continue;
1437 		/* clear ctx->dev */
1438 		ctx->dev = NULL;
1439 	}
1440 	mutex_unlock(&dev->mfc_mutex);
1441 
1442 	del_timer_sync(&dev->watchdog_timer);
1443 	flush_work(&dev->watchdog_work);
1444 
1445 	video_unregister_device(dev->vfd_enc);
1446 	video_unregister_device(dev->vfd_dec);
1447 	video_device_release(dev->vfd_enc);
1448 	video_device_release(dev->vfd_dec);
1449 	v4l2_device_unregister(&dev->v4l2_dev);
1450 	s5p_mfc_unconfigure_dma_memory(dev);
1451 
1452 	s5p_mfc_final_pm(dev);
1453 	return 0;
1454 }
1455 
1456 #ifdef CONFIG_PM_SLEEP
1457 
s5p_mfc_suspend(struct device * dev)1458 static int s5p_mfc_suspend(struct device *dev)
1459 {
1460 	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1461 	int ret;
1462 
1463 	if (m_dev->num_inst == 0)
1464 		return 0;
1465 
1466 	if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1467 		mfc_err("Error: going to suspend for a second time\n");
1468 		return -EIO;
1469 	}
1470 
1471 	/* Check if we're processing then wait if it necessary. */
1472 	while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1473 		/* Try and lock the HW */
1474 		/* Wait on the interrupt waitqueue */
1475 		ret = wait_event_interruptible_timeout(m_dev->queue,
1476 			m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1477 		if (ret == 0) {
1478 			mfc_err("Waiting for hardware to finish timed out\n");
1479 			clear_bit(0, &m_dev->enter_suspend);
1480 			return -EIO;
1481 		}
1482 	}
1483 
1484 	ret = s5p_mfc_sleep(m_dev);
1485 	if (ret) {
1486 		clear_bit(0, &m_dev->enter_suspend);
1487 		clear_bit(0, &m_dev->hw_lock);
1488 	}
1489 	return ret;
1490 }
1491 
s5p_mfc_resume(struct device * dev)1492 static int s5p_mfc_resume(struct device *dev)
1493 {
1494 	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1495 
1496 	if (m_dev->num_inst == 0)
1497 		return 0;
1498 	return s5p_mfc_wakeup(m_dev);
1499 }
1500 #endif
1501 
1502 /* Power management */
1503 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1504 	SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1505 };
1506 
1507 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1508 	.h264_ctx	= MFC_H264_CTX_BUF_SIZE,
1509 	.non_h264_ctx	= MFC_CTX_BUF_SIZE,
1510 	.dsc		= DESC_BUF_SIZE,
1511 	.shm		= SHARED_BUF_SIZE,
1512 };
1513 
1514 static struct s5p_mfc_buf_size buf_size_v5 = {
1515 	.fw	= MAX_FW_SIZE,
1516 	.cpb	= MAX_CPB_SIZE,
1517 	.priv	= &mfc_buf_size_v5,
1518 };
1519 
1520 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1521 	.version	= MFC_VERSION,
1522 	.version_bit	= MFC_V5_BIT,
1523 	.port_num	= MFC_NUM_PORTS,
1524 	.buf_size	= &buf_size_v5,
1525 	.fw_name[0]	= "s5p-mfc.fw",
1526 	.clk_names	= {"mfc", "sclk_mfc"},
1527 	.num_clocks	= 2,
1528 	.use_clock_gating = true,
1529 };
1530 
1531 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1532 	.dev_ctx	= MFC_CTX_BUF_SIZE_V6,
1533 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V6,
1534 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1535 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V6,
1536 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1537 };
1538 
1539 static struct s5p_mfc_buf_size buf_size_v6 = {
1540 	.fw	= MAX_FW_SIZE_V6,
1541 	.cpb	= MAX_CPB_SIZE_V6,
1542 	.priv	= &mfc_buf_size_v6,
1543 };
1544 
1545 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1546 	.version	= MFC_VERSION_V6,
1547 	.version_bit	= MFC_V6_BIT,
1548 	.port_num	= MFC_NUM_PORTS_V6,
1549 	.buf_size	= &buf_size_v6,
1550 	.fw_name[0]     = "s5p-mfc-v6.fw",
1551 	/*
1552 	 * v6-v2 firmware contains bug fixes and interface change
1553 	 * for init buffer command
1554 	 */
1555 	.fw_name[1]     = "s5p-mfc-v6-v2.fw",
1556 	.clk_names	= {"mfc"},
1557 	.num_clocks	= 1,
1558 };
1559 
1560 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1561 	.dev_ctx	= MFC_CTX_BUF_SIZE_V7,
1562 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V7,
1563 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1564 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V7,
1565 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1566 };
1567 
1568 static struct s5p_mfc_buf_size buf_size_v7 = {
1569 	.fw	= MAX_FW_SIZE_V7,
1570 	.cpb	= MAX_CPB_SIZE_V7,
1571 	.priv	= &mfc_buf_size_v7,
1572 };
1573 
1574 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1575 	.version	= MFC_VERSION_V7,
1576 	.version_bit	= MFC_V7_BIT,
1577 	.port_num	= MFC_NUM_PORTS_V7,
1578 	.buf_size	= &buf_size_v7,
1579 	.fw_name[0]     = "s5p-mfc-v7.fw",
1580 	.clk_names	= {"mfc", "sclk_mfc"},
1581 	.num_clocks	= 2,
1582 };
1583 
1584 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1585 	.dev_ctx	= MFC_CTX_BUF_SIZE_V8,
1586 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V8,
1587 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1588 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V8,
1589 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1590 };
1591 
1592 static struct s5p_mfc_buf_size buf_size_v8 = {
1593 	.fw	= MAX_FW_SIZE_V8,
1594 	.cpb	= MAX_CPB_SIZE_V8,
1595 	.priv	= &mfc_buf_size_v8,
1596 };
1597 
1598 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1599 	.version	= MFC_VERSION_V8,
1600 	.version_bit	= MFC_V8_BIT,
1601 	.port_num	= MFC_NUM_PORTS_V8,
1602 	.buf_size	= &buf_size_v8,
1603 	.fw_name[0]     = "s5p-mfc-v8.fw",
1604 	.clk_names	= {"mfc"},
1605 	.num_clocks	= 1,
1606 };
1607 
1608 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1609 	.version	= MFC_VERSION_V8,
1610 	.version_bit	= MFC_V8_BIT,
1611 	.port_num	= MFC_NUM_PORTS_V8,
1612 	.buf_size	= &buf_size_v8,
1613 	.fw_name[0]     = "s5p-mfc-v8.fw",
1614 	.clk_names	= {"pclk", "aclk", "aclk_xiu"},
1615 	.num_clocks	= 3,
1616 };
1617 
1618 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1619 	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
1620 	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1621 	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1622 	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1623 	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1624 	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1625 };
1626 
1627 static struct s5p_mfc_buf_size buf_size_v10 = {
1628 	.fw     = MAX_FW_SIZE_V10,
1629 	.cpb    = MAX_CPB_SIZE_V10,
1630 	.priv   = &mfc_buf_size_v10,
1631 };
1632 
1633 static struct s5p_mfc_variant mfc_drvdata_v10 = {
1634 	.version        = MFC_VERSION_V10,
1635 	.version_bit    = MFC_V10_BIT,
1636 	.port_num       = MFC_NUM_PORTS_V10,
1637 	.buf_size       = &buf_size_v10,
1638 	.fw_name[0]     = "s5p-mfc-v10.fw",
1639 };
1640 
1641 static const struct of_device_id exynos_mfc_match[] = {
1642 	{
1643 		.compatible = "samsung,mfc-v5",
1644 		.data = &mfc_drvdata_v5,
1645 	}, {
1646 		.compatible = "samsung,mfc-v6",
1647 		.data = &mfc_drvdata_v6,
1648 	}, {
1649 		.compatible = "samsung,mfc-v7",
1650 		.data = &mfc_drvdata_v7,
1651 	}, {
1652 		.compatible = "samsung,mfc-v8",
1653 		.data = &mfc_drvdata_v8,
1654 	}, {
1655 		.compatible = "samsung,exynos5433-mfc",
1656 		.data = &mfc_drvdata_v8_5433,
1657 	}, {
1658 		.compatible = "samsung,mfc-v10",
1659 		.data = &mfc_drvdata_v10,
1660 	},
1661 	{},
1662 };
1663 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1664 
1665 static struct platform_driver s5p_mfc_driver = {
1666 	.probe		= s5p_mfc_probe,
1667 	.remove		= s5p_mfc_remove,
1668 	.driver	= {
1669 		.name	= S5P_MFC_NAME,
1670 		.pm	= &s5p_mfc_pm_ops,
1671 		.of_match_table = exynos_mfc_match,
1672 	},
1673 };
1674 
1675 module_platform_driver(s5p_mfc_driver);
1676 
1677 MODULE_LICENSE("GPL");
1678 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1679 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1680 
1681