1 /* linux/arch/arm/plat-s5p/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P - Common clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
21 #include <linux/io.h>
22 #include <asm/div64.h>
23
24 #include <mach/regs-clock.h>
25
26 #include <plat/clock.h>
27 #include <plat/clock-clksrc.h>
28 #include <plat/s5p-clock.h>
29
30 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
31 * clk_ext_xtal_mux.
32 */
33 struct clk clk_ext_xtal_mux = {
34 .name = "ext_xtal",
35 .id = -1,
36 };
37
38 struct clk clk_xusbxti = {
39 .name = "xusbxti",
40 .id = -1,
41 };
42
43 struct clk s5p_clk_27m = {
44 .name = "clk_27m",
45 .id = -1,
46 .rate = 27000000,
47 };
48
49 /* 48MHz USB Phy clock output */
50 struct clk clk_48m = {
51 .name = "clk_48m",
52 .id = -1,
53 .rate = 48000000,
54 };
55
56 /* APLL clock output
57 * No need .ctrlbit, this is always on
58 */
59 struct clk clk_fout_apll = {
60 .name = "fout_apll",
61 .id = -1,
62 };
63
64 /* MPLL clock output
65 * No need .ctrlbit, this is always on
66 */
67 struct clk clk_fout_mpll = {
68 .name = "fout_mpll",
69 .id = -1,
70 };
71
72 /* EPLL clock output */
73 struct clk clk_fout_epll = {
74 .name = "fout_epll",
75 .id = -1,
76 .ctrlbit = (1 << 31),
77 };
78
79 /* DPLL clock output */
80 struct clk clk_fout_dpll = {
81 .name = "fout_dpll",
82 .id = -1,
83 .ctrlbit = (1 << 31),
84 };
85
86 /* VPLL clock output */
87 struct clk clk_fout_vpll = {
88 .name = "fout_vpll",
89 .id = -1,
90 .ctrlbit = (1 << 31),
91 };
92
93 /* Possible clock sources for APLL Mux */
94 static struct clk *clk_src_apll_list[] = {
95 [0] = &clk_fin_apll,
96 [1] = &clk_fout_apll,
97 };
98
99 struct clksrc_sources clk_src_apll = {
100 .sources = clk_src_apll_list,
101 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
102 };
103
104 /* Possible clock sources for MPLL Mux */
105 static struct clk *clk_src_mpll_list[] = {
106 [0] = &clk_fin_mpll,
107 [1] = &clk_fout_mpll,
108 };
109
110 struct clksrc_sources clk_src_mpll = {
111 .sources = clk_src_mpll_list,
112 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
113 };
114
115 /* Possible clock sources for EPLL Mux */
116 static struct clk *clk_src_epll_list[] = {
117 [0] = &clk_fin_epll,
118 [1] = &clk_fout_epll,
119 };
120
121 struct clksrc_sources clk_src_epll = {
122 .sources = clk_src_epll_list,
123 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
124 };
125
126 /* Possible clock sources for DPLL Mux */
127 static struct clk *clk_src_dpll_list[] = {
128 [0] = &clk_fin_dpll,
129 [1] = &clk_fout_dpll,
130 };
131
132 struct clksrc_sources clk_src_dpll = {
133 .sources = clk_src_dpll_list,
134 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
135 };
136
137 struct clk clk_vpll = {
138 .name = "vpll",
139 .id = -1,
140 };
141
s5p_gatectrl(void __iomem * reg,struct clk * clk,int enable)142 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
143 {
144 unsigned int ctrlbit = clk->ctrlbit;
145 u32 con;
146
147 con = __raw_readl(reg);
148 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
149 __raw_writel(con, reg);
150 return 0;
151 }
152
s5p_epll_enable(struct clk * clk,int enable)153 int s5p_epll_enable(struct clk *clk, int enable)
154 {
155 unsigned int ctrlbit = clk->ctrlbit;
156 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
157
158 if (enable)
159 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
160 else
161 __raw_writel(epll_con, S5P_EPLL_CON);
162
163 return 0;
164 }
165
s5p_epll_get_rate(struct clk * clk)166 unsigned long s5p_epll_get_rate(struct clk *clk)
167 {
168 return clk->rate;
169 }
170
171 static struct clk *s5p_clks[] __initdata = {
172 &clk_ext_xtal_mux,
173 &clk_48m,
174 &s5p_clk_27m,
175 &clk_fout_apll,
176 &clk_fout_mpll,
177 &clk_fout_epll,
178 &clk_fout_dpll,
179 &clk_fout_vpll,
180 &clk_vpll,
181 &clk_xusbxti,
182 };
183
s5p_register_clocks(unsigned long xtal_freq)184 void __init s5p_register_clocks(unsigned long xtal_freq)
185 {
186 int ret;
187
188 clk_ext_xtal_mux.rate = xtal_freq;
189
190 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
191 if (ret > 0)
192 printk(KERN_ERR "Failed to register s5p clocks\n");
193 }
194