1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5433 TM2 board device tree source 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * 7 * Common device tree source file for Samsung's TM2 and TM2E boards 8 * which are based on Samsung Exynos5433 SoC. 9 */ 10 11/dts-v1/; 12#include "exynos5433.dtsi" 13#include <dt-bindings/clock/samsung,s2mps11.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/input/input.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17#include <dt-bindings/sound/samsung-i2s.h> 18 19/ { 20 aliases { 21 gsc0 = &gsc_0; 22 gsc1 = &gsc_1; 23 gsc2 = &gsc_2; 24 mmc0 = &mshc_0; 25 mmc2 = &mshc_2; 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_aud; 28 pinctrl2 = &pinctrl_cpif; 29 pinctrl3 = &pinctrl_ese; 30 pinctrl4 = &pinctrl_finger; 31 pinctrl5 = &pinctrl_fsys; 32 pinctrl6 = &pinctrl_imem; 33 pinctrl7 = &pinctrl_nfc; 34 pinctrl8 = &pinctrl_peric; 35 pinctrl9 = &pinctrl_touch; 36 serial0 = &serial_0; 37 serial1 = &serial_1; 38 serial2 = &serial_2; 39 serial3 = &serial_3; 40 spi0 = &spi_0; 41 spi1 = &spi_1; 42 spi2 = &spi_2; 43 spi3 = &spi_3; 44 spi4 = &spi_4; 45 }; 46 47 chosen { 48 stdout-path = &serial_1; 49 }; 50 51 memory@20000000 { 52 device_type = "memory"; 53 reg = <0x0 0x20000000 0x0 0xc0000000>; 54 }; 55 56 gpio-keys { 57 compatible = "gpio-keys"; 58 59 power-key { 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; 61 linux,code = <KEY_POWER>; 62 label = "power key"; 63 debounce-interval = <10>; 64 }; 65 66 volume-up-key { 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; 68 linux,code = <KEY_VOLUMEUP>; 69 label = "volume-up key"; 70 debounce-interval = <10>; 71 }; 72 73 volume-down-key { 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; 75 linux,code = <KEY_VOLUMEDOWN>; 76 label = "volume-down key"; 77 debounce-interval = <10>; 78 }; 79 80 homepage-key { 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; 82 linux,code = <KEY_MENU>; 83 label = "homepage key"; 84 debounce-interval = <10>; 85 }; 86 }; 87 88 i2c_max98504: i2c-gpio-0 { 89 compatible = "i2c-gpio"; 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>; 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>; 92 i2c-gpio,delay-us = <2>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 max98504: amplifier@31 { 97 compatible = "maxim,max98504"; 98 reg = <0x31>; 99 100 DIOVDD-supply = <&ldo3_reg>; 101 DVDD-supply = <&ldo3_reg>; 102 PVDD-supply = <&vph_pwr_regulator>; 103 }; 104 }; 105 106 vph_pwr_regulator: regulator-vph-pwr { 107 compatible = "regulator-fixed"; 108 regulator-name = "VPH_PWR"; 109 regulator-min-microvolt = <4200000>; 110 regulator-max-microvolt = <4200000>; 111 }; 112 113 irda_regulator: regulator-irda { 114 compatible = "regulator-fixed"; 115 enable-active-high; 116 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>; 117 regulator-name = "irda_regulator"; 118 }; 119 120 sound { 121 compatible = "samsung,tm2-audio"; 122 audio-codec = <&wm5110>, <&hdmi>; 123 i2s-controller = <&i2s0 0>, <&i2s1 0>; 124 audio-amplifier = <&max98504>; 125 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; 126 model = "wm5110"; 127 samsung,audio-routing = 128 /* Headphone */ 129 "HP", "HPOUT1L", 130 "HP", "HPOUT1R", 131 132 /* Speaker */ 133 "SPK", "SPKOUT", 134 "SPKOUT", "HPOUT2L", 135 "SPKOUT", "HPOUT2R", 136 137 /* Receiver */ 138 "RCV", "HPOUT3L", 139 "RCV", "HPOUT3R"; 140 }; 141}; 142 143&adc { 144 vdd-supply = <&ldo3_reg>; 145 status = "okay"; 146 147 thermistor-ap { 148 compatible = "murata,ncp03wf104"; 149 pullup-uv = <1800000>; 150 pullup-ohm = <100000>; 151 pulldown-ohm = <0>; 152 io-channels = <&adc 0>; 153 }; 154 155 thermistor-battery { 156 compatible = "murata,ncp03wf104"; 157 pullup-uv = <1800000>; 158 pullup-ohm = <100000>; 159 pulldown-ohm = <0>; 160 io-channels = <&adc 1>; 161 #thermal-sensor-cells = <0>; 162 }; 163 164 thermistor-charger { 165 compatible = "murata,ncp03wf104"; 166 pullup-uv = <1800000>; 167 pullup-ohm = <100000>; 168 pulldown-ohm = <0>; 169 io-channels = <&adc 2>; 170 }; 171}; 172 173&bus_g2d_400 { 174 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; 175 vdd-supply = <&buck4_reg>; 176 exynos,saturation-ratio = <10>; 177 status = "okay"; 178}; 179 180&bus_g2d_266 { 181 devfreq = <&bus_g2d_400>; 182 status = "okay"; 183}; 184 185&bus_gscl { 186 devfreq = <&bus_g2d_400>; 187 status = "okay"; 188}; 189 190&bus_hevc { 191 devfreq = <&bus_g2d_400>; 192 status = "okay"; 193}; 194 195&bus_jpeg { 196 devfreq = <&bus_g2d_400>; 197 status = "okay"; 198}; 199 200&bus_mfc { 201 devfreq = <&bus_g2d_400>; 202 status = "okay"; 203}; 204 205&bus_mscl { 206 devfreq = <&bus_g2d_400>; 207 status = "okay"; 208}; 209 210&bus_noc0 { 211 devfreq = <&bus_g2d_400>; 212 status = "okay"; 213}; 214 215&bus_noc1 { 216 devfreq = <&bus_g2d_400>; 217 status = "okay"; 218}; 219 220&bus_noc2 { 221 devfreq = <&bus_g2d_400>; 222 status = "okay"; 223}; 224 225&cmu_aud { 226 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 227 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, 228 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, 229 <&cmu_top CLK_MOUT_AUD_PLL>, 230 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 231 <&cmu_top CLK_MOUT_SCLK_AUDIO0>, 232 <&cmu_top CLK_MOUT_SCLK_AUDIO1>, 233 <&cmu_top CLK_MOUT_SCLK_SPDIF>, 234 235 <&cmu_aud CLK_DIV_AUD_CA5>, 236 <&cmu_aud CLK_DIV_ACLK_AUD>, 237 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, 238 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, 239 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, 240 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, 241 <&cmu_aud CLK_DIV_SCLK_AUD_UART>, 242 <&cmu_top CLK_DIV_SCLK_AUDIO0>, 243 <&cmu_top CLK_DIV_SCLK_AUDIO1>, 244 <&cmu_top CLK_DIV_SCLK_PCM1>, 245 <&cmu_top CLK_DIV_SCLK_I2S1>; 246 247 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, 248 <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 249 <&cmu_aud CLK_MOUT_AUD_PLL_USER>, 250 <&cmu_top CLK_FOUT_AUD_PLL>, 251 <&cmu_top CLK_MOUT_AUD_PLL>, 252 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 253 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, 254 <&cmu_top CLK_SCLK_AUDIO0>; 255 256 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, 257 <196608001>, <65536001>, <32768001>, <49152001>, 258 <2048001>, <24576001>, <196608001>, 259 <24576001>, <98304001>, <2048001>, <49152001>; 260}; 261 262&cmu_fsys { 263 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, 264 <&cmu_top CLK_MOUT_SCLK_USBHOST30>, 265 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, 266 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, 267 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, 268 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, 269 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, 270 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, 271 <&cmu_top CLK_DIV_SCLK_USBDRD30>, 272 <&cmu_top CLK_DIV_SCLK_USBHOST30>; 273 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, 274 <&cmu_top CLK_MOUT_BUS_PLL_USER>, 275 <&cmu_top CLK_SCLK_USBDRD30_FSYS>, 276 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 277 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, 278 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, 279 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, 280 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; 281 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, 282 <66700000>, <66700000>; 283}; 284 285&cmu_gscl { 286 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, 287 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; 288 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, 289 <&cmu_top CLK_ACLK_GSCL_333>; 290}; 291 292&cmu_mfc { 293 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; 294 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; 295}; 296 297&cmu_mif { 298 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>; 299 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>; 300 assigned-clock-rates = <0>, <333000000>; 301}; 302 303&cmu_mscl { 304 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, 305 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, 306 <&cmu_mscl CLK_MOUT_SCLK_JPEG>, 307 <&cmu_top CLK_MOUT_SCLK_JPEG_A>; 308 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, 309 <&cmu_top CLK_SCLK_JPEG_MSCL>, 310 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, 311 <&cmu_top CLK_MOUT_BUS_PLL_USER>; 312}; 313 314&cmu_top { 315 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>; 316 assigned-clock-rates = <196608001>; 317}; 318 319&cpu0 { 320 cpu-supply = <&buck3_reg>; 321}; 322 323&cpu4 { 324 cpu-supply = <&buck2_reg>; 325}; 326 327&decon { 328 status = "okay"; 329}; 330 331&decon_tv { 332 status = "okay"; 333 334 ports { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 port@0 { 339 reg = <0>; 340 tv_to_hdmi: endpoint { 341 remote-endpoint = <&hdmi_to_tv>; 342 }; 343 }; 344 }; 345}; 346 347&dsi { 348 status = "okay"; 349 vddcore-supply = <&ldo6_reg>; 350 vddio-supply = <&ldo7_reg>; 351 samsung,burst-clock-frequency = <512000000>; 352 samsung,esc-clock-frequency = <16000000>; 353 samsung,pll-clock-frequency = <24000000>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&te_irq>; 356}; 357 358&gpu { 359 mali-supply = <&buck6_reg>; 360 status = "okay"; 361}; 362 363&hdmi { 364 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; 365 status = "okay"; 366 vdd-supply = <&ldo6_reg>; 367 vdd_osc-supply = <&ldo7_reg>; 368 vdd_pll-supply = <&ldo6_reg>; 369 370 ports { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 port@0 { 375 reg = <0>; 376 hdmi_to_tv: endpoint { 377 remote-endpoint = <&tv_to_hdmi>; 378 }; 379 }; 380 381 port@1 { 382 reg = <1>; 383 hdmi_to_mhl: endpoint { 384 remote-endpoint = <&mhl_to_hdmi>; 385 }; 386 }; 387 }; 388}; 389 390&hsi2c_0 { 391 status = "okay"; 392 clock-frequency = <2500000>; 393 394 pmic@66 { 395 compatible = "samsung,s2mps13-pmic"; 396 interrupt-parent = <&gpa0>; 397 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 398 reg = <0x66>; 399 samsung,s2mps11-wrstbi-ground; 400 wakeup-source; 401 402 s2mps13_osc: clocks { 403 compatible = "samsung,s2mps13-clk"; 404 #clock-cells = <1>; 405 clock-output-names = "s2mps13_ap", "s2mps13_cp", 406 "s2mps13_bt"; 407 }; 408 409 regulators { 410 ldo1_reg: LDO1 { 411 regulator-name = "VDD_ALIVE_0.9V_AP"; 412 regulator-min-microvolt = <900000>; 413 regulator-max-microvolt = <900000>; 414 regulator-always-on; 415 }; 416 417 ldo2_reg: LDO2 { 418 regulator-name = "VDDQ_MMC2_2.8V_AP"; 419 regulator-min-microvolt = <2800000>; 420 regulator-max-microvolt = <2800000>; 421 regulator-always-on; 422 regulator-state-mem { 423 regulator-off-in-suspend; 424 }; 425 }; 426 427 ldo3_reg: LDO3 { 428 regulator-name = "VDD1_E_1.8V_AP"; 429 regulator-min-microvolt = <1800000>; 430 regulator-max-microvolt = <1800000>; 431 regulator-always-on; 432 }; 433 434 ldo4_reg: LDO4 { 435 regulator-name = "VDD10_MIF_PLL_1.0V_AP"; 436 regulator-min-microvolt = <1300000>; 437 regulator-max-microvolt = <1300000>; 438 regulator-always-on; 439 regulator-state-mem { 440 regulator-off-in-suspend; 441 }; 442 }; 443 444 ldo5_reg: LDO5 { 445 regulator-name = "VDD10_DPLL_1.0V_AP"; 446 regulator-min-microvolt = <1000000>; 447 regulator-max-microvolt = <1000000>; 448 regulator-always-on; 449 regulator-state-mem { 450 regulator-off-in-suspend; 451 }; 452 }; 453 454 ldo6_reg: LDO6 { 455 regulator-name = "VDD10_MIPI2L_1.0V_AP"; 456 regulator-min-microvolt = <1000000>; 457 regulator-max-microvolt = <1000000>; 458 regulator-state-mem { 459 regulator-off-in-suspend; 460 }; 461 }; 462 463 ldo7_reg: LDO7 { 464 regulator-name = "VDD18_MIPI2L_1.8V_AP"; 465 regulator-min-microvolt = <1800000>; 466 regulator-max-microvolt = <1800000>; 467 regulator-always-on; 468 regulator-state-mem { 469 regulator-off-in-suspend; 470 }; 471 }; 472 473 ldo8_reg: LDO8 { 474 regulator-name = "VDD18_LLI_1.8V_AP"; 475 regulator-min-microvolt = <1800000>; 476 regulator-max-microvolt = <1800000>; 477 regulator-always-on; 478 regulator-state-mem { 479 regulator-off-in-suspend; 480 }; 481 }; 482 483 ldo9_reg: LDO9 { 484 regulator-name = "VDD18_ABB_ETC_1.8V_AP"; 485 regulator-min-microvolt = <1800000>; 486 regulator-max-microvolt = <1800000>; 487 regulator-always-on; 488 regulator-state-mem { 489 regulator-off-in-suspend; 490 }; 491 }; 492 493 ldo10_reg: LDO10 { 494 regulator-name = "VDD33_USB30_3.0V_AP"; 495 regulator-min-microvolt = <3000000>; 496 regulator-max-microvolt = <3000000>; 497 regulator-state-mem { 498 regulator-off-in-suspend; 499 }; 500 }; 501 502 ldo11_reg: LDO11 { 503 regulator-name = "VDD_INT_M_1.0V_AP"; 504 regulator-min-microvolt = <1000000>; 505 regulator-max-microvolt = <1000000>; 506 regulator-always-on; 507 regulator-state-mem { 508 regulator-off-in-suspend; 509 }; 510 }; 511 512 ldo12_reg: LDO12 { 513 regulator-name = "VDD_KFC_M_1.1V_AP"; 514 regulator-min-microvolt = <800000>; 515 regulator-max-microvolt = <1350000>; 516 regulator-always-on; 517 }; 518 519 ldo13_reg: LDO13 { 520 regulator-name = "VDD_G3D_M_0.95V_AP"; 521 regulator-min-microvolt = <950000>; 522 regulator-max-microvolt = <950000>; 523 regulator-always-on; 524 regulator-state-mem { 525 regulator-off-in-suspend; 526 }; 527 }; 528 529 ldo14_reg: LDO14 { 530 regulator-name = "VDDQ_M1_LDO_1.2V_AP"; 531 regulator-min-microvolt = <1200000>; 532 regulator-max-microvolt = <1200000>; 533 regulator-always-on; 534 regulator-state-mem { 535 regulator-off-in-suspend; 536 }; 537 }; 538 539 ldo15_reg: LDO15 { 540 regulator-name = "VDDQ_M2_LDO_1.2V_AP"; 541 regulator-min-microvolt = <1200000>; 542 regulator-max-microvolt = <1200000>; 543 regulator-always-on; 544 regulator-state-mem { 545 regulator-off-in-suspend; 546 }; 547 }; 548 549 ldo16_reg: LDO16 { 550 regulator-name = "VDDQ_EFUSE"; 551 regulator-min-microvolt = <1400000>; 552 regulator-max-microvolt = <3400000>; 553 regulator-always-on; 554 }; 555 556 ldo17_reg: LDO17 { 557 regulator-name = "V_TFLASH_2.8V_AP"; 558 regulator-min-microvolt = <2800000>; 559 regulator-max-microvolt = <2800000>; 560 }; 561 562 ldo18_reg: LDO18 { 563 regulator-name = "V_CODEC_1.8V_AP"; 564 regulator-min-microvolt = <1800000>; 565 regulator-max-microvolt = <1800000>; 566 }; 567 568 ldo19_reg: LDO19 { 569 regulator-name = "VDDA_1.8V_COMP"; 570 regulator-min-microvolt = <1800000>; 571 regulator-max-microvolt = <1800000>; 572 regulator-always-on; 573 }; 574 575 ldo20_reg: LDO20 { 576 regulator-name = "VCC_2.8V_AP"; 577 regulator-min-microvolt = <2800000>; 578 regulator-max-microvolt = <2800000>; 579 regulator-always-on; 580 }; 581 582 ldo21_reg: LDO21 { 583 regulator-name = "VT_CAM_1.8V"; 584 regulator-min-microvolt = <1800000>; 585 regulator-max-microvolt = <1800000>; 586 }; 587 588 ldo22_reg: LDO22 { 589 regulator-name = "CAM_IO_1.8V_AP"; 590 regulator-min-microvolt = <1800000>; 591 regulator-max-microvolt = <1800000>; 592 }; 593 594 ldo23_reg: LDO23 { 595 regulator-name = "CAM_SEN_CORE_1.05V_AP"; 596 regulator-min-microvolt = <1050000>; 597 regulator-max-microvolt = <1050000>; 598 }; 599 600 ldo24_reg: LDO24 { 601 regulator-name = "VT_CAM_1.2V"; 602 regulator-min-microvolt = <1200000>; 603 regulator-max-microvolt = <1200000>; 604 }; 605 606 ldo25_reg: LDO25 { 607 regulator-name = "UNUSED_LDO25"; 608 regulator-min-microvolt = <2800000>; 609 regulator-max-microvolt = <2800000>; 610 }; 611 612 ldo26_reg: LDO26 { 613 regulator-name = "CAM_AF_2.8V_AP"; 614 regulator-min-microvolt = <2800000>; 615 regulator-max-microvolt = <2800000>; 616 }; 617 618 ldo27_reg: LDO27 { 619 regulator-name = "VCC_3.0V_LCD_AP"; 620 regulator-min-microvolt = <3000000>; 621 regulator-max-microvolt = <3000000>; 622 }; 623 624 ldo28_reg: LDO28 { 625 regulator-name = "VCC_1.8V_LCD_AP"; 626 regulator-min-microvolt = <1800000>; 627 regulator-max-microvolt = <1800000>; 628 }; 629 630 ldo29_reg: LDO29 { 631 regulator-name = "VT_CAM_2.8V"; 632 regulator-min-microvolt = <3000000>; 633 regulator-max-microvolt = <3000000>; 634 }; 635 636 ldo30_reg: LDO30 { 637 regulator-name = "TSP_AVDD_3.3V_AP"; 638 regulator-min-microvolt = <3300000>; 639 regulator-max-microvolt = <3300000>; 640 }; 641 642 ldo31_reg: LDO31 { 643 /* 644 * LDO31 differs from target to target, 645 * its definition is in the .dts 646 */ 647 }; 648 649 ldo32_reg: LDO32 { 650 regulator-name = "VTOUCH_1.8V_AP"; 651 regulator-min-microvolt = <1800000>; 652 regulator-max-microvolt = <1800000>; 653 }; 654 655 ldo33_reg: LDO33 { 656 regulator-name = "VTOUCH_LED_3.3V"; 657 regulator-min-microvolt = <2500000>; 658 regulator-max-microvolt = <3300000>; 659 regulator-ramp-delay = <12500>; 660 }; 661 662 ldo34_reg: LDO34 { 663 regulator-name = "VCC_1.8V_MHL_AP"; 664 regulator-min-microvolt = <1000000>; 665 regulator-max-microvolt = <2100000>; 666 }; 667 668 ldo35_reg: LDO35 { 669 regulator-name = "OIS_VM_2.8V"; 670 regulator-min-microvolt = <1800000>; 671 regulator-max-microvolt = <2800000>; 672 }; 673 674 ldo36_reg: LDO36 { 675 regulator-name = "VSIL_1.0V"; 676 regulator-min-microvolt = <1000000>; 677 regulator-max-microvolt = <1000000>; 678 }; 679 680 ldo37_reg: LDO37 { 681 regulator-name = "VF_1.8V"; 682 regulator-min-microvolt = <1800000>; 683 regulator-max-microvolt = <1800000>; 684 }; 685 686 ldo38_reg: LDO38 { 687 /* 688 * LDO38 differs from target to target, 689 * its definition is in the .dts 690 */ 691 }; 692 693 ldo39_reg: LDO39 { 694 regulator-name = "V_HRM_1.8V"; 695 regulator-min-microvolt = <1800000>; 696 regulator-max-microvolt = <1800000>; 697 }; 698 699 ldo40_reg: LDO40 { 700 regulator-name = "V_HRM_3.3V"; 701 regulator-min-microvolt = <3300000>; 702 regulator-max-microvolt = <3300000>; 703 }; 704 705 buck1_reg: BUCK1 { 706 regulator-name = "VDD_MIF_0.9V_AP"; 707 regulator-min-microvolt = <600000>; 708 regulator-max-microvolt = <1500000>; 709 regulator-always-on; 710 regulator-state-mem { 711 regulator-off-in-suspend; 712 }; 713 }; 714 715 buck2_reg: BUCK2 { 716 regulator-name = "VDD_EGL_1.0V_AP"; 717 regulator-min-microvolt = <900000>; 718 regulator-max-microvolt = <1300000>; 719 regulator-always-on; 720 regulator-state-mem { 721 regulator-off-in-suspend; 722 }; 723 }; 724 725 buck3_reg: BUCK3 { 726 regulator-name = "VDD_KFC_1.0V_AP"; 727 regulator-min-microvolt = <800000>; 728 regulator-max-microvolt = <1200000>; 729 regulator-always-on; 730 regulator-state-mem { 731 regulator-off-in-suspend; 732 }; 733 }; 734 735 buck4_reg: BUCK4 { 736 regulator-name = "VDD_INT_0.95V_AP"; 737 regulator-min-microvolt = <600000>; 738 regulator-max-microvolt = <1500000>; 739 regulator-always-on; 740 regulator-state-mem { 741 regulator-off-in-suspend; 742 }; 743 }; 744 745 buck5_reg: BUCK5 { 746 regulator-name = "VDD_DISP_CAM0_0.9V_AP"; 747 regulator-min-microvolt = <600000>; 748 regulator-max-microvolt = <1500000>; 749 regulator-always-on; 750 regulator-state-mem { 751 regulator-off-in-suspend; 752 }; 753 }; 754 755 buck6_reg: BUCK6 { 756 regulator-name = "VDD_G3D_0.9V_AP"; 757 regulator-min-microvolt = <600000>; 758 regulator-max-microvolt = <1500000>; 759 regulator-always-on; 760 regulator-state-mem { 761 regulator-off-in-suspend; 762 }; 763 }; 764 765 buck7_reg: BUCK7 { 766 regulator-name = "VDD_MEM1_1.2V_AP"; 767 regulator-min-microvolt = <1200000>; 768 regulator-max-microvolt = <1200000>; 769 regulator-always-on; 770 }; 771 772 buck8_reg: BUCK8 { 773 regulator-name = "VDD_LLDO_1.35V_AP"; 774 regulator-min-microvolt = <1350000>; 775 regulator-max-microvolt = <3300000>; 776 regulator-always-on; 777 }; 778 779 buck9_reg: BUCK9 { 780 regulator-name = "VDD_MLDO_2.0V_AP"; 781 regulator-min-microvolt = <1350000>; 782 regulator-max-microvolt = <3300000>; 783 regulator-always-on; 784 }; 785 786 buck10_reg: BUCK10 { 787 regulator-name = "vdd_mem2"; 788 regulator-min-microvolt = <550000>; 789 regulator-max-microvolt = <1500000>; 790 regulator-always-on; 791 }; 792 }; 793 }; 794}; 795 796&hsi2c_4 { 797 status = "okay"; 798 799 s3fwrn5: nfc@27 { 800 compatible = "samsung,s3fwrn5-i2c"; 801 reg = <0x27>; 802 interrupt-parent = <&gpa1>; 803 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 804 en-gpios = <&gpf1 4 GPIO_ACTIVE_LOW>; 805 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; 806 }; 807}; 808 809&hsi2c_5 { 810 status = "okay"; 811 812 stmfts: touchscreen@49 { 813 compatible = "st,stmfts"; 814 reg = <0x49>; 815 interrupt-parent = <&gpa1>; 816 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 817 avdd-supply = <&ldo30_reg>; 818 vdd-supply = <&ldo31_reg>; 819 }; 820}; 821 822&hsi2c_7 { 823 status = "okay"; 824 clock-frequency = <1000000>; 825 826 bridge@39 { 827 reg = <0x39>; 828 compatible = "sil,sii8620"; 829 cvcc10-supply = <&ldo36_reg>; 830 iovcc18-supply = <&ldo34_reg>; 831 interrupt-parent = <&gpf0>; 832 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 833 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; 834 clocks = <&pmu_system_controller 0>; 835 clock-names = "xtal"; 836 837 ports { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 port@0 { 842 reg = <0>; 843 mhl_to_hdmi: endpoint { 844 remote-endpoint = <&hdmi_to_mhl>; 845 }; 846 }; 847 848 port@1 { 849 reg = <1>; 850 mhl_to_musb_con: endpoint { 851 remote-endpoint = <&musb_con_to_mhl>; 852 }; 853 }; 854 }; 855 }; 856}; 857 858&hsi2c_8 { 859 status = "okay"; 860 861 pmic@66 { 862 compatible = "maxim,max77843"; 863 interrupt-parent = <&gpa1>; 864 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 865 reg = <0x66>; 866 867 muic: extcon { 868 compatible = "maxim,max77843-muic"; 869 870 musb_con: connector { 871 compatible = "samsung,usb-connector-11pin", 872 "usb-b-connector"; 873 label = "micro-USB"; 874 type = "micro"; 875 876 ports { 877 #address-cells = <1>; 878 #size-cells = <0>; 879 880 port@0 { 881 /* 882 * TODO: The DTS this is based on does not have 883 * port@0 which is a required property. The ports 884 * look incomplete and need fixing. 885 * Add a disabled port just to satisfy dtschema. 886 */ 887 reg = <0>; 888 status = "disabled"; 889 }; 890 891 port@3 { 892 reg = <3>; 893 musb_con_to_mhl: endpoint { 894 remote-endpoint = <&mhl_to_musb_con>; 895 }; 896 }; 897 }; 898 }; 899 900 ports { 901 port { 902 muic_to_usb: endpoint { 903 remote-endpoint = <&usb_to_muic>; 904 }; 905 }; 906 }; 907 }; 908 909 regulators { 910 compatible = "maxim,max77843-regulator"; 911 safeout1_reg: SAFEOUT1 { 912 regulator-name = "SAFEOUT1"; 913 regulator-min-microvolt = <3300000>; 914 regulator-max-microvolt = <4950000>; 915 }; 916 917 safeout2_reg: SAFEOUT2 { 918 regulator-name = "SAFEOUT2"; 919 regulator-min-microvolt = <3300000>; 920 regulator-max-microvolt = <4950000>; 921 }; 922 923 charger_reg: CHARGER { 924 regulator-name = "CHARGER"; 925 regulator-min-microamp = <100000>; 926 regulator-max-microamp = <3150000>; 927 }; 928 }; 929 930 haptic: motor-driver { 931 compatible = "maxim,max77843-haptic"; 932 haptic-supply = <&ldo38_reg>; 933 pwms = <&pwm 0 33670 0>; 934 }; 935 }; 936}; 937 938&hsi2c_11 { 939 status = "okay"; 940}; 941 942&i2s0 { 943 status = "okay"; 944}; 945 946&i2s1 { 947 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; 948 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; 949 status = "okay"; 950}; 951 952&mshc_0 { 953 status = "okay"; 954 mmc-ddr-1_8v; 955 mmc-hs200-1_8v; 956 mmc-hs400-1_8v; 957 cap-mmc-highspeed; 958 non-removable; 959 card-detect-delay = <200>; 960 samsung,dw-mshc-ciu-div = <3>; 961 samsung,dw-mshc-sdr-timing = <0 4>; 962 samsung,dw-mshc-ddr-timing = <0 2>; 963 samsung,dw-mshc-hs400-timing = <0 3>; 964 samsung,read-strobe-delay = <90>; 965 fifo-depth = <0x80>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 968 &sd0_bus8 &sd0_rdqs>; 969 bus-width = <8>; 970 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; 971 assigned-clock-rates = <800000000>; 972}; 973 974&mshc_2 { 975 status = "okay"; 976 cap-sd-highspeed; 977 disable-wp; 978 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 979 card-detect-delay = <200>; 980 samsung,dw-mshc-ciu-div = <3>; 981 samsung,dw-mshc-sdr-timing = <0 4>; 982 samsung,dw-mshc-ddr-timing = <0 2>; 983 fifo-depth = <0x80>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; 986 bus-width = <4>; 987}; 988 989&pcie { 990 status = "okay"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 993 vdd10-supply = <&ldo6_reg>; 994 vdd18-supply = <&ldo7_reg>; 995 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, 996 <&cmu_top CLK_MOUT_SCLK_PCIE_100>; 997 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 998 <&cmu_top CLK_MOUT_BUS_PLL_USER>; 999 assigned-clock-rates = <0>, <100000000>; 1000 interrupt-map-mask = <0 0 0 0>; 1001 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1002}; 1003 1004&pcie_phy { 1005 status = "okay"; 1006}; 1007 1008&ppmu_d0_general { 1009 status = "okay"; 1010 events { 1011 ppmu_event0_d0_general: ppmu-event0-d0-general { 1012 event-name = "ppmu-event0-d0-general"; 1013 }; 1014 }; 1015}; 1016 1017&ppmu_d1_general { 1018 status = "okay"; 1019 events { 1020 ppmu_event0_d1_general: ppmu-event0-d1-general { 1021 event-name = "ppmu-event0-d1-general"; 1022 }; 1023 }; 1024}; 1025 1026&pinctrl_alive { 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&initial_alive>; 1029 1030 initial_alive: initial-state { 1031 PIN_IN(gpa0-0, DOWN, FAST_SR1); 1032 PIN_IN(gpa0-1, NONE, FAST_SR1); 1033 PIN_IN(gpa0-2, DOWN, FAST_SR1); 1034 PIN_IN(gpa0-3, NONE, FAST_SR1); 1035 PIN_IN(gpa0-4, NONE, FAST_SR1); 1036 PIN_IN(gpa0-5, DOWN, FAST_SR1); 1037 PIN_IN(gpa0-6, NONE, FAST_SR1); 1038 PIN_IN(gpa0-7, NONE, FAST_SR1); 1039 1040 PIN_IN(gpa1-0, UP, FAST_SR1); 1041 PIN_IN(gpa1-1, UP, FAST_SR1); 1042 PIN_IN(gpa1-2, NONE, FAST_SR1); 1043 PIN_IN(gpa1-3, DOWN, FAST_SR1); 1044 PIN_IN(gpa1-4, DOWN, FAST_SR1); 1045 PIN_IN(gpa1-5, NONE, FAST_SR1); 1046 PIN_IN(gpa1-6, NONE, FAST_SR1); 1047 PIN_IN(gpa1-7, NONE, FAST_SR1); 1048 1049 PIN_IN(gpa2-0, NONE, FAST_SR1); 1050 PIN_IN(gpa2-1, NONE, FAST_SR1); 1051 PIN_IN(gpa2-2, NONE, FAST_SR1); 1052 PIN_IN(gpa2-3, DOWN, FAST_SR1); 1053 PIN_IN(gpa2-4, NONE, FAST_SR1); 1054 PIN_IN(gpa2-5, DOWN, FAST_SR1); 1055 PIN_IN(gpa2-6, DOWN, FAST_SR1); 1056 PIN_IN(gpa2-7, NONE, FAST_SR1); 1057 1058 PIN_IN(gpa3-0, DOWN, FAST_SR1); 1059 PIN_IN(gpa3-1, DOWN, FAST_SR1); 1060 PIN_IN(gpa3-2, NONE, FAST_SR1); 1061 PIN_IN(gpa3-3, DOWN, FAST_SR1); 1062 PIN_IN(gpa3-4, NONE, FAST_SR1); 1063 PIN_IN(gpa3-5, DOWN, FAST_SR1); 1064 PIN_IN(gpa3-6, DOWN, FAST_SR1); 1065 PIN_IN(gpa3-7, DOWN, FAST_SR1); 1066 1067 PIN_IN(gpf1-0, NONE, FAST_SR1); 1068 PIN_IN(gpf1-1, NONE, FAST_SR1); 1069 PIN_IN(gpf1-2, DOWN, FAST_SR1); 1070 PIN_IN(gpf1-4, UP, FAST_SR1); 1071 PIN_OT(gpf1-5, NONE, FAST_SR1); 1072 PIN_IN(gpf1-6, DOWN, FAST_SR1); 1073 PIN_IN(gpf1-7, DOWN, FAST_SR1); 1074 1075 PIN_IN(gpf2-0, DOWN, FAST_SR1); 1076 PIN_IN(gpf2-1, DOWN, FAST_SR1); 1077 PIN_IN(gpf2-2, DOWN, FAST_SR1); 1078 PIN_IN(gpf2-3, DOWN, FAST_SR1); 1079 1080 PIN_IN(gpf3-0, DOWN, FAST_SR1); 1081 PIN_IN(gpf3-1, DOWN, FAST_SR1); 1082 PIN_IN(gpf3-2, NONE, FAST_SR1); 1083 PIN_IN(gpf3-3, DOWN, FAST_SR1); 1084 1085 PIN_IN(gpf4-0, DOWN, FAST_SR1); 1086 PIN_IN(gpf4-1, DOWN, FAST_SR1); 1087 PIN_IN(gpf4-2, DOWN, FAST_SR1); 1088 PIN_IN(gpf4-3, DOWN, FAST_SR1); 1089 PIN_IN(gpf4-4, DOWN, FAST_SR1); 1090 PIN_IN(gpf4-5, DOWN, FAST_SR1); 1091 PIN_IN(gpf4-6, DOWN, FAST_SR1); 1092 PIN_IN(gpf4-7, DOWN, FAST_SR1); 1093 1094 PIN_IN(gpf5-0, DOWN, FAST_SR1); 1095 PIN_IN(gpf5-1, DOWN, FAST_SR1); 1096 PIN_IN(gpf5-2, DOWN, FAST_SR1); 1097 PIN_IN(gpf5-3, DOWN, FAST_SR1); 1098 PIN_OT(gpf5-4, NONE, FAST_SR1); 1099 PIN_IN(gpf5-5, DOWN, FAST_SR1); 1100 PIN_IN(gpf5-6, DOWN, FAST_SR1); 1101 PIN_IN(gpf5-7, DOWN, FAST_SR1); 1102 }; 1103 1104 te_irq: te-irq-pins { 1105 samsung,pins = "gpf1-3"; 1106 samsung,pin-function = <0xf>; 1107 }; 1108}; 1109 1110&pinctrl_cpif { 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&initial_cpif>; 1113 1114 initial_cpif: initial-state { 1115 PIN_IN(gpv6-0, DOWN, FAST_SR1); 1116 PIN_IN(gpv6-1, DOWN, FAST_SR1); 1117 }; 1118}; 1119 1120&pinctrl_ese { 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&initial_ese>; 1123 1124 pcie_wlanen: pcie-wlanen-pins { 1125 samsung,pins = "gpj2-0"; 1126 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 1127 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 1128 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>; 1129 }; 1130 1131 initial_ese: initial-state { 1132 PIN_IN(gpj2-1, DOWN, FAST_SR1); 1133 PIN_IN(gpj2-2, DOWN, FAST_SR1); 1134 }; 1135}; 1136 1137&pinctrl_fsys { 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&initial_fsys>; 1140 1141 initial_fsys: initial-state { 1142 PIN_IN(gpr3-0, NONE, FAST_SR1); 1143 PIN_IN(gpr3-1, DOWN, FAST_SR1); 1144 PIN_IN(gpr3-2, DOWN, FAST_SR1); 1145 PIN_IN(gpr3-3, DOWN, FAST_SR1); 1146 PIN_IN(gpr3-7, NONE, FAST_SR1); 1147 }; 1148}; 1149 1150&pinctrl_imem { 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&initial_imem>; 1153 1154 initial_imem: initial-state { 1155 PIN_IN(gpf0-0, UP, FAST_SR1); 1156 PIN_IN(gpf0-1, UP, FAST_SR1); 1157 PIN_IN(gpf0-2, DOWN, FAST_SR1); 1158 PIN_IN(gpf0-3, UP, FAST_SR1); 1159 PIN_IN(gpf0-4, DOWN, FAST_SR1); 1160 PIN_IN(gpf0-5, NONE, FAST_SR1); 1161 PIN_IN(gpf0-6, DOWN, FAST_SR1); 1162 PIN_IN(gpf0-7, UP, FAST_SR1); 1163 }; 1164}; 1165 1166&pinctrl_nfc { 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&initial_nfc>; 1169 1170 initial_nfc: initial-state { 1171 PIN_IN(gpj0-2, DOWN, FAST_SR1); 1172 }; 1173}; 1174 1175&pinctrl_peric { 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&initial_peric>; 1178 1179 initial_peric: initial-state { 1180 PIN_IN(gpv7-0, DOWN, FAST_SR1); 1181 PIN_IN(gpv7-1, DOWN, FAST_SR1); 1182 PIN_IN(gpv7-2, NONE, FAST_SR1); 1183 PIN_IN(gpv7-3, DOWN, FAST_SR1); 1184 PIN_IN(gpv7-4, DOWN, FAST_SR1); 1185 PIN_IN(gpv7-5, DOWN, FAST_SR1); 1186 1187 PIN_IN(gpb0-4, DOWN, FAST_SR1); 1188 1189 PIN_IN(gpc0-2, DOWN, FAST_SR1); 1190 PIN_IN(gpc0-5, DOWN, FAST_SR1); 1191 PIN_IN(gpc0-7, DOWN, FAST_SR1); 1192 1193 PIN_IN(gpc1-1, DOWN, FAST_SR1); 1194 1195 PIN_IN(gpc3-4, NONE, FAST_SR1); 1196 PIN_IN(gpc3-5, NONE, FAST_SR1); 1197 PIN_IN(gpc3-6, NONE, FAST_SR1); 1198 PIN_IN(gpc3-7, NONE, FAST_SR1); 1199 1200 PIN_OT(gpg0-0, NONE, FAST_SR1); 1201 PIN_F2(gpg0-1, DOWN, FAST_SR1); 1202 1203 PIN_IN(gpd2-5, DOWN, FAST_SR1); 1204 1205 PIN_IN(gpd4-0, NONE, FAST_SR1); 1206 PIN_IN(gpd4-1, DOWN, FAST_SR1); 1207 PIN_IN(gpd4-2, DOWN, FAST_SR1); 1208 PIN_IN(gpd4-3, DOWN, FAST_SR1); 1209 PIN_IN(gpd4-4, DOWN, FAST_SR1); 1210 1211 PIN_IN(gpd6-3, DOWN, FAST_SR1); 1212 1213 PIN_IN(gpd8-1, UP, FAST_SR1); 1214 1215 PIN_IN(gpg1-0, DOWN, FAST_SR1); 1216 PIN_IN(gpg1-1, DOWN, FAST_SR1); 1217 PIN_IN(gpg1-2, DOWN, FAST_SR1); 1218 PIN_IN(gpg1-3, DOWN, FAST_SR1); 1219 PIN_IN(gpg1-4, DOWN, FAST_SR1); 1220 1221 PIN_IN(gpg2-0, DOWN, FAST_SR1); 1222 PIN_IN(gpg2-1, DOWN, FAST_SR1); 1223 1224 PIN_IN(gpg3-0, DOWN, FAST_SR1); 1225 PIN_IN(gpg3-1, DOWN, FAST_SR1); 1226 PIN_IN(gpg3-5, DOWN, FAST_SR1); 1227 }; 1228}; 1229 1230&pinctrl_touch { 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&initial_touch>; 1233 1234 initial_touch: initial-state { 1235 PIN_IN(gpj1-2, DOWN, FAST_SR1); 1236 }; 1237}; 1238 1239&pwm { 1240 pinctrl-0 = <&pwm0_out>; 1241 pinctrl-names = "default"; 1242 status = "okay"; 1243}; 1244 1245&mic { 1246 status = "okay"; 1247}; 1248 1249&pmu_system_controller { 1250 assigned-clocks = <&pmu_system_controller 0>; 1251 assigned-clock-parents = <&xxti>; 1252}; 1253 1254&serial_1 { 1255 status = "okay"; 1256}; 1257 1258&serial_3 { 1259 status = "okay"; 1260 1261 bluetooth { 1262 compatible = "brcm,bcm43438-bt"; 1263 max-speed = <3000000>; 1264 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>; 1265 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>; 1266 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>; 1267 clocks = <&s2mps13_osc S2MPS11_CLK_BT>; 1268 clock-names = "extclk"; 1269 }; 1270}; 1271 1272&spi_1 { 1273 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; 1274 status = "okay"; 1275 1276 wm5110: audio-codec@0 { 1277 compatible = "wlf,wm5110"; 1278 reg = <0x0>; 1279 spi-max-frequency = <20000000>; 1280 interrupt-parent = <&gpa0>; 1281 interrupts = <4 IRQ_TYPE_NONE>; 1282 clocks = <&pmu_system_controller 0>, 1283 <&s2mps13_osc S2MPS11_CLK_BT>; 1284 clock-names = "mclk1", "mclk2"; 1285 1286 gpio-controller; 1287 #gpio-cells = <2>; 1288 interrupt-controller; 1289 #interrupt-cells = <2>; 1290 1291 wlf,micd-detect-debounce = <300>; 1292 wlf,micd-bias-start-time = <0x1>; 1293 wlf,micd-rate = <0x7>; 1294 wlf,micd-dbtime = <0x2>; 1295 wlf,micd-force-micbias; 1296 wlf,micd-configs = <0x0 1 0>; 1297 wlf,hpdet-channel = <1>; 1298 wlf,gpsw = <0x1>; 1299 wlf,inmode = <2 0 2 0>; 1300 1301 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; 1302 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; 1303 1304 /* core supplies */ 1305 AVDD-supply = <&ldo18_reg>; 1306 DBVDD1-supply = <&ldo18_reg>; 1307 CPVDD-supply = <&ldo18_reg>; 1308 DBVDD2-supply = <&ldo18_reg>; 1309 DBVDD3-supply = <&ldo18_reg>; 1310 SPKVDDL-supply = <&vph_pwr_regulator>; 1311 SPKVDDR-supply = <&vph_pwr_regulator>; 1312 1313 controller-data { 1314 samsung,spi-feedback-delay = <0>; 1315 }; 1316 }; 1317}; 1318 1319&spi_3 { 1320 status = "okay"; 1321 no-cs-readback; 1322 1323 irled@0 { 1324 compatible = "ir-spi-led"; 1325 reg = <0x0>; 1326 spi-max-frequency = <5000000>; 1327 power-supply = <&irda_regulator>; 1328 duty-cycle = /bits/ 8 <60>; 1329 led-active-low; 1330 1331 controller-data { 1332 samsung,spi-feedback-delay = <0>; 1333 }; 1334 }; 1335}; 1336 1337&timer { 1338 clock-frequency = <24000000>; 1339}; 1340 1341&tmu_atlas0 { 1342 vtmu-supply = <&ldo3_reg>; 1343 status = "okay"; 1344}; 1345 1346&tmu_apollo { 1347 vtmu-supply = <&ldo3_reg>; 1348 status = "okay"; 1349}; 1350 1351&tmu_g3d { 1352 vtmu-supply = <&ldo3_reg>; 1353 status = "okay"; 1354}; 1355 1356&usbdrd30 { 1357 vdd33-supply = <&ldo10_reg>; 1358 vdd10-supply = <&ldo6_reg>; 1359 status = "okay"; 1360}; 1361 1362&usbdrd_dwc3 { 1363 dr_mode = "otg"; 1364}; 1365 1366&usbdrd30_phy { 1367 vbus-supply = <&safeout1_reg>; 1368 status = "okay"; 1369 1370 port { 1371 usb_to_muic: endpoint { 1372 remote-endpoint = <&muic_to_usb>; 1373 }; 1374 }; 1375}; 1376 1377&xxti { 1378 clock-frequency = <24000000>; 1379}; 1380