1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
4 //
5 // Copyright (c) 2006 Wolfson Microelectronics PLC.
6 // Graeme Gregory graeme.gregory@wolfsonmicro.com
7 // linux@wolfsonmicro.com
8 //
9 // Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 // http://armlinux.simtec.co.uk/
11 // Ben Dooks <ben@simtec.co.uk>
12
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 #include <linux/io.h>
17
18 #include <sound/soc.h>
19 #include <sound/pcm_params.h>
20
21 #include "regs-i2s-v2.h"
22 #include "s3c-i2s-v2.h"
23
24 #define S3C2412_I2S_DEBUG_CON 0
25
to_info(struct snd_soc_dai * cpu_dai)26 static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
27 {
28 return snd_soc_dai_get_drvdata(cpu_dai);
29 }
30
31 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
32
33 #if S3C2412_I2S_DEBUG_CON
dbg_showcon(const char * fn,u32 con)34 static void dbg_showcon(const char *fn, u32 con)
35 {
36 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
37 bit_set(con, S3C2412_IISCON_LRINDEX),
38 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
39 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
40 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
41 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
42
43 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
44 fn,
45 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
46 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
47 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
48 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
49 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
50 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
51 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
52 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
53 }
54 #else
dbg_showcon(const char * fn,u32 con)55 static inline void dbg_showcon(const char *fn, u32 con)
56 {
57 }
58 #endif
59
60 /* Turn on or off the transmission path. */
s3c2412_snd_txctrl(struct s3c_i2sv2_info * i2s,int on)61 static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
62 {
63 void __iomem *regs = i2s->regs;
64 u32 fic, con, mod;
65
66 pr_debug("%s(%d)\n", __func__, on);
67
68 fic = readl(regs + S3C2412_IISFIC);
69 con = readl(regs + S3C2412_IISCON);
70 mod = readl(regs + S3C2412_IISMOD);
71
72 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
73
74 if (on) {
75 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
76 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
77 con &= ~S3C2412_IISCON_TXCH_PAUSE;
78
79 switch (mod & S3C2412_IISMOD_MODE_MASK) {
80 case S3C2412_IISMOD_MODE_TXONLY:
81 case S3C2412_IISMOD_MODE_TXRX:
82 /* do nothing, we are in the right mode */
83 break;
84
85 case S3C2412_IISMOD_MODE_RXONLY:
86 mod &= ~S3C2412_IISMOD_MODE_MASK;
87 mod |= S3C2412_IISMOD_MODE_TXRX;
88 break;
89
90 default:
91 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
92 mod & S3C2412_IISMOD_MODE_MASK);
93 break;
94 }
95
96 writel(con, regs + S3C2412_IISCON);
97 writel(mod, regs + S3C2412_IISMOD);
98 } else {
99 /* Note, we do not have any indication that the FIFO problems
100 * tha the S3C2410/2440 had apply here, so we should be able
101 * to disable the DMA and TX without resetting the FIFOS.
102 */
103
104 con |= S3C2412_IISCON_TXDMA_PAUSE;
105 con |= S3C2412_IISCON_TXCH_PAUSE;
106 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
107
108 switch (mod & S3C2412_IISMOD_MODE_MASK) {
109 case S3C2412_IISMOD_MODE_TXRX:
110 mod &= ~S3C2412_IISMOD_MODE_MASK;
111 mod |= S3C2412_IISMOD_MODE_RXONLY;
112 break;
113
114 case S3C2412_IISMOD_MODE_TXONLY:
115 mod &= ~S3C2412_IISMOD_MODE_MASK;
116 con &= ~S3C2412_IISCON_IIS_ACTIVE;
117 break;
118
119 default:
120 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
121 mod & S3C2412_IISMOD_MODE_MASK);
122 break;
123 }
124
125 writel(mod, regs + S3C2412_IISMOD);
126 writel(con, regs + S3C2412_IISCON);
127 }
128
129 fic = readl(regs + S3C2412_IISFIC);
130 dbg_showcon(__func__, con);
131 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
132 }
133
s3c2412_snd_rxctrl(struct s3c_i2sv2_info * i2s,int on)134 static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
135 {
136 void __iomem *regs = i2s->regs;
137 u32 fic, con, mod;
138
139 pr_debug("%s(%d)\n", __func__, on);
140
141 fic = readl(regs + S3C2412_IISFIC);
142 con = readl(regs + S3C2412_IISCON);
143 mod = readl(regs + S3C2412_IISMOD);
144
145 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
146
147 if (on) {
148 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
149 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
150 con &= ~S3C2412_IISCON_RXCH_PAUSE;
151
152 switch (mod & S3C2412_IISMOD_MODE_MASK) {
153 case S3C2412_IISMOD_MODE_TXRX:
154 case S3C2412_IISMOD_MODE_RXONLY:
155 /* do nothing, we are in the right mode */
156 break;
157
158 case S3C2412_IISMOD_MODE_TXONLY:
159 mod &= ~S3C2412_IISMOD_MODE_MASK;
160 mod |= S3C2412_IISMOD_MODE_TXRX;
161 break;
162
163 default:
164 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
165 mod & S3C2412_IISMOD_MODE_MASK);
166 }
167
168 writel(mod, regs + S3C2412_IISMOD);
169 writel(con, regs + S3C2412_IISCON);
170 } else {
171 /* See txctrl notes on FIFOs. */
172
173 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
174 con |= S3C2412_IISCON_RXDMA_PAUSE;
175 con |= S3C2412_IISCON_RXCH_PAUSE;
176
177 switch (mod & S3C2412_IISMOD_MODE_MASK) {
178 case S3C2412_IISMOD_MODE_RXONLY:
179 con &= ~S3C2412_IISCON_IIS_ACTIVE;
180 mod &= ~S3C2412_IISMOD_MODE_MASK;
181 break;
182
183 case S3C2412_IISMOD_MODE_TXRX:
184 mod &= ~S3C2412_IISMOD_MODE_MASK;
185 mod |= S3C2412_IISMOD_MODE_TXONLY;
186 break;
187
188 default:
189 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
190 mod & S3C2412_IISMOD_MODE_MASK);
191 }
192
193 writel(con, regs + S3C2412_IISCON);
194 writel(mod, regs + S3C2412_IISMOD);
195 }
196
197 fic = readl(regs + S3C2412_IISFIC);
198 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
199 }
200
201 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
202
203 /*
204 * Wait for the LR signal to allow synchronisation to the L/R clock
205 * from the codec. May only be needed for slave mode.
206 */
s3c2412_snd_lrsync(struct s3c_i2sv2_info * i2s)207 static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
208 {
209 u32 iiscon;
210 unsigned long loops = msecs_to_loops(5);
211
212 pr_debug("Entered %s\n", __func__);
213
214 while (--loops) {
215 iiscon = readl(i2s->regs + S3C2412_IISCON);
216 if (iiscon & S3C2412_IISCON_LRINDEX)
217 break;
218
219 cpu_relax();
220 }
221
222 if (!loops) {
223 printk(KERN_ERR "%s: timeout\n", __func__);
224 return -ETIMEDOUT;
225 }
226
227 return 0;
228 }
229
230 /*
231 * Set S3C2412 I2S DAI format
232 */
s3c2412_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)233 static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
234 unsigned int fmt)
235 {
236 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
237 u32 iismod;
238
239 pr_debug("Entered %s\n", __func__);
240
241 iismod = readl(i2s->regs + S3C2412_IISMOD);
242 pr_debug("hw_params r: IISMOD: %x \n", iismod);
243
244 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
245 case SND_SOC_DAIFMT_BC_FC:
246 i2s->master = 0;
247 iismod |= S3C2412_IISMOD_SLAVE;
248 break;
249 case SND_SOC_DAIFMT_BP_FP:
250 i2s->master = 1;
251 iismod &= ~S3C2412_IISMOD_SLAVE;
252 break;
253 default:
254 pr_err("unknown master/slave format\n");
255 return -EINVAL;
256 }
257
258 iismod &= ~S3C2412_IISMOD_SDF_MASK;
259
260 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
261 case SND_SOC_DAIFMT_RIGHT_J:
262 iismod |= S3C2412_IISMOD_LR_RLOW;
263 iismod |= S3C2412_IISMOD_SDF_MSB;
264 break;
265 case SND_SOC_DAIFMT_LEFT_J:
266 iismod |= S3C2412_IISMOD_LR_RLOW;
267 iismod |= S3C2412_IISMOD_SDF_LSB;
268 break;
269 case SND_SOC_DAIFMT_I2S:
270 iismod &= ~S3C2412_IISMOD_LR_RLOW;
271 iismod |= S3C2412_IISMOD_SDF_IIS;
272 break;
273 default:
274 pr_err("Unknown data format\n");
275 return -EINVAL;
276 }
277
278 writel(iismod, i2s->regs + S3C2412_IISMOD);
279 pr_debug("hw_params w: IISMOD: %x \n", iismod);
280 return 0;
281 }
282
s3c_i2sv2_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)283 static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
284 struct snd_pcm_hw_params *params,
285 struct snd_soc_dai *dai)
286 {
287 struct s3c_i2sv2_info *i2s = to_info(dai);
288 struct snd_dmaengine_dai_dma_data *dma_data;
289 u32 iismod;
290
291 pr_debug("Entered %s\n", __func__);
292
293 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
294 dma_data = i2s->dma_playback;
295 else
296 dma_data = i2s->dma_capture;
297
298 snd_soc_dai_set_dma_data(dai, substream, dma_data);
299
300 /* Working copies of register */
301 iismod = readl(i2s->regs + S3C2412_IISMOD);
302 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
303
304 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
305 /* Sample size */
306 switch (params_width(params)) {
307 case 8:
308 iismod |= S3C64XX_IISMOD_BLC_8BIT;
309 break;
310 case 16:
311 break;
312 case 24:
313 iismod |= S3C64XX_IISMOD_BLC_24BIT;
314 break;
315 }
316
317 writel(iismod, i2s->regs + S3C2412_IISMOD);
318 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
319
320 return 0;
321 }
322
s3c_i2sv2_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)323 static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
324 int clk_id, unsigned int freq, int dir)
325 {
326 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
327 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
328
329 pr_debug("Entered %s\n", __func__);
330 pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
331
332 switch (clk_id) {
333 case S3C_I2SV2_CLKSRC_PCLK:
334 iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
335 break;
336
337 case S3C_I2SV2_CLKSRC_AUDIOBUS:
338 iismod |= S3C2412_IISMOD_IMS_SYSMUX;
339 break;
340
341 case S3C_I2SV2_CLKSRC_CDCLK:
342 /* Error if controller doesn't have the CDCLKCON bit */
343 if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
344 return -EINVAL;
345
346 switch (dir) {
347 case SND_SOC_CLOCK_IN:
348 iismod |= S3C64XX_IISMOD_CDCLKCON;
349 break;
350 case SND_SOC_CLOCK_OUT:
351 iismod &= ~S3C64XX_IISMOD_CDCLKCON;
352 break;
353 default:
354 return -EINVAL;
355 }
356 break;
357
358 default:
359 return -EINVAL;
360 }
361
362 writel(iismod, i2s->regs + S3C2412_IISMOD);
363 pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
364
365 return 0;
366 }
367
s3c2412_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)368 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
369 struct snd_soc_dai *dai)
370 {
371 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
372 struct s3c_i2sv2_info *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
373 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
374 unsigned long irqs;
375 int ret = 0;
376
377 pr_debug("Entered %s\n", __func__);
378
379 switch (cmd) {
380 case SNDRV_PCM_TRIGGER_START:
381 /* On start, ensure that the FIFOs are cleared and reset. */
382
383 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
384 i2s->regs + S3C2412_IISFIC);
385
386 /* clear again, just in case */
387 writel(0x0, i2s->regs + S3C2412_IISFIC);
388
389 fallthrough;
390
391 case SNDRV_PCM_TRIGGER_RESUME:
392 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
393 if (!i2s->master) {
394 ret = s3c2412_snd_lrsync(i2s);
395 if (ret)
396 goto exit_err;
397 }
398
399 local_irq_save(irqs);
400
401 if (capture)
402 s3c2412_snd_rxctrl(i2s, 1);
403 else
404 s3c2412_snd_txctrl(i2s, 1);
405
406 local_irq_restore(irqs);
407
408 break;
409
410 case SNDRV_PCM_TRIGGER_STOP:
411 case SNDRV_PCM_TRIGGER_SUSPEND:
412 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
413 local_irq_save(irqs);
414
415 if (capture)
416 s3c2412_snd_rxctrl(i2s, 0);
417 else
418 s3c2412_snd_txctrl(i2s, 0);
419
420 local_irq_restore(irqs);
421 break;
422 default:
423 ret = -EINVAL;
424 break;
425 }
426
427 exit_err:
428 return ret;
429 }
430
431 /*
432 * Set S3C2412 Clock dividers
433 */
s3c2412_i2s_set_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)434 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
435 int div_id, int div)
436 {
437 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
438 u32 reg;
439
440 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
441
442 switch (div_id) {
443 case S3C_I2SV2_DIV_BCLK:
444 switch (div) {
445 case 16:
446 div = S3C2412_IISMOD_BCLK_16FS;
447 break;
448
449 case 32:
450 div = S3C2412_IISMOD_BCLK_32FS;
451 break;
452
453 case 24:
454 div = S3C2412_IISMOD_BCLK_24FS;
455 break;
456
457 case 48:
458 div = S3C2412_IISMOD_BCLK_48FS;
459 break;
460
461 default:
462 return -EINVAL;
463 }
464
465 reg = readl(i2s->regs + S3C2412_IISMOD);
466 reg &= ~S3C2412_IISMOD_BCLK_MASK;
467 writel(reg | div, i2s->regs + S3C2412_IISMOD);
468
469 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
470 break;
471
472 case S3C_I2SV2_DIV_RCLK:
473 switch (div) {
474 case 256:
475 div = S3C2412_IISMOD_RCLK_256FS;
476 break;
477
478 case 384:
479 div = S3C2412_IISMOD_RCLK_384FS;
480 break;
481
482 case 512:
483 div = S3C2412_IISMOD_RCLK_512FS;
484 break;
485
486 case 768:
487 div = S3C2412_IISMOD_RCLK_768FS;
488 break;
489
490 default:
491 return -EINVAL;
492 }
493
494 reg = readl(i2s->regs + S3C2412_IISMOD);
495 reg &= ~S3C2412_IISMOD_RCLK_MASK;
496 writel(reg | div, i2s->regs + S3C2412_IISMOD);
497 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
498 break;
499
500 case S3C_I2SV2_DIV_PRESCALER:
501 if (div >= 0) {
502 writel((div << 8) | S3C2412_IISPSR_PSREN,
503 i2s->regs + S3C2412_IISPSR);
504 } else {
505 writel(0x0, i2s->regs + S3C2412_IISPSR);
506 }
507 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
508 break;
509
510 default:
511 return -EINVAL;
512 }
513
514 return 0;
515 }
516
s3c2412_i2s_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)517 static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
518 struct snd_soc_dai *dai)
519 {
520 struct s3c_i2sv2_info *i2s = to_info(dai);
521 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
522 snd_pcm_sframes_t delay;
523
524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
525 delay = S3C2412_IISFIC_TXCOUNT(reg);
526 else
527 delay = S3C2412_IISFIC_RXCOUNT(reg);
528
529 return delay;
530 }
531
s3c_i2sv2_get_clock(struct snd_soc_dai * cpu_dai)532 struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
533 {
534 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
535 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
536
537 if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
538 return i2s->iis_cclk;
539 else
540 return i2s->iis_pclk;
541 }
542 EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
543
544 /* default table of all avaialable root fs divisors */
545 static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
546
s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc * info,unsigned int * fstab,unsigned int rate,struct clk * clk)547 int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
548 unsigned int *fstab,
549 unsigned int rate, struct clk *clk)
550 {
551 unsigned long clkrate = clk_get_rate(clk);
552 unsigned int div;
553 unsigned int fsclk;
554 unsigned int actual;
555 unsigned int fs;
556 unsigned int fsdiv;
557 signed int deviation = 0;
558 unsigned int best_fs = 0;
559 unsigned int best_div = 0;
560 unsigned int best_rate = 0;
561 unsigned int best_deviation = INT_MAX;
562
563 pr_debug("Input clock rate %ldHz\n", clkrate);
564
565 if (fstab == NULL)
566 fstab = iis_fs_tab;
567
568 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
569 fsdiv = iis_fs_tab[fs];
570
571 fsclk = clkrate / fsdiv;
572 div = fsclk / rate;
573
574 if ((fsclk % rate) > (rate / 2))
575 div++;
576
577 if (div <= 1)
578 continue;
579
580 actual = clkrate / (fsdiv * div);
581 deviation = actual - rate;
582
583 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
584 fsdiv, div, actual, deviation);
585
586 deviation = abs(deviation);
587
588 if (deviation < best_deviation) {
589 best_fs = fsdiv;
590 best_div = div;
591 best_rate = actual;
592 best_deviation = deviation;
593 }
594
595 if (deviation == 0)
596 break;
597 }
598
599 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
600 best_fs, best_div, best_rate);
601
602 info->fs_div = best_fs;
603 info->clk_div = best_div;
604
605 return 0;
606 }
607 EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
608
s3c_i2sv2_probe(struct snd_soc_dai * dai,struct s3c_i2sv2_info * i2s)609 int s3c_i2sv2_probe(struct snd_soc_dai *dai,
610 struct s3c_i2sv2_info *i2s)
611 {
612 struct device *dev = dai->dev;
613 unsigned int iismod;
614
615 i2s->dev = dev;
616
617 /* record our i2s structure for later use in the callbacks */
618 snd_soc_dai_set_drvdata(dai, i2s);
619
620 i2s->iis_pclk = clk_get(dev, "iis");
621 if (IS_ERR(i2s->iis_pclk)) {
622 dev_err(dev, "failed to get iis_clock\n");
623 return -ENOENT;
624 }
625
626 clk_prepare_enable(i2s->iis_pclk);
627
628 /* Mark ourselves as in TXRX mode so we can run through our cleanup
629 * process without warnings. */
630 iismod = readl(i2s->regs + S3C2412_IISMOD);
631 iismod |= S3C2412_IISMOD_MODE_TXRX;
632 writel(iismod, i2s->regs + S3C2412_IISMOD);
633 s3c2412_snd_txctrl(i2s, 0);
634 s3c2412_snd_rxctrl(i2s, 0);
635
636 return 0;
637 }
638 EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
639
s3c_i2sv2_cleanup(struct snd_soc_dai * dai,struct s3c_i2sv2_info * i2s)640 void s3c_i2sv2_cleanup(struct snd_soc_dai *dai,
641 struct s3c_i2sv2_info *i2s)
642 {
643 clk_disable_unprepare(i2s->iis_pclk);
644 clk_put(i2s->iis_pclk);
645 i2s->iis_pclk = NULL;
646 }
647 EXPORT_SYMBOL_GPL(s3c_i2sv2_cleanup);
648
s3c_i2sv2_register_component(struct device * dev,int id,const struct snd_soc_component_driver * cmp_drv,struct snd_soc_dai_driver * dai_drv)649 int s3c_i2sv2_register_component(struct device *dev, int id,
650 const struct snd_soc_component_driver *cmp_drv,
651 struct snd_soc_dai_driver *dai_drv)
652 {
653 struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops;
654
655 ops->trigger = s3c2412_i2s_trigger;
656 if (!ops->hw_params)
657 ops->hw_params = s3c_i2sv2_hw_params;
658 ops->set_fmt = s3c2412_i2s_set_fmt;
659 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
660 ops->set_sysclk = s3c_i2sv2_set_sysclk;
661
662 /* Allow overriding by (for example) IISv4 */
663 if (!ops->delay)
664 ops->delay = s3c2412_i2s_delay;
665
666 return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
667 }
668 EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
669
670 MODULE_LICENSE("GPL");
671