1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 //		http://www.samsung.com
5 //
6 // Copyright 2008 Openmoko, Inc.
7 // Copyright 2008 Simtec Electronics
8 //	Ben Dooks <ben@simtec.co.uk>
9 //	http://armlinux.simtec.co.uk/
10 //
11 // Common Codes for S3C64XX machines
12 
13 /*
14  * NOTE: Code in this file is not used when booting with Device Tree support.
15  */
16 
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial_s3c.h>
24 #include <linux/platform_device.h>
25 #include <linux/reboot.h>
26 #include <linux/io.h>
27 #include <linux/clk/samsung.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/irq.h>
30 #include <linux/gpio.h>
31 #include <linux/irqchip/arm-vic.h>
32 #include <clocksource/samsung_pwm.h>
33 
34 #include <asm/mach/arch.h>
35 #include <asm/mach/map.h>
36 #include <asm/system_misc.h>
37 
38 #include "map.h"
39 #include "irqs.h"
40 #include "regs-gpio.h"
41 #include "gpio-samsung.h"
42 
43 #include "cpu.h"
44 #include "devs.h"
45 #include "pm.h"
46 #include "gpio-cfg.h"
47 #include "pwm-core.h"
48 #include "regs-irqtype.h"
49 #include "s3c64xx.h"
50 #include "irq-uart-s3c64xx.h"
51 
52 /* External clock frequency */
53 static unsigned long xtal_f __ro_after_init = 12000000;
54 static unsigned long xusbxti_f __ro_after_init = 48000000;
55 
s3c64xx_set_xtal_freq(unsigned long freq)56 void __init s3c64xx_set_xtal_freq(unsigned long freq)
57 {
58 	xtal_f = freq;
59 }
60 
s3c64xx_set_xusbxti_freq(unsigned long freq)61 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
62 {
63 	xusbxti_f = freq;
64 }
65 
66 /* uart registration process */
67 
s3c64xx_init_uarts(struct s3c2410_uartcfg * cfg,int no)68 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
69 {
70 	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
71 }
72 
73 /* table of supported CPUs */
74 
75 static const char name_s3c6400[] = "S3C6400";
76 static const char name_s3c6410[] = "S3C6410";
77 
78 static struct cpu_table cpu_ids[] __initdata = {
79 	{
80 		.idcode		= S3C6400_CPU_ID,
81 		.idmask		= S3C64XX_CPU_MASK,
82 		.map_io		= s3c6400_map_io,
83 		.init_uarts	= s3c64xx_init_uarts,
84 		.init		= s3c6400_init,
85 		.name		= name_s3c6400,
86 	}, {
87 		.idcode		= S3C6410_CPU_ID,
88 		.idmask		= S3C64XX_CPU_MASK,
89 		.map_io		= s3c6410_map_io,
90 		.init_uarts	= s3c64xx_init_uarts,
91 		.init		= s3c6410_init,
92 		.name		= name_s3c6410,
93 	},
94 };
95 
96 /* minimal IO mapping */
97 
98 /*
99  * note, for the boot process to work we have to keep the UART
100  * virtual address aligned to an 1MiB boundary for the L1
101  * mapping the head code makes. We keep the UART virtual address
102  * aligned and add in the offset when we load the value here.
103  */
104 #define UART_OFFS (S3C_PA_UART & 0xfffff)
105 
106 static struct map_desc s3c_iodesc[] __initdata = {
107 	{
108 		.virtual	= (unsigned long)S3C_VA_SYS,
109 		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
110 		.length		= SZ_4K,
111 		.type		= MT_DEVICE,
112 	}, {
113 		.virtual	= (unsigned long)S3C_VA_MEM,
114 		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
115 		.length		= SZ_4K,
116 		.type		= MT_DEVICE,
117 	}, {
118 		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
119 		.pfn		= __phys_to_pfn(S3C_PA_UART),
120 		.length		= SZ_4K,
121 		.type		= MT_DEVICE,
122 	}, {
123 		.virtual	= (unsigned long)VA_VIC0,
124 		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
125 		.length		= SZ_16K,
126 		.type		= MT_DEVICE,
127 	}, {
128 		.virtual	= (unsigned long)VA_VIC1,
129 		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
130 		.length		= SZ_16K,
131 		.type		= MT_DEVICE,
132 	}, {
133 		.virtual	= (unsigned long)S3C_VA_TIMER,
134 		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
135 		.length		= SZ_16K,
136 		.type		= MT_DEVICE,
137 	}, {
138 		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
139 		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
140 		.length		= SZ_4K,
141 		.type		= MT_DEVICE,
142 	}, {
143 		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
144 		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
145 		.length		= SZ_4K,
146 		.type		= MT_DEVICE,
147 	}, {
148 		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
149 		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
150 		.length		= SZ_4K,
151 		.type		= MT_DEVICE,
152 	}, {
153 		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
154 		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
155 		.length		= SZ_1K,
156 		.type		= MT_DEVICE,
157 	},
158 };
159 
160 static struct bus_type s3c64xx_subsys = {
161 	.name		= "s3c64xx-core",
162 	.dev_name	= "s3c64xx-core",
163 };
164 
165 static struct device s3c64xx_dev = {
166 	.bus	= &s3c64xx_subsys,
167 };
168 
169 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
170 	.bits		= 32,
171 	.div_base	= 0,
172 	.has_tint_cstat	= true,
173 	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
174 };
175 
s3c64xx_set_timer_source(unsigned int event,unsigned int source)176 void __init s3c64xx_set_timer_source(unsigned int event, unsigned int source)
177 {
178 	s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
179 	s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
180 }
181 
s3c64xx_timer_init(void)182 void __init s3c64xx_timer_init(void)
183 {
184 	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
185 		IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
186 		IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
187 	};
188 
189 	samsung_pwm_clocksource_init(S3C_VA_TIMER,
190 					timer_irqs, &s3c64xx_pwm_variant);
191 }
192 
193 /* read cpu identification code */
194 
s3c64xx_init_io(struct map_desc * mach_desc,int size)195 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
196 {
197 	/* initialise the io descriptors we need for initialisation */
198 	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
199 	iotable_init(mach_desc, size);
200 
201 	/* detect cpu id */
202 	s3c64xx_init_cpu();
203 
204 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
205 
206 	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
207 }
208 
s3c64xx_dev_init(void)209 static __init int s3c64xx_dev_init(void)
210 {
211 	/* Not applicable when using DT. */
212 	if (of_have_populated_dt() || !soc_is_s3c64xx())
213 		return 0;
214 
215 	subsys_system_register(&s3c64xx_subsys, NULL);
216 	return device_register(&s3c64xx_dev);
217 }
218 core_initcall(s3c64xx_dev_init);
219 
220 /*
221  * setup the sources the vic should advertise resume
222  * for, even though it is not doing the wake
223  * (set_irq_wake needs to be valid)
224  */
225 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
226 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
227 			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
228 			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
229 			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
230 			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
231 
s3c64xx_init_irq(u32 vic0_valid,u32 vic1_valid)232 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
233 {
234 	s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
235 
236 	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
237 
238 	/* initialise the pair of VICs */
239 	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
240 	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
241 }
242 
243 #define eint_offset(irq)	((irq) - IRQ_EINT(0))
244 #define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))
245 
s3c_irq_eint_mask(struct irq_data * data)246 static inline void s3c_irq_eint_mask(struct irq_data *data)
247 {
248 	u32 mask;
249 
250 	mask = __raw_readl(S3C64XX_EINT0MASK);
251 	mask |= (u32)data->chip_data;
252 	__raw_writel(mask, S3C64XX_EINT0MASK);
253 }
254 
s3c_irq_eint_unmask(struct irq_data * data)255 static void s3c_irq_eint_unmask(struct irq_data *data)
256 {
257 	u32 mask;
258 
259 	mask = __raw_readl(S3C64XX_EINT0MASK);
260 	mask &= ~((u32)data->chip_data);
261 	__raw_writel(mask, S3C64XX_EINT0MASK);
262 }
263 
s3c_irq_eint_ack(struct irq_data * data)264 static inline void s3c_irq_eint_ack(struct irq_data *data)
265 {
266 	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
267 }
268 
s3c_irq_eint_maskack(struct irq_data * data)269 static void s3c_irq_eint_maskack(struct irq_data *data)
270 {
271 	/* compiler should in-line these */
272 	s3c_irq_eint_mask(data);
273 	s3c_irq_eint_ack(data);
274 }
275 
s3c_irq_eint_set_type(struct irq_data * data,unsigned int type)276 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
277 {
278 	int offs = eint_offset(data->irq);
279 	int pin, pin_val;
280 	int shift;
281 	u32 ctrl, mask;
282 	u32 newvalue = 0;
283 	void __iomem *reg;
284 
285 	if (offs > 27)
286 		return -EINVAL;
287 
288 	if (offs <= 15)
289 		reg = S3C64XX_EINT0CON0;
290 	else
291 		reg = S3C64XX_EINT0CON1;
292 
293 	switch (type) {
294 	case IRQ_TYPE_NONE:
295 		printk(KERN_WARNING "No edge setting!\n");
296 		break;
297 
298 	case IRQ_TYPE_EDGE_RISING:
299 		newvalue = S3C2410_EXTINT_RISEEDGE;
300 		break;
301 
302 	case IRQ_TYPE_EDGE_FALLING:
303 		newvalue = S3C2410_EXTINT_FALLEDGE;
304 		break;
305 
306 	case IRQ_TYPE_EDGE_BOTH:
307 		newvalue = S3C2410_EXTINT_BOTHEDGE;
308 		break;
309 
310 	case IRQ_TYPE_LEVEL_LOW:
311 		newvalue = S3C2410_EXTINT_LOWLEV;
312 		break;
313 
314 	case IRQ_TYPE_LEVEL_HIGH:
315 		newvalue = S3C2410_EXTINT_HILEV;
316 		break;
317 
318 	default:
319 		printk(KERN_ERR "No such irq type %d", type);
320 		return -1;
321 	}
322 
323 	if (offs <= 15)
324 		shift = (offs / 2) * 4;
325 	else
326 		shift = ((offs - 16) / 2) * 4;
327 	mask = 0x7 << shift;
328 
329 	ctrl = __raw_readl(reg);
330 	ctrl &= ~mask;
331 	ctrl |= newvalue << shift;
332 	__raw_writel(ctrl, reg);
333 
334 	/* set the GPIO pin appropriately */
335 
336 	if (offs < 16) {
337 		pin = S3C64XX_GPN(offs);
338 		pin_val = S3C_GPIO_SFN(2);
339 	} else if (offs < 23) {
340 		pin = S3C64XX_GPL(offs + 8 - 16);
341 		pin_val = S3C_GPIO_SFN(3);
342 	} else {
343 		pin = S3C64XX_GPM(offs - 23);
344 		pin_val = S3C_GPIO_SFN(3);
345 	}
346 
347 	s3c_gpio_cfgpin(pin, pin_val);
348 
349 	return 0;
350 }
351 
352 static struct irq_chip s3c_irq_eint = {
353 	.name		= "s3c-eint",
354 	.irq_mask	= s3c_irq_eint_mask,
355 	.irq_unmask	= s3c_irq_eint_unmask,
356 	.irq_mask_ack	= s3c_irq_eint_maskack,
357 	.irq_ack	= s3c_irq_eint_ack,
358 	.irq_set_type	= s3c_irq_eint_set_type,
359 	.irq_set_wake	= s3c_irqext_wake,
360 };
361 
362 /* s3c_irq_demux_eint
363  *
364  * This function demuxes the IRQ from the group0 external interrupts,
365  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
366  * the specific handlers s3c_irq_demux_eintX_Y.
367  */
s3c_irq_demux_eint(unsigned int start,unsigned int end)368 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
369 {
370 	u32 status = __raw_readl(S3C64XX_EINT0PEND);
371 	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
372 	unsigned int irq;
373 
374 	status &= ~mask;
375 	status >>= start;
376 	status &= (1 << (end - start + 1)) - 1;
377 
378 	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
379 		if (status & 1)
380 			generic_handle_irq(irq);
381 
382 		status >>= 1;
383 	}
384 }
385 
s3c_irq_demux_eint0_3(struct irq_desc * desc)386 static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
387 {
388 	s3c_irq_demux_eint(0, 3);
389 }
390 
s3c_irq_demux_eint4_11(struct irq_desc * desc)391 static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
392 {
393 	s3c_irq_demux_eint(4, 11);
394 }
395 
s3c_irq_demux_eint12_19(struct irq_desc * desc)396 static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
397 {
398 	s3c_irq_demux_eint(12, 19);
399 }
400 
s3c_irq_demux_eint20_27(struct irq_desc * desc)401 static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
402 {
403 	s3c_irq_demux_eint(20, 27);
404 }
405 
s3c64xx_init_irq_eint(void)406 static int __init s3c64xx_init_irq_eint(void)
407 {
408 	int irq;
409 
410 	/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
411 	if (of_have_populated_dt() || !soc_is_s3c64xx())
412 		return -ENODEV;
413 
414 	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
415 		irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
416 		irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
417 		irq_clear_status_flags(irq, IRQ_NOREQUEST);
418 	}
419 
420 	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
421 	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
422 	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
423 	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
424 
425 	return 0;
426 }
427 arch_initcall(s3c64xx_init_irq_eint);
428 
429 #ifndef CONFIG_COMPILE_TEST
430 #pragma message "The platform is deprecated and scheduled for removal. " \
431 		"Please reach to the maintainers of the platform " \
432 		"and linux-samsung-soc@vger.kernel.org if you still use it." \
433 		"Without such feedback, the platform will be removed after 2024."
434 #endif
435