1 /* 2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions. 3 * 4 * Author: Ivan Passos <ivan.passos@cyclades.com> 5 * 6 * Copyright: (c) 1999-2003 Cyclades Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 */ 14 15 #ifndef _PC300_H 16 #define _PC300_H 17 18 #ifndef __HDLC_H 19 #include <linux/hdlc.h> 20 #endif 21 22 #ifndef _HD64572_H 23 #include "hd64572.h" 24 #endif 25 #ifndef _FALC_LH_H 26 #include "pc300_falc-lh.h" 27 #endif 28 29 #ifndef CY_TYPES 30 #define CY_TYPES 31 #if defined(__alpha__) 32 typedef unsigned long ucdouble; /* 64 bits, unsigned */ 33 typedef unsigned int uclong; /* 32 bits, unsigned */ 34 #else 35 typedef unsigned long uclong; /* 32 bits, unsigned */ 36 #endif 37 typedef unsigned short ucshort; /* 16 bits, unsigned */ 38 typedef unsigned char ucchar; /* 8 bits, unsigned */ 39 #endif /* CY_TYPES */ 40 41 #define PC300_PROTO_MLPPP 1 42 43 #define PC300_KERNEL "2.4.x" /* Kernel supported by this driver */ 44 45 #define PC300_DEVNAME "hdlc" /* Dev. name base (for hdlc0, hdlc1, etc.) */ 46 #define PC300_MAXINDEX 100 /* Max dev. name index (the '0' in hdlc0) */ 47 48 #define PC300_MAXCARDS 4 /* Max number of cards per system */ 49 #define PC300_MAXCHAN 2 /* Number of channels per card */ 50 51 #define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */ 52 #define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ 53 #define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */ 54 #define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ 55 56 #define PC300_OSC_CLOCK 24576000 57 #define PC300_PCI_CLOCK 33000000 58 59 #define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */ 60 #define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */ 61 #define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */ 62 63 #define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */ 64 #define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */ 65 66 /* DMA Buffer Offsets */ 67 #define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \ 68 PC300_MAXCHAN * sizeof(pcsca_bd_t)) 69 #define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ) 70 71 /* DMA Descriptor Offsets */ 72 #define DMA_TX_BD_BASE 0x0000 73 #define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \ 74 BD_DEF_LEN) * sizeof(pcsca_bd_t))) 75 76 /* DMA Descriptor Macros */ 77 #define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \ 78 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t)) 79 #define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \ 80 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t)) 81 82 /* Macro to access the FALC registers (TE only) */ 83 #define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2)) 84 85 /*************************************** 86 * Memory access functions/macros * 87 * (required to support Alpha systems) * 88 ***************************************/ 89 #ifdef __KERNEL__ 90 #define cpc_writeb(port,val) {writeb((ucchar)(val),(ulong)(port)); mb();} 91 #define cpc_writew(port,val) {writew((ushort)(val),(ulong)(port)); mb();} 92 #define cpc_writel(port,val) {writel((uclong)(val),(ulong)(port)); mb();} 93 94 #define cpc_readb(port) readb(port) 95 #define cpc_readw(port) readw(port) 96 #define cpc_readl(port) readl(port) 97 98 #else /* __KERNEL__ */ 99 #define cpc_writeb(port,val) (*(volatile ucchar *)(port) = (ucchar)(val)) 100 #define cpc_writew(port,val) (*(volatile ucshort *)(port) = (ucshort)(val)) 101 #define cpc_writel(port,val) (*(volatile uclong *)(port) = (uclong)(val)) 102 103 #define cpc_readb(port) (*(volatile ucchar *)(port)) 104 #define cpc_readw(port) (*(volatile ucshort *)(port)) 105 #define cpc_readl(port) (*(volatile uclong *)(port)) 106 107 #endif /* __KERNEL__ */ 108 109 /****** Data Structures *****************************************************/ 110 111 /* 112 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime 113 * registers. This structure can be used to access the 9050 registers 114 * (memory mapped). 115 */ 116 struct RUNTIME_9050 { 117 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 118 uclong loc_rom_range; /* 10h : Local ROM Range */ 119 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 120 uclong loc_rom_base; /* 24h : Local ROM Base */ 121 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 122 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */ 123 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 124 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 125 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 126 }; 127 128 #define PLX_9050_LINT1_ENABLE 0x01 129 #define PLX_9050_LINT1_POL 0x02 130 #define PLX_9050_LINT1_STATUS 0x04 131 #define PLX_9050_LINT2_ENABLE 0x08 132 #define PLX_9050_LINT2_POL 0x10 133 #define PLX_9050_LINT2_STATUS 0x20 134 #define PLX_9050_INTR_ENABLE 0x40 135 #define PLX_9050_SW_INTR 0x80 136 137 /* Masks to access the init_ctrl PLX register */ 138 #define PC300_CLKSEL_MASK (0x00000004UL) 139 #define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3)) 140 #define PC300_CTYPE_MASK (0x00000800UL) 141 142 /* CPLD Registers (base addr = falcbase, TE only) */ 143 /* CPLD v. 0 */ 144 #define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */ 145 #define CPLD_REG2 0x144 /* Clock enable , LED control */ 146 /* CPLD v. 2 or higher */ 147 #define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */ 148 #define CPLD_V2_REG2 0x104 /* Clock enable , LED control */ 149 #define CPLD_ID_REG 0x108 /* CPLD version */ 150 151 /* CPLD Register bit description: for the FALC bits, they should always be 152 set based on the channel (use (bit<<(2*ch)) to access the correct bit for 153 that channel) */ 154 #define CPLD_REG1_FALC_RESET 0x01 155 #define CPLD_REG1_SCA_RESET 0x02 156 #define CPLD_REG1_GLOBAL_CLK 0x08 157 #define CPLD_REG1_FALC_DCD 0x10 158 #define CPLD_REG1_FALC_CTS 0x20 159 160 #define CPLD_REG2_FALC_TX_CLK 0x01 161 #define CPLD_REG2_FALC_RX_CLK 0x02 162 #define CPLD_REG2_FALC_LED1 0x10 163 #define CPLD_REG2_FALC_LED2 0x20 164 165 /* Structure with FALC-related fields (TE only) */ 166 #define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ 167 168 typedef struct falc { 169 ucchar sync; /* If true FALC is synchronized */ 170 ucchar active; /* if TRUE then already active */ 171 ucchar loop_active; /* if TRUE a line loopback UP was received */ 172 ucchar loop_gen; /* if TRUE a line loopback UP was issued */ 173 174 ucchar num_channels; 175 ucchar offset; /* 1 for T1, 0 for E1 */ 176 ucchar full_bandwidth; 177 178 ucchar xmb_cause; 179 ucchar multiframe_mode; 180 181 /* Statistics */ 182 ucshort pden; /* Pulse Density violation count */ 183 ucshort los; /* Loss of Signal count */ 184 ucshort losr; /* Loss of Signal recovery count */ 185 ucshort lfa; /* Loss of frame alignment count */ 186 ucshort farec; /* Frame Alignment Recovery count */ 187 ucshort lmfa; /* Loss of multiframe alignment count */ 188 ucshort ais; /* Remote Alarm indication Signal count */ 189 ucshort sec; /* One-second timer */ 190 ucshort es; /* Errored second */ 191 ucshort rai; /* remote alarm received */ 192 ucshort bec; 193 ucshort fec; 194 ucshort cvc; 195 ucshort cec; 196 ucshort ebc; 197 198 /* Status */ 199 ucchar red_alarm; 200 ucchar blue_alarm; 201 ucchar loss_fa; 202 ucchar yellow_alarm; 203 ucchar loss_mfa; 204 ucchar prbs; 205 } falc_t; 206 207 typedef struct falc_status { 208 ucchar sync; /* If true FALC is synchronized */ 209 ucchar red_alarm; 210 ucchar blue_alarm; 211 ucchar loss_fa; 212 ucchar yellow_alarm; 213 ucchar loss_mfa; 214 ucchar prbs; 215 } falc_status_t; 216 217 typedef struct rsv_x21_status { 218 ucchar dcd; 219 ucchar dsr; 220 ucchar cts; 221 ucchar rts; 222 ucchar dtr; 223 } rsv_x21_status_t; 224 225 typedef struct pc300stats { 226 int hw_type; 227 uclong line_on; 228 uclong line_off; 229 struct net_device_stats gen_stats; 230 falc_t te_stats; 231 } pc300stats_t; 232 233 typedef struct pc300status { 234 int hw_type; 235 rsv_x21_status_t gen_status; 236 falc_status_t te_status; 237 } pc300status_t; 238 239 typedef struct pc300loopback { 240 char loop_type; 241 char loop_on; 242 } pc300loopback_t; 243 244 typedef struct pc300patterntst { 245 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */ 246 ucshort num_errors; 247 } pc300patterntst_t; 248 249 typedef struct pc300dev { 250 void *if_ptr; /* General purpose pointer */ 251 struct pc300ch *chan; 252 ucchar trace_on; 253 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */ 254 uclong line_off; 255 #ifdef __KERNEL__ 256 char name[16]; 257 hdlc_device *hdlc; 258 259 void *private; 260 struct sk_buff *tx_skb; 261 union { /* This union has all the protocol-specific structures */ 262 struct ppp_device pppdev; 263 }ifu; 264 #ifdef CONFIG_PC300_MLPPP 265 void *cpc_tty; /* information to PC300 TTY driver */ 266 #endif 267 #endif /* __KERNEL__ */ 268 }pc300dev_t; 269 270 typedef struct pc300hw { 271 int type; /* RSV, X21, etc. */ 272 int bus; /* Bus (PCI, PMC, etc.) */ 273 int nchan; /* number of channels */ 274 int irq; /* interrupt request level */ 275 uclong clock; /* Board clock */ 276 ucchar cpld_id; /* CPLD ID (TE only) */ 277 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */ 278 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */ 279 ucshort gpioc_reg; /* PLX GPIOC reg */ 280 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */ 281 uclong iophys; /* PLX registers I/O base */ 282 uclong iosize; /* PLX registers I/O size */ 283 uclong plxphys; /* PLX registers MMIO base (physical) */ 284 uclong plxbase; /* PLX registers MMIO base (virtual) */ 285 uclong plxsize; /* PLX registers MMIO size */ 286 uclong scaphys; /* SCA registers MMIO base (physical) */ 287 uclong scabase; /* SCA registers MMIO base (virtual) */ 288 uclong scasize; /* SCA registers MMIO size */ 289 uclong ramphys; /* On-board RAM MMIO base (physical) */ 290 uclong rambase; /* On-board RAM MMIO base (virtual) */ 291 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */ 292 uclong ramsize; /* On-board RAM MMIO size */ 293 uclong falcphys; /* FALC registers MMIO base (physical) */ 294 uclong falcbase; /* FALC registers MMIO base (virtual) */ 295 uclong falcsize; /* FALC registers MMIO size */ 296 } pc300hw_t; 297 298 typedef struct pc300chconf { 299 sync_serial_settings phys_settings; /* Clock type/rate (in bps), 300 loopback mode */ 301 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */ 302 uclong media; /* HW media (RS232, V.35, etc.) */ 303 uclong proto; /* Protocol (PPP, X.25, etc.) */ 304 ucchar monitor; /* Monitor mode (0 = off, !0 = on) */ 305 306 /* TE-specific parameters */ 307 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */ 308 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */ 309 ucchar lbo; /* Line Build Out */ 310 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */ 311 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */ 312 } pc300chconf_t; 313 314 typedef struct pc300ch { 315 struct pc300 *card; 316 int channel; 317 pc300dev_t d; 318 pc300chconf_t conf; 319 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */ 320 ucchar tx_next_bd; /* Next free TX DMA block descriptor */ 321 ucchar rx_first_bd; /* First free RX DMA block descriptor */ 322 ucchar rx_last_bd; /* Last free RX DMA block descriptor */ 323 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */ 324 falc_t falc; /* FALC structure (TE only) */ 325 } pc300ch_t; 326 327 typedef struct pc300 { 328 pc300hw_t hw; /* hardware config. */ 329 pc300ch_t chan[PC300_MAXCHAN]; 330 #ifdef __KERNEL__ 331 spinlock_t card_lock; 332 #endif /* __KERNEL__ */ 333 } pc300_t; 334 335 typedef struct pc300conf { 336 pc300hw_t hw; 337 pc300chconf_t conf; 338 } pc300conf_t; 339 340 /* DEV ioctl() commands */ 341 #define N_SPPP_IOCTLS 2 342 343 enum pc300_ioctl_cmds { 344 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS), 345 SIOCGPC300CONF, 346 SIOCSPC300CONF, 347 SIOCGPC300STATUS, 348 SIOCGPC300FALCSTATUS, 349 SIOCGPC300UTILSTATS, 350 SIOCGPC300UTILSTATUS, 351 SIOCSPC300TRACE, 352 SIOCSPC300LOOPBACK, 353 SIOCSPC300PATTERNTEST, 354 }; 355 356 /* Loopback types - PC300/TE boards */ 357 enum pc300_loopback_cmds { 358 PC300LOCLOOP = 1, 359 PC300REMLOOP, 360 PC300PAYLOADLOOP, 361 PC300GENLOOPUP, 362 PC300GENLOOPDOWN, 363 }; 364 365 /* Control Constant Definitions */ 366 #define PC300_RSV 0x01 367 #define PC300_X21 0x02 368 #define PC300_TE 0x03 369 370 #define PC300_PCI 0x00 371 #define PC300_PMC 0x01 372 373 #define PC300_LC_AMI 0x01 374 #define PC300_LC_B8ZS 0x02 375 #define PC300_LC_NRZ 0x03 376 #define PC300_LC_HDB3 0x04 377 378 /* Framing (T1) */ 379 #define PC300_FR_ESF 0x01 380 #define PC300_FR_D4 0x02 381 #define PC300_FR_ESF_JAPAN 0x03 382 383 /* Framing (E1) */ 384 #define PC300_FR_MF_CRC4 0x04 385 #define PC300_FR_MF_NON_CRC4 0x05 386 #define PC300_FR_UNFRAMED 0x06 387 388 #define PC300_LBO_0_DB 0x00 389 #define PC300_LBO_7_5_DB 0x01 390 #define PC300_LBO_15_DB 0x02 391 #define PC300_LBO_22_5_DB 0x03 392 393 #define PC300_RX_SENS_SH 0x01 394 #define PC300_RX_SENS_LH 0x02 395 396 #define PC300_TX_TIMEOUT (2*HZ) 397 #define PC300_TX_QUEUE_LEN 100 398 #define PC300_DEF_MTU 1600 399 400 #ifdef __KERNEL__ 401 /* Function Prototypes */ 402 int dma_buf_write(pc300_t *, int, ucchar *, int); 403 int dma_buf_read(pc300_t *, int, struct sk_buff *); 404 void tx_dma_start(pc300_t *, int); 405 void rx_dma_start(pc300_t *, int); 406 void tx_dma_stop(pc300_t *, int); 407 void rx_dma_stop(pc300_t *, int); 408 int cpc_queue_xmit(struct sk_buff *, struct net_device *); 409 void cpc_net_rx(hdlc_device *); 410 void cpc_sca_status(pc300_t *, int); 411 int cpc_change_mtu(struct net_device *, int); 412 int cpc_ioctl(struct net_device *, struct ifreq *, int); 413 int ch_config(pc300dev_t *); 414 int rx_config(pc300dev_t *); 415 int tx_config(pc300dev_t *); 416 void cpc_opench(pc300dev_t *); 417 void cpc_closech(pc300dev_t *); 418 int cpc_open(struct net_device *dev); 419 int cpc_close(struct net_device *dev); 420 int cpc_set_media(hdlc_device *, int); 421 #endif /* __KERNEL__ */ 422 423 #endif /* _PC300_H */ 424 425