1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * UFS Host Controller driver for Exynos specific extensions
4  *
5  * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6  *
7  */
8 
9 #ifndef _UFS_EXYNOS_H_
10 #define _UFS_EXYNOS_H_
11 
12 /*
13  * UNIPRO registers
14  */
15 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE		0x150
16 
17 /*
18  * MIBs for PA debug registers
19  */
20 #define PA_DBG_CLK_PERIOD	0x9514
21 #define PA_DBG_TXPHY_CFGUPDT	0x9518
22 #define PA_DBG_RXPHY_CFGUPDT	0x9519
23 #define PA_DBG_MODE		0x9529
24 #define PA_DBG_SKIP_RESET_PHY	0x9539
25 #define PA_DBG_OV_TM		0x9540
26 #define PA_DBG_SKIP_LINE_RESET	0x9541
27 #define PA_DBG_LINE_RESET_REQ	0x9543
28 #define PA_DBG_OPTION_SUITE	0x9564
29 #define PA_DBG_OPTION_SUITE_DYN	0x9565
30 
31 /*
32  * MIBs for Transport Layer debug registers
33  */
34 #define T_DBG_SKIP_INIT_HIBERN8_EXIT	0xc001
35 
36 /*
37  * Exynos MPHY attributes
38  */
39 #define TX_LINERESET_N_VAL	0x0277
40 #define TX_LINERESET_N(v)	(((v) >> 10) & 0xFF)
41 #define TX_LINERESET_P_VAL	0x027D
42 #define TX_LINERESET_P(v)	(((v) >> 12) & 0xFF)
43 #define TX_OV_SLEEP_CNT_TIMER	0x028E
44 #define TX_OV_H8_ENTER_EN	(1 << 7)
45 #define TX_OV_SLEEP_CNT(v)	(((v) >> 5) & 0x7F)
46 #define TX_HIGH_Z_CNT_11_08	0x028C
47 #define TX_HIGH_Z_CNT_H(v)	(((v) >> 8) & 0xF)
48 #define TX_HIGH_Z_CNT_07_00	0x028D
49 #define TX_HIGH_Z_CNT_L(v)	((v) & 0xFF)
50 #define TX_BASE_NVAL_07_00	0x0293
51 #define TX_BASE_NVAL_L(v)	((v) & 0xFF)
52 #define TX_BASE_NVAL_15_08	0x0294
53 #define TX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
54 #define TX_GRAN_NVAL_07_00	0x0295
55 #define TX_GRAN_NVAL_L(v)	((v) & 0xFF)
56 #define TX_GRAN_NVAL_10_08	0x0296
57 #define TX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
58 
59 #define VND_TX_CLK_PRD		0xAA
60 #define VND_TX_CLK_PRD_EN	0xA9
61 #define VND_TX_LINERESET_PVALUE0	0xAD
62 #define VND_TX_LINERESET_PVALUE1	0xAC
63 #define VND_TX_LINERESET_PVALUE2	0xAB
64 
65 #define TX_LINE_RESET_TIME	3200
66 
67 #define VND_RX_CLK_PRD		0x12
68 #define VND_RX_CLK_PRD_EN	0x11
69 #define VND_RX_LINERESET_VALUE0	0x1D
70 #define VND_RX_LINERESET_VALUE1	0x1C
71 #define VND_RX_LINERESET_VALUE2	0x1B
72 
73 #define RX_LINE_RESET_TIME	1000
74 
75 #define RX_FILLER_ENABLE	0x0316
76 #define RX_FILLER_EN		(1 << 1)
77 #define RX_LINERESET_VAL	0x0317
78 #define RX_LINERESET(v)	(((v) >> 12) & 0xFF)
79 #define RX_LCC_IGNORE		0x0318
80 #define RX_SYNC_MASK_LENGTH	0x0321
81 #define RX_HIBERN8_WAIT_VAL_BIT_20_16	0x0331
82 #define RX_HIBERN8_WAIT_VAL_BIT_15_08	0x0332
83 #define RX_HIBERN8_WAIT_VAL_BIT_07_00	0x0333
84 #define RX_OV_SLEEP_CNT_TIMER	0x0340
85 #define RX_OV_SLEEP_CNT(v)	(((v) >> 6) & 0x1F)
86 #define RX_OV_STALL_CNT_TIMER	0x0341
87 #define RX_OV_STALL_CNT(v)	(((v) >> 4) & 0xFF)
88 #define RX_BASE_NVAL_07_00	0x0355
89 #define RX_BASE_NVAL_L(v)	((v) & 0xFF)
90 #define RX_BASE_NVAL_15_08	0x0354
91 #define RX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
92 #define RX_GRAN_NVAL_07_00	0x0353
93 #define RX_GRAN_NVAL_L(v)	((v) & 0xFF)
94 #define RX_GRAN_NVAL_10_08	0x0352
95 #define RX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
96 
97 #define CMN_PWM_CLK_CTRL	0x0402
98 #define PWM_CLK_CTRL_MASK	0x3
99 
100 #define IATOVAL_NSEC		20000	/* unit: ns */
101 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
102 
103 struct exynos_ufs;
104 
105 /* vendor specific pre-defined parameters */
106 #define SLOW 1
107 #define FAST 2
108 
109 #define RX_ADV_FINE_GRAN_SUP_EN	0x1
110 #define RX_ADV_FINE_GRAN_STEP_VAL	0x3
111 #define RX_ADV_MIN_ACTV_TIME_CAP	0x9
112 
113 #define PA_GRANULARITY_VAL	0x6
114 #define PA_TACTIVATE_VAL	0x3
115 #define PA_HIBERN8TIME_VAL	0x20
116 
117 #define PCLK_AVAIL_MIN	70000000
118 #define PCLK_AVAIL_MAX	167000000
119 
120 struct exynos_ufs_uic_attr {
121 	/* TX Attributes */
122 	unsigned int tx_trailingclks;
123 	unsigned int tx_dif_p_nsec;
124 	unsigned int tx_dif_n_nsec;
125 	unsigned int tx_high_z_cnt_nsec;
126 	unsigned int tx_base_unit_nsec;
127 	unsigned int tx_gran_unit_nsec;
128 	unsigned int tx_sleep_cnt;
129 	unsigned int tx_min_activatetime;
130 	/* RX Attributes */
131 	unsigned int rx_filler_enable;
132 	unsigned int rx_dif_p_nsec;
133 	unsigned int rx_hibern8_wait_nsec;
134 	unsigned int rx_base_unit_nsec;
135 	unsigned int rx_gran_unit_nsec;
136 	unsigned int rx_sleep_cnt;
137 	unsigned int rx_stall_cnt;
138 	unsigned int rx_hs_g1_sync_len_cap;
139 	unsigned int rx_hs_g2_sync_len_cap;
140 	unsigned int rx_hs_g3_sync_len_cap;
141 	unsigned int rx_hs_g1_prep_sync_len_cap;
142 	unsigned int rx_hs_g2_prep_sync_len_cap;
143 	unsigned int rx_hs_g3_prep_sync_len_cap;
144 	/* Common Attributes */
145 	unsigned int cmn_pwm_clk_ctrl;
146 	/* Internal Attributes */
147 	unsigned int pa_dbg_option_suite;
148 	/* Changeable Attributes */
149 	unsigned int rx_adv_fine_gran_sup_en;
150 	unsigned int rx_adv_fine_gran_step;
151 	unsigned int rx_min_actv_time_cap;
152 	unsigned int rx_hibern8_time_cap;
153 	unsigned int rx_adv_min_actv_time_cap;
154 	unsigned int rx_adv_hibern8_time_cap;
155 	unsigned int pa_granularity;
156 	unsigned int pa_tactivate;
157 	unsigned int pa_hibern8time;
158 };
159 
160 struct exynos_ufs_drv_data {
161 	const struct ufs_hba_variant_ops *vops;
162 	struct exynos_ufs_uic_attr *uic_attr;
163 	unsigned int quirks;
164 	unsigned int opts;
165 	/* SoC's specific operations */
166 	int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
167 	int (*pre_link)(struct exynos_ufs *ufs);
168 	int (*post_link)(struct exynos_ufs *ufs);
169 	int (*pre_pwr_change)(struct exynos_ufs *ufs,
170 				struct ufs_pa_layer_attr *pwr);
171 	int (*post_pwr_change)(struct exynos_ufs *ufs,
172 				struct ufs_pa_layer_attr *pwr);
173 	int (*pre_hce_enable)(struct exynos_ufs *ufs);
174 	int (*post_hce_enable)(struct exynos_ufs *ufs);
175 };
176 
177 struct ufs_phy_time_cfg {
178 	u32 tx_linereset_p;
179 	u32 tx_linereset_n;
180 	u32 tx_high_z_cnt;
181 	u32 tx_base_n_val;
182 	u32 tx_gran_n_val;
183 	u32 tx_sleep_cnt;
184 	u32 rx_linereset;
185 	u32 rx_hibern8_wait;
186 	u32 rx_base_n_val;
187 	u32 rx_gran_n_val;
188 	u32 rx_sleep_cnt;
189 	u32 rx_stall_cnt;
190 };
191 
192 struct exynos_ufs {
193 	struct ufs_hba *hba;
194 	struct phy *phy;
195 	void __iomem *reg_hci;
196 	void __iomem *reg_unipro;
197 	void __iomem *reg_ufsp;
198 	struct clk *clk_hci_core;
199 	struct clk *clk_unipro_main;
200 	struct clk *clk_apb;
201 	u32 pclk_rate;
202 	u32 pclk_div;
203 	u32 pclk_avail_min;
204 	u32 pclk_avail_max;
205 	unsigned long mclk_rate;
206 	int avail_ln_rx;
207 	int avail_ln_tx;
208 	int rx_sel_idx;
209 	struct ufs_pa_layer_attr dev_req_params;
210 	struct ufs_phy_time_cfg t_cfg;
211 	ktime_t entry_hibern8_t;
212 	const struct exynos_ufs_drv_data *drv_data;
213 	struct regmap *sysreg;
214 	u32 shareability_reg_offset;
215 
216 	u32 opts;
217 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
218 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB	BIT(1)
219 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
220 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
221 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
222 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
223 };
224 
225 #define for_each_ufs_rx_lane(ufs, i) \
226 	for (i = (ufs)->rx_sel_idx; \
227 		i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
228 #define for_each_ufs_tx_lane(ufs, i) \
229 	for (i = 0; i < (ufs)->avail_ln_tx; i++)
230 
231 #define EXYNOS_UFS_MMIO_FUNC(name)					  \
232 static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
233 {									  \
234 	writel(val, ufs->reg_##name + reg);				  \
235 }									  \
236 									  \
237 static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg)		  \
238 {									  \
239 	return readl(ufs->reg_##name + reg);				  \
240 }
241 
242 EXYNOS_UFS_MMIO_FUNC(hci);
243 EXYNOS_UFS_MMIO_FUNC(unipro);
244 EXYNOS_UFS_MMIO_FUNC(ufsp);
245 #undef EXYNOS_UFS_MMIO_FUNC
246 
247 long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
248 
exynos_ufs_enable_ov_tm(struct ufs_hba * hba)249 static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
250 {
251 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true);
252 }
253 
exynos_ufs_disable_ov_tm(struct ufs_hba * hba)254 static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
255 {
256 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false);
257 }
258 
exynos_ufs_enable_dbg_mode(struct ufs_hba * hba)259 static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
260 {
261 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true);
262 }
263 
exynos_ufs_disable_dbg_mode(struct ufs_hba * hba)264 static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
265 {
266 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false);
267 }
268 
269 #endif /* _UFS_EXYNOS_H_ */
270