1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef RVU_H
9 #define RVU_H
10 
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13 
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20 
21 /* PCI device IDs */
22 #define	PCI_DEVID_OCTEONTX2_RVU_AF		0xA065
23 #define	PCI_DEVID_OCTEONTX2_LBK			0xA061
24 
25 /* Subsystem Device ID */
26 #define PCI_SUBSYS_DEVID_96XX                  0xB200
27 #define PCI_SUBSYS_DEVID_CN10K_A	       0xB900
28 #define PCI_SUBSYS_DEVID_CNF10K_B              0xBC00
29 #define PCI_SUBSYS_DEVID_CN10K_B               0xBD00
30 
31 /* PCI BAR nos */
32 #define	PCI_AF_REG_BAR_NUM			0
33 #define	PCI_PF_REG_BAR_NUM			2
34 #define	PCI_MBOX_BAR_NUM			4
35 
36 #define NAME_SIZE				32
37 #define MAX_NIX_BLKS				2
38 #define MAX_CPT_BLKS				2
39 
40 /* PF_FUNC */
41 #define RVU_PFVF_PF_SHIFT	10
42 #define RVU_PFVF_PF_MASK	0x3F
43 #define RVU_PFVF_FUNC_SHIFT	0
44 #define RVU_PFVF_FUNC_MASK	0x3FF
45 
46 #ifdef CONFIG_DEBUG_FS
47 struct dump_ctx {
48 	int	lf;
49 	int	id;
50 	bool	all;
51 };
52 
53 struct cpt_ctx {
54 	int blkaddr;
55 	struct rvu *rvu;
56 };
57 
58 struct rvu_debugfs {
59 	struct dentry *root;
60 	struct dentry *cgx_root;
61 	struct dentry *cgx;
62 	struct dentry *lmac;
63 	struct dentry *npa;
64 	struct dentry *nix;
65 	struct dentry *npc;
66 	struct dentry *cpt;
67 	struct dentry *mcs_root;
68 	struct dentry *mcs;
69 	struct dentry *mcs_rx;
70 	struct dentry *mcs_tx;
71 	struct dump_ctx npa_aura_ctx;
72 	struct dump_ctx npa_pool_ctx;
73 	struct dump_ctx nix_cq_ctx;
74 	struct dump_ctx nix_rq_ctx;
75 	struct dump_ctx nix_sq_ctx;
76 	struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
77 	int npa_qsize_id;
78 	int nix_qsize_id;
79 };
80 #endif
81 
82 struct rvu_work {
83 	struct	work_struct work;
84 	struct	rvu *rvu;
85 	int num_msgs;
86 	int up_num_msgs;
87 };
88 
89 struct rsrc_bmap {
90 	unsigned long *bmap;	/* Pointer to resource bitmap */
91 	u16  max;		/* Max resource id or count */
92 };
93 
94 struct rvu_block {
95 	struct rsrc_bmap	lf;
96 	struct admin_queue	*aq; /* NIX/NPA AQ */
97 	u16  *fn_map; /* LF to pcifunc mapping */
98 	bool multislot;
99 	bool implemented;
100 	u8   addr;  /* RVU_BLOCK_ADDR_E */
101 	u8   type;  /* RVU_BLOCK_TYPE_E */
102 	u8   lfshift;
103 	u64  lookup_reg;
104 	u64  pf_lfcnt_reg;
105 	u64  vf_lfcnt_reg;
106 	u64  lfcfg_reg;
107 	u64  msixcfg_reg;
108 	u64  lfreset_reg;
109 	unsigned char name[NAME_SIZE];
110 	struct rvu *rvu;
111 };
112 
113 struct nix_mcast {
114 	struct qmem	*mce_ctx;
115 	struct qmem	*mcast_buf;
116 	int		replay_pkind;
117 	int		next_free_mce;
118 	struct mutex	mce_lock; /* Serialize MCE updates */
119 };
120 
121 struct nix_mce_list {
122 	struct hlist_head	head;
123 	int			count;
124 	int			max;
125 };
126 
127 /* layer metadata to uniquely identify a packet header field */
128 struct npc_layer_mdata {
129 	u8 lid;
130 	u8 ltype;
131 	u8 hdr;
132 	u8 key;
133 	u8 len;
134 };
135 
136 /* Structure to represent a field present in the
137  * generated key. A key field may present anywhere and can
138  * be of any size in the generated key. Once this structure
139  * is populated for fields of interest then field's presence
140  * and location (if present) can be known.
141  */
142 struct npc_key_field {
143 	/* Masks where all set bits indicate position
144 	 * of a field in the key
145 	 */
146 	u64 kw_mask[NPC_MAX_KWS_IN_KEY];
147 	/* Number of words in the key a field spans. If a field is
148 	 * of 16 bytes and key offset is 4 then the field will use
149 	 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
150 	 * nr_kws will be 3(KW0, KW1 and KW2).
151 	 */
152 	int nr_kws;
153 	/* used by packet header fields */
154 	struct npc_layer_mdata layer_mdata;
155 };
156 
157 struct npc_mcam {
158 	struct rsrc_bmap counters;
159 	struct mutex	lock;	/* MCAM entries and counters update lock */
160 	unsigned long	*bmap;		/* bitmap, 0 => bmap_entries */
161 	unsigned long	*bmap_reverse;	/* Reverse bitmap, bmap_entries => 0 */
162 	u16	bmap_entries;	/* Number of unreserved MCAM entries */
163 	u16	bmap_fcnt;	/* MCAM entries free count */
164 	u16	*entry2pfvf_map;
165 	u16	*entry2cntr_map;
166 	u16	*cntr2pfvf_map;
167 	u16	*cntr_refcnt;
168 	u16	*entry2target_pffunc;
169 	u8	keysize;	/* MCAM keysize 112/224/448 bits */
170 	u8	banks;		/* Number of MCAM banks */
171 	u8	banks_per_entry;/* Number of keywords in key */
172 	u16	banksize;	/* Number of MCAM entries in each bank */
173 	u16	total_entries;	/* Total number of MCAM entries */
174 	u16	nixlf_offset;	/* Offset of nixlf rsvd uncast entries */
175 	u16	pf_offset;	/* Offset of PF's rsvd bcast, promisc entries */
176 	u16	lprio_count;
177 	u16	lprio_start;
178 	u16	hprio_count;
179 	u16	hprio_end;
180 	u16     rx_miss_act_cntr; /* Counter for RX MISS action */
181 	/* fields present in the generated key */
182 	struct npc_key_field	tx_key_fields[NPC_KEY_FIELDS_MAX];
183 	struct npc_key_field	rx_key_fields[NPC_KEY_FIELDS_MAX];
184 	u64	tx_features;
185 	u64	rx_features;
186 	struct list_head mcam_rules;
187 };
188 
189 /* Structure for per RVU func info ie PF/VF */
190 struct rvu_pfvf {
191 	bool		npalf; /* Only one NPALF per RVU_FUNC */
192 	bool		nixlf; /* Only one NIXLF per RVU_FUNC */
193 	u16		sso;
194 	u16		ssow;
195 	u16		cptlfs;
196 	u16		timlfs;
197 	u16		cpt1_lfs;
198 	u8		cgx_lmac;
199 
200 	/* Block LF's MSIX vector info */
201 	struct rsrc_bmap msix;      /* Bitmap for MSIX vector alloc */
202 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
203 	u16		 *msix_lfmap; /* Vector to block LF mapping */
204 
205 	/* NPA contexts */
206 	struct qmem	*aura_ctx;
207 	struct qmem	*pool_ctx;
208 	struct qmem	*npa_qints_ctx;
209 	unsigned long	*aura_bmap;
210 	unsigned long	*pool_bmap;
211 
212 	/* NIX contexts */
213 	struct qmem	*rq_ctx;
214 	struct qmem	*sq_ctx;
215 	struct qmem	*cq_ctx;
216 	struct qmem	*rss_ctx;
217 	struct qmem	*cq_ints_ctx;
218 	struct qmem	*nix_qints_ctx;
219 	unsigned long	*sq_bmap;
220 	unsigned long	*rq_bmap;
221 	unsigned long	*cq_bmap;
222 
223 	u16		rx_chan_base;
224 	u16		tx_chan_base;
225 	u8              rx_chan_cnt; /* total number of RX channels */
226 	u8              tx_chan_cnt; /* total number of TX channels */
227 	u16		maxlen;
228 	u16		minlen;
229 
230 	bool		hw_rx_tstamp_en; /* Is rx_tstamp enabled */
231 	u8		mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
232 	u8		default_mac[ETH_ALEN]; /* MAC address from FWdata */
233 
234 	/* Broadcast/Multicast/Promisc pkt replication info */
235 	u16			bcast_mce_idx;
236 	u16			mcast_mce_idx;
237 	u16			promisc_mce_idx;
238 	struct nix_mce_list	bcast_mce_list;
239 	struct nix_mce_list	mcast_mce_list;
240 	struct nix_mce_list	promisc_mce_list;
241 	bool			use_mce_list;
242 
243 	struct rvu_npc_mcam_rule *def_ucast_rule;
244 
245 	bool	cgx_in_use; /* this PF/VF using CGX? */
246 	int	cgx_users;  /* number of cgx users - used only by PFs */
247 
248 	int     intf_mode;
249 	u8	nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
250 	u8	nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
251 	u8	nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
252 	u8	lbkid;	     /* NIX0/1 lbk link ID */
253 	u64     lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
254 	u64     lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
255 	unsigned long flags;
256 	struct  sdp_node_info *sdp_info;
257 };
258 
259 enum rvu_pfvf_flags {
260 	NIXLF_INITIALIZED = 0,
261 	PF_SET_VF_MAC,
262 	PF_SET_VF_CFG,
263 	PF_SET_VF_TRUSTED,
264 };
265 
266 #define RVU_CLEAR_VF_PERM  ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
267 
268 struct nix_txsch {
269 	struct rsrc_bmap schq;
270 	u8   lvl;
271 #define NIX_TXSCHQ_FREE		      BIT_ULL(1)
272 #define NIX_TXSCHQ_CFG_DONE	      BIT_ULL(0)
273 #define TXSCH_MAP_FUNC(__pfvf_map)    ((__pfvf_map) & 0xFFFF)
274 #define TXSCH_MAP_FLAGS(__pfvf_map)   ((__pfvf_map) >> 16)
275 #define TXSCH_MAP(__func, __flags)    (((__func) & 0xFFFF) | ((__flags) << 16))
276 #define TXSCH_SET_FLAG(__pfvf_map, flag)    ((__pfvf_map) | ((flag) << 16))
277 	u32  *pfvf_map;
278 };
279 
280 struct nix_mark_format {
281 	u8 total;
282 	u8 in_use;
283 	u32 *cfg;
284 };
285 
286 struct npc_pkind {
287 	struct rsrc_bmap rsrc;
288 	u32	*pfchan_map;
289 };
290 
291 struct nix_flowkey {
292 #define NIX_FLOW_KEY_ALG_MAX 32
293 	u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
294 	int in_use;
295 };
296 
297 struct nix_lso {
298 	u8 total;
299 	u8 in_use;
300 };
301 
302 struct nix_txvlan {
303 #define NIX_TX_VTAG_DEF_MAX 0x400
304 	struct rsrc_bmap rsrc;
305 	u16 *entry2pfvf_map;
306 	struct mutex rsrc_lock; /* Serialize resource alloc/free */
307 };
308 
309 struct nix_ipolicer {
310 	struct rsrc_bmap band_prof;
311 	u16 *pfvf_map;
312 	u16 *match_id;
313 	u16 *ref_count;
314 };
315 
316 struct nix_hw {
317 	int blkaddr;
318 	struct rvu *rvu;
319 	struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
320 	struct nix_mcast mcast;
321 	struct nix_flowkey flowkey;
322 	struct nix_mark_format mark_format;
323 	struct nix_lso lso;
324 	struct nix_txvlan txvlan;
325 	struct nix_ipolicer *ipolicer;
326 	u64    *tx_credits;
327 };
328 
329 /* RVU block's capabilities or functionality,
330  * which vary by silicon version/skew.
331  */
332 struct hw_cap {
333 	/* Transmit side supported functionality */
334 	u8	nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
335 	u16	nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
336 	u16	nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
337 	u16	nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
338 	bool	nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
339 	bool	nix_shaping;		 /* Is shaping and coloring supported */
340 	bool    nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
341 	bool	nix_tx_link_bp;		 /* Can link backpressure TL queues ? */
342 	bool	nix_rx_multicast;	 /* Rx packet replication support */
343 	bool	nix_common_dwrr_mtu;	 /* Common DWRR MTU for quantum config */
344 	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
345 	bool	programmable_chans; /* Channels programmable ? */
346 	bool	ipolicer;
347 	bool	npc_hash_extract; /* Hash extract enabled ? */
348 	bool	npc_exact_match_enabled; /* Exact match supported ? */
349 };
350 
351 struct rvu_hwinfo {
352 	u8	total_pfs;   /* MAX RVU PFs HW supports */
353 	u16	total_vfs;   /* Max RVU VFs HW supports */
354 	u16	max_vfs_per_pf; /* Max VFs that can be attached to a PF */
355 	u8	cgx;
356 	u8	lmac_per_cgx;
357 	u16	cgx_chan_base;	/* CGX base channel number */
358 	u16	lbk_chan_base;	/* LBK base channel number */
359 	u16	sdp_chan_base;	/* SDP base channel number */
360 	u16	cpt_chan_base;	/* CPT base channel number */
361 	u8	cgx_links;
362 	u8	lbk_links;
363 	u8	sdp_links;
364 	u8	cpt_links;	/* Number of CPT links */
365 	u8	npc_kpus;          /* No of parser units */
366 	u8	npc_pkinds;        /* No of port kinds */
367 	u8	npc_intfs;         /* No of interfaces */
368 	u8	npc_kpu_entries;   /* No of KPU entries */
369 	u16	npc_counters;	   /* No of match stats counters */
370 	u32	lbk_bufsize;	   /* FIFO size supported by LBK */
371 	bool	npc_ext_set;	   /* Extended register set */
372 	u64     npc_stat_ena;      /* Match stats enable bit */
373 
374 	struct hw_cap    cap;
375 	struct rvu_block block[BLK_COUNT]; /* Block info */
376 	struct nix_hw    *nix;
377 	struct rvu	 *rvu;
378 	struct npc_pkind pkind;
379 	struct npc_mcam  mcam;
380 	struct npc_exact_table *table;
381 };
382 
383 struct mbox_wq_info {
384 	struct otx2_mbox mbox;
385 	struct rvu_work *mbox_wrk;
386 
387 	struct otx2_mbox mbox_up;
388 	struct rvu_work *mbox_wrk_up;
389 
390 	struct workqueue_struct *mbox_wq;
391 };
392 
393 struct rvu_fwdata {
394 #define RVU_FWDATA_HEADER_MAGIC	0xCFDA	/* Custom Firmware Data*/
395 #define RVU_FWDATA_VERSION	0x0001
396 	u32 header_magic;
397 	u32 version;		/* version id */
398 
399 	/* MAC address */
400 #define PF_MACNUM_MAX	32
401 #define VF_MACNUM_MAX	256
402 	u64 pf_macs[PF_MACNUM_MAX];
403 	u64 vf_macs[VF_MACNUM_MAX];
404 	u64 sclk;
405 	u64 rclk;
406 	u64 mcam_addr;
407 	u64 mcam_sz;
408 	u64 msixtr_base;
409 	u32 ptp_ext_clk_rate;
410 	u32 ptp_ext_tstamp;
411 #define FWDATA_RESERVED_MEM 1022
412 	u64 reserved[FWDATA_RESERVED_MEM];
413 #define CGX_MAX         5
414 #define CGX_LMACS_MAX   4
415 	struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
416 	/* Do not add new fields below this line */
417 };
418 
419 struct ptp;
420 
421 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
422  * source where it came from.
423  */
424 struct npc_kpu_profile_adapter {
425 	const char			*name;
426 	u64				version;
427 	const struct npc_lt_def_cfg	*lt_def;
428 	const struct npc_kpu_profile_action	*ikpu; /* array[pkinds] */
429 	const struct npc_kpu_profile	*kpu; /* array[kpus] */
430 	struct npc_mcam_kex		*mkex;
431 	struct npc_mcam_kex_hash	*mkex_hash;
432 	bool				custom;
433 	size_t				pkinds;
434 	size_t				kpus;
435 };
436 
437 #define RVU_SWITCH_LBK_CHAN	63
438 
439 struct rvu_switch {
440 	struct mutex switch_lock; /* Serialize flow installation */
441 	u32 used_entries;
442 	u16 *entry2pcifunc;
443 	u16 mode;
444 	u16 start_entry;
445 };
446 
447 struct rvu {
448 	void __iomem		*afreg_base;
449 	void __iomem		*pfreg_base;
450 	struct pci_dev		*pdev;
451 	struct device		*dev;
452 	struct rvu_hwinfo       *hw;
453 	struct rvu_pfvf		*pf;
454 	struct rvu_pfvf		*hwvf;
455 	struct mutex		rsrc_lock; /* Serialize resource alloc/free */
456 	int			vfs; /* Number of VFs attached to RVU */
457 	int			nix_blkaddr[MAX_NIX_BLKS];
458 
459 	/* Mbox */
460 	struct mbox_wq_info	afpf_wq_info;
461 	struct mbox_wq_info	afvf_wq_info;
462 
463 	/* PF FLR */
464 	struct rvu_work		*flr_wrk;
465 	struct workqueue_struct *flr_wq;
466 	struct mutex		flr_lock; /* Serialize FLRs */
467 
468 	/* MSI-X */
469 	u16			num_vec;
470 	char			*irq_name;
471 	bool			*irq_allocated;
472 	dma_addr_t		msix_base_iova;
473 	u64			msixtr_base_phy; /* Register reset value */
474 
475 	/* CGX */
476 #define PF_CGXMAP_BASE		1 /* PF 0 is reserved for RVU PF */
477 	u16			cgx_mapped_vfs; /* maximum CGX mapped VFs */
478 	u8			cgx_mapped_pfs;
479 	u8			cgx_cnt_max;	 /* CGX port count max */
480 	u8			*pf2cgxlmac_map; /* pf to cgx_lmac map */
481 	u16			*cgxlmac2pf_map; /* bitmap of mapped pfs for
482 						  * every cgx lmac port
483 						  */
484 	unsigned long		pf_notify_bmap; /* Flags for PF notification */
485 	void			**cgx_idmap; /* cgx id to cgx data map table */
486 	struct			work_struct cgx_evh_work;
487 	struct			workqueue_struct *cgx_evh_wq;
488 	spinlock_t		cgx_evq_lock; /* cgx event queue lock */
489 	struct list_head	cgx_evq_head; /* cgx event queue head */
490 	struct mutex		cgx_cfg_lock; /* serialize cgx configuration */
491 
492 	char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
493 	char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
494 
495 	/* Firmware data */
496 	struct rvu_fwdata	*fwdata;
497 	void			*kpu_fwdata;
498 	size_t			kpu_fwdata_sz;
499 	void __iomem		*kpu_prfl_addr;
500 
501 	/* NPC KPU data */
502 	struct npc_kpu_profile_adapter kpu;
503 
504 	struct ptp		*ptp;
505 
506 	int			mcs_blk_cnt;
507 
508 #ifdef CONFIG_DEBUG_FS
509 	struct rvu_debugfs	rvu_dbg;
510 #endif
511 	struct rvu_devlink	*rvu_dl;
512 
513 	/* RVU switch implementation over NPC with DMAC rules */
514 	struct rvu_switch	rswitch;
515 
516 	struct			work_struct mcs_intr_work;
517 	struct			workqueue_struct *mcs_intr_wq;
518 	struct list_head	mcs_intrq_head;
519 	/* mcs interrupt queue lock */
520 	spinlock_t		mcs_intrq_lock;
521 };
522 
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)523 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
524 {
525 	writeq(val, rvu->afreg_base + ((block << 28) | offset));
526 }
527 
rvu_read64(struct rvu * rvu,u64 block,u64 offset)528 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
529 {
530 	return readq(rvu->afreg_base + ((block << 28) | offset));
531 }
532 
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)533 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
534 {
535 	writeq(val, rvu->pfreg_base + offset);
536 }
537 
rvupf_read64(struct rvu * rvu,u64 offset)538 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
539 {
540 	return readq(rvu->pfreg_base + offset);
541 }
542 
543 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)544 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
545 {
546 	struct pci_dev *pdev = rvu->pdev;
547 	/* 96XX A0/B0, 95XX A0/A1/B0 chips */
548 	return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
549 		(pdev->revision == 0x10) || (pdev->revision == 0x11) ||
550 		(pdev->revision == 0x14));
551 }
552 
is_rvu_96xx_A0(struct rvu * rvu)553 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
554 {
555 	struct pci_dev *pdev = rvu->pdev;
556 
557 	return (pdev->revision == 0x00);
558 }
559 
is_rvu_96xx_B0(struct rvu * rvu)560 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
561 {
562 	struct pci_dev *pdev = rvu->pdev;
563 
564 	return (pdev->revision == 0x00) || (pdev->revision == 0x01);
565 }
566 
is_rvu_95xx_A0(struct rvu * rvu)567 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
568 {
569 	struct pci_dev *pdev = rvu->pdev;
570 
571 	return (pdev->revision == 0x10) || (pdev->revision == 0x11);
572 }
573 
574 /* REVID for PCIe devices.
575  * Bits 0..1: minor pass, bit 3..2: major pass
576  * bits 7..4: midr id
577  */
578 #define PCI_REVISION_ID_96XX		0x00
579 #define PCI_REVISION_ID_95XX		0x10
580 #define PCI_REVISION_ID_95XXN		0x20
581 #define PCI_REVISION_ID_98XX		0x30
582 #define PCI_REVISION_ID_95XXMM		0x40
583 #define PCI_REVISION_ID_95XXO		0xE0
584 
is_rvu_otx2(struct rvu * rvu)585 static inline bool is_rvu_otx2(struct rvu *rvu)
586 {
587 	struct pci_dev *pdev = rvu->pdev;
588 
589 	u8 midr = pdev->revision & 0xF0;
590 
591 	return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
592 		midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
593 		midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
594 }
595 
is_rvu_npc_hash_extract_en(struct rvu * rvu)596 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
597 {
598 	u64 npc_const3;
599 
600 	npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
601 	if (!(npc_const3 & BIT_ULL(62)))
602 		return false;
603 
604 	return true;
605 }
606 
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)607 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
608 				   u8 lmacid, u8 chan)
609 {
610 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
611 	u16 cgx_chans = nix_const & 0xFFULL;
612 	struct rvu_hwinfo *hw = rvu->hw;
613 
614 	if (!hw->cap.programmable_chans)
615 		return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
616 
617 	return rvu->hw->cgx_chan_base +
618 		(cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
619 }
620 
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)621 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
622 				   u8 chan)
623 {
624 	u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
625 	u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
626 	struct rvu_hwinfo *hw = rvu->hw;
627 
628 	if (!hw->cap.programmable_chans)
629 		return NIX_CHAN_LBK_CHX(lbkid, chan);
630 
631 	return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
632 }
633 
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)634 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
635 {
636 	struct rvu_hwinfo *hw = rvu->hw;
637 
638 	if (!hw->cap.programmable_chans)
639 		return NIX_CHAN_SDP_CHX(chan);
640 
641 	return hw->sdp_chan_base + chan;
642 }
643 
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)644 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
645 {
646 	return rvu->hw->cpt_chan_base + chan;
647 }
648 
649 /* Function Prototypes
650  * RVU
651  */
is_afvf(u16 pcifunc)652 static inline bool is_afvf(u16 pcifunc)
653 {
654 	return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
655 }
656 
is_vf(u16 pcifunc)657 static inline bool is_vf(u16 pcifunc)
658 {
659 	return !!(pcifunc & RVU_PFVF_FUNC_MASK);
660 }
661 
662 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)663 static inline bool is_pffunc_af(u16 pcifunc)
664 {
665 	return !pcifunc;
666 }
667 
is_rvu_fwdata_valid(struct rvu * rvu)668 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
669 {
670 	return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
671 		(rvu->fwdata->version == RVU_FWDATA_VERSION);
672 }
673 
674 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
675 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
676 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
677 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
678 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
679 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
680 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
681 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
682 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
683 int rvu_get_pf(u16 pcifunc);
684 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
685 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
686 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
687 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
688 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
689 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
690 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
691 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
692 int rvu_get_num_lbk_chans(void);
693 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
694 			      u16 global_slot, u16 *slot_in_block);
695 
696 /* RVU HW reg validation */
697 enum regmap_block {
698 	TXSCHQ_HWREGMAP = 0,
699 	MAX_HWREGMAP,
700 };
701 
702 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
703 
704 /* NPA/NIX AQ APIs */
705 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
706 		 int qsize, int inst_size, int res_size);
707 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
708 
709 /* SDP APIs */
710 int rvu_sdp_init(struct rvu *rvu);
711 bool is_sdp_pfvf(u16 pcifunc);
712 bool is_sdp_pf(u16 pcifunc);
713 bool is_sdp_vf(u16 pcifunc);
714 
715 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)716 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
717 {
718 	return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
719 		!is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
720 }
721 
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)722 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
723 {
724 	*cgx_id = (map >> 4) & 0xF;
725 	*lmac_id = (map & 0xF);
726 }
727 
is_cgx_vf(struct rvu * rvu,u16 pcifunc)728 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
729 {
730 	return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
731 		is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
732 }
733 
734 #define M(_name, _id, fn_name, req, rsp)				\
735 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
736 MBOX_MESSAGES
737 #undef M
738 
739 int rvu_cgx_init(struct rvu *rvu);
740 int rvu_cgx_exit(struct rvu *rvu);
741 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
742 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
743 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
744 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
745 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
746 			   int rxtxflag, u64 *stat);
747 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
748 
749 /* NPA APIs */
750 int rvu_npa_init(struct rvu *rvu);
751 void rvu_npa_freemem(struct rvu *rvu);
752 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
753 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
754 			struct npa_aq_enq_rsp *rsp);
755 
756 /* NIX APIs */
757 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
758 int rvu_nix_init(struct rvu *rvu);
759 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
760 				int blkaddr, u32 cfg);
761 void rvu_nix_freemem(struct rvu *rvu);
762 int rvu_get_nixlf_count(struct rvu *rvu);
763 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
764 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
765 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
766 			struct nix_mce_list *mce_list,
767 			int mce_idx, int mcam_index, bool add);
768 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
769 		      struct nix_mce_list **mce_list, int *mce_idx);
770 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
771 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
772 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
773 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
774 			struct nix_hw **nix_hw, int *blkaddr);
775 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
776 				 u16 rq_idx, u16 match_id);
777 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
778 			struct nix_cn10k_aq_enq_req *aq_req,
779 			struct nix_cn10k_aq_enq_rsp *aq_rsp,
780 			u16 pcifunc, u8 ctype, u32 qidx);
781 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
782 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
783 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
784 
785 /* NPC APIs */
786 void rvu_npc_freemem(struct rvu *rvu);
787 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
788 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
789 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
790 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
791 				 int nixlf, u64 chan, u8 *mac_addr);
792 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
793 				   int nixlf, u64 chan, u8 chan_cnt);
794 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
795 				  bool enable);
796 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
797 				       int nixlf, u64 chan);
798 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
799 				bool enable);
800 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
801 				    u64 chan);
802 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
803 				   bool enable);
804 
805 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
806 				  int nixlf, int type, bool enable);
807 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
808 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
809 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
810 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
811 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
812 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
813 				    int group, int alg_idx, int mcam_index);
814 
815 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
816 				       int blkaddr, int *alloc_cnt,
817 				       int *enable_cnt);
818 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
819 					 int blkaddr, int *alloc_cnt,
820 					 int *enable_cnt);
821 bool is_npc_intf_tx(u8 intf);
822 bool is_npc_intf_rx(u8 intf);
823 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
824 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
825 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
826 const char *npc_get_field_name(u8 hdr);
827 int npc_get_bank(struct npc_mcam *mcam, int index);
828 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
829 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
830 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
831 			   int blkaddr, int index, bool enable);
832 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
833 			 int blkaddr, u16 src, struct mcam_entry *entry,
834 			 u8 *intf, u8 *ena);
835 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
836 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
837 u32  rvu_cgx_get_fifolen(struct rvu *rvu);
838 void *rvu_first_cgx_pdata(struct rvu *rvu);
839 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
840 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
841 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
842 			       u16 pfc_en);
843 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
844 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
845 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
846 			     int type);
847 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
848 			   int index);
849 int rvu_npc_init(struct rvu *rvu);
850 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
851 			       u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
852 			       u64 bcast_mcast_val, u64 bcast_mcast_mask);
853 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
854 
855 /* CPT APIs */
856 int rvu_cpt_register_interrupts(struct rvu *rvu);
857 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
858 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
859 			int slot);
860 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
861 
862 /* CN10K RVU */
863 int rvu_set_channels_base(struct rvu *rvu);
864 void rvu_program_channels(struct rvu *rvu);
865 
866 /* CN10K RVU - LMT*/
867 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
868 
869 #ifdef CONFIG_DEBUG_FS
870 void rvu_dbg_init(struct rvu *rvu);
871 void rvu_dbg_exit(struct rvu *rvu);
872 #else
rvu_dbg_init(struct rvu * rvu)873 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)874 static inline void rvu_dbg_exit(struct rvu *rvu) {}
875 #endif
876 
877 /* RVU Switch */
878 void rvu_switch_enable(struct rvu *rvu);
879 void rvu_switch_disable(struct rvu *rvu);
880 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
881 
882 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
883 			   u64 pkind, u8 var_len_off, u8 var_len_off_mask,
884 			   u8 shift_dir);
885 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
886 
887 /* CN10K MCS */
888 int rvu_mcs_init(struct rvu *rvu);
889 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
890 void rvu_mcs_exit(struct rvu *rvu);
891 
892 #endif /* RVU_H */
893