1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 
12 #include "rvu_struct.h"
13 #include "rvu_reg.h"
14 #include "rvu.h"
15 #include "npc.h"
16 #include "cgx.h"
17 #include "npc_profile.h"
18 #include "rvu_npc_hash.h"
19 
20 #define RSVD_MCAM_ENTRIES_PER_PF	3 /* Broadcast, Promisc and AllMulticast */
21 #define RSVD_MCAM_ENTRIES_PER_NIXLF	1 /* Ucast for LFs */
22 
23 #define NPC_PARSE_RESULT_DMAC_OFFSET	8
24 #define NPC_HW_TSTAMP_OFFSET		8ULL
25 #define NPC_KEX_CHAN_MASK		0xFFFULL
26 #define NPC_KEX_PF_FUNC_MASK		0xFFFFULL
27 
28 #define ALIGN_8B_CEIL(__a)	(((__a) + 7) & (-8))
29 
30 static const char def_pfl_name[] = "default";
31 
32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
33 				      int blkaddr, u16 pcifunc);
34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
35 				       u16 pcifunc);
36 
is_npc_intf_tx(u8 intf)37 bool is_npc_intf_tx(u8 intf)
38 {
39 	return !!(intf & 0x1);
40 }
41 
is_npc_intf_rx(u8 intf)42 bool is_npc_intf_rx(u8 intf)
43 {
44 	return !(intf & 0x1);
45 }
46 
is_npc_interface_valid(struct rvu * rvu,u8 intf)47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf)
48 {
49 	struct rvu_hwinfo *hw = rvu->hw;
50 
51 	return intf < hw->npc_intfs;
52 }
53 
rvu_npc_get_tx_nibble_cfg(struct rvu * rvu,u64 nibble_ena)54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena)
55 {
56 	/* Due to a HW issue in these silicon versions, parse nibble enable
57 	 * configuration has to be identical for both Rx and Tx interfaces.
58 	 */
59 	if (is_rvu_96xx_B0(rvu))
60 		return nibble_ena;
61 	return 0;
62 }
63 
npc_mcam_verify_pf_func(struct rvu * rvu,struct mcam_entry * entry_data,u8 intf,u16 pcifunc)64 static int npc_mcam_verify_pf_func(struct rvu *rvu,
65 				   struct mcam_entry *entry_data, u8 intf,
66 				   u16 pcifunc)
67 {
68 	u16 pf_func, pf_func_mask;
69 
70 	if (is_npc_intf_rx(intf))
71 		return 0;
72 
73 	pf_func_mask = (entry_data->kw_mask[0] >> 32) &
74 		NPC_KEX_PF_FUNC_MASK;
75 	pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK;
76 
77 	pf_func = be16_to_cpu((__force __be16)pf_func);
78 	if (pf_func_mask != NPC_KEX_PF_FUNC_MASK ||
79 	    ((pf_func & ~RVU_PFVF_FUNC_MASK) !=
80 	     (pcifunc & ~RVU_PFVF_FUNC_MASK)))
81 		return -EINVAL;
82 
83 	return 0;
84 }
85 
rvu_npc_set_pkind(struct rvu * rvu,int pkind,struct rvu_pfvf * pfvf)86 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
87 {
88 	int blkaddr;
89 	u64 val = 0;
90 
91 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
92 	if (blkaddr < 0)
93 		return;
94 
95 	/* Config CPI base for the PKIND */
96 	val = pkind | 1ULL << 62;
97 	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
98 }
99 
rvu_npc_get_pkind(struct rvu * rvu,u16 pf)100 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
101 {
102 	struct npc_pkind *pkind = &rvu->hw->pkind;
103 	u32 map;
104 	int i;
105 
106 	for (i = 0; i < pkind->rsrc.max; i++) {
107 		map = pkind->pfchan_map[i];
108 		if (((map >> 16) & 0x3F) == pf)
109 			return i;
110 	}
111 	return -1;
112 }
113 
114 #define NPC_AF_ACTION0_PTR_ADVANCE	GENMASK_ULL(27, 20)
115 
npc_config_ts_kpuaction(struct rvu * rvu,int pf,u16 pcifunc,bool enable)116 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
117 {
118 	int pkind, blkaddr;
119 	u64 val;
120 
121 	pkind = rvu_npc_get_pkind(rvu, pf);
122 	if (pkind < 0) {
123 		dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
124 		return -EINVAL;
125 	}
126 
127 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
128 	if (blkaddr < 0) {
129 		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
130 		return -EINVAL;
131 	}
132 
133 	val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
134 	val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
135 	/* If timestamp is enabled then configure NPC to shift 8 bytes */
136 	if (enable)
137 		val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
138 				  NPC_HW_TSTAMP_OFFSET);
139 	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
140 
141 	return 0;
142 }
143 
npc_get_ucast_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf)144 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc,
145 				    int nixlf)
146 {
147 	struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
148 	struct rvu *rvu = hw->rvu;
149 	int blkaddr = 0, max = 0;
150 	struct rvu_block *block;
151 	struct rvu_pfvf *pfvf;
152 
153 	pfvf = rvu_get_pfvf(rvu, pcifunc);
154 	/* Given a PF/VF and NIX LF number calculate the unicast mcam
155 	 * entry index based on the NIX block assigned to the PF/VF.
156 	 */
157 	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
158 	while (blkaddr) {
159 		if (pfvf->nix_blkaddr == blkaddr)
160 			break;
161 		block = &rvu->hw->block[blkaddr];
162 		max += block->lf.max;
163 		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
164 	}
165 
166 	return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF;
167 }
168 
npc_get_nixlf_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf,int type)169 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
170 			     u16 pcifunc, int nixlf, int type)
171 {
172 	int pf = rvu_get_pf(pcifunc);
173 	int index;
174 
175 	/* Check if this is for a PF */
176 	if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
177 		/* Reserved entries exclude PF0 */
178 		pf--;
179 		index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
180 		/* Broadcast address matching entry should be first so
181 		 * that the packet can be replicated to all VFs.
182 		 */
183 		if (type == NIXLF_BCAST_ENTRY)
184 			return index;
185 		else if (type == NIXLF_ALLMULTI_ENTRY)
186 			return index + 1;
187 		else if (type == NIXLF_PROMISC_ENTRY)
188 			return index + 2;
189 	}
190 
191 	return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf);
192 }
193 
npc_get_bank(struct npc_mcam * mcam,int index)194 int npc_get_bank(struct npc_mcam *mcam, int index)
195 {
196 	int bank = index / mcam->banksize;
197 
198 	/* 0,1 & 2,3 banks are combined for this keysize */
199 	if (mcam->keysize == NPC_MCAM_KEY_X2)
200 		return bank ? 2 : 0;
201 
202 	return bank;
203 }
204 
is_mcam_entry_enabled(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)205 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
206 			   int blkaddr, int index)
207 {
208 	int bank = npc_get_bank(mcam, index);
209 	u64 cfg;
210 
211 	index &= (mcam->banksize - 1);
212 	cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
213 	return (cfg & 1);
214 }
215 
npc_enable_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,bool enable)216 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
217 			   int blkaddr, int index, bool enable)
218 {
219 	int bank = npc_get_bank(mcam, index);
220 	int actbank = bank;
221 
222 	index &= (mcam->banksize - 1);
223 	for (; bank < (actbank + mcam->banks_per_entry); bank++) {
224 		rvu_write64(rvu, blkaddr,
225 			    NPC_AF_MCAMEX_BANKX_CFG(index, bank),
226 			    enable ? 1 : 0);
227 	}
228 }
229 
npc_clear_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)230 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
231 				 int blkaddr, int index)
232 {
233 	int bank = npc_get_bank(mcam, index);
234 	int actbank = bank;
235 
236 	index &= (mcam->banksize - 1);
237 	for (; bank < (actbank + mcam->banks_per_entry); bank++) {
238 		rvu_write64(rvu, blkaddr,
239 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
240 		rvu_write64(rvu, blkaddr,
241 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
242 
243 		rvu_write64(rvu, blkaddr,
244 			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
245 		rvu_write64(rvu, blkaddr,
246 			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
247 
248 		rvu_write64(rvu, blkaddr,
249 			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
250 		rvu_write64(rvu, blkaddr,
251 			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
252 	}
253 }
254 
npc_get_keyword(struct mcam_entry * entry,int idx,u64 * cam0,u64 * cam1)255 static void npc_get_keyword(struct mcam_entry *entry, int idx,
256 			    u64 *cam0, u64 *cam1)
257 {
258 	u64 kw_mask = 0x00;
259 
260 #define CAM_MASK(n)	(BIT_ULL(n) - 1)
261 
262 	/* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
263 	 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
264 	 *
265 	 * Also, only 48 bits of BANKX_CAMX_W1 are valid.
266 	 */
267 	switch (idx) {
268 	case 0:
269 		/* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
270 		*cam1 = entry->kw[0];
271 		kw_mask = entry->kw_mask[0];
272 		break;
273 	case 1:
274 		/* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
275 		*cam1 = entry->kw[1] & CAM_MASK(48);
276 		kw_mask = entry->kw_mask[1] & CAM_MASK(48);
277 		break;
278 	case 2:
279 		/* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
280 		 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
281 		 */
282 		*cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
283 		*cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
284 		kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
285 		kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
286 		break;
287 	case 3:
288 		/* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
289 		 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
290 		 */
291 		*cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
292 		*cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
293 		kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
294 		kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
295 		break;
296 	case 4:
297 		/* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
298 		 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
299 		 */
300 		*cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
301 		*cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
302 		kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
303 		kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
304 		break;
305 	case 5:
306 		/* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
307 		 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
308 		 */
309 		*cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
310 		*cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
311 		kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
312 		kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
313 		break;
314 	case 6:
315 		/* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
316 		 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
317 		 */
318 		*cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
319 		*cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
320 		kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
321 		kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
322 		break;
323 	case 7:
324 		/* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
325 		*cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
326 		kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
327 		break;
328 	}
329 
330 	*cam1 &= kw_mask;
331 	*cam0 = ~*cam1 & kw_mask;
332 }
333 
npc_fill_entryword(struct mcam_entry * entry,int idx,u64 cam0,u64 cam1)334 static void npc_fill_entryword(struct mcam_entry *entry, int idx,
335 			       u64 cam0, u64 cam1)
336 {
337 	/* Similar to npc_get_keyword, but fills mcam_entry structure from
338 	 * CAM registers.
339 	 */
340 	switch (idx) {
341 	case 0:
342 		entry->kw[0] = cam1;
343 		entry->kw_mask[0] = cam1 ^ cam0;
344 		break;
345 	case 1:
346 		entry->kw[1] = cam1;
347 		entry->kw_mask[1] = cam1 ^ cam0;
348 		break;
349 	case 2:
350 		entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48;
351 		entry->kw[2] = (cam1 >> 16) & CAM_MASK(48);
352 		entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
353 		entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48);
354 		break;
355 	case 3:
356 		entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48;
357 		entry->kw[3] = (cam1 >> 16) & CAM_MASK(32);
358 		entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
359 		entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32);
360 		break;
361 	case 4:
362 		entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32;
363 		entry->kw[4] = (cam1 >> 32) & CAM_MASK(32);
364 		entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
365 		entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32);
366 		break;
367 	case 5:
368 		entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32;
369 		entry->kw[5] = (cam1 >> 32) & CAM_MASK(16);
370 		entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
371 		entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16);
372 		break;
373 	case 6:
374 		entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16;
375 		entry->kw[6] = (cam1 >> 48) & CAM_MASK(16);
376 		entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
377 		entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16);
378 		break;
379 	case 7:
380 		entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16;
381 		entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
382 		break;
383 	}
384 }
385 
npc_get_default_entry_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pf_func)386 static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam,
387 					int blkaddr, u16 pf_func)
388 {
389 	int bank, nixlf, index;
390 
391 	/* get ucast entry rule entry index */
392 	nix_get_nixlf(rvu, pf_func, &nixlf, NULL);
393 	index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf,
394 					 NIXLF_UCAST_ENTRY);
395 	bank = npc_get_bank(mcam, index);
396 	index &= (mcam->banksize - 1);
397 
398 	return rvu_read64(rvu, blkaddr,
399 			  NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
400 }
401 
npc_fixup_vf_rule(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,struct mcam_entry * entry,bool * enable)402 static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam,
403 			      int blkaddr, int index, struct mcam_entry *entry,
404 			      bool *enable)
405 {
406 	struct rvu_npc_mcam_rule *rule;
407 	u16 owner, target_func;
408 	struct rvu_pfvf *pfvf;
409 	u64 rx_action;
410 
411 	owner = mcam->entry2pfvf_map[index];
412 	target_func = (entry->action >> 4) & 0xffff;
413 	/* do nothing when target is LBK/PF or owner is not PF */
414 	if (is_pffunc_af(owner) || is_afvf(target_func) ||
415 	    (owner & RVU_PFVF_FUNC_MASK) ||
416 	    !(target_func & RVU_PFVF_FUNC_MASK))
417 		return;
418 
419 	/* save entry2target_pffunc */
420 	pfvf = rvu_get_pfvf(rvu, target_func);
421 	mcam->entry2target_pffunc[index] = target_func;
422 
423 	/* don't enable rule when nixlf not attached or initialized */
424 	if (!(is_nixlf_attached(rvu, target_func) &&
425 	      test_bit(NIXLF_INITIALIZED, &pfvf->flags)))
426 		*enable = false;
427 
428 	/* fix up not needed for the rules added by user(ntuple filters) */
429 	list_for_each_entry(rule, &mcam->mcam_rules, list) {
430 		if (rule->entry == index)
431 			return;
432 	}
433 
434 	/* copy VF default entry action to the VF mcam entry */
435 	rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr,
436 						 target_func);
437 	if (rx_action)
438 		entry->action = rx_action;
439 }
440 
npc_config_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,u8 intf,struct mcam_entry * entry,bool enable)441 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
442 				  int blkaddr, int index, u8 intf,
443 				  struct mcam_entry *entry, bool enable)
444 {
445 	int bank = npc_get_bank(mcam, index);
446 	int kw = 0, actbank, actindex;
447 	u8 tx_intf_mask = ~intf & 0x3;
448 	u8 tx_intf = intf;
449 	u64 cam0, cam1;
450 
451 	actbank = bank; /* Save bank id, to set action later on */
452 	actindex = index;
453 	index &= (mcam->banksize - 1);
454 
455 	/* Disable before mcam entry update */
456 	npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
457 
458 	/* Clear mcam entry to avoid writes being suppressed by NPC */
459 	npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
460 
461 	/* CAM1 takes the comparison value and
462 	 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
463 	 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
464 	 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
465 	 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
466 	 */
467 	for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
468 		/* Interface should be set in all banks */
469 		if (is_npc_intf_tx(intf)) {
470 			/* Last bit must be set and rest don't care
471 			 * for TX interfaces
472 			 */
473 			tx_intf_mask = 0x1;
474 			tx_intf = intf & tx_intf_mask;
475 			tx_intf_mask = ~tx_intf & tx_intf_mask;
476 		}
477 
478 		rvu_write64(rvu, blkaddr,
479 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
480 			    tx_intf);
481 		rvu_write64(rvu, blkaddr,
482 			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
483 			    tx_intf_mask);
484 
485 		/* Set the match key */
486 		npc_get_keyword(entry, kw, &cam0, &cam1);
487 		rvu_write64(rvu, blkaddr,
488 			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
489 		rvu_write64(rvu, blkaddr,
490 			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
491 
492 		npc_get_keyword(entry, kw + 1, &cam0, &cam1);
493 		rvu_write64(rvu, blkaddr,
494 			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
495 		rvu_write64(rvu, blkaddr,
496 			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
497 	}
498 
499 	/* PF installing VF rule */
500 	if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries)
501 		npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable);
502 
503 	/* Set 'action' */
504 	rvu_write64(rvu, blkaddr,
505 		    NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
506 
507 	/* Set TAG 'action' */
508 	rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
509 		    entry->vtag_action);
510 
511 	/* Enable the entry */
512 	if (enable)
513 		npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
514 }
515 
npc_read_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,struct mcam_entry * entry,u8 * intf,u8 * ena)516 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
517 			 int blkaddr, u16 src,
518 			 struct mcam_entry *entry, u8 *intf, u8 *ena)
519 {
520 	int sbank = npc_get_bank(mcam, src);
521 	int bank, kw = 0;
522 	u64 cam0, cam1;
523 
524 	src &= (mcam->banksize - 1);
525 	bank = sbank;
526 
527 	for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
528 		cam1 = rvu_read64(rvu, blkaddr,
529 				  NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1));
530 		cam0 = rvu_read64(rvu, blkaddr,
531 				  NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0));
532 		npc_fill_entryword(entry, kw, cam0, cam1);
533 
534 		cam1 = rvu_read64(rvu, blkaddr,
535 				  NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1));
536 		cam0 = rvu_read64(rvu, blkaddr,
537 				  NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0));
538 		npc_fill_entryword(entry, kw + 1, cam0, cam1);
539 	}
540 
541 	entry->action = rvu_read64(rvu, blkaddr,
542 				   NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
543 	entry->vtag_action =
544 		rvu_read64(rvu, blkaddr,
545 			   NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
546 	*intf = rvu_read64(rvu, blkaddr,
547 			   NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3;
548 	*ena = rvu_read64(rvu, blkaddr,
549 			  NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1;
550 }
551 
npc_copy_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,u16 dest)552 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
553 				int blkaddr, u16 src, u16 dest)
554 {
555 	int dbank = npc_get_bank(mcam, dest);
556 	int sbank = npc_get_bank(mcam, src);
557 	u64 cfg, sreg, dreg;
558 	int bank, i;
559 
560 	src &= (mcam->banksize - 1);
561 	dest &= (mcam->banksize - 1);
562 
563 	/* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
564 	for (bank = 0; bank < mcam->banks_per_entry; bank++) {
565 		sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
566 		dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
567 		for (i = 0; i < 6; i++) {
568 			cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
569 			rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
570 		}
571 	}
572 
573 	/* Copy action */
574 	cfg = rvu_read64(rvu, blkaddr,
575 			 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
576 	rvu_write64(rvu, blkaddr,
577 		    NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
578 
579 	/* Copy TAG action */
580 	cfg = rvu_read64(rvu, blkaddr,
581 			 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
582 	rvu_write64(rvu, blkaddr,
583 		    NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
584 
585 	/* Enable or disable */
586 	cfg = rvu_read64(rvu, blkaddr,
587 			 NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
588 	rvu_write64(rvu, blkaddr,
589 		    NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
590 }
591 
npc_get_mcam_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)592 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
593 			       int blkaddr, int index)
594 {
595 	int bank = npc_get_bank(mcam, index);
596 
597 	index &= (mcam->banksize - 1);
598 	return rvu_read64(rvu, blkaddr,
599 			  NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
600 }
601 
rvu_npc_install_ucast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 * mac_addr)602 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
603 				 int nixlf, u64 chan, u8 *mac_addr)
604 {
605 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
606 	struct npc_install_flow_req req = { 0 };
607 	struct npc_install_flow_rsp rsp = { 0 };
608 	struct npc_mcam *mcam = &rvu->hw->mcam;
609 	struct nix_rx_action action = { 0 };
610 	int blkaddr, index;
611 
612 	/* AF's and SDP VFs work in promiscuous mode */
613 	if (is_afvf(pcifunc) || is_sdp_vf(pcifunc))
614 		return;
615 
616 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
617 	if (blkaddr < 0)
618 		return;
619 
620 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
621 					 nixlf, NIXLF_UCAST_ENTRY);
622 
623 	/* Don't change the action if entry is already enabled
624 	 * Otherwise RSS action may get overwritten.
625 	 */
626 	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
627 		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
628 						      blkaddr, index);
629 	} else {
630 		action.op = NIX_RX_ACTIONOP_UCAST;
631 		action.pf_func = pcifunc;
632 	}
633 
634 	req.default_rule = 1;
635 	ether_addr_copy(req.packet.dmac, mac_addr);
636 	eth_broadcast_addr((u8 *)&req.mask.dmac);
637 	req.features = BIT_ULL(NPC_DMAC);
638 	req.channel = chan;
639 	req.chan_mask = 0xFFFU;
640 	req.intf = pfvf->nix_rx_intf;
641 	req.op = action.op;
642 	req.hdr.pcifunc = 0; /* AF is requester */
643 	req.vf = action.pf_func;
644 	req.index = action.index;
645 	req.match_id = action.match_id;
646 	req.flow_key_alg = action.flow_key_alg;
647 
648 	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
649 }
650 
rvu_npc_install_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 chan_cnt)651 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
652 				   int nixlf, u64 chan, u8 chan_cnt)
653 {
654 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
655 	struct npc_install_flow_req req = { 0 };
656 	struct npc_install_flow_rsp rsp = { 0 };
657 	struct npc_mcam *mcam = &rvu->hw->mcam;
658 	struct rvu_hwinfo *hw = rvu->hw;
659 	int blkaddr, ucast_idx, index;
660 	struct nix_rx_action action = { 0 };
661 	u64 relaxed_mask;
662 
663 	if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc))
664 		return;
665 
666 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
667 	if (blkaddr < 0)
668 		return;
669 
670 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
671 					 nixlf, NIXLF_PROMISC_ENTRY);
672 
673 	if (is_cgx_vf(rvu, pcifunc))
674 		index = npc_get_nixlf_mcam_index(mcam,
675 						 pcifunc & ~RVU_PFVF_FUNC_MASK,
676 						 nixlf, NIXLF_PROMISC_ENTRY);
677 
678 	/* If the corresponding PF's ucast action is RSS,
679 	 * use the same action for promisc also
680 	 */
681 	ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
682 					     nixlf, NIXLF_UCAST_ENTRY);
683 	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
684 		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
685 						      blkaddr, ucast_idx);
686 
687 	if (action.op != NIX_RX_ACTIONOP_RSS) {
688 		*(u64 *)&action = 0;
689 		action.op = NIX_RX_ACTIONOP_UCAST;
690 	}
691 
692 	/* RX_ACTION set to MCAST for CGX PF's */
693 	if (hw->cap.nix_rx_multicast && pfvf->use_mce_list &&
694 	    is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
695 		*(u64 *)&action = 0;
696 		action.op = NIX_RX_ACTIONOP_MCAST;
697 		pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
698 		action.index = pfvf->promisc_mce_idx;
699 	}
700 
701 	/* For cn10k the upper two bits of the channel number are
702 	 * cpt channel number. with masking out these bits in the
703 	 * mcam entry, same entry used for NIX will allow packets
704 	 * received from cpt for parsing.
705 	 */
706 	if (!is_rvu_otx2(rvu)) {
707 		req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
708 	} else {
709 		req.chan_mask = 0xFFFU;
710 	}
711 
712 	if (chan_cnt > 1) {
713 		if (!is_power_of_2(chan_cnt)) {
714 			dev_err(rvu->dev,
715 				"%s: channel count more than 1, must be power of 2\n", __func__);
716 			return;
717 		}
718 		relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1,
719 					   ilog2(chan_cnt));
720 		req.chan_mask &= relaxed_mask;
721 	}
722 
723 	req.channel = chan;
724 	req.intf = pfvf->nix_rx_intf;
725 	req.entry = index;
726 	req.op = action.op;
727 	req.hdr.pcifunc = 0; /* AF is requester */
728 	req.vf = pcifunc;
729 	req.index = action.index;
730 	req.match_id = action.match_id;
731 	req.flow_key_alg = action.flow_key_alg;
732 
733 	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
734 }
735 
rvu_npc_enable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)736 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc,
737 				  int nixlf, bool enable)
738 {
739 	struct npc_mcam *mcam = &rvu->hw->mcam;
740 	int blkaddr, index;
741 
742 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
743 	if (blkaddr < 0)
744 		return;
745 
746 	/* Get 'pcifunc' of PF device */
747 	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
748 
749 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
750 					 nixlf, NIXLF_PROMISC_ENTRY);
751 	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
752 }
753 
rvu_npc_install_bcast_match_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)754 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
755 				       int nixlf, u64 chan)
756 {
757 	struct rvu_pfvf *pfvf;
758 	struct npc_install_flow_req req = { 0 };
759 	struct npc_install_flow_rsp rsp = { 0 };
760 	struct npc_mcam *mcam = &rvu->hw->mcam;
761 	struct rvu_hwinfo *hw = rvu->hw;
762 	int blkaddr, index;
763 
764 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
765 	if (blkaddr < 0)
766 		return;
767 
768 	/* Skip LBK VFs */
769 	if (is_afvf(pcifunc))
770 		return;
771 
772 	/* If pkt replication is not supported,
773 	 * then only PF is allowed to add a bcast match entry.
774 	 */
775 	if (!hw->cap.nix_rx_multicast && is_vf(pcifunc))
776 		return;
777 
778 	/* Get 'pcifunc' of PF device */
779 	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
780 	pfvf = rvu_get_pfvf(rvu, pcifunc);
781 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
782 					 nixlf, NIXLF_BCAST_ENTRY);
783 
784 	if (!hw->cap.nix_rx_multicast) {
785 		/* Early silicon doesn't support pkt replication,
786 		 * so install entry with UCAST action, so that PF
787 		 * receives all broadcast packets.
788 		 */
789 		req.op = NIX_RX_ACTIONOP_UCAST;
790 	} else {
791 		req.op = NIX_RX_ACTIONOP_MCAST;
792 		req.index = pfvf->bcast_mce_idx;
793 	}
794 
795 	eth_broadcast_addr((u8 *)&req.packet.dmac);
796 	eth_broadcast_addr((u8 *)&req.mask.dmac);
797 	req.features = BIT_ULL(NPC_DMAC);
798 	req.channel = chan;
799 	req.chan_mask = 0xFFFU;
800 	req.intf = pfvf->nix_rx_intf;
801 	req.entry = index;
802 	req.hdr.pcifunc = 0; /* AF is requester */
803 	req.vf = pcifunc;
804 
805 	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
806 }
807 
rvu_npc_enable_bcast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)808 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
809 				bool enable)
810 {
811 	struct npc_mcam *mcam = &rvu->hw->mcam;
812 	int blkaddr, index;
813 
814 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
815 	if (blkaddr < 0)
816 		return;
817 
818 	/* Get 'pcifunc' of PF device */
819 	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
820 
821 	index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
822 					 NIXLF_BCAST_ENTRY);
823 	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
824 }
825 
rvu_npc_install_allmulti_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)826 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
827 				    u64 chan)
828 {
829 	struct npc_install_flow_req req = { 0 };
830 	struct npc_install_flow_rsp rsp = { 0 };
831 	struct npc_mcam *mcam = &rvu->hw->mcam;
832 	struct rvu_hwinfo *hw = rvu->hw;
833 	int blkaddr, ucast_idx, index;
834 	u8 mac_addr[ETH_ALEN] = { 0 };
835 	struct nix_rx_action action = { 0 };
836 	struct rvu_pfvf *pfvf;
837 	u16 vf_func;
838 
839 	/* Only CGX PF/VF can add allmulticast entry */
840 	if (is_afvf(pcifunc) && is_sdp_vf(pcifunc))
841 		return;
842 
843 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
844 	if (blkaddr < 0)
845 		return;
846 
847 	/* Get 'pcifunc' of PF device */
848 	vf_func = pcifunc & RVU_PFVF_FUNC_MASK;
849 	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
850 	pfvf = rvu_get_pfvf(rvu, pcifunc);
851 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
852 					 nixlf, NIXLF_ALLMULTI_ENTRY);
853 
854 	/* If the corresponding PF's ucast action is RSS,
855 	 * use the same action for multicast entry also
856 	 */
857 	ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
858 					     nixlf, NIXLF_UCAST_ENTRY);
859 	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
860 		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
861 							blkaddr, ucast_idx);
862 
863 	if (action.op != NIX_RX_ACTIONOP_RSS) {
864 		*(u64 *)&action = 0;
865 		action.op = NIX_RX_ACTIONOP_UCAST;
866 		action.pf_func = pcifunc;
867 	}
868 
869 	/* RX_ACTION set to MCAST for CGX PF's */
870 	if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) {
871 		*(u64 *)&action = 0;
872 		action.op = NIX_RX_ACTIONOP_MCAST;
873 		action.index = pfvf->mcast_mce_idx;
874 	}
875 
876 	mac_addr[0] = 0x01;	/* LSB bit of 1st byte in DMAC */
877 	ether_addr_copy(req.packet.dmac, mac_addr);
878 	ether_addr_copy(req.mask.dmac, mac_addr);
879 	req.features = BIT_ULL(NPC_DMAC);
880 
881 	/* For cn10k the upper two bits of the channel number are
882 	 * cpt channel number. with masking out these bits in the
883 	 * mcam entry, same entry used for NIX will allow packets
884 	 * received from cpt for parsing.
885 	 */
886 	if (!is_rvu_otx2(rvu))
887 		req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
888 	else
889 		req.chan_mask = 0xFFFU;
890 
891 	req.channel = chan;
892 	req.intf = pfvf->nix_rx_intf;
893 	req.entry = index;
894 	req.op = action.op;
895 	req.hdr.pcifunc = 0; /* AF is requester */
896 	req.vf = pcifunc | vf_func;
897 	req.index = action.index;
898 	req.match_id = action.match_id;
899 	req.flow_key_alg = action.flow_key_alg;
900 
901 	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
902 }
903 
rvu_npc_enable_allmulti_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)904 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
905 				   bool enable)
906 {
907 	struct npc_mcam *mcam = &rvu->hw->mcam;
908 	int blkaddr, index;
909 
910 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
911 	if (blkaddr < 0)
912 		return;
913 
914 	/* Get 'pcifunc' of PF device */
915 	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
916 
917 	index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
918 					 NIXLF_ALLMULTI_ENTRY);
919 	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
920 }
921 
npc_update_vf_flow_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc,u64 rx_action)922 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam,
923 				     int blkaddr, u16 pcifunc, u64 rx_action)
924 {
925 	int actindex, index, bank, entry;
926 	struct rvu_npc_mcam_rule *rule;
927 	bool enable, update;
928 
929 	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
930 		return;
931 
932 	mutex_lock(&mcam->lock);
933 	for (index = 0; index < mcam->bmap_entries; index++) {
934 		if (mcam->entry2target_pffunc[index] == pcifunc) {
935 			update = true;
936 			/* update not needed for the rules added via ntuple filters */
937 			list_for_each_entry(rule, &mcam->mcam_rules, list) {
938 				if (rule->entry == index)
939 					update = false;
940 			}
941 			if (!update)
942 				continue;
943 			bank = npc_get_bank(mcam, index);
944 			actindex = index;
945 			entry = index & (mcam->banksize - 1);
946 
947 			/* read vf flow entry enable status */
948 			enable = is_mcam_entry_enabled(rvu, mcam, blkaddr,
949 						       actindex);
950 			/* disable before mcam entry update */
951 			npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex,
952 					      false);
953 			/* update 'action' */
954 			rvu_write64(rvu, blkaddr,
955 				    NPC_AF_MCAMEX_BANKX_ACTION(entry, bank),
956 				    rx_action);
957 			if (enable)
958 				npc_enable_mcam_entry(rvu, mcam, blkaddr,
959 						      actindex, true);
960 		}
961 	}
962 	mutex_unlock(&mcam->lock);
963 }
964 
rvu_npc_update_flowkey_alg_idx(struct rvu * rvu,u16 pcifunc,int nixlf,int group,int alg_idx,int mcam_index)965 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
966 				    int group, int alg_idx, int mcam_index)
967 {
968 	struct npc_mcam *mcam = &rvu->hw->mcam;
969 	struct rvu_hwinfo *hw = rvu->hw;
970 	struct nix_rx_action action;
971 	int blkaddr, index, bank;
972 	struct rvu_pfvf *pfvf;
973 
974 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
975 	if (blkaddr < 0)
976 		return;
977 
978 	/* Check if this is for reserved default entry */
979 	if (mcam_index < 0) {
980 		if (group != DEFAULT_RSS_CONTEXT_GROUP)
981 			return;
982 		index = npc_get_nixlf_mcam_index(mcam, pcifunc,
983 						 nixlf, NIXLF_UCAST_ENTRY);
984 	} else {
985 		/* TODO: validate this mcam index */
986 		index = mcam_index;
987 	}
988 
989 	if (index >= mcam->total_entries)
990 		return;
991 
992 	bank = npc_get_bank(mcam, index);
993 	index &= (mcam->banksize - 1);
994 
995 	*(u64 *)&action = rvu_read64(rvu, blkaddr,
996 				     NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
997 	/* Ignore if no action was set earlier */
998 	if (!*(u64 *)&action)
999 		return;
1000 
1001 	action.op = NIX_RX_ACTIONOP_RSS;
1002 	action.pf_func = pcifunc;
1003 	action.index = group;
1004 	action.flow_key_alg = alg_idx;
1005 
1006 	rvu_write64(rvu, blkaddr,
1007 		    NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
1008 
1009 	/* update the VF flow rule action with the VF default entry action */
1010 	if (mcam_index < 0)
1011 		npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc,
1012 					 *(u64 *)&action);
1013 
1014 	/* update the action change in default rule */
1015 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1016 	if (pfvf->def_ucast_rule)
1017 		pfvf->def_ucast_rule->rx_action = action;
1018 
1019 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1020 					 nixlf, NIXLF_PROMISC_ENTRY);
1021 
1022 	/* If PF's promiscuous entry is enabled,
1023 	 * Set RSS action for that entry as well
1024 	 */
1025 	if ((!hw->cap.nix_rx_multicast || !pfvf->use_mce_list) &&
1026 	    is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
1027 		bank = npc_get_bank(mcam, index);
1028 		index &= (mcam->banksize - 1);
1029 
1030 		rvu_write64(rvu, blkaddr,
1031 			    NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
1032 			    *(u64 *)&action);
1033 	}
1034 }
1035 
npc_enadis_default_mce_entry(struct rvu * rvu,u16 pcifunc,int nixlf,int type,bool enable)1036 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
1037 				  int nixlf, int type, bool enable)
1038 {
1039 	struct npc_mcam *mcam = &rvu->hw->mcam;
1040 	struct rvu_hwinfo *hw = rvu->hw;
1041 	struct nix_mce_list *mce_list;
1042 	int index, blkaddr, mce_idx;
1043 	struct rvu_pfvf *pfvf;
1044 
1045 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1046 	if (blkaddr < 0)
1047 		return;
1048 
1049 	index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
1050 					 nixlf, type);
1051 
1052 	/* disable MCAM entry when packet replication is not supported by hw */
1053 	if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) {
1054 		npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1055 		return;
1056 	}
1057 
1058 	/* return incase mce list is not enabled */
1059 	pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1060 	if (hw->cap.nix_rx_multicast && is_vf(pcifunc) &&
1061 	    type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list)
1062 		return;
1063 
1064 	nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx);
1065 
1066 	nix_update_mce_list(rvu, pcifunc, mce_list,
1067 			    mce_idx, index, enable);
1068 	if (enable)
1069 		npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1070 }
1071 
npc_enadis_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)1072 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
1073 				       int nixlf, bool enable)
1074 {
1075 	struct npc_mcam *mcam = &rvu->hw->mcam;
1076 	int index, blkaddr;
1077 
1078 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1079 	if (blkaddr < 0)
1080 		return;
1081 
1082 	/* Ucast MCAM match entry of this PF/VF */
1083 	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1084 					 nixlf, NIXLF_UCAST_ENTRY);
1085 	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1086 
1087 	/* Nothing to do for VFs, on platforms where pkt replication
1088 	 * is not supported
1089 	 */
1090 	if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast)
1091 		return;
1092 
1093 	/* add/delete pf_func to broadcast MCE list */
1094 	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1095 				     NIXLF_BCAST_ENTRY, enable);
1096 }
1097 
rvu_npc_disable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1098 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1099 {
1100 	if (nixlf < 0)
1101 		return;
1102 
1103 	npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
1104 
1105 	/* Delete multicast and promisc MCAM entries */
1106 	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1107 				     NIXLF_ALLMULTI_ENTRY, false);
1108 	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1109 				     NIXLF_PROMISC_ENTRY, false);
1110 }
1111 
rvu_npc_enable_mcam_by_entry_index(struct rvu * rvu,int entry,int intf,bool enable)1112 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable)
1113 {
1114 	int blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1115 	struct npc_mcam *mcam = &rvu->hw->mcam;
1116 	struct rvu_npc_mcam_rule *rule, *tmp;
1117 
1118 	mutex_lock(&mcam->lock);
1119 
1120 	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1121 		if (rule->intf != intf)
1122 			continue;
1123 
1124 		if (rule->entry != entry)
1125 			continue;
1126 
1127 		rule->enable = enable;
1128 		mutex_unlock(&mcam->lock);
1129 
1130 		npc_enable_mcam_entry(rvu, mcam, blkaddr,
1131 				      entry, enable);
1132 
1133 		return true;
1134 	}
1135 
1136 	mutex_unlock(&mcam->lock);
1137 	return false;
1138 }
1139 
rvu_npc_enable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1140 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1141 {
1142 	if (nixlf < 0)
1143 		return;
1144 
1145 	/* Enables only broadcast match entry. Promisc/Allmulti are enabled
1146 	 * in set_rx_mode mbox handler.
1147 	 */
1148 	npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
1149 }
1150 
rvu_npc_disable_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1151 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1152 {
1153 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1154 	struct npc_mcam *mcam = &rvu->hw->mcam;
1155 	struct rvu_npc_mcam_rule *rule, *tmp;
1156 	int blkaddr;
1157 
1158 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1159 	if (blkaddr < 0)
1160 		return;
1161 
1162 	mutex_lock(&mcam->lock);
1163 
1164 	/* Disable MCAM entries directing traffic to this 'pcifunc' */
1165 	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1166 		if (is_npc_intf_rx(rule->intf) &&
1167 		    rule->rx_action.pf_func == pcifunc &&
1168 		    rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) {
1169 			npc_enable_mcam_entry(rvu, mcam, blkaddr,
1170 					      rule->entry, false);
1171 			rule->enable = false;
1172 			/* Indicate that default rule is disabled */
1173 			if (rule->default_rule) {
1174 				pfvf->def_ucast_rule = NULL;
1175 				list_del(&rule->list);
1176 				kfree(rule);
1177 			}
1178 		}
1179 	}
1180 
1181 	mutex_unlock(&mcam->lock);
1182 
1183 	npc_mcam_disable_flows(rvu, pcifunc);
1184 
1185 	rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1186 }
1187 
rvu_npc_free_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1188 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1189 {
1190 	struct npc_mcam *mcam = &rvu->hw->mcam;
1191 	struct rvu_npc_mcam_rule *rule, *tmp;
1192 	int blkaddr;
1193 
1194 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1195 	if (blkaddr < 0)
1196 		return;
1197 
1198 	mutex_lock(&mcam->lock);
1199 
1200 	/* Free all MCAM entries owned by this 'pcifunc' */
1201 	npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1202 
1203 	/* Free all MCAM counters owned by this 'pcifunc' */
1204 	npc_mcam_free_all_counters(rvu, mcam, pcifunc);
1205 
1206 	/* Delete MCAM entries owned by this 'pcifunc' */
1207 	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1208 		if (rule->owner == pcifunc && !rule->default_rule) {
1209 			list_del(&rule->list);
1210 			kfree(rule);
1211 		}
1212 	}
1213 
1214 	mutex_unlock(&mcam->lock);
1215 
1216 	rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1217 }
1218 
npc_program_mkex_rx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1219 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr,
1220 				struct npc_mcam_kex *mkex, u8 intf)
1221 {
1222 	int lid, lt, ld, fl;
1223 
1224 	if (is_npc_intf_tx(intf))
1225 		return;
1226 
1227 	rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1228 		    mkex->keyx_cfg[NIX_INTF_RX]);
1229 
1230 	/* Program LDATA */
1231 	for (lid = 0; lid < NPC_MAX_LID; lid++) {
1232 		for (lt = 0; lt < NPC_MAX_LT; lt++) {
1233 			for (ld = 0; ld < NPC_MAX_LD; ld++)
1234 				SET_KEX_LD(intf, lid, lt, ld,
1235 					   mkex->intf_lid_lt_ld[NIX_INTF_RX]
1236 					   [lid][lt][ld]);
1237 		}
1238 	}
1239 	/* Program LFLAGS */
1240 	for (ld = 0; ld < NPC_MAX_LD; ld++) {
1241 		for (fl = 0; fl < NPC_MAX_LFL; fl++)
1242 			SET_KEX_LDFLAGS(intf, ld, fl,
1243 					mkex->intf_ld_flags[NIX_INTF_RX]
1244 					[ld][fl]);
1245 	}
1246 }
1247 
npc_program_mkex_tx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1248 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr,
1249 				struct npc_mcam_kex *mkex, u8 intf)
1250 {
1251 	int lid, lt, ld, fl;
1252 
1253 	if (is_npc_intf_rx(intf))
1254 		return;
1255 
1256 	rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1257 		    mkex->keyx_cfg[NIX_INTF_TX]);
1258 
1259 	/* Program LDATA */
1260 	for (lid = 0; lid < NPC_MAX_LID; lid++) {
1261 		for (lt = 0; lt < NPC_MAX_LT; lt++) {
1262 			for (ld = 0; ld < NPC_MAX_LD; ld++)
1263 				SET_KEX_LD(intf, lid, lt, ld,
1264 					   mkex->intf_lid_lt_ld[NIX_INTF_TX]
1265 					   [lid][lt][ld]);
1266 		}
1267 	}
1268 	/* Program LFLAGS */
1269 	for (ld = 0; ld < NPC_MAX_LD; ld++) {
1270 		for (fl = 0; fl < NPC_MAX_LFL; fl++)
1271 			SET_KEX_LDFLAGS(intf, ld, fl,
1272 					mkex->intf_ld_flags[NIX_INTF_TX]
1273 					[ld][fl]);
1274 	}
1275 }
1276 
npc_program_mkex_profile(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex)1277 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
1278 				     struct npc_mcam_kex *mkex)
1279 {
1280 	struct rvu_hwinfo *hw = rvu->hw;
1281 	u8 intf;
1282 	int ld;
1283 
1284 	for (ld = 0; ld < NPC_MAX_LD; ld++)
1285 		rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
1286 			    mkex->kex_ld_flags[ld]);
1287 
1288 	for (intf = 0; intf < hw->npc_intfs; intf++) {
1289 		npc_program_mkex_rx(rvu, blkaddr, mkex, intf);
1290 		npc_program_mkex_tx(rvu, blkaddr, mkex, intf);
1291 	}
1292 
1293 	/* Programme mkex hash profile */
1294 	npc_program_mkex_hash(rvu, blkaddr);
1295 }
1296 
npc_fwdb_prfl_img_map(struct rvu * rvu,void __iomem ** prfl_img_addr,u64 * size)1297 static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr,
1298 				 u64 *size)
1299 {
1300 	u64 prfl_addr, prfl_sz;
1301 
1302 	if (!rvu->fwdata)
1303 		return -EINVAL;
1304 
1305 	prfl_addr = rvu->fwdata->mcam_addr;
1306 	prfl_sz = rvu->fwdata->mcam_sz;
1307 
1308 	if (!prfl_addr || !prfl_sz)
1309 		return -EINVAL;
1310 
1311 	*prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz);
1312 	if (!(*prfl_img_addr))
1313 		return -ENOMEM;
1314 
1315 	*size = prfl_sz;
1316 
1317 	return 0;
1318 }
1319 
1320 /* strtoull of "mkexprof" with base:36 */
1321 #define MKEX_END_SIGN  0xdeadbeef
1322 
npc_load_mkex_profile(struct rvu * rvu,int blkaddr,const char * mkex_profile)1323 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
1324 				  const char *mkex_profile)
1325 {
1326 	struct device *dev = &rvu->pdev->dev;
1327 	struct npc_mcam_kex *mcam_kex;
1328 	void __iomem *mkex_prfl_addr = NULL;
1329 	u64 prfl_sz;
1330 	int ret;
1331 
1332 	/* If user not selected mkex profile */
1333 	if (rvu->kpu_fwdata_sz ||
1334 	    !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
1335 		goto program_mkex;
1336 
1337 	/* Setting up the mapping for mkex profile image */
1338 	ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz);
1339 	if (ret < 0)
1340 		goto program_mkex;
1341 
1342 	mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr;
1343 
1344 	while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
1345 		/* Compare with mkex mod_param name string */
1346 		if (mcam_kex->mkex_sign == MKEX_SIGN &&
1347 		    !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
1348 			/* Due to an errata (35786) in A0/B0 pass silicon,
1349 			 * parse nibble enable configuration has to be
1350 			 * identical for both Rx and Tx interfaces.
1351 			 */
1352 			if (!is_rvu_96xx_B0(rvu) ||
1353 			    mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
1354 				rvu->kpu.mkex = mcam_kex;
1355 			goto program_mkex;
1356 		}
1357 
1358 		mcam_kex++;
1359 		prfl_sz -= sizeof(struct npc_mcam_kex);
1360 	}
1361 	dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
1362 
1363 program_mkex:
1364 	dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
1365 	/* Program selected mkex profile */
1366 	npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
1367 	if (mkex_prfl_addr)
1368 		iounmap(mkex_prfl_addr);
1369 }
1370 
npc_config_kpuaction(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_action * kpuaction,int kpu,int entry,bool pkind)1371 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
1372 				 const struct npc_kpu_profile_action *kpuaction,
1373 				 int kpu, int entry, bool pkind)
1374 {
1375 	struct npc_kpu_action0 action0 = {0};
1376 	struct npc_kpu_action1 action1 = {0};
1377 	u64 reg;
1378 
1379 	action1.errlev = kpuaction->errlev;
1380 	action1.errcode = kpuaction->errcode;
1381 	action1.dp0_offset = kpuaction->dp0_offset;
1382 	action1.dp1_offset = kpuaction->dp1_offset;
1383 	action1.dp2_offset = kpuaction->dp2_offset;
1384 
1385 	if (pkind)
1386 		reg = NPC_AF_PKINDX_ACTION1(entry);
1387 	else
1388 		reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
1389 
1390 	rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
1391 
1392 	action0.byp_count = kpuaction->bypass_count;
1393 	action0.capture_ena = kpuaction->cap_ena;
1394 	action0.parse_done = kpuaction->parse_done;
1395 	action0.next_state = kpuaction->next_state;
1396 	action0.capture_lid = kpuaction->lid;
1397 	action0.capture_ltype = kpuaction->ltype;
1398 	action0.capture_flags = kpuaction->flags;
1399 	action0.ptr_advance = kpuaction->ptr_advance;
1400 	action0.var_len_offset = kpuaction->offset;
1401 	action0.var_len_mask = kpuaction->mask;
1402 	action0.var_len_right = kpuaction->right;
1403 	action0.var_len_shift = kpuaction->shift;
1404 
1405 	if (pkind)
1406 		reg = NPC_AF_PKINDX_ACTION0(entry);
1407 	else
1408 		reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
1409 
1410 	rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
1411 }
1412 
npc_config_kpucam(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_cam * kpucam,int kpu,int entry)1413 static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
1414 			      const struct npc_kpu_profile_cam *kpucam,
1415 			      int kpu, int entry)
1416 {
1417 	struct npc_kpu_cam cam0 = {0};
1418 	struct npc_kpu_cam cam1 = {0};
1419 
1420 	cam1.state = kpucam->state & kpucam->state_mask;
1421 	cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
1422 	cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
1423 	cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
1424 
1425 	cam0.state = ~kpucam->state & kpucam->state_mask;
1426 	cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
1427 	cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
1428 	cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
1429 
1430 	rvu_write64(rvu, blkaddr,
1431 		    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
1432 	rvu_write64(rvu, blkaddr,
1433 		    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
1434 }
1435 
enable_mask(int count)1436 static inline u64 enable_mask(int count)
1437 {
1438 	return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
1439 }
1440 
npc_program_kpu_profile(struct rvu * rvu,int blkaddr,int kpu,const struct npc_kpu_profile * profile)1441 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
1442 				    const struct npc_kpu_profile *profile)
1443 {
1444 	int entry, num_entries, max_entries;
1445 	u64 entry_mask;
1446 
1447 	if (profile->cam_entries != profile->action_entries) {
1448 		dev_err(rvu->dev,
1449 			"KPU%d: CAM and action entries [%d != %d] not equal\n",
1450 			kpu, profile->cam_entries, profile->action_entries);
1451 	}
1452 
1453 	max_entries = rvu->hw->npc_kpu_entries;
1454 
1455 	/* Program CAM match entries for previous KPU extracted data */
1456 	num_entries = min_t(int, profile->cam_entries, max_entries);
1457 	for (entry = 0; entry < num_entries; entry++)
1458 		npc_config_kpucam(rvu, blkaddr,
1459 				  &profile->cam[entry], kpu, entry);
1460 
1461 	/* Program this KPU's actions */
1462 	num_entries = min_t(int, profile->action_entries, max_entries);
1463 	for (entry = 0; entry < num_entries; entry++)
1464 		npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
1465 				     kpu, entry, false);
1466 
1467 	/* Enable all programmed entries */
1468 	num_entries = min_t(int, profile->action_entries, profile->cam_entries);
1469 	entry_mask = enable_mask(num_entries);
1470 	/* Disable first KPU_MAX_CST_ENT entries for built-in profile */
1471 	if (!rvu->kpu.custom)
1472 		entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0);
1473 	rvu_write64(rvu, blkaddr,
1474 		    NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask);
1475 	if (num_entries > 64) {
1476 		rvu_write64(rvu, blkaddr,
1477 			    NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
1478 			    enable_mask(num_entries - 64));
1479 	}
1480 
1481 	/* Enable this KPU */
1482 	rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
1483 }
1484 
npc_prepare_default_kpu(struct npc_kpu_profile_adapter * profile)1485 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
1486 {
1487 	profile->custom = 0;
1488 	profile->name = def_pfl_name;
1489 	profile->version = NPC_KPU_PROFILE_VER;
1490 	profile->ikpu = ikpu_action_entries;
1491 	profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
1492 	profile->kpu = npc_kpu_profiles;
1493 	profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
1494 	profile->lt_def = &npc_lt_defaults;
1495 	profile->mkex = &npc_mkex_default;
1496 	profile->mkex_hash = &npc_mkex_hash_default;
1497 
1498 	return 0;
1499 }
1500 
npc_apply_custom_kpu(struct rvu * rvu,struct npc_kpu_profile_adapter * profile)1501 static int npc_apply_custom_kpu(struct rvu *rvu,
1502 				struct npc_kpu_profile_adapter *profile)
1503 {
1504 	size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0;
1505 	struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata;
1506 	struct npc_kpu_profile_action *action;
1507 	struct npc_kpu_profile_cam *cam;
1508 	struct npc_kpu_fwdata *fw_kpu;
1509 	int entries;
1510 	u16 kpu, entry;
1511 
1512 	if (rvu->kpu_fwdata_sz < hdr_sz) {
1513 		dev_warn(rvu->dev, "Invalid KPU profile size\n");
1514 		return -EINVAL;
1515 	}
1516 	if (le64_to_cpu(fw->signature) != KPU_SIGN) {
1517 		dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n",
1518 			 fw->signature);
1519 		return -EINVAL;
1520 	}
1521 	/* Verify if the using known profile structure */
1522 	if (NPC_KPU_VER_MAJ(profile->version) >
1523 	    NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) {
1524 		dev_warn(rvu->dev, "Not supported Major version: %d > %d\n",
1525 			 NPC_KPU_VER_MAJ(profile->version),
1526 			 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER));
1527 		return -EINVAL;
1528 	}
1529 	/* Verify if profile is aligned with the required kernel changes */
1530 	if (NPC_KPU_VER_MIN(profile->version) <
1531 	    NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) {
1532 		dev_warn(rvu->dev,
1533 			 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n",
1534 			 NPC_KPU_VER_MAJ(profile->version),
1535 			 NPC_KPU_VER_MIN(profile->version),
1536 			 NPC_KPU_VER_PATCH(profile->version),
1537 			 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER),
1538 			 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER),
1539 			 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER));
1540 		return -EINVAL;
1541 	}
1542 	/* Verify if profile fits the HW */
1543 	if (fw->kpus > profile->kpus) {
1544 		dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus,
1545 			 profile->kpus);
1546 		return -EINVAL;
1547 	}
1548 
1549 	profile->custom = 1;
1550 	profile->name = fw->name;
1551 	profile->version = le64_to_cpu(fw->version);
1552 	profile->mkex = &fw->mkex;
1553 	profile->lt_def = &fw->lt_def;
1554 
1555 	for (kpu = 0; kpu < fw->kpus; kpu++) {
1556 		fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset);
1557 		if (fw_kpu->entries > KPU_MAX_CST_ENT)
1558 			dev_warn(rvu->dev,
1559 				 "Too many custom entries on KPU%d: %d > %d\n",
1560 				 kpu, fw_kpu->entries, KPU_MAX_CST_ENT);
1561 		entries = min(fw_kpu->entries, KPU_MAX_CST_ENT);
1562 		cam = (struct npc_kpu_profile_cam *)fw_kpu->data;
1563 		offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam);
1564 		action = (struct npc_kpu_profile_action *)(fw->data + offset);
1565 		offset += fw_kpu->entries * sizeof(*action);
1566 		if (rvu->kpu_fwdata_sz < hdr_sz + offset) {
1567 			dev_warn(rvu->dev,
1568 				 "Profile size mismatch on KPU%i parsing.\n",
1569 				 kpu + 1);
1570 			return -EINVAL;
1571 		}
1572 		for (entry = 0; entry < entries; entry++) {
1573 			profile->kpu[kpu].cam[entry] = cam[entry];
1574 			profile->kpu[kpu].action[entry] = action[entry];
1575 		}
1576 	}
1577 
1578 	return 0;
1579 }
1580 
npc_load_kpu_prfl_img(struct rvu * rvu,void __iomem * prfl_addr,u64 prfl_sz,const char * kpu_profile)1581 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr,
1582 				 u64 prfl_sz, const char *kpu_profile)
1583 {
1584 	struct npc_kpu_profile_fwdata *kpu_data = NULL;
1585 	int rc = -EINVAL;
1586 
1587 	kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr;
1588 	if (le64_to_cpu(kpu_data->signature) == KPU_SIGN &&
1589 	    !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) {
1590 		dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n",
1591 			 kpu_profile);
1592 		rvu->kpu_fwdata = kpu_data;
1593 		rvu->kpu_fwdata_sz = prfl_sz;
1594 		rvu->kpu_prfl_addr = prfl_addr;
1595 		rc = 0;
1596 	}
1597 
1598 	return rc;
1599 }
1600 
npc_fwdb_detect_load_prfl_img(struct rvu * rvu,uint64_t prfl_sz,const char * kpu_profile)1601 static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz,
1602 					 const char *kpu_profile)
1603 {
1604 	struct npc_coalesced_kpu_prfl *img_data = NULL;
1605 	int i = 0, rc = -EINVAL;
1606 	void __iomem *kpu_prfl_addr;
1607 	u16 offset;
1608 
1609 	img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr;
1610 	if (le64_to_cpu(img_data->signature) == KPU_SIGN &&
1611 	    !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) {
1612 		/* Loaded profile is a single KPU profile. */
1613 		rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr,
1614 					   prfl_sz, kpu_profile);
1615 		goto done;
1616 	}
1617 
1618 	/* Loaded profile is coalesced image, offset of first KPU profile.*/
1619 	offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) +
1620 		(img_data->num_prfl * sizeof(uint16_t));
1621 	/* Check if mapped image is coalesced image. */
1622 	while (i < img_data->num_prfl) {
1623 		/* Profile image offsets are rounded up to next 8 multiple.*/
1624 		offset = ALIGN_8B_CEIL(offset);
1625 		kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr +
1626 					 offset);
1627 		rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr,
1628 					   img_data->prfl_sz[i], kpu_profile);
1629 		if (!rc)
1630 			break;
1631 		/* Calculating offset of profile image based on profile size.*/
1632 		offset += img_data->prfl_sz[i];
1633 		i++;
1634 	}
1635 done:
1636 	return rc;
1637 }
1638 
npc_load_kpu_profile_fwdb(struct rvu * rvu,const char * kpu_profile)1639 static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile)
1640 {
1641 	int ret = -EINVAL;
1642 	u64 prfl_sz;
1643 
1644 	/* Setting up the mapping for NPC profile image */
1645 	ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz);
1646 	if (ret < 0)
1647 		goto done;
1648 
1649 	/* Detect if profile is coalesced or single KPU profile and load */
1650 	ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile);
1651 	if (ret == 0)
1652 		goto done;
1653 
1654 	/* Cleaning up if KPU profile image from fwdata is not valid. */
1655 	if (rvu->kpu_prfl_addr) {
1656 		iounmap(rvu->kpu_prfl_addr);
1657 		rvu->kpu_prfl_addr = NULL;
1658 		rvu->kpu_fwdata_sz = 0;
1659 		rvu->kpu_fwdata = NULL;
1660 	}
1661 
1662 done:
1663 	return ret;
1664 }
1665 
npc_load_kpu_profile(struct rvu * rvu)1666 static void npc_load_kpu_profile(struct rvu *rvu)
1667 {
1668 	struct npc_kpu_profile_adapter *profile = &rvu->kpu;
1669 	const char *kpu_profile = rvu->kpu_pfl_name;
1670 	const struct firmware *fw = NULL;
1671 	bool retry_fwdb = false;
1672 
1673 	/* If user not specified profile customization */
1674 	if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN))
1675 		goto revert_to_default;
1676 	/* First prepare default KPU, then we'll customize top entries. */
1677 	npc_prepare_default_kpu(profile);
1678 
1679 	/* Order of preceedence for load loading NPC profile (high to low)
1680 	 * Firmware binary in filesystem.
1681 	 * Firmware database method.
1682 	 * Default KPU profile.
1683 	 */
1684 	if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) {
1685 		dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n",
1686 			 kpu_profile);
1687 		rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL);
1688 		if (rvu->kpu_fwdata) {
1689 			memcpy(rvu->kpu_fwdata, fw->data, fw->size);
1690 			rvu->kpu_fwdata_sz = fw->size;
1691 		}
1692 		release_firmware(fw);
1693 		retry_fwdb = true;
1694 		goto program_kpu;
1695 	}
1696 
1697 load_image_fwdb:
1698 	/* Loading the KPU profile using firmware database */
1699 	if (npc_load_kpu_profile_fwdb(rvu, kpu_profile))
1700 		goto revert_to_default;
1701 
1702 program_kpu:
1703 	/* Apply profile customization if firmware was loaded. */
1704 	if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) {
1705 		/* If image from firmware filesystem fails to load or invalid
1706 		 * retry with firmware database method.
1707 		 */
1708 		if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) {
1709 			/* Loading image from firmware database failed. */
1710 			if (rvu->kpu_prfl_addr) {
1711 				iounmap(rvu->kpu_prfl_addr);
1712 				rvu->kpu_prfl_addr = NULL;
1713 			} else {
1714 				kfree(rvu->kpu_fwdata);
1715 			}
1716 			rvu->kpu_fwdata = NULL;
1717 			rvu->kpu_fwdata_sz = 0;
1718 			if (retry_fwdb) {
1719 				retry_fwdb = false;
1720 				goto load_image_fwdb;
1721 			}
1722 		}
1723 
1724 		dev_warn(rvu->dev,
1725 			 "Can't load KPU profile %s. Using default.\n",
1726 			 kpu_profile);
1727 		kfree(rvu->kpu_fwdata);
1728 		rvu->kpu_fwdata = NULL;
1729 		goto revert_to_default;
1730 	}
1731 
1732 	dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n",
1733 		 profile->name, NPC_KPU_VER_MAJ(profile->version),
1734 		 NPC_KPU_VER_MIN(profile->version),
1735 		 NPC_KPU_VER_PATCH(profile->version));
1736 
1737 	return;
1738 
1739 revert_to_default:
1740 	npc_prepare_default_kpu(profile);
1741 }
1742 
npc_parser_profile_init(struct rvu * rvu,int blkaddr)1743 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
1744 {
1745 	struct rvu_hwinfo *hw = rvu->hw;
1746 	int num_pkinds, num_kpus, idx;
1747 
1748 	/* Disable all KPUs and their entries */
1749 	for (idx = 0; idx < hw->npc_kpus; idx++) {
1750 		rvu_write64(rvu, blkaddr,
1751 			    NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
1752 		rvu_write64(rvu, blkaddr,
1753 			    NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1754 		rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1755 	}
1756 
1757 	/* Load and customize KPU profile. */
1758 	npc_load_kpu_profile(rvu);
1759 
1760 	/* First program IKPU profile i.e PKIND configs.
1761 	 * Check HW max count to avoid configuring junk or
1762 	 * writing to unsupported CSR addresses.
1763 	 */
1764 	num_pkinds = rvu->kpu.pkinds;
1765 	num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds);
1766 
1767 	for (idx = 0; idx < num_pkinds; idx++)
1768 		npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
1769 
1770 	/* Program KPU CAM and Action profiles */
1771 	num_kpus = rvu->kpu.kpus;
1772 	num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1773 
1774 	for (idx = 0; idx < num_kpus; idx++)
1775 		npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
1776 }
1777 
npc_mcam_rsrcs_init(struct rvu * rvu,int blkaddr)1778 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1779 {
1780 	int nixlf_count = rvu_get_nixlf_count(rvu);
1781 	struct npc_mcam *mcam = &rvu->hw->mcam;
1782 	int rsvd, err;
1783 	u16 index;
1784 	int cntr;
1785 	u64 cfg;
1786 
1787 	/* Actual number of MCAM entries vary by entry size */
1788 	cfg = (rvu_read64(rvu, blkaddr,
1789 			  NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1790 	mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1791 	mcam->keysize = cfg;
1792 
1793 	/* Number of banks combined per MCAM entry */
1794 	if (cfg == NPC_MCAM_KEY_X4)
1795 		mcam->banks_per_entry = 4;
1796 	else if (cfg == NPC_MCAM_KEY_X2)
1797 		mcam->banks_per_entry = 2;
1798 	else
1799 		mcam->banks_per_entry = 1;
1800 
1801 	/* Reserve one MCAM entry for each of the NIX LF to
1802 	 * guarantee space to install default matching DMAC rule.
1803 	 * Also reserve 2 MCAM entries for each PF for default
1804 	 * channel based matching or 'bcast & promisc' matching to
1805 	 * support BCAST and PROMISC modes of operation for PFs.
1806 	 * PF0 is excluded.
1807 	 */
1808 	rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1809 		((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1810 	if (mcam->total_entries <= rsvd) {
1811 		dev_warn(rvu->dev,
1812 			 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1813 			 mcam->total_entries);
1814 		return -ENOMEM;
1815 	}
1816 
1817 	mcam->bmap_entries = mcam->total_entries - rsvd;
1818 	mcam->nixlf_offset = mcam->bmap_entries;
1819 	mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1820 
1821 	/* Allocate bitmaps for managing MCAM entries */
1822 	mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1823 				  sizeof(long), GFP_KERNEL);
1824 	if (!mcam->bmap)
1825 		return -ENOMEM;
1826 
1827 	mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1828 					  BITS_TO_LONGS(mcam->bmap_entries),
1829 					  sizeof(long), GFP_KERNEL);
1830 	if (!mcam->bmap_reverse)
1831 		return -ENOMEM;
1832 
1833 	mcam->bmap_fcnt = mcam->bmap_entries;
1834 
1835 	/* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1836 	mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1837 					    sizeof(u16), GFP_KERNEL);
1838 	if (!mcam->entry2pfvf_map)
1839 		return -ENOMEM;
1840 
1841 	/* Reserve 1/8th of MCAM entries at the bottom for low priority
1842 	 * allocations and another 1/8th at the top for high priority
1843 	 * allocations.
1844 	 */
1845 	mcam->lprio_count = mcam->bmap_entries / 8;
1846 	if (mcam->lprio_count > BITS_PER_LONG)
1847 		mcam->lprio_count = round_down(mcam->lprio_count,
1848 					       BITS_PER_LONG);
1849 	mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1850 	mcam->hprio_count = mcam->lprio_count;
1851 	mcam->hprio_end = mcam->hprio_count;
1852 
1853 	/* Allocate bitmap for managing MCAM counters and memory
1854 	 * for saving counter to RVU PFFUNC allocation mapping.
1855 	 */
1856 	err = rvu_alloc_bitmap(&mcam->counters);
1857 	if (err)
1858 		return err;
1859 
1860 	mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1861 					   sizeof(u16), GFP_KERNEL);
1862 	if (!mcam->cntr2pfvf_map)
1863 		goto free_mem;
1864 
1865 	/* Alloc memory for MCAM entry to counter mapping and for tracking
1866 	 * counter's reference count.
1867 	 */
1868 	mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1869 					    sizeof(u16), GFP_KERNEL);
1870 	if (!mcam->entry2cntr_map)
1871 		goto free_mem;
1872 
1873 	mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1874 					 sizeof(u16), GFP_KERNEL);
1875 	if (!mcam->cntr_refcnt)
1876 		goto free_mem;
1877 
1878 	/* Alloc memory for saving target device of mcam rule */
1879 	mcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries,
1880 						 sizeof(u16), GFP_KERNEL);
1881 	if (!mcam->entry2target_pffunc)
1882 		goto free_mem;
1883 
1884 	for (index = 0; index < mcam->bmap_entries; index++) {
1885 		mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1886 		mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1887 	}
1888 
1889 	for (cntr = 0; cntr < mcam->counters.max; cntr++)
1890 		mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1891 
1892 	mutex_init(&mcam->lock);
1893 
1894 	return 0;
1895 
1896 free_mem:
1897 	kfree(mcam->counters.bmap);
1898 	return -ENOMEM;
1899 }
1900 
rvu_npc_hw_init(struct rvu * rvu,int blkaddr)1901 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr)
1902 {
1903 	struct npc_pkind *pkind = &rvu->hw->pkind;
1904 	struct npc_mcam *mcam = &rvu->hw->mcam;
1905 	struct rvu_hwinfo *hw = rvu->hw;
1906 	u64 npc_const, npc_const1;
1907 	u64 npc_const2 = 0;
1908 
1909 	npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1910 	npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1);
1911 	if (npc_const1 & BIT_ULL(63))
1912 		npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
1913 
1914 	pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT;
1915 	hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL;
1916 	hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
1917 	hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
1918 	hw->npc_intfs = npc_const & 0xFULL;
1919 	hw->npc_counters = (npc_const >> 48) & 0xFFFFULL;
1920 
1921 	mcam->banks = (npc_const >> 44) & 0xFULL;
1922 	mcam->banksize = (npc_const >> 28) & 0xFFFFULL;
1923 	hw->npc_stat_ena = BIT_ULL(9);
1924 	/* Extended set */
1925 	if (npc_const2) {
1926 		hw->npc_ext_set = true;
1927 		/* 96xx supports only match_stats and npc_counters
1928 		 * reflected in NPC_AF_CONST reg.
1929 		 * STAT_SEL and ENA are at [0:8] and 9 bit positions.
1930 		 * 98xx has both match_stat and ext and npc_counter
1931 		 * reflected in NPC_AF_CONST2
1932 		 * STAT_SEL_EXT added at [12:14] bit position.
1933 		 * cn10k supports only ext and hence npc_counters in
1934 		 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2.
1935 		 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63
1936 		 */
1937 		if (!hw->npc_counters)
1938 			hw->npc_stat_ena = BIT_ULL(63);
1939 		hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL;
1940 		mcam->banksize = npc_const2 & 0xFFFFULL;
1941 	}
1942 
1943 	mcam->counters.max = hw->npc_counters;
1944 }
1945 
rvu_npc_setup_interfaces(struct rvu * rvu,int blkaddr)1946 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)
1947 {
1948 	struct npc_mcam_kex *mkex = rvu->kpu.mkex;
1949 	struct npc_mcam *mcam = &rvu->hw->mcam;
1950 	struct rvu_hwinfo *hw = rvu->hw;
1951 	u64 nibble_ena, rx_kex, tx_kex;
1952 	u8 intf;
1953 
1954 	/* Reserve last counter for MCAM RX miss action which is set to
1955 	 * drop packet. This way we will know how many pkts didn't match
1956 	 * any MCAM entry.
1957 	 */
1958 	mcam->counters.max--;
1959 	mcam->rx_miss_act_cntr = mcam->counters.max;
1960 
1961 	rx_kex = mkex->keyx_cfg[NIX_INTF_RX];
1962 	tx_kex = mkex->keyx_cfg[NIX_INTF_TX];
1963 	nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
1964 
1965 	nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);
1966 	if (nibble_ena) {
1967 		tx_kex &= ~NPC_PARSE_NIBBLE;
1968 		tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
1969 		mkex->keyx_cfg[NIX_INTF_TX] = tx_kex;
1970 	}
1971 
1972 	/* Configure RX interfaces */
1973 	for (intf = 0; intf < hw->npc_intfs; intf++) {
1974 		if (is_npc_intf_tx(intf))
1975 			continue;
1976 
1977 		/* Set RX MCAM search key size. LA..LE (ltype only) + Channel */
1978 		rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1979 			    rx_kex);
1980 
1981 		/* If MCAM lookup doesn't result in a match, drop the received
1982 		 * packet. And map this action to a counter to count dropped
1983 		 * packets.
1984 		 */
1985 		rvu_write64(rvu, blkaddr,
1986 			    NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);
1987 
1988 		/* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]
1989 		 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]
1990 		 */
1991 		rvu_write64(rvu, blkaddr,
1992 			    NPC_AF_INTFX_MISS_STAT_ACT(intf),
1993 			    ((mcam->rx_miss_act_cntr >> 9) << 12) |
1994 			    hw->npc_stat_ena | mcam->rx_miss_act_cntr);
1995 	}
1996 
1997 	/* Configure TX interfaces */
1998 	for (intf = 0; intf < hw->npc_intfs; intf++) {
1999 		if (is_npc_intf_rx(intf))
2000 			continue;
2001 
2002 		/* Extract Ltypes LID_LA to LID_LE */
2003 		rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
2004 			    tx_kex);
2005 
2006 		/* Set TX miss action to UCAST_DEFAULT i.e
2007 		 * transmit the packet on NIX LF SQ's default channel.
2008 		 */
2009 		rvu_write64(rvu, blkaddr,
2010 			    NPC_AF_INTFX_MISS_ACT(intf),
2011 			    NIX_TX_ACTIONOP_UCAST_DEFAULT);
2012 	}
2013 }
2014 
rvu_npc_init(struct rvu * rvu)2015 int rvu_npc_init(struct rvu *rvu)
2016 {
2017 	struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
2018 	struct npc_pkind *pkind = &rvu->hw->pkind;
2019 	struct npc_mcam *mcam = &rvu->hw->mcam;
2020 	int blkaddr, entry, bank, err;
2021 
2022 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2023 	if (blkaddr < 0) {
2024 		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
2025 		return -ENODEV;
2026 	}
2027 
2028 	rvu_npc_hw_init(rvu, blkaddr);
2029 
2030 	/* First disable all MCAM entries, to stop traffic towards NIXLFs */
2031 	for (bank = 0; bank < mcam->banks; bank++) {
2032 		for (entry = 0; entry < mcam->banksize; entry++)
2033 			rvu_write64(rvu, blkaddr,
2034 				    NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
2035 	}
2036 
2037 	err = rvu_alloc_bitmap(&pkind->rsrc);
2038 	if (err)
2039 		return err;
2040 	/* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0',
2041 	 * no need to configure PKIND for all LBKs separately.
2042 	 */
2043 	rvu_alloc_rsrc(&pkind->rsrc);
2044 
2045 	/* Allocate mem for pkind to PF and channel mapping info */
2046 	pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
2047 					 sizeof(u32), GFP_KERNEL);
2048 	if (!pkind->pfchan_map)
2049 		return -ENOMEM;
2050 
2051 	/* Configure KPU profile */
2052 	npc_parser_profile_init(rvu, blkaddr);
2053 
2054 	/* Config Outer L2, IPv4's NPC layer info */
2055 	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
2056 		    (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
2057 		    kpu->lt_def->pck_ol2.ltype_mask);
2058 	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
2059 		    (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
2060 		    kpu->lt_def->pck_oip4.ltype_mask);
2061 
2062 	/* Config Inner IPV4 NPC layer info */
2063 	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
2064 		    (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
2065 		    kpu->lt_def->pck_iip4.ltype_mask);
2066 
2067 	/* Enable below for Rx pkts.
2068 	 * - Outer IPv4 header checksum validation.
2069 	 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B].
2070 	 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M].
2071 	 * - Inner IPv4 header checksum validation.
2072 	 * - Set non zero checksum error code value
2073 	 */
2074 	rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
2075 		    rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
2076 		    ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) |
2077 		    BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1));
2078 
2079 	rvu_npc_setup_interfaces(rvu, blkaddr);
2080 
2081 	npc_config_secret_key(rvu, blkaddr);
2082 	/* Configure MKEX profile */
2083 	npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
2084 
2085 	err = npc_mcam_rsrcs_init(rvu, blkaddr);
2086 	if (err)
2087 		return err;
2088 
2089 	err = npc_flow_steering_init(rvu, blkaddr);
2090 	if (err) {
2091 		dev_err(rvu->dev,
2092 			"Incorrect mkex profile loaded using default mkex\n");
2093 		npc_load_mkex_profile(rvu, blkaddr, def_pfl_name);
2094 	}
2095 
2096 	return 0;
2097 }
2098 
rvu_npc_freemem(struct rvu * rvu)2099 void rvu_npc_freemem(struct rvu *rvu)
2100 {
2101 	struct npc_pkind *pkind = &rvu->hw->pkind;
2102 	struct npc_mcam *mcam = &rvu->hw->mcam;
2103 
2104 	kfree(pkind->rsrc.bmap);
2105 	kfree(mcam->counters.bmap);
2106 	if (rvu->kpu_prfl_addr)
2107 		iounmap(rvu->kpu_prfl_addr);
2108 	else
2109 		kfree(rvu->kpu_fwdata);
2110 	mutex_destroy(&mcam->lock);
2111 }
2112 
rvu_npc_get_mcam_entry_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)2113 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
2114 				       int blkaddr, int *alloc_cnt,
2115 				       int *enable_cnt)
2116 {
2117 	struct npc_mcam *mcam = &rvu->hw->mcam;
2118 	int entry;
2119 
2120 	*alloc_cnt = 0;
2121 	*enable_cnt = 0;
2122 
2123 	for (entry = 0; entry < mcam->bmap_entries; entry++) {
2124 		if (mcam->entry2pfvf_map[entry] == pcifunc) {
2125 			(*alloc_cnt)++;
2126 			if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
2127 				(*enable_cnt)++;
2128 		}
2129 	}
2130 }
2131 
rvu_npc_get_mcam_counter_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)2132 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
2133 					 int blkaddr, int *alloc_cnt,
2134 					 int *enable_cnt)
2135 {
2136 	struct npc_mcam *mcam = &rvu->hw->mcam;
2137 	int cntr;
2138 
2139 	*alloc_cnt = 0;
2140 	*enable_cnt = 0;
2141 
2142 	for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2143 		if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2144 			(*alloc_cnt)++;
2145 			if (mcam->cntr_refcnt[cntr])
2146 				(*enable_cnt)++;
2147 		}
2148 	}
2149 }
2150 
npc_mcam_verify_entry(struct npc_mcam * mcam,u16 pcifunc,int entry)2151 static int npc_mcam_verify_entry(struct npc_mcam *mcam,
2152 				 u16 pcifunc, int entry)
2153 {
2154 	/* verify AF installed entries */
2155 	if (is_pffunc_af(pcifunc))
2156 		return 0;
2157 	/* Verify if entry is valid and if it is indeed
2158 	 * allocated to the requesting PFFUNC.
2159 	 */
2160 	if (entry >= mcam->bmap_entries)
2161 		return NPC_MCAM_INVALID_REQ;
2162 
2163 	if (pcifunc != mcam->entry2pfvf_map[entry])
2164 		return NPC_MCAM_PERM_DENIED;
2165 
2166 	return 0;
2167 }
2168 
npc_mcam_verify_counter(struct npc_mcam * mcam,u16 pcifunc,int cntr)2169 static int npc_mcam_verify_counter(struct npc_mcam *mcam,
2170 				   u16 pcifunc, int cntr)
2171 {
2172 	/* Verify if counter is valid and if it is indeed
2173 	 * allocated to the requesting PFFUNC.
2174 	 */
2175 	if (cntr >= mcam->counters.max)
2176 		return NPC_MCAM_INVALID_REQ;
2177 
2178 	if (pcifunc != mcam->cntr2pfvf_map[cntr])
2179 		return NPC_MCAM_PERM_DENIED;
2180 
2181 	return 0;
2182 }
2183 
npc_map_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)2184 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
2185 					int blkaddr, u16 entry, u16 cntr)
2186 {
2187 	u16 index = entry & (mcam->banksize - 1);
2188 	u32 bank = npc_get_bank(mcam, entry);
2189 	struct rvu_hwinfo *hw = rvu->hw;
2190 
2191 	/* Set mapping and increment counter's refcnt */
2192 	mcam->entry2cntr_map[entry] = cntr;
2193 	mcam->cntr_refcnt[cntr]++;
2194 	/* Enable stats */
2195 	rvu_write64(rvu, blkaddr,
2196 		    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
2197 		    ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr);
2198 }
2199 
npc_unmap_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)2200 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
2201 					  struct npc_mcam *mcam,
2202 					  int blkaddr, u16 entry, u16 cntr)
2203 {
2204 	u16 index = entry & (mcam->banksize - 1);
2205 	u32 bank = npc_get_bank(mcam, entry);
2206 
2207 	/* Remove mapping and reduce counter's refcnt */
2208 	mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
2209 	mcam->cntr_refcnt[cntr]--;
2210 	/* Disable stats */
2211 	rvu_write64(rvu, blkaddr,
2212 		    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
2213 }
2214 
2215 /* Sets MCAM entry in bitmap as used. Update
2216  * reverse bitmap too. Should be called with
2217  * 'mcam->lock' held.
2218  */
npc_mcam_set_bit(struct npc_mcam * mcam,u16 index)2219 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
2220 {
2221 	u16 entry, rentry;
2222 
2223 	entry = index;
2224 	rentry = mcam->bmap_entries - index - 1;
2225 
2226 	__set_bit(entry, mcam->bmap);
2227 	__set_bit(rentry, mcam->bmap_reverse);
2228 	mcam->bmap_fcnt--;
2229 }
2230 
2231 /* Sets MCAM entry in bitmap as free. Update
2232  * reverse bitmap too. Should be called with
2233  * 'mcam->lock' held.
2234  */
npc_mcam_clear_bit(struct npc_mcam * mcam,u16 index)2235 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
2236 {
2237 	u16 entry, rentry;
2238 
2239 	entry = index;
2240 	rentry = mcam->bmap_entries - index - 1;
2241 
2242 	__clear_bit(entry, mcam->bmap);
2243 	__clear_bit(rentry, mcam->bmap_reverse);
2244 	mcam->bmap_fcnt++;
2245 }
2246 
npc_mcam_free_all_entries(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc)2247 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
2248 				      int blkaddr, u16 pcifunc)
2249 {
2250 	u16 index, cntr;
2251 
2252 	/* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
2253 	for (index = 0; index < mcam->bmap_entries; index++) {
2254 		if (mcam->entry2pfvf_map[index] == pcifunc) {
2255 			mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
2256 			/* Free the entry in bitmap */
2257 			npc_mcam_clear_bit(mcam, index);
2258 			/* Disable the entry */
2259 			npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
2260 
2261 			/* Update entry2counter mapping */
2262 			cntr = mcam->entry2cntr_map[index];
2263 			if (cntr != NPC_MCAM_INVALID_MAP)
2264 				npc_unmap_mcam_entry_and_cntr(rvu, mcam,
2265 							      blkaddr, index,
2266 							      cntr);
2267 			mcam->entry2target_pffunc[index] = 0x0;
2268 		}
2269 	}
2270 }
2271 
npc_mcam_free_all_counters(struct rvu * rvu,struct npc_mcam * mcam,u16 pcifunc)2272 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
2273 				       u16 pcifunc)
2274 {
2275 	u16 cntr;
2276 
2277 	/* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
2278 	for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2279 		if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2280 			mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
2281 			mcam->cntr_refcnt[cntr] = 0;
2282 			rvu_free_rsrc(&mcam->counters, cntr);
2283 			/* This API is expected to be called after freeing
2284 			 * MCAM entries, which inturn will remove
2285 			 * 'entry to counter' mapping.
2286 			 * No need to do it again.
2287 			 */
2288 		}
2289 	}
2290 }
2291 
2292 /* Find area of contiguous free entries of size 'nr'.
2293  * If not found return max contiguous free entries available.
2294  */
npc_mcam_find_zero_area(unsigned long * map,u16 size,u16 start,u16 nr,u16 * max_area)2295 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
2296 				   u16 nr, u16 *max_area)
2297 {
2298 	u16 max_area_start = 0;
2299 	u16 index, next, end;
2300 
2301 	*max_area = 0;
2302 
2303 again:
2304 	index = find_next_zero_bit(map, size, start);
2305 	if (index >= size)
2306 		return max_area_start;
2307 
2308 	end = ((index + nr) >= size) ? size : index + nr;
2309 	next = find_next_bit(map, end, index);
2310 	if (*max_area < (next - index)) {
2311 		*max_area = next - index;
2312 		max_area_start = index;
2313 	}
2314 
2315 	if (next < end) {
2316 		start = next + 1;
2317 		goto again;
2318 	}
2319 
2320 	return max_area_start;
2321 }
2322 
2323 /* Find number of free MCAM entries available
2324  * within range i.e in between 'start' and 'end'.
2325  */
npc_mcam_get_free_count(unsigned long * map,u16 start,u16 end)2326 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
2327 {
2328 	u16 index, next;
2329 	u16 fcnt = 0;
2330 
2331 again:
2332 	if (start >= end)
2333 		return fcnt;
2334 
2335 	index = find_next_zero_bit(map, end, start);
2336 	if (index >= end)
2337 		return fcnt;
2338 
2339 	next = find_next_bit(map, end, index);
2340 	if (next <= end) {
2341 		fcnt += next - index;
2342 		start = next + 1;
2343 		goto again;
2344 	}
2345 
2346 	fcnt += end - index;
2347 	return fcnt;
2348 }
2349 
2350 static void
npc_get_mcam_search_range_priority(struct npc_mcam * mcam,struct npc_mcam_alloc_entry_req * req,u16 * start,u16 * end,bool * reverse)2351 npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
2352 				   struct npc_mcam_alloc_entry_req *req,
2353 				   u16 *start, u16 *end, bool *reverse)
2354 {
2355 	u16 fcnt;
2356 
2357 	if (req->priority == NPC_MCAM_HIGHER_PRIO)
2358 		goto hprio;
2359 
2360 	/* For a low priority entry allocation
2361 	 * - If reference entry is not in hprio zone then
2362 	 *      search range: ref_entry to end.
2363 	 * - If reference entry is in hprio zone and if
2364 	 *   request can be accomodated in non-hprio zone then
2365 	 *      search range: 'start of middle zone' to 'end'
2366 	 * - else search in reverse, so that less number of hprio
2367 	 *   zone entries are allocated.
2368 	 */
2369 
2370 	*reverse = false;
2371 	*start = req->ref_entry + 1;
2372 	*end = mcam->bmap_entries;
2373 
2374 	if (req->ref_entry >= mcam->hprio_end)
2375 		return;
2376 
2377 	fcnt = npc_mcam_get_free_count(mcam->bmap,
2378 				       mcam->hprio_end, mcam->bmap_entries);
2379 	if (fcnt > req->count)
2380 		*start = mcam->hprio_end;
2381 	else
2382 		*reverse = true;
2383 	return;
2384 
2385 hprio:
2386 	/* For a high priority entry allocation, search is always
2387 	 * in reverse to preserve hprio zone entries.
2388 	 * - If reference entry is not in lprio zone then
2389 	 *      search range: 0 to ref_entry.
2390 	 * - If reference entry is in lprio zone and if
2391 	 *   request can be accomodated in middle zone then
2392 	 *      search range: 'hprio_end' to 'lprio_start'
2393 	 */
2394 
2395 	*reverse = true;
2396 	*start = 0;
2397 	*end = req->ref_entry;
2398 
2399 	if (req->ref_entry <= mcam->lprio_start)
2400 		return;
2401 
2402 	fcnt = npc_mcam_get_free_count(mcam->bmap,
2403 				       mcam->hprio_end, mcam->lprio_start);
2404 	if (fcnt < req->count)
2405 		return;
2406 	*start = mcam->hprio_end;
2407 	*end = mcam->lprio_start;
2408 }
2409 
npc_mcam_alloc_entries(struct npc_mcam * mcam,u16 pcifunc,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)2410 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
2411 				  struct npc_mcam_alloc_entry_req *req,
2412 				  struct npc_mcam_alloc_entry_rsp *rsp)
2413 {
2414 	u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
2415 	u16 fcnt, hp_fcnt, lp_fcnt;
2416 	u16 start, end, index;
2417 	int entry, next_start;
2418 	bool reverse = false;
2419 	unsigned long *bmap;
2420 	u16 max_contig;
2421 
2422 	mutex_lock(&mcam->lock);
2423 
2424 	/* Check if there are any free entries */
2425 	if (!mcam->bmap_fcnt) {
2426 		mutex_unlock(&mcam->lock);
2427 		return NPC_MCAM_ALLOC_FAILED;
2428 	}
2429 
2430 	/* MCAM entries are divided into high priority, middle and
2431 	 * low priority zones. Idea is to not allocate top and lower
2432 	 * most entries as much as possible, this is to increase
2433 	 * probability of honouring priority allocation requests.
2434 	 *
2435 	 * Two bitmaps are used for mcam entry management,
2436 	 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
2437 	 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
2438 	 *
2439 	 * Reverse bitmap is used to allocate entries
2440 	 * - when a higher priority entry is requested
2441 	 * - when available free entries are less.
2442 	 * Lower priority ones out of avaialble free entries are always
2443 	 * chosen when 'high vs low' question arises.
2444 	 */
2445 
2446 	/* Get the search range for priority allocation request */
2447 	if (req->priority) {
2448 		npc_get_mcam_search_range_priority(mcam, req,
2449 						   &start, &end, &reverse);
2450 		goto alloc;
2451 	}
2452 
2453 	/* For a VF base MCAM match rule is set by its PF. And all the
2454 	 * further MCAM rules installed by VF on its own are
2455 	 * concatenated with the base rule set by its PF. Hence PF entries
2456 	 * should be at lower priority compared to VF entries. Otherwise
2457 	 * base rule is hit always and rules installed by VF will be of
2458 	 * no use. Hence if the request is from PF and NOT a priority
2459 	 * allocation request then allocate low priority entries.
2460 	 */
2461 	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
2462 		goto lprio_alloc;
2463 
2464 	/* Find out the search range for non-priority allocation request
2465 	 *
2466 	 * Get MCAM free entry count in middle zone.
2467 	 */
2468 	lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
2469 					  mcam->lprio_start,
2470 					  mcam->bmap_entries);
2471 	hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
2472 	fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
2473 
2474 	/* Check if request can be accomodated in the middle zone */
2475 	if (fcnt > req->count) {
2476 		start = mcam->hprio_end;
2477 		end = mcam->lprio_start;
2478 	} else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
2479 		/* Expand search zone from half of hprio zone to
2480 		 * half of lprio zone.
2481 		 */
2482 		start = mcam->hprio_end / 2;
2483 		end = mcam->bmap_entries - (mcam->lprio_count / 2);
2484 		reverse = true;
2485 	} else {
2486 		/* Not enough free entries, search all entries in reverse,
2487 		 * so that low priority ones will get used up.
2488 		 */
2489 lprio_alloc:
2490 		reverse = true;
2491 		start = 0;
2492 		end = mcam->bmap_entries;
2493 	}
2494 
2495 alloc:
2496 	if (reverse) {
2497 		bmap = mcam->bmap_reverse;
2498 		start = mcam->bmap_entries - start;
2499 		end = mcam->bmap_entries - end;
2500 		swap(start, end);
2501 	} else {
2502 		bmap = mcam->bmap;
2503 	}
2504 
2505 	if (req->contig) {
2506 		/* Allocate requested number of contiguous entries, if
2507 		 * unsuccessful find max contiguous entries available.
2508 		 */
2509 		index = npc_mcam_find_zero_area(bmap, end, start,
2510 						req->count, &max_contig);
2511 		rsp->count = max_contig;
2512 		if (reverse)
2513 			rsp->entry = mcam->bmap_entries - index - max_contig;
2514 		else
2515 			rsp->entry = index;
2516 	} else {
2517 		/* Allocate requested number of non-contiguous entries,
2518 		 * if unsuccessful allocate as many as possible.
2519 		 */
2520 		rsp->count = 0;
2521 		next_start = start;
2522 		for (entry = 0; entry < req->count; entry++) {
2523 			index = find_next_zero_bit(bmap, end, next_start);
2524 			if (index >= end)
2525 				break;
2526 
2527 			next_start = start + (index - start) + 1;
2528 
2529 			/* Save the entry's index */
2530 			if (reverse)
2531 				index = mcam->bmap_entries - index - 1;
2532 			entry_list[entry] = index;
2533 			rsp->count++;
2534 		}
2535 	}
2536 
2537 	/* If allocating requested no of entries is unsucessful,
2538 	 * expand the search range to full bitmap length and retry.
2539 	 */
2540 	if (!req->priority && (rsp->count < req->count) &&
2541 	    ((end - start) != mcam->bmap_entries)) {
2542 		reverse = true;
2543 		start = 0;
2544 		end = mcam->bmap_entries;
2545 		goto alloc;
2546 	}
2547 
2548 	/* For priority entry allocation requests, if allocation is
2549 	 * failed then expand search to max possible range and retry.
2550 	 */
2551 	if (req->priority && rsp->count < req->count) {
2552 		if (req->priority == NPC_MCAM_LOWER_PRIO &&
2553 		    (start != (req->ref_entry + 1))) {
2554 			start = req->ref_entry + 1;
2555 			end = mcam->bmap_entries;
2556 			reverse = false;
2557 			goto alloc;
2558 		} else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
2559 			   ((end - start) != req->ref_entry)) {
2560 			start = 0;
2561 			end = req->ref_entry;
2562 			reverse = true;
2563 			goto alloc;
2564 		}
2565 	}
2566 
2567 	/* Copy MCAM entry indices into mbox response entry_list.
2568 	 * Requester always expects indices in ascending order, so
2569 	 * reverse the list if reverse bitmap is used for allocation.
2570 	 */
2571 	if (!req->contig && rsp->count) {
2572 		index = 0;
2573 		for (entry = rsp->count - 1; entry >= 0; entry--) {
2574 			if (reverse)
2575 				rsp->entry_list[index++] = entry_list[entry];
2576 			else
2577 				rsp->entry_list[entry] = entry_list[entry];
2578 		}
2579 	}
2580 
2581 	/* Mark the allocated entries as used and set nixlf mapping */
2582 	for (entry = 0; entry < rsp->count; entry++) {
2583 		index = req->contig ?
2584 			(rsp->entry + entry) : rsp->entry_list[entry];
2585 		npc_mcam_set_bit(mcam, index);
2586 		mcam->entry2pfvf_map[index] = pcifunc;
2587 		mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
2588 	}
2589 
2590 	/* Update available free count in mbox response */
2591 	rsp->free_count = mcam->bmap_fcnt;
2592 
2593 	mutex_unlock(&mcam->lock);
2594 	return 0;
2595 }
2596 
2597 /* Marks bitmaps to reserved the mcam slot */
npc_mcam_rsrcs_reserve(struct rvu * rvu,int blkaddr,int entry_idx)2598 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx)
2599 {
2600 	struct npc_mcam *mcam = &rvu->hw->mcam;
2601 
2602 	npc_mcam_set_bit(mcam, entry_idx);
2603 }
2604 
rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu * rvu,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)2605 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
2606 					  struct npc_mcam_alloc_entry_req *req,
2607 					  struct npc_mcam_alloc_entry_rsp *rsp)
2608 {
2609 	struct npc_mcam *mcam = &rvu->hw->mcam;
2610 	u16 pcifunc = req->hdr.pcifunc;
2611 	int blkaddr;
2612 
2613 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2614 	if (blkaddr < 0)
2615 		return NPC_MCAM_INVALID_REQ;
2616 
2617 	rsp->entry = NPC_MCAM_ENTRY_INVALID;
2618 	rsp->free_count = 0;
2619 
2620 	/* Check if ref_entry is within range */
2621 	if (req->priority && req->ref_entry >= mcam->bmap_entries) {
2622 		dev_err(rvu->dev, "%s: reference entry %d is out of range\n",
2623 			__func__, req->ref_entry);
2624 		return NPC_MCAM_INVALID_REQ;
2625 	}
2626 
2627 	/* ref_entry can't be '0' if requested priority is high.
2628 	 * Can't be last entry if requested priority is low.
2629 	 */
2630 	if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
2631 	    ((req->ref_entry == (mcam->bmap_entries - 1)) &&
2632 	     req->priority == NPC_MCAM_LOWER_PRIO))
2633 		return NPC_MCAM_INVALID_REQ;
2634 
2635 	/* Since list of allocated indices needs to be sent to requester,
2636 	 * max number of non-contiguous entries per mbox msg is limited.
2637 	 */
2638 	if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) {
2639 		dev_err(rvu->dev,
2640 			"%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n",
2641 			__func__, req->count, NPC_MAX_NONCONTIG_ENTRIES);
2642 		return NPC_MCAM_INVALID_REQ;
2643 	}
2644 
2645 	/* Alloc request from PFFUNC with no NIXLF attached should be denied */
2646 	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2647 		return NPC_MCAM_ALLOC_DENIED;
2648 
2649 	return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
2650 }
2651 
rvu_mbox_handler_npc_mcam_free_entry(struct rvu * rvu,struct npc_mcam_free_entry_req * req,struct msg_rsp * rsp)2652 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
2653 					 struct npc_mcam_free_entry_req *req,
2654 					 struct msg_rsp *rsp)
2655 {
2656 	struct npc_mcam *mcam = &rvu->hw->mcam;
2657 	u16 pcifunc = req->hdr.pcifunc;
2658 	int blkaddr, rc = 0;
2659 	u16 cntr;
2660 
2661 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2662 	if (blkaddr < 0)
2663 		return NPC_MCAM_INVALID_REQ;
2664 
2665 	/* Free request from PFFUNC with no NIXLF attached, ignore */
2666 	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2667 		return NPC_MCAM_INVALID_REQ;
2668 
2669 	mutex_lock(&mcam->lock);
2670 
2671 	if (req->all)
2672 		goto free_all;
2673 
2674 	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2675 	if (rc)
2676 		goto exit;
2677 
2678 	mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP;
2679 	mcam->entry2target_pffunc[req->entry] = 0x0;
2680 	npc_mcam_clear_bit(mcam, req->entry);
2681 	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2682 
2683 	/* Update entry2counter mapping */
2684 	cntr = mcam->entry2cntr_map[req->entry];
2685 	if (cntr != NPC_MCAM_INVALID_MAP)
2686 		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2687 					      req->entry, cntr);
2688 
2689 	goto exit;
2690 
2691 free_all:
2692 	/* Free up all entries allocated to requesting PFFUNC */
2693 	npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
2694 exit:
2695 	mutex_unlock(&mcam->lock);
2696 	return rc;
2697 }
2698 
rvu_mbox_handler_npc_mcam_read_entry(struct rvu * rvu,struct npc_mcam_read_entry_req * req,struct npc_mcam_read_entry_rsp * rsp)2699 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu,
2700 					 struct npc_mcam_read_entry_req *req,
2701 					 struct npc_mcam_read_entry_rsp *rsp)
2702 {
2703 	struct npc_mcam *mcam = &rvu->hw->mcam;
2704 	u16 pcifunc = req->hdr.pcifunc;
2705 	int blkaddr, rc;
2706 
2707 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2708 	if (blkaddr < 0)
2709 		return NPC_MCAM_INVALID_REQ;
2710 
2711 	mutex_lock(&mcam->lock);
2712 	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2713 	if (!rc) {
2714 		npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry,
2715 				    &rsp->entry_data,
2716 				    &rsp->intf, &rsp->enable);
2717 	}
2718 
2719 	mutex_unlock(&mcam->lock);
2720 	return rc;
2721 }
2722 
rvu_mbox_handler_npc_mcam_write_entry(struct rvu * rvu,struct npc_mcam_write_entry_req * req,struct msg_rsp * rsp)2723 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
2724 					  struct npc_mcam_write_entry_req *req,
2725 					  struct msg_rsp *rsp)
2726 {
2727 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2728 	struct npc_mcam *mcam = &rvu->hw->mcam;
2729 	u16 pcifunc = req->hdr.pcifunc;
2730 	int blkaddr, rc;
2731 	u8 nix_intf;
2732 
2733 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2734 	if (blkaddr < 0)
2735 		return NPC_MCAM_INVALID_REQ;
2736 
2737 	mutex_lock(&mcam->lock);
2738 	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2739 	if (rc)
2740 		goto exit;
2741 
2742 	if (req->set_cntr &&
2743 	    npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
2744 		rc = NPC_MCAM_INVALID_REQ;
2745 		goto exit;
2746 	}
2747 
2748 	if (!is_npc_interface_valid(rvu, req->intf)) {
2749 		rc = NPC_MCAM_INVALID_REQ;
2750 		goto exit;
2751 	}
2752 
2753 	if (is_npc_intf_tx(req->intf))
2754 		nix_intf = pfvf->nix_tx_intf;
2755 	else
2756 		nix_intf = pfvf->nix_rx_intf;
2757 
2758 	if (!is_pffunc_af(pcifunc) &&
2759 	    npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) {
2760 		rc = NPC_MCAM_INVALID_REQ;
2761 		goto exit;
2762 	}
2763 
2764 	/* For AF installed rules, the nix_intf should be set to target NIX */
2765 	if (is_pffunc_af(req->hdr.pcifunc))
2766 		nix_intf = req->intf;
2767 
2768 	npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf,
2769 			      &req->entry_data, req->enable_entry);
2770 
2771 	if (req->set_cntr)
2772 		npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2773 					    req->entry, req->cntr);
2774 
2775 	rc = 0;
2776 exit:
2777 	mutex_unlock(&mcam->lock);
2778 	return rc;
2779 }
2780 
rvu_mbox_handler_npc_mcam_ena_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2781 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
2782 					struct npc_mcam_ena_dis_entry_req *req,
2783 					struct msg_rsp *rsp)
2784 {
2785 	struct npc_mcam *mcam = &rvu->hw->mcam;
2786 	u16 pcifunc = req->hdr.pcifunc;
2787 	int blkaddr, rc;
2788 
2789 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2790 	if (blkaddr < 0)
2791 		return NPC_MCAM_INVALID_REQ;
2792 
2793 	mutex_lock(&mcam->lock);
2794 	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2795 	mutex_unlock(&mcam->lock);
2796 	if (rc)
2797 		return rc;
2798 
2799 	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
2800 
2801 	return 0;
2802 }
2803 
rvu_mbox_handler_npc_mcam_dis_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2804 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
2805 					struct npc_mcam_ena_dis_entry_req *req,
2806 					struct msg_rsp *rsp)
2807 {
2808 	struct npc_mcam *mcam = &rvu->hw->mcam;
2809 	u16 pcifunc = req->hdr.pcifunc;
2810 	int blkaddr, rc;
2811 
2812 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2813 	if (blkaddr < 0)
2814 		return NPC_MCAM_INVALID_REQ;
2815 
2816 	mutex_lock(&mcam->lock);
2817 	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2818 	mutex_unlock(&mcam->lock);
2819 	if (rc)
2820 		return rc;
2821 
2822 	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2823 
2824 	return 0;
2825 }
2826 
rvu_mbox_handler_npc_mcam_shift_entry(struct rvu * rvu,struct npc_mcam_shift_entry_req * req,struct npc_mcam_shift_entry_rsp * rsp)2827 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
2828 					  struct npc_mcam_shift_entry_req *req,
2829 					  struct npc_mcam_shift_entry_rsp *rsp)
2830 {
2831 	struct npc_mcam *mcam = &rvu->hw->mcam;
2832 	u16 pcifunc = req->hdr.pcifunc;
2833 	u16 old_entry, new_entry;
2834 	int blkaddr, rc = 0;
2835 	u16 index, cntr;
2836 
2837 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2838 	if (blkaddr < 0)
2839 		return NPC_MCAM_INVALID_REQ;
2840 
2841 	if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
2842 		return NPC_MCAM_INVALID_REQ;
2843 
2844 	mutex_lock(&mcam->lock);
2845 	for (index = 0; index < req->shift_count; index++) {
2846 		old_entry = req->curr_entry[index];
2847 		new_entry = req->new_entry[index];
2848 
2849 		/* Check if both old and new entries are valid and
2850 		 * does belong to this PFFUNC or not.
2851 		 */
2852 		rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
2853 		if (rc)
2854 			break;
2855 
2856 		rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
2857 		if (rc)
2858 			break;
2859 
2860 		/* new_entry should not have a counter mapped */
2861 		if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
2862 			rc = NPC_MCAM_PERM_DENIED;
2863 			break;
2864 		}
2865 
2866 		/* Disable the new_entry */
2867 		npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
2868 
2869 		/* Copy rule from old entry to new entry */
2870 		npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
2871 
2872 		/* Copy counter mapping, if any */
2873 		cntr = mcam->entry2cntr_map[old_entry];
2874 		if (cntr != NPC_MCAM_INVALID_MAP) {
2875 			npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2876 						      old_entry, cntr);
2877 			npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2878 						    new_entry, cntr);
2879 		}
2880 
2881 		/* Enable new_entry and disable old_entry */
2882 		npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
2883 		npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
2884 	}
2885 
2886 	/* If shift has failed then report the failed index */
2887 	if (index != req->shift_count) {
2888 		rc = NPC_MCAM_PERM_DENIED;
2889 		rsp->failed_entry_idx = index;
2890 	}
2891 
2892 	mutex_unlock(&mcam->lock);
2893 	return rc;
2894 }
2895 
rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu * rvu,struct npc_mcam_alloc_counter_req * req,struct npc_mcam_alloc_counter_rsp * rsp)2896 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
2897 			struct npc_mcam_alloc_counter_req *req,
2898 			struct npc_mcam_alloc_counter_rsp *rsp)
2899 {
2900 	struct npc_mcam *mcam = &rvu->hw->mcam;
2901 	u16 pcifunc = req->hdr.pcifunc;
2902 	u16 max_contig, cntr;
2903 	int blkaddr, index;
2904 
2905 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2906 	if (blkaddr < 0)
2907 		return NPC_MCAM_INVALID_REQ;
2908 
2909 	/* If the request is from a PFFUNC with no NIXLF attached, ignore */
2910 	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2911 		return NPC_MCAM_INVALID_REQ;
2912 
2913 	/* Since list of allocated counter IDs needs to be sent to requester,
2914 	 * max number of non-contiguous counters per mbox msg is limited.
2915 	 */
2916 	if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
2917 		return NPC_MCAM_INVALID_REQ;
2918 
2919 	mutex_lock(&mcam->lock);
2920 
2921 	/* Check if unused counters are available or not */
2922 	if (!rvu_rsrc_free_count(&mcam->counters)) {
2923 		mutex_unlock(&mcam->lock);
2924 		return NPC_MCAM_ALLOC_FAILED;
2925 	}
2926 
2927 	rsp->count = 0;
2928 
2929 	if (req->contig) {
2930 		/* Allocate requested number of contiguous counters, if
2931 		 * unsuccessful find max contiguous entries available.
2932 		 */
2933 		index = npc_mcam_find_zero_area(mcam->counters.bmap,
2934 						mcam->counters.max, 0,
2935 						req->count, &max_contig);
2936 		rsp->count = max_contig;
2937 		rsp->cntr = index;
2938 		for (cntr = index; cntr < (index + max_contig); cntr++) {
2939 			__set_bit(cntr, mcam->counters.bmap);
2940 			mcam->cntr2pfvf_map[cntr] = pcifunc;
2941 		}
2942 	} else {
2943 		/* Allocate requested number of non-contiguous counters,
2944 		 * if unsuccessful allocate as many as possible.
2945 		 */
2946 		for (cntr = 0; cntr < req->count; cntr++) {
2947 			index = rvu_alloc_rsrc(&mcam->counters);
2948 			if (index < 0)
2949 				break;
2950 			rsp->cntr_list[cntr] = index;
2951 			rsp->count++;
2952 			mcam->cntr2pfvf_map[index] = pcifunc;
2953 		}
2954 	}
2955 
2956 	mutex_unlock(&mcam->lock);
2957 	return 0;
2958 }
2959 
rvu_mbox_handler_npc_mcam_free_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2960 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2961 		struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2962 {
2963 	struct npc_mcam *mcam = &rvu->hw->mcam;
2964 	u16 index, entry = 0;
2965 	int blkaddr, err;
2966 
2967 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2968 	if (blkaddr < 0)
2969 		return NPC_MCAM_INVALID_REQ;
2970 
2971 	mutex_lock(&mcam->lock);
2972 	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2973 	if (err) {
2974 		mutex_unlock(&mcam->lock);
2975 		return err;
2976 	}
2977 
2978 	/* Mark counter as free/unused */
2979 	mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2980 	rvu_free_rsrc(&mcam->counters, req->cntr);
2981 
2982 	/* Disable all MCAM entry's stats which are using this counter */
2983 	while (entry < mcam->bmap_entries) {
2984 		if (!mcam->cntr_refcnt[req->cntr])
2985 			break;
2986 
2987 		index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2988 		if (index >= mcam->bmap_entries)
2989 			break;
2990 		entry = index + 1;
2991 		if (mcam->entry2cntr_map[index] != req->cntr)
2992 			continue;
2993 
2994 		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2995 					      index, req->cntr);
2996 	}
2997 
2998 	mutex_unlock(&mcam->lock);
2999 	return 0;
3000 }
3001 
rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu * rvu,struct npc_mcam_unmap_counter_req * req,struct msg_rsp * rsp)3002 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
3003 		struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
3004 {
3005 	struct npc_mcam *mcam = &rvu->hw->mcam;
3006 	u16 index, entry = 0;
3007 	int blkaddr, rc;
3008 
3009 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3010 	if (blkaddr < 0)
3011 		return NPC_MCAM_INVALID_REQ;
3012 
3013 	mutex_lock(&mcam->lock);
3014 	rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3015 	if (rc)
3016 		goto exit;
3017 
3018 	/* Unmap the MCAM entry and counter */
3019 	if (!req->all) {
3020 		rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
3021 		if (rc)
3022 			goto exit;
3023 		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3024 					      req->entry, req->cntr);
3025 		goto exit;
3026 	}
3027 
3028 	/* Disable all MCAM entry's stats which are using this counter */
3029 	while (entry < mcam->bmap_entries) {
3030 		if (!mcam->cntr_refcnt[req->cntr])
3031 			break;
3032 
3033 		index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
3034 		if (index >= mcam->bmap_entries)
3035 			break;
3036 		entry = index + 1;
3037 
3038 		if (mcam->entry2cntr_map[index] != req->cntr)
3039 			continue;
3040 
3041 		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3042 					      index, req->cntr);
3043 	}
3044 exit:
3045 	mutex_unlock(&mcam->lock);
3046 	return rc;
3047 }
3048 
rvu_mbox_handler_npc_mcam_clear_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)3049 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
3050 		struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
3051 {
3052 	struct npc_mcam *mcam = &rvu->hw->mcam;
3053 	int blkaddr, err;
3054 
3055 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3056 	if (blkaddr < 0)
3057 		return NPC_MCAM_INVALID_REQ;
3058 
3059 	mutex_lock(&mcam->lock);
3060 	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3061 	mutex_unlock(&mcam->lock);
3062 	if (err)
3063 		return err;
3064 
3065 	rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
3066 
3067 	return 0;
3068 }
3069 
rvu_mbox_handler_npc_mcam_counter_stats(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct npc_mcam_oper_counter_rsp * rsp)3070 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
3071 			struct npc_mcam_oper_counter_req *req,
3072 			struct npc_mcam_oper_counter_rsp *rsp)
3073 {
3074 	struct npc_mcam *mcam = &rvu->hw->mcam;
3075 	int blkaddr, err;
3076 
3077 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3078 	if (blkaddr < 0)
3079 		return NPC_MCAM_INVALID_REQ;
3080 
3081 	mutex_lock(&mcam->lock);
3082 	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3083 	mutex_unlock(&mcam->lock);
3084 	if (err)
3085 		return err;
3086 
3087 	rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
3088 	rsp->stat &= BIT_ULL(48) - 1;
3089 
3090 	return 0;
3091 }
3092 
rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu * rvu,struct npc_mcam_alloc_and_write_entry_req * req,struct npc_mcam_alloc_and_write_entry_rsp * rsp)3093 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
3094 			  struct npc_mcam_alloc_and_write_entry_req *req,
3095 			  struct npc_mcam_alloc_and_write_entry_rsp *rsp)
3096 {
3097 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
3098 	struct npc_mcam_alloc_counter_req cntr_req;
3099 	struct npc_mcam_alloc_counter_rsp cntr_rsp;
3100 	struct npc_mcam_alloc_entry_req entry_req;
3101 	struct npc_mcam_alloc_entry_rsp entry_rsp;
3102 	struct npc_mcam *mcam = &rvu->hw->mcam;
3103 	u16 entry = NPC_MCAM_ENTRY_INVALID;
3104 	u16 cntr = NPC_MCAM_ENTRY_INVALID;
3105 	int blkaddr, rc;
3106 	u8 nix_intf;
3107 
3108 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3109 	if (blkaddr < 0)
3110 		return NPC_MCAM_INVALID_REQ;
3111 
3112 	if (!is_npc_interface_valid(rvu, req->intf))
3113 		return NPC_MCAM_INVALID_REQ;
3114 
3115 	if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
3116 				    req->hdr.pcifunc))
3117 		return NPC_MCAM_INVALID_REQ;
3118 
3119 	/* Try to allocate a MCAM entry */
3120 	entry_req.hdr.pcifunc = req->hdr.pcifunc;
3121 	entry_req.contig = true;
3122 	entry_req.priority = req->priority;
3123 	entry_req.ref_entry = req->ref_entry;
3124 	entry_req.count = 1;
3125 
3126 	rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
3127 						   &entry_req, &entry_rsp);
3128 	if (rc)
3129 		return rc;
3130 
3131 	if (!entry_rsp.count)
3132 		return NPC_MCAM_ALLOC_FAILED;
3133 
3134 	entry = entry_rsp.entry;
3135 
3136 	if (!req->alloc_cntr)
3137 		goto write_entry;
3138 
3139 	/* Now allocate counter */
3140 	cntr_req.hdr.pcifunc = req->hdr.pcifunc;
3141 	cntr_req.contig = true;
3142 	cntr_req.count = 1;
3143 
3144 	rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
3145 	if (rc) {
3146 		/* Free allocated MCAM entry */
3147 		mutex_lock(&mcam->lock);
3148 		mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP;
3149 		npc_mcam_clear_bit(mcam, entry);
3150 		mutex_unlock(&mcam->lock);
3151 		return rc;
3152 	}
3153 
3154 	cntr = cntr_rsp.cntr;
3155 
3156 write_entry:
3157 	mutex_lock(&mcam->lock);
3158 
3159 	if (is_npc_intf_tx(req->intf))
3160 		nix_intf = pfvf->nix_tx_intf;
3161 	else
3162 		nix_intf = pfvf->nix_rx_intf;
3163 
3164 	npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf,
3165 			      &req->entry_data, req->enable_entry);
3166 
3167 	if (req->alloc_cntr)
3168 		npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
3169 	mutex_unlock(&mcam->lock);
3170 
3171 	rsp->entry = entry;
3172 	rsp->cntr = cntr;
3173 
3174 	return 0;
3175 }
3176 
3177 #define GET_KEX_CFG(intf) \
3178 	rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
3179 
3180 #define GET_KEX_FLAGS(ld) \
3181 	rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
3182 
3183 #define GET_KEX_LD(intf, lid, lt, ld)	\
3184 	rvu_read64(rvu, BLKADDR_NPC,	\
3185 		NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
3186 
3187 #define GET_KEX_LDFLAGS(intf, ld, fl)	\
3188 	rvu_read64(rvu, BLKADDR_NPC,	\
3189 		NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
3190 
rvu_mbox_handler_npc_get_kex_cfg(struct rvu * rvu,struct msg_req * req,struct npc_get_kex_cfg_rsp * rsp)3191 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
3192 				     struct npc_get_kex_cfg_rsp *rsp)
3193 {
3194 	int lid, lt, ld, fl;
3195 
3196 	rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
3197 	rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
3198 	for (lid = 0; lid < NPC_MAX_LID; lid++) {
3199 		for (lt = 0; lt < NPC_MAX_LT; lt++) {
3200 			for (ld = 0; ld < NPC_MAX_LD; ld++) {
3201 				rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
3202 					GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
3203 				rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
3204 					GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
3205 			}
3206 		}
3207 	}
3208 	for (ld = 0; ld < NPC_MAX_LD; ld++)
3209 		rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
3210 
3211 	for (ld = 0; ld < NPC_MAX_LD; ld++) {
3212 		for (fl = 0; fl < NPC_MAX_LFL; fl++) {
3213 			rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
3214 					GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
3215 			rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
3216 					GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
3217 		}
3218 	}
3219 	memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
3220 	return 0;
3221 }
3222 
3223 static int
npc_set_var_len_offset_pkind(struct rvu * rvu,u16 pcifunc,u64 pkind,u8 var_len_off,u8 var_len_off_mask,u8 shift_dir)3224 npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind,
3225 			     u8 var_len_off, u8 var_len_off_mask, u8 shift_dir)
3226 {
3227 	struct npc_kpu_action0 *act0;
3228 	u8 shift_count = 0;
3229 	int blkaddr;
3230 	u64 val;
3231 
3232 	if (!var_len_off_mask)
3233 		return -EINVAL;
3234 
3235 	if (var_len_off_mask != 0xff) {
3236 		if (shift_dir)
3237 			shift_count = __ffs(var_len_off_mask);
3238 		else
3239 			shift_count = (8 - __fls(var_len_off_mask));
3240 	}
3241 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
3242 	if (blkaddr < 0) {
3243 		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
3244 		return -EINVAL;
3245 	}
3246 	val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
3247 	act0 = (struct npc_kpu_action0 *)&val;
3248 	act0->var_len_shift = shift_count;
3249 	act0->var_len_right = shift_dir;
3250 	act0->var_len_mask = var_len_off_mask;
3251 	act0->var_len_offset = var_len_off;
3252 	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
3253 	return 0;
3254 }
3255 
rvu_npc_set_parse_mode(struct rvu * rvu,u16 pcifunc,u64 mode,u8 dir,u64 pkind,u8 var_len_off,u8 var_len_off_mask,u8 shift_dir)3256 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
3257 			   u64 pkind, u8 var_len_off, u8 var_len_off_mask,
3258 			   u8 shift_dir)
3259 
3260 {
3261 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
3262 	int blkaddr, nixlf, rc, intf_mode;
3263 	int pf = rvu_get_pf(pcifunc);
3264 	u64 rxpkind, txpkind;
3265 	u8 cgx_id, lmac_id;
3266 
3267 	/* use default pkind to disable edsa/higig */
3268 	rxpkind = rvu_npc_get_pkind(rvu, pf);
3269 	txpkind = NPC_TX_DEF_PKIND;
3270 	intf_mode = NPC_INTF_MODE_DEF;
3271 
3272 	if (mode & OTX2_PRIV_FLAGS_CUSTOM) {
3273 		if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) {
3274 			rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind,
3275 							  var_len_off,
3276 							  var_len_off_mask,
3277 							  shift_dir);
3278 			if (rc)
3279 				return rc;
3280 		}
3281 		rxpkind = pkind;
3282 		txpkind = pkind;
3283 	}
3284 
3285 	if (dir & PKIND_RX) {
3286 		/* rx pkind set req valid only for cgx mapped PFs */
3287 		if (!is_cgx_config_permitted(rvu, pcifunc))
3288 			return 0;
3289 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
3290 
3291 		rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
3292 				   rxpkind);
3293 		if (rc)
3294 			return rc;
3295 	}
3296 
3297 	if (dir & PKIND_TX) {
3298 		/* Tx pkind set request valid if PCIFUNC has NIXLF attached */
3299 		rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3300 		if (rc)
3301 			return rc;
3302 
3303 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf),
3304 			    txpkind);
3305 	}
3306 
3307 	pfvf->intf_mode = intf_mode;
3308 	return 0;
3309 }
3310 
rvu_mbox_handler_npc_set_pkind(struct rvu * rvu,struct npc_set_pkind * req,struct msg_rsp * rsp)3311 int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req,
3312 				   struct msg_rsp *rsp)
3313 {
3314 	return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode,
3315 				      req->dir, req->pkind, req->var_len_off,
3316 				      req->var_len_off_mask, req->shift_dir);
3317 }
3318 
rvu_mbox_handler_npc_read_base_steer_rule(struct rvu * rvu,struct msg_req * req,struct npc_mcam_read_base_rule_rsp * rsp)3319 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu,
3320 					      struct msg_req *req,
3321 					      struct npc_mcam_read_base_rule_rsp *rsp)
3322 {
3323 	struct npc_mcam *mcam = &rvu->hw->mcam;
3324 	int index, blkaddr, nixlf, rc = 0;
3325 	u16 pcifunc = req->hdr.pcifunc;
3326 	struct rvu_pfvf *pfvf;
3327 	u8 intf, enable;
3328 
3329 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3330 	if (blkaddr < 0)
3331 		return NPC_MCAM_INVALID_REQ;
3332 
3333 	/* Return the channel number in case of PF */
3334 	if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
3335 		pfvf = rvu_get_pfvf(rvu, pcifunc);
3336 		rsp->entry.kw[0] = pfvf->rx_chan_base;
3337 		rsp->entry.kw_mask[0] = 0xFFFULL;
3338 		goto out;
3339 	}
3340 
3341 	/* Find the pkt steering rule installed by PF to this VF */
3342 	mutex_lock(&mcam->lock);
3343 	for (index = 0; index < mcam->bmap_entries; index++) {
3344 		if (mcam->entry2target_pffunc[index] == pcifunc)
3345 			goto read_entry;
3346 	}
3347 
3348 	rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
3349 	if (rc < 0) {
3350 		mutex_unlock(&mcam->lock);
3351 		goto out;
3352 	}
3353 	/* Read the default ucast entry if there is no pkt steering rule */
3354 	index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
3355 					 NIXLF_UCAST_ENTRY);
3356 read_entry:
3357 	/* Read the mcam entry */
3358 	npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf,
3359 			    &enable);
3360 	mutex_unlock(&mcam->lock);
3361 out:
3362 	return rc;
3363 }
3364 
rvu_mbox_handler_npc_mcam_entry_stats(struct rvu * rvu,struct npc_mcam_get_stats_req * req,struct npc_mcam_get_stats_rsp * rsp)3365 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu,
3366 					  struct npc_mcam_get_stats_req *req,
3367 					  struct npc_mcam_get_stats_rsp *rsp)
3368 {
3369 	struct npc_mcam *mcam = &rvu->hw->mcam;
3370 	u16 index, cntr;
3371 	int blkaddr;
3372 	u64 regval;
3373 	u32 bank;
3374 
3375 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3376 	if (blkaddr < 0)
3377 		return NPC_MCAM_INVALID_REQ;
3378 
3379 	mutex_lock(&mcam->lock);
3380 
3381 	index = req->entry & (mcam->banksize - 1);
3382 	bank = npc_get_bank(mcam, req->entry);
3383 
3384 	/* read MCAM entry STAT_ACT register */
3385 	regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));
3386 
3387 	if (!(regval & rvu->hw->npc_stat_ena)) {
3388 		rsp->stat_ena = 0;
3389 		mutex_unlock(&mcam->lock);
3390 		return 0;
3391 	}
3392 
3393 	cntr = regval & 0x1FF;
3394 
3395 	rsp->stat_ena = 1;
3396 	rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr));
3397 	rsp->stat &= BIT_ULL(48) - 1;
3398 
3399 	mutex_unlock(&mcam->lock);
3400 
3401 	return 0;
3402 }
3403