1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2020 Marvell.
5 */
6
7 #include <linux/bitfield.h>
8
9 #include "rvu_struct.h"
10 #include "rvu_reg.h"
11 #include "rvu.h"
12 #include "npc.h"
13
14 #define NPC_BYTESM GENMASK_ULL(19, 16)
15 #define NPC_HDR_OFFSET GENMASK_ULL(15, 8)
16 #define NPC_KEY_OFFSET GENMASK_ULL(5, 0)
17 #define NPC_LDATA_EN BIT_ULL(7)
18
19 static const char * const npc_flow_names[] = {
20 [NPC_DMAC] = "dmac",
21 [NPC_SMAC] = "smac",
22 [NPC_ETYPE] = "ether type",
23 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag",
24 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag",
25 [NPC_OUTER_VID] = "outer vlan id",
26 [NPC_TOS] = "tos",
27 [NPC_SIP_IPV4] = "ipv4 source ip",
28 [NPC_DIP_IPV4] = "ipv4 destination ip",
29 [NPC_SIP_IPV6] = "ipv6 source ip",
30 [NPC_DIP_IPV6] = "ipv6 destination ip",
31 [NPC_IPPROTO_TCP] = "ip proto tcp",
32 [NPC_IPPROTO_UDP] = "ip proto udp",
33 [NPC_IPPROTO_SCTP] = "ip proto sctp",
34 [NPC_IPPROTO_ICMP] = "ip proto icmp",
35 [NPC_IPPROTO_ICMP6] = "ip proto icmp6",
36 [NPC_IPPROTO_AH] = "ip proto AH",
37 [NPC_IPPROTO_ESP] = "ip proto ESP",
38 [NPC_SPORT_TCP] = "tcp source port",
39 [NPC_DPORT_TCP] = "tcp destination port",
40 [NPC_SPORT_UDP] = "udp source port",
41 [NPC_DPORT_UDP] = "udp destination port",
42 [NPC_SPORT_SCTP] = "sctp source port",
43 [NPC_DPORT_SCTP] = "sctp destination port",
44 [NPC_UNKNOWN] = "unknown",
45 };
46
npc_get_field_name(u8 hdr)47 const char *npc_get_field_name(u8 hdr)
48 {
49 if (hdr >= ARRAY_SIZE(npc_flow_names))
50 return npc_flow_names[NPC_UNKNOWN];
51
52 return npc_flow_names[hdr];
53 }
54
55 /* Compute keyword masks and figure out the number of keywords a field
56 * spans in the key.
57 */
npc_set_kw_masks(struct npc_mcam * mcam,u8 type,u8 nr_bits,int start_kwi,int offset,u8 intf)58 static void npc_set_kw_masks(struct npc_mcam *mcam, u8 type,
59 u8 nr_bits, int start_kwi, int offset, u8 intf)
60 {
61 struct npc_key_field *field = &mcam->rx_key_fields[type];
62 u8 bits_in_kw;
63 int max_kwi;
64
65 if (mcam->banks_per_entry == 1)
66 max_kwi = 1; /* NPC_MCAM_KEY_X1 */
67 else if (mcam->banks_per_entry == 2)
68 max_kwi = 3; /* NPC_MCAM_KEY_X2 */
69 else
70 max_kwi = 6; /* NPC_MCAM_KEY_X4 */
71
72 if (is_npc_intf_tx(intf))
73 field = &mcam->tx_key_fields[type];
74
75 if (offset + nr_bits <= 64) {
76 /* one KW only */
77 if (start_kwi > max_kwi)
78 return;
79 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0)
80 << offset;
81 field->nr_kws = 1;
82 } else if (offset + nr_bits > 64 &&
83 offset + nr_bits <= 128) {
84 /* two KWs */
85 if (start_kwi + 1 > max_kwi)
86 return;
87 /* first KW mask */
88 bits_in_kw = 64 - offset;
89 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)
90 << offset;
91 /* second KW mask i.e. mask for rest of bits */
92 bits_in_kw = nr_bits + offset - 64;
93 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0);
94 field->nr_kws = 2;
95 } else {
96 /* three KWs */
97 if (start_kwi + 2 > max_kwi)
98 return;
99 /* first KW mask */
100 bits_in_kw = 64 - offset;
101 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)
102 << offset;
103 /* second KW mask */
104 field->kw_mask[start_kwi + 1] = ~0ULL;
105 /* third KW mask i.e. mask for rest of bits */
106 bits_in_kw = nr_bits + offset - 128;
107 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0);
108 field->nr_kws = 3;
109 }
110 }
111
112 /* Helper function to figure out whether field exists in the key */
npc_is_field_present(struct rvu * rvu,enum key_fields type,u8 intf)113 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf)
114 {
115 struct npc_mcam *mcam = &rvu->hw->mcam;
116 struct npc_key_field *input;
117
118 input = &mcam->rx_key_fields[type];
119 if (is_npc_intf_tx(intf))
120 input = &mcam->tx_key_fields[type];
121
122 return input->nr_kws > 0;
123 }
124
npc_is_same(struct npc_key_field * input,struct npc_key_field * field)125 static bool npc_is_same(struct npc_key_field *input,
126 struct npc_key_field *field)
127 {
128 return memcmp(&input->layer_mdata, &field->layer_mdata,
129 sizeof(struct npc_layer_mdata)) == 0;
130 }
131
npc_set_layer_mdata(struct npc_mcam * mcam,enum key_fields type,u64 cfg,u8 lid,u8 lt,u8 intf)132 static void npc_set_layer_mdata(struct npc_mcam *mcam, enum key_fields type,
133 u64 cfg, u8 lid, u8 lt, u8 intf)
134 {
135 struct npc_key_field *input = &mcam->rx_key_fields[type];
136
137 if (is_npc_intf_tx(intf))
138 input = &mcam->tx_key_fields[type];
139
140 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
141 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg);
142 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1;
143 input->layer_mdata.ltype = lt;
144 input->layer_mdata.lid = lid;
145 }
146
npc_check_overlap_fields(struct npc_key_field * input1,struct npc_key_field * input2)147 static bool npc_check_overlap_fields(struct npc_key_field *input1,
148 struct npc_key_field *input2)
149 {
150 int kwi;
151
152 /* Fields with same layer id and different ltypes are mutually
153 * exclusive hence they can be overlapped
154 */
155 if (input1->layer_mdata.lid == input2->layer_mdata.lid &&
156 input1->layer_mdata.ltype != input2->layer_mdata.ltype)
157 return false;
158
159 for (kwi = 0; kwi < NPC_MAX_KWS_IN_KEY; kwi++) {
160 if (input1->kw_mask[kwi] & input2->kw_mask[kwi])
161 return true;
162 }
163
164 return false;
165 }
166
167 /* Helper function to check whether given field overlaps with any other fields
168 * in the key. Due to limitations on key size and the key extraction profile in
169 * use higher layers can overwrite lower layer's header fields. Hence overlap
170 * needs to be checked.
171 */
npc_check_overlap(struct rvu * rvu,int blkaddr,enum key_fields type,u8 start_lid,u8 intf)172 static bool npc_check_overlap(struct rvu *rvu, int blkaddr,
173 enum key_fields type, u8 start_lid, u8 intf)
174 {
175 struct npc_mcam *mcam = &rvu->hw->mcam;
176 struct npc_key_field *dummy, *input;
177 int start_kwi, offset;
178 u8 nr_bits, lid, lt, ld;
179 u64 cfg;
180
181 dummy = &mcam->rx_key_fields[NPC_UNKNOWN];
182 input = &mcam->rx_key_fields[type];
183
184 if (is_npc_intf_tx(intf)) {
185 dummy = &mcam->tx_key_fields[NPC_UNKNOWN];
186 input = &mcam->tx_key_fields[type];
187 }
188
189 for (lid = start_lid; lid < NPC_MAX_LID; lid++) {
190 for (lt = 0; lt < NPC_MAX_LT; lt++) {
191 for (ld = 0; ld < NPC_MAX_LD; ld++) {
192 cfg = rvu_read64(rvu, blkaddr,
193 NPC_AF_INTFX_LIDX_LTX_LDX_CFG
194 (intf, lid, lt, ld));
195 if (!FIELD_GET(NPC_LDATA_EN, cfg))
196 continue;
197 memset(dummy, 0, sizeof(struct npc_key_field));
198 npc_set_layer_mdata(mcam, NPC_UNKNOWN, cfg,
199 lid, lt, intf);
200 /* exclude input */
201 if (npc_is_same(input, dummy))
202 continue;
203 start_kwi = dummy->layer_mdata.key / 8;
204 offset = (dummy->layer_mdata.key * 8) % 64;
205 nr_bits = dummy->layer_mdata.len * 8;
206 /* form KW masks */
207 npc_set_kw_masks(mcam, NPC_UNKNOWN, nr_bits,
208 start_kwi, offset, intf);
209 /* check any input field bits falls in any
210 * other field bits.
211 */
212 if (npc_check_overlap_fields(dummy, input))
213 return true;
214 }
215 }
216 }
217
218 return false;
219 }
220
npc_check_field(struct rvu * rvu,int blkaddr,enum key_fields type,u8 intf)221 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type,
222 u8 intf)
223 {
224 if (!npc_is_field_present(rvu, type, intf) ||
225 npc_check_overlap(rvu, blkaddr, type, 0, intf))
226 return false;
227 return true;
228 }
229
npc_scan_parse_result(struct npc_mcam * mcam,u8 bit_number,u8 key_nibble,u8 intf)230 static void npc_scan_parse_result(struct npc_mcam *mcam, u8 bit_number,
231 u8 key_nibble, u8 intf)
232 {
233 u8 offset = (key_nibble * 4) % 64; /* offset within key word */
234 u8 kwi = (key_nibble * 4) / 64; /* which word in key */
235 u8 nr_bits = 4; /* bits in a nibble */
236 u8 type;
237
238 switch (bit_number) {
239 case 0 ... 2:
240 type = NPC_CHAN;
241 break;
242 case 3:
243 type = NPC_ERRLEV;
244 break;
245 case 4 ... 5:
246 type = NPC_ERRCODE;
247 break;
248 case 6:
249 type = NPC_LXMB;
250 break;
251 /* check for LTYPE only as of now */
252 case 9:
253 type = NPC_LA;
254 break;
255 case 12:
256 type = NPC_LB;
257 break;
258 case 15:
259 type = NPC_LC;
260 break;
261 case 18:
262 type = NPC_LD;
263 break;
264 case 21:
265 type = NPC_LE;
266 break;
267 case 24:
268 type = NPC_LF;
269 break;
270 case 27:
271 type = NPC_LG;
272 break;
273 case 30:
274 type = NPC_LH;
275 break;
276 default:
277 return;
278 }
279 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf);
280 }
281
npc_handle_multi_layer_fields(struct rvu * rvu,int blkaddr,u8 intf)282 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf)
283 {
284 struct npc_mcam *mcam = &rvu->hw->mcam;
285 struct npc_key_field *key_fields;
286 /* Ether type can come from three layers
287 * (ethernet, single tagged, double tagged)
288 */
289 struct npc_key_field *etype_ether;
290 struct npc_key_field *etype_tag1;
291 struct npc_key_field *etype_tag2;
292 /* Outer VLAN TCI can come from two layers
293 * (single tagged, double tagged)
294 */
295 struct npc_key_field *vlan_tag1;
296 struct npc_key_field *vlan_tag2;
297 u64 *features;
298 u8 start_lid;
299 int i;
300
301 key_fields = mcam->rx_key_fields;
302 features = &mcam->rx_features;
303
304 if (is_npc_intf_tx(intf)) {
305 key_fields = mcam->tx_key_fields;
306 features = &mcam->tx_features;
307 }
308
309 /* Handle header fields which can come from multiple layers like
310 * etype, outer vlan tci. These fields should have same position in
311 * the key otherwise to install a mcam rule more than one entry is
312 * needed which complicates mcam space management.
313 */
314 etype_ether = &key_fields[NPC_ETYPE_ETHER];
315 etype_tag1 = &key_fields[NPC_ETYPE_TAG1];
316 etype_tag2 = &key_fields[NPC_ETYPE_TAG2];
317 vlan_tag1 = &key_fields[NPC_VLAN_TAG1];
318 vlan_tag2 = &key_fields[NPC_VLAN_TAG2];
319
320 /* if key profile programmed does not extract Ethertype at all */
321 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws)
322 goto vlan_tci;
323
324 /* if key profile programmed extracts Ethertype from one layer */
325 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws)
326 key_fields[NPC_ETYPE] = *etype_ether;
327 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws)
328 key_fields[NPC_ETYPE] = *etype_tag1;
329 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws)
330 key_fields[NPC_ETYPE] = *etype_tag2;
331
332 /* if key profile programmed extracts Ethertype from multiple layers */
333 if (etype_ether->nr_kws && etype_tag1->nr_kws) {
334 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
335 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i])
336 goto vlan_tci;
337 }
338 key_fields[NPC_ETYPE] = *etype_tag1;
339 }
340 if (etype_ether->nr_kws && etype_tag2->nr_kws) {
341 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
342 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i])
343 goto vlan_tci;
344 }
345 key_fields[NPC_ETYPE] = *etype_tag2;
346 }
347 if (etype_tag1->nr_kws && etype_tag2->nr_kws) {
348 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
349 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i])
350 goto vlan_tci;
351 }
352 key_fields[NPC_ETYPE] = *etype_tag2;
353 }
354
355 /* check none of higher layers overwrite Ethertype */
356 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1;
357 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf))
358 goto vlan_tci;
359 *features |= BIT_ULL(NPC_ETYPE);
360 vlan_tci:
361 /* if key profile does not extract outer vlan tci at all */
362 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws)
363 goto done;
364
365 /* if key profile extracts outer vlan tci from one layer */
366 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws)
367 key_fields[NPC_OUTER_VID] = *vlan_tag1;
368 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws)
369 key_fields[NPC_OUTER_VID] = *vlan_tag2;
370
371 /* if key profile extracts outer vlan tci from multiple layers */
372 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) {
373 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
374 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i])
375 goto done;
376 }
377 key_fields[NPC_OUTER_VID] = *vlan_tag2;
378 }
379 /* check none of higher layers overwrite outer vlan tci */
380 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1;
381 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf))
382 goto done;
383 *features |= BIT_ULL(NPC_OUTER_VID);
384 done:
385 return;
386 }
387
npc_scan_ldata(struct rvu * rvu,int blkaddr,u8 lid,u8 lt,u64 cfg,u8 intf)388 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid,
389 u8 lt, u64 cfg, u8 intf)
390 {
391 struct npc_mcam *mcam = &rvu->hw->mcam;
392 u8 hdr, key, nr_bytes, bit_offset;
393 u8 la_ltype, la_start;
394 /* starting KW index and starting bit position */
395 int start_kwi, offset;
396
397 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1;
398 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
399 key = FIELD_GET(NPC_KEY_OFFSET, cfg);
400 start_kwi = key / 8;
401 offset = (key * 8) % 64;
402
403 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding
404 * ethernet header.
405 */
406 if (is_npc_intf_tx(intf)) {
407 la_ltype = NPC_LT_LA_IH_NIX_ETHER;
408 la_start = 8;
409 } else {
410 la_ltype = NPC_LT_LA_ETHER;
411 la_start = 0;
412 }
413
414 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \
415 do { \
416 if (lid == (hlid) && lt == (hlt)) { \
417 if ((hstart) >= hdr && \
418 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \
419 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \
420 npc_set_layer_mdata(mcam, (name), cfg, lid, lt, intf); \
421 npc_set_kw_masks(mcam, (name), (hlen) * 8, \
422 start_kwi, offset + bit_offset, intf);\
423 } \
424 } \
425 } while (0)
426
427 /* List LID, LTYPE, start offset from layer and length(in bytes) of
428 * packet header fields below.
429 * Example: Source IP is 4 bytes and starts at 12th byte of IP header
430 */
431 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1);
432 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4);
433 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4);
434 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16);
435 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16);
436 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2);
437 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2);
438 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2);
439 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2);
440 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2);
441 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2);
442 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2);
443 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2);
444 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2);
445 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2);
446 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2);
447 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6);
448 /* SMAC follows the DMAC(which is 6 bytes) */
449 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6);
450 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */
451 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2);
452 }
453
npc_set_features(struct rvu * rvu,int blkaddr,u8 intf)454 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)
455 {
456 struct npc_mcam *mcam = &rvu->hw->mcam;
457 u64 *features = &mcam->rx_features;
458 u64 tcp_udp_sctp;
459 int hdr;
460
461 if (is_npc_intf_tx(intf))
462 features = &mcam->tx_features;
463
464 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) {
465 if (npc_check_field(rvu, blkaddr, hdr, intf))
466 *features |= BIT_ULL(hdr);
467 }
468
469 tcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |
470 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) |
471 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP);
472
473 /* for tcp/udp/sctp corresponding layer type should be in the key */
474 if (*features & tcp_udp_sctp) {
475 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf))
476 *features &= ~tcp_udp_sctp;
477 else
478 *features |= BIT_ULL(NPC_IPPROTO_TCP) |
479 BIT_ULL(NPC_IPPROTO_UDP) |
480 BIT_ULL(NPC_IPPROTO_SCTP);
481 }
482
483 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */
484 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) {
485 *features |= BIT_ULL(NPC_IPPROTO_AH);
486 *features |= BIT_ULL(NPC_IPPROTO_ICMP);
487 *features |= BIT_ULL(NPC_IPPROTO_ICMP6);
488 }
489
490 /* for ESP, check if corresponding layer type is present in the key */
491 if (npc_check_field(rvu, blkaddr, NPC_LE, intf))
492 *features |= BIT_ULL(NPC_IPPROTO_ESP);
493
494 /* for vlan corresponding layer type should be in the key */
495 if (*features & BIT_ULL(NPC_OUTER_VID))
496 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf))
497 *features &= ~BIT_ULL(NPC_OUTER_VID);
498
499 /* for vlan ethertypes corresponding layer type should be in the key */
500 if (npc_check_field(rvu, blkaddr, NPC_LB, intf))
501 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) |
502 BIT_ULL(NPC_VLAN_ETYPE_STAG);
503 }
504
505 /* Scan key extraction profile and record how fields of our interest
506 * fill the key structure. Also verify Channel and DMAC exists in
507 * key and not overwritten by other header fields.
508 */
npc_scan_kex(struct rvu * rvu,int blkaddr,u8 intf)509 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf)
510 {
511 struct npc_mcam *mcam = &rvu->hw->mcam;
512 u8 lid, lt, ld, bitnr;
513 u8 key_nibble = 0;
514 u64 cfg;
515
516 /* Scan and note how parse result is going to be in key.
517 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from
518 * parse result in the key. The enabled nibbles from parse result
519 * will be concatenated in key.
520 */
521 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf));
522 cfg &= NPC_PARSE_NIBBLE;
523 for_each_set_bit(bitnr, (unsigned long *)&cfg, 31) {
524 npc_scan_parse_result(mcam, bitnr, key_nibble, intf);
525 key_nibble++;
526 }
527
528 /* Scan and note how layer data is going to be in key */
529 for (lid = 0; lid < NPC_MAX_LID; lid++) {
530 for (lt = 0; lt < NPC_MAX_LT; lt++) {
531 for (ld = 0; ld < NPC_MAX_LD; ld++) {
532 cfg = rvu_read64(rvu, blkaddr,
533 NPC_AF_INTFX_LIDX_LTX_LDX_CFG
534 (intf, lid, lt, ld));
535 if (!FIELD_GET(NPC_LDATA_EN, cfg))
536 continue;
537 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg,
538 intf);
539 }
540 }
541 }
542
543 return 0;
544 }
545
npc_scan_verify_kex(struct rvu * rvu,int blkaddr)546 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr)
547 {
548 int err;
549
550 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX);
551 if (err)
552 return err;
553
554 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX);
555 if (err)
556 return err;
557
558 /* Channel is mandatory */
559 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) {
560 dev_err(rvu->dev, "Channel not present in Key\n");
561 return -EINVAL;
562 }
563 /* check that none of the fields overwrite channel */
564 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) {
565 dev_err(rvu->dev, "Channel cannot be overwritten\n");
566 return -EINVAL;
567 }
568 /* DMAC should be present in key for unicast filter to work */
569 if (!npc_is_field_present(rvu, NPC_DMAC, NIX_INTF_RX)) {
570 dev_err(rvu->dev, "DMAC not present in Key\n");
571 return -EINVAL;
572 }
573 /* check that none of the fields overwrite DMAC */
574 if (npc_check_overlap(rvu, blkaddr, NPC_DMAC, 0, NIX_INTF_RX)) {
575 dev_err(rvu->dev, "DMAC cannot be overwritten\n");
576 return -EINVAL;
577 }
578
579 npc_set_features(rvu, blkaddr, NIX_INTF_TX);
580 npc_set_features(rvu, blkaddr, NIX_INTF_RX);
581 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX);
582 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX);
583
584 return 0;
585 }
586
npc_flow_steering_init(struct rvu * rvu,int blkaddr)587 int npc_flow_steering_init(struct rvu *rvu, int blkaddr)
588 {
589 struct npc_mcam *mcam = &rvu->hw->mcam;
590
591 INIT_LIST_HEAD(&mcam->mcam_rules);
592
593 return npc_scan_verify_kex(rvu, blkaddr);
594 }
595
npc_check_unsupported_flows(struct rvu * rvu,u64 features,u8 intf)596 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf)
597 {
598 struct npc_mcam *mcam = &rvu->hw->mcam;
599 u64 *mcam_features = &mcam->rx_features;
600 u64 unsupported;
601 u8 bit;
602
603 if (is_npc_intf_tx(intf))
604 mcam_features = &mcam->tx_features;
605
606 unsupported = (*mcam_features ^ features) & ~(*mcam_features);
607 if (unsupported) {
608 dev_info(rvu->dev, "Unsupported flow(s):\n");
609 for_each_set_bit(bit, (unsigned long *)&unsupported, 64)
610 dev_info(rvu->dev, "%s ", npc_get_field_name(bit));
611 return -EOPNOTSUPP;
612 }
613
614 return 0;
615 }
616
617 /* npc_update_entry - Based on the masks generated during
618 * the key scanning, updates the given entry with value and
619 * masks for the field of interest. Maximum 16 bytes of a packet
620 * header can be extracted by HW hence lo and hi are sufficient.
621 * When field bytes are less than or equal to 8 then hi should be
622 * 0 for value and mask.
623 *
624 * If exact match of value is required then mask should be all 1's.
625 * If any bits in mask are 0 then corresponding bits in value are
626 * dont care.
627 */
npc_update_entry(struct rvu * rvu,enum key_fields type,struct mcam_entry * entry,u64 val_lo,u64 val_hi,u64 mask_lo,u64 mask_hi,u8 intf)628 static void npc_update_entry(struct rvu *rvu, enum key_fields type,
629 struct mcam_entry *entry, u64 val_lo,
630 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf)
631 {
632 struct npc_mcam *mcam = &rvu->hw->mcam;
633 struct mcam_entry dummy = { {0} };
634 struct npc_key_field *field;
635 u64 kw1, kw2, kw3;
636 u8 shift;
637 int i;
638
639 field = &mcam->rx_key_fields[type];
640 if (is_npc_intf_tx(intf))
641 field = &mcam->tx_key_fields[type];
642
643 if (!field->nr_kws)
644 return;
645
646 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
647 if (!field->kw_mask[i])
648 continue;
649 /* place key value in kw[x] */
650 shift = __ffs64(field->kw_mask[i]);
651 /* update entry value */
652 kw1 = (val_lo << shift) & field->kw_mask[i];
653 dummy.kw[i] = kw1;
654 /* update entry mask */
655 kw1 = (mask_lo << shift) & field->kw_mask[i];
656 dummy.kw_mask[i] = kw1;
657
658 if (field->nr_kws == 1)
659 break;
660 /* place remaining bits of key value in kw[x + 1] */
661 if (field->nr_kws == 2) {
662 /* update entry value */
663 kw2 = shift ? val_lo >> (64 - shift) : 0;
664 kw2 |= (val_hi << shift);
665 kw2 &= field->kw_mask[i + 1];
666 dummy.kw[i + 1] = kw2;
667 /* update entry mask */
668 kw2 = shift ? mask_lo >> (64 - shift) : 0;
669 kw2 |= (mask_hi << shift);
670 kw2 &= field->kw_mask[i + 1];
671 dummy.kw_mask[i + 1] = kw2;
672 break;
673 }
674 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */
675 if (field->nr_kws == 3) {
676 /* update entry value */
677 kw2 = shift ? val_lo >> (64 - shift) : 0;
678 kw2 |= (val_hi << shift);
679 kw2 &= field->kw_mask[i + 1];
680 kw3 = shift ? val_hi >> (64 - shift) : 0;
681 kw3 &= field->kw_mask[i + 2];
682 dummy.kw[i + 1] = kw2;
683 dummy.kw[i + 2] = kw3;
684 /* update entry mask */
685 kw2 = shift ? mask_lo >> (64 - shift) : 0;
686 kw2 |= (mask_hi << shift);
687 kw2 &= field->kw_mask[i + 1];
688 kw3 = shift ? mask_hi >> (64 - shift) : 0;
689 kw3 &= field->kw_mask[i + 2];
690 dummy.kw_mask[i + 1] = kw2;
691 dummy.kw_mask[i + 2] = kw3;
692 break;
693 }
694 }
695 /* dummy is ready with values and masks for given key
696 * field now clear and update input entry with those
697 */
698 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
699 if (!field->kw_mask[i])
700 continue;
701 entry->kw[i] &= ~field->kw_mask[i];
702 entry->kw_mask[i] &= ~field->kw_mask[i];
703
704 entry->kw[i] |= dummy.kw[i];
705 entry->kw_mask[i] |= dummy.kw_mask[i];
706 }
707 }
708
709 #define IPV6_WORDS 4
710
npc_update_ipv6_flow(struct rvu * rvu,struct mcam_entry * entry,u64 features,struct flow_msg * pkt,struct flow_msg * mask,struct rvu_npc_mcam_rule * output,u8 intf)711 static void npc_update_ipv6_flow(struct rvu *rvu, struct mcam_entry *entry,
712 u64 features, struct flow_msg *pkt,
713 struct flow_msg *mask,
714 struct rvu_npc_mcam_rule *output, u8 intf)
715 {
716 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS];
717 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS];
718 struct flow_msg *opkt = &output->packet;
719 struct flow_msg *omask = &output->mask;
720 u64 mask_lo, mask_hi;
721 u64 val_lo, val_hi;
722
723 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet
724 * values to be programmed in MCAM should as below:
725 * val_high: 0xfe80000000000000
726 * val_low: 0x2c6863fffe5e2d0a
727 */
728 if (features & BIT_ULL(NPC_SIP_IPV6)) {
729 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS);
730 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS);
731
732 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1];
733 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3];
734 val_hi = (u64)src_ip[0] << 32 | src_ip[1];
735 val_lo = (u64)src_ip[2] << 32 | src_ip[3];
736
737 npc_update_entry(rvu, NPC_SIP_IPV6, entry, val_lo, val_hi,
738 mask_lo, mask_hi, intf);
739 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src));
740 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src));
741 }
742 if (features & BIT_ULL(NPC_DIP_IPV6)) {
743 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS);
744 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS);
745
746 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1];
747 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3];
748 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1];
749 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3];
750
751 npc_update_entry(rvu, NPC_DIP_IPV6, entry, val_lo, val_hi,
752 mask_lo, mask_hi, intf);
753 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst));
754 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst));
755 }
756 }
757
npc_update_vlan_features(struct rvu * rvu,struct mcam_entry * entry,u64 features,u8 intf)758 static void npc_update_vlan_features(struct rvu *rvu, struct mcam_entry *entry,
759 u64 features, u8 intf)
760 {
761 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG));
762 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG));
763 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID));
764
765 /* If only VLAN id is given then always match outer VLAN id */
766 if (vid && !ctag && !stag) {
767 npc_update_entry(rvu, NPC_LB, entry,
768 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0,
769 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf);
770 return;
771 }
772 if (ctag)
773 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_CTAG, 0,
774 ~0ULL, 0, intf);
775 if (stag)
776 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_STAG_QINQ, 0,
777 ~0ULL, 0, intf);
778 }
779
npc_update_flow(struct rvu * rvu,struct mcam_entry * entry,u64 features,struct flow_msg * pkt,struct flow_msg * mask,struct rvu_npc_mcam_rule * output,u8 intf)780 static void npc_update_flow(struct rvu *rvu, struct mcam_entry *entry,
781 u64 features, struct flow_msg *pkt,
782 struct flow_msg *mask,
783 struct rvu_npc_mcam_rule *output, u8 intf)
784 {
785 u64 dmac_mask = ether_addr_to_u64(mask->dmac);
786 u64 smac_mask = ether_addr_to_u64(mask->smac);
787 u64 dmac_val = ether_addr_to_u64(pkt->dmac);
788 u64 smac_val = ether_addr_to_u64(pkt->smac);
789 struct flow_msg *opkt = &output->packet;
790 struct flow_msg *omask = &output->mask;
791
792 if (!features)
793 return;
794
795 /* For tcp/udp/sctp LTYPE should be present in entry */
796 if (features & BIT_ULL(NPC_IPPROTO_TCP))
797 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_TCP,
798 0, ~0ULL, 0, intf);
799 if (features & BIT_ULL(NPC_IPPROTO_UDP))
800 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_UDP,
801 0, ~0ULL, 0, intf);
802 if (features & BIT_ULL(NPC_IPPROTO_SCTP))
803 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_SCTP,
804 0, ~0ULL, 0, intf);
805 if (features & BIT_ULL(NPC_IPPROTO_ICMP))
806 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP,
807 0, ~0ULL, 0, intf);
808 if (features & BIT_ULL(NPC_IPPROTO_ICMP6))
809 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP6,
810 0, ~0ULL, 0, intf);
811
812 /* For AH, LTYPE should be present in entry */
813 if (features & BIT_ULL(NPC_IPPROTO_AH))
814 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_AH,
815 0, ~0ULL, 0, intf);
816 /* For ESP, LTYPE should be present in entry */
817 if (features & BIT_ULL(NPC_IPPROTO_ESP))
818 npc_update_entry(rvu, NPC_LE, entry, NPC_LT_LE_ESP,
819 0, ~0ULL, 0, intf);
820
821 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \
822 do { \
823 if (features & BIT_ULL((field))) { \
824 npc_update_entry(rvu, (field), entry, (val_lo), (val_hi), \
825 (mask_lo), (mask_hi), intf); \
826 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \
827 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \
828 } \
829 } while (0)
830
831 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0);
832 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0);
833 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0,
834 ntohs(mask->etype), 0);
835 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0);
836 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0,
837 ntohl(mask->ip4src), 0);
838 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0,
839 ntohl(mask->ip4dst), 0);
840 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0,
841 ntohs(mask->sport), 0);
842 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0,
843 ntohs(mask->sport), 0);
844 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0,
845 ntohs(mask->dport), 0);
846 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0,
847 ntohs(mask->dport), 0);
848 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0,
849 ntohs(mask->sport), 0);
850 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0,
851 ntohs(mask->dport), 0);
852
853 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0,
854 ntohs(mask->vlan_tci), 0);
855
856 npc_update_ipv6_flow(rvu, entry, features, pkt, mask, output, intf);
857 npc_update_vlan_features(rvu, entry, features, intf);
858 }
859
rvu_mcam_find_rule(struct npc_mcam * mcam,u16 entry)860 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam,
861 u16 entry)
862 {
863 struct rvu_npc_mcam_rule *iter;
864
865 mutex_lock(&mcam->lock);
866 list_for_each_entry(iter, &mcam->mcam_rules, list) {
867 if (iter->entry == entry) {
868 mutex_unlock(&mcam->lock);
869 return iter;
870 }
871 }
872 mutex_unlock(&mcam->lock);
873
874 return NULL;
875 }
876
rvu_mcam_add_rule(struct npc_mcam * mcam,struct rvu_npc_mcam_rule * rule)877 static void rvu_mcam_add_rule(struct npc_mcam *mcam,
878 struct rvu_npc_mcam_rule *rule)
879 {
880 struct list_head *head = &mcam->mcam_rules;
881 struct rvu_npc_mcam_rule *iter;
882
883 mutex_lock(&mcam->lock);
884 list_for_each_entry(iter, &mcam->mcam_rules, list) {
885 if (iter->entry > rule->entry)
886 break;
887 head = &iter->list;
888 }
889
890 list_add(&rule->list, head);
891 mutex_unlock(&mcam->lock);
892 }
893
rvu_mcam_remove_counter_from_rule(struct rvu * rvu,u16 pcifunc,struct rvu_npc_mcam_rule * rule)894 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc,
895 struct rvu_npc_mcam_rule *rule)
896 {
897 struct npc_mcam_oper_counter_req free_req = { 0 };
898 struct msg_rsp free_rsp;
899
900 if (!rule->has_cntr)
901 return;
902
903 free_req.hdr.pcifunc = pcifunc;
904 free_req.cntr = rule->cntr;
905
906 rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp);
907 rule->has_cntr = false;
908 }
909
rvu_mcam_add_counter_to_rule(struct rvu * rvu,u16 pcifunc,struct rvu_npc_mcam_rule * rule,struct npc_install_flow_rsp * rsp)910 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,
911 struct rvu_npc_mcam_rule *rule,
912 struct npc_install_flow_rsp *rsp)
913 {
914 struct npc_mcam_alloc_counter_req cntr_req = { 0 };
915 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 };
916 int err;
917
918 cntr_req.hdr.pcifunc = pcifunc;
919 cntr_req.contig = true;
920 cntr_req.count = 1;
921
922 /* we try to allocate a counter to track the stats of this
923 * rule. If counter could not be allocated then proceed
924 * without counter because counters are limited than entries.
925 */
926 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req,
927 &cntr_rsp);
928 if (!err && cntr_rsp.count) {
929 rule->cntr = cntr_rsp.cntr;
930 rule->has_cntr = true;
931 rsp->counter = rule->cntr;
932 } else {
933 rsp->counter = err;
934 }
935 }
936
npc_update_rx_entry(struct rvu * rvu,struct rvu_pfvf * pfvf,struct mcam_entry * entry,struct npc_install_flow_req * req,u16 target,bool pf_set_vfs_mac)937 static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,
938 struct mcam_entry *entry,
939 struct npc_install_flow_req *req,
940 u16 target, bool pf_set_vfs_mac)
941 {
942 struct rvu_switch *rswitch = &rvu->rswitch;
943 struct nix_rx_action action;
944
945 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac)
946 req->chan_mask = 0x0; /* Do not care channel */
947
948 npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask,
949 0, NIX_INTF_RX);
950
951 *(u64 *)&action = 0x00;
952 action.pf_func = target;
953 action.op = req->op;
954 action.index = req->index;
955 action.match_id = req->match_id;
956 action.flow_key_alg = req->flow_key_alg;
957
958 if (req->op == NIX_RX_ACTION_DEFAULT && pfvf->def_ucast_rule)
959 action = pfvf->def_ucast_rule->rx_action;
960
961 entry->action = *(u64 *)&action;
962
963 /* VTAG0 starts at 0th byte of LID_B.
964 * VTAG1 starts at 4th byte of LID_B.
965 */
966 entry->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) |
967 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) |
968 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) |
969 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) |
970 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) |
971 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) |
972 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) |
973 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4);
974 }
975
npc_update_tx_entry(struct rvu * rvu,struct rvu_pfvf * pfvf,struct mcam_entry * entry,struct npc_install_flow_req * req,u16 target)976 static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,
977 struct mcam_entry *entry,
978 struct npc_install_flow_req *req, u16 target)
979 {
980 struct nix_tx_action action;
981 u64 mask = ~0ULL;
982
983 /* If AF is installing then do not care about
984 * PF_FUNC in Send Descriptor
985 */
986 if (is_pffunc_af(req->hdr.pcifunc))
987 mask = 0;
988
989 npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target),
990 0, mask, 0, NIX_INTF_TX);
991
992 *(u64 *)&action = 0x00;
993 action.op = req->op;
994 action.index = req->index;
995 action.match_id = req->match_id;
996
997 entry->action = *(u64 *)&action;
998
999 /* VTAG0 starts at 0th byte of LID_B.
1000 * VTAG1 starts at 4th byte of LID_B.
1001 */
1002 entry->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) |
1003 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) |
1004 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) |
1005 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) |
1006 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) |
1007 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) |
1008 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) |
1009 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24);
1010 }
1011
npc_install_flow(struct rvu * rvu,int blkaddr,u16 target,int nixlf,struct rvu_pfvf * pfvf,struct npc_install_flow_req * req,struct npc_install_flow_rsp * rsp,bool enable,bool pf_set_vfs_mac)1012 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target,
1013 int nixlf, struct rvu_pfvf *pfvf,
1014 struct npc_install_flow_req *req,
1015 struct npc_install_flow_rsp *rsp, bool enable,
1016 bool pf_set_vfs_mac)
1017 {
1018 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule;
1019 u64 features, installed_features, missing_features = 0;
1020 struct npc_mcam_write_entry_req write_req = { 0 };
1021 struct npc_mcam *mcam = &rvu->hw->mcam;
1022 struct rvu_npc_mcam_rule dummy = { 0 };
1023 struct rvu_npc_mcam_rule *rule;
1024 u16 owner = req->hdr.pcifunc;
1025 struct msg_rsp write_rsp;
1026 struct mcam_entry *entry;
1027 int entry_index, err;
1028 bool new = false;
1029
1030 installed_features = req->features;
1031 features = req->features;
1032 entry = &write_req.entry_data;
1033 entry_index = req->entry;
1034
1035 npc_update_flow(rvu, entry, features, &req->packet, &req->mask, &dummy,
1036 req->intf);
1037
1038 if (is_npc_intf_rx(req->intf))
1039 npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac);
1040 else
1041 npc_update_tx_entry(rvu, pfvf, entry, req, target);
1042
1043 /* Default unicast rules do not exist for TX */
1044 if (is_npc_intf_tx(req->intf))
1045 goto find_rule;
1046
1047 if (req->default_rule) {
1048 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf,
1049 NIXLF_UCAST_ENTRY);
1050 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index);
1051 }
1052
1053 /* update mcam entry with default unicast rule attributes */
1054 if (def_ucast_rule && (req->default_rule && req->append)) {
1055 missing_features = (def_ucast_rule->features ^ features) &
1056 def_ucast_rule->features;
1057 if (missing_features)
1058 npc_update_flow(rvu, entry, missing_features,
1059 &def_ucast_rule->packet,
1060 &def_ucast_rule->mask,
1061 &dummy, req->intf);
1062 installed_features = req->features | missing_features;
1063 }
1064
1065 find_rule:
1066 rule = rvu_mcam_find_rule(mcam, entry_index);
1067 if (!rule) {
1068 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
1069 if (!rule)
1070 return -ENOMEM;
1071 new = true;
1072 }
1073
1074 /* allocate new counter if rule has no counter */
1075 if (!req->default_rule && req->set_cntr && !rule->has_cntr)
1076 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp);
1077
1078 /* if user wants to delete an existing counter for a rule then
1079 * free the counter
1080 */
1081 if (!req->set_cntr && rule->has_cntr)
1082 rvu_mcam_remove_counter_from_rule(rvu, owner, rule);
1083
1084 write_req.hdr.pcifunc = owner;
1085
1086 /* AF owns the default rules so change the owner just to relax
1087 * the checks in rvu_mbox_handler_npc_mcam_write_entry
1088 */
1089 if (req->default_rule)
1090 write_req.hdr.pcifunc = 0;
1091
1092 write_req.entry = entry_index;
1093 write_req.intf = req->intf;
1094 write_req.enable_entry = (u8)enable;
1095 /* if counter is available then clear and use it */
1096 if (req->set_cntr && rule->has_cntr) {
1097 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), 0x00);
1098 write_req.set_cntr = 1;
1099 write_req.cntr = rule->cntr;
1100 }
1101
1102 /* update rule */
1103 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet));
1104 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask));
1105 rule->entry = entry_index;
1106 memcpy(&rule->rx_action, &entry->action, sizeof(struct nix_rx_action));
1107 if (is_npc_intf_tx(req->intf))
1108 memcpy(&rule->tx_action, &entry->action,
1109 sizeof(struct nix_tx_action));
1110 rule->vtag_action = entry->vtag_action;
1111 rule->features = installed_features;
1112 rule->default_rule = req->default_rule;
1113 rule->owner = owner;
1114 rule->enable = enable;
1115 rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
1116 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK;
1117 rule->chan &= rule->chan_mask;
1118 if (is_npc_intf_tx(req->intf))
1119 rule->intf = pfvf->nix_tx_intf;
1120 else
1121 rule->intf = pfvf->nix_rx_intf;
1122
1123 if (new)
1124 rvu_mcam_add_rule(mcam, rule);
1125 if (req->default_rule)
1126 pfvf->def_ucast_rule = rule;
1127
1128 /* write to mcam entry registers */
1129 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req,
1130 &write_rsp);
1131 if (err) {
1132 rvu_mcam_remove_counter_from_rule(rvu, owner, rule);
1133 if (new) {
1134 list_del(&rule->list);
1135 kfree(rule);
1136 }
1137 return err;
1138 }
1139
1140 /* VF's MAC address is being changed via PF */
1141 if (pf_set_vfs_mac) {
1142 ether_addr_copy(pfvf->default_mac, req->packet.dmac);
1143 ether_addr_copy(pfvf->mac_addr, req->packet.dmac);
1144 set_bit(PF_SET_VF_MAC, &pfvf->flags);
1145 }
1146
1147 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) &&
1148 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7)
1149 rule->vfvlan_cfg = true;
1150
1151 if (is_npc_intf_rx(req->intf) && req->match_id &&
1152 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS))
1153 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc,
1154 req->index, req->match_id);
1155
1156 return 0;
1157 }
1158
rvu_mbox_handler_npc_install_flow(struct rvu * rvu,struct npc_install_flow_req * req,struct npc_install_flow_rsp * rsp)1159 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu,
1160 struct npc_install_flow_req *req,
1161 struct npc_install_flow_rsp *rsp)
1162 {
1163 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK);
1164 struct rvu_switch *rswitch = &rvu->rswitch;
1165 int blkaddr, nixlf, err;
1166 struct rvu_pfvf *pfvf;
1167 bool pf_set_vfs_mac = false;
1168 bool enable = true;
1169 u16 target;
1170
1171 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1172 if (blkaddr < 0) {
1173 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1174 return NPC_MCAM_INVALID_REQ;
1175 }
1176
1177 if (!is_npc_interface_valid(rvu, req->intf))
1178 return NPC_FLOW_INTF_INVALID;
1179
1180 if (from_vf && req->default_rule)
1181 return NPC_FLOW_VF_PERM_DENIED;
1182
1183 /* Each PF/VF info is maintained in struct rvu_pfvf.
1184 * rvu_pfvf for the target PF/VF needs to be retrieved
1185 * hence modify pcifunc accordingly.
1186 */
1187
1188 /* AF installing for a PF/VF */
1189 if (!req->hdr.pcifunc)
1190 target = req->vf;
1191 /* PF installing for its VF */
1192 else if (!from_vf && req->vf) {
1193 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf;
1194 pf_set_vfs_mac = req->default_rule &&
1195 (req->features & BIT_ULL(NPC_DMAC));
1196 }
1197 /* msg received from PF/VF */
1198 else
1199 target = req->hdr.pcifunc;
1200
1201 /* ignore chan_mask in case pf func is not AF, revisit later */
1202 if (!is_pffunc_af(req->hdr.pcifunc))
1203 req->chan_mask = 0xFFF;
1204
1205 err = npc_check_unsupported_flows(rvu, req->features, req->intf);
1206 if (err)
1207 return NPC_FLOW_NOT_SUPPORTED;
1208
1209 pfvf = rvu_get_pfvf(rvu, target);
1210
1211 /* PF installing for its VF */
1212 if (req->hdr.pcifunc && !from_vf && req->vf)
1213 set_bit(PF_SET_VF_CFG, &pfvf->flags);
1214
1215 /* update req destination mac addr */
1216 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) &&
1217 is_zero_ether_addr(req->packet.dmac)) {
1218 ether_addr_copy(req->packet.dmac, pfvf->mac_addr);
1219 eth_broadcast_addr((u8 *)&req->mask.dmac);
1220 }
1221
1222 /* Proceed if NIXLF is attached or not for TX rules */
1223 err = nix_get_nixlf(rvu, target, &nixlf, NULL);
1224 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac)
1225 return NPC_FLOW_NO_NIXLF;
1226
1227 /* don't enable rule when nixlf not attached or initialized */
1228 if (!(is_nixlf_attached(rvu, target) &&
1229 test_bit(NIXLF_INITIALIZED, &pfvf->flags)))
1230 enable = false;
1231
1232 /* Packets reaching NPC in Tx path implies that a
1233 * NIXLF is properly setup and transmitting.
1234 * Hence rules can be enabled for Tx.
1235 */
1236 if (is_npc_intf_tx(req->intf))
1237 enable = true;
1238
1239 /* Do not allow requests from uninitialized VFs */
1240 if (from_vf && !enable)
1241 return NPC_FLOW_VF_NOT_INIT;
1242
1243 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */
1244 if (pf_set_vfs_mac && !enable) {
1245 ether_addr_copy(pfvf->default_mac, req->packet.dmac);
1246 ether_addr_copy(pfvf->mac_addr, req->packet.dmac);
1247 set_bit(PF_SET_VF_MAC, &pfvf->flags);
1248 return 0;
1249 }
1250
1251 mutex_lock(&rswitch->switch_lock);
1252 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf,
1253 req, rsp, enable, pf_set_vfs_mac);
1254 mutex_unlock(&rswitch->switch_lock);
1255
1256 return err;
1257 }
1258
npc_delete_flow(struct rvu * rvu,struct rvu_npc_mcam_rule * rule,u16 pcifunc)1259 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule,
1260 u16 pcifunc)
1261 {
1262 struct npc_mcam_ena_dis_entry_req dis_req = { 0 };
1263 struct msg_rsp dis_rsp;
1264
1265 if (rule->default_rule)
1266 return 0;
1267
1268 if (rule->has_cntr)
1269 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule);
1270
1271 dis_req.hdr.pcifunc = pcifunc;
1272 dis_req.entry = rule->entry;
1273
1274 list_del(&rule->list);
1275 kfree(rule);
1276
1277 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp);
1278 }
1279
rvu_mbox_handler_npc_delete_flow(struct rvu * rvu,struct npc_delete_flow_req * req,struct msg_rsp * rsp)1280 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu,
1281 struct npc_delete_flow_req *req,
1282 struct msg_rsp *rsp)
1283 {
1284 struct npc_mcam *mcam = &rvu->hw->mcam;
1285 struct rvu_npc_mcam_rule *iter, *tmp;
1286 u16 pcifunc = req->hdr.pcifunc;
1287 struct list_head del_list;
1288
1289 INIT_LIST_HEAD(&del_list);
1290
1291 mutex_lock(&mcam->lock);
1292 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) {
1293 if (iter->owner == pcifunc) {
1294 /* All rules */
1295 if (req->all) {
1296 list_move_tail(&iter->list, &del_list);
1297 /* Range of rules */
1298 } else if (req->end && iter->entry >= req->start &&
1299 iter->entry <= req->end) {
1300 list_move_tail(&iter->list, &del_list);
1301 /* single rule */
1302 } else if (req->entry == iter->entry) {
1303 list_move_tail(&iter->list, &del_list);
1304 break;
1305 }
1306 }
1307 }
1308 mutex_unlock(&mcam->lock);
1309
1310 list_for_each_entry_safe(iter, tmp, &del_list, list) {
1311 u16 entry = iter->entry;
1312
1313 /* clear the mcam entry target pcifunc */
1314 mcam->entry2target_pffunc[entry] = 0x0;
1315 if (npc_delete_flow(rvu, iter, pcifunc))
1316 dev_err(rvu->dev, "rule deletion failed for entry:%u",
1317 entry);
1318 }
1319
1320 return 0;
1321 }
1322
npc_update_dmac_value(struct rvu * rvu,int npcblkaddr,struct rvu_npc_mcam_rule * rule,struct rvu_pfvf * pfvf)1323 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr,
1324 struct rvu_npc_mcam_rule *rule,
1325 struct rvu_pfvf *pfvf)
1326 {
1327 struct npc_mcam_write_entry_req write_req = { 0 };
1328 struct mcam_entry *entry = &write_req.entry_data;
1329 struct npc_mcam *mcam = &rvu->hw->mcam;
1330 struct msg_rsp rsp;
1331 u8 intf, enable;
1332 int err;
1333
1334 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr);
1335
1336 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry,
1337 entry, &intf, &enable);
1338
1339 npc_update_entry(rvu, NPC_DMAC, entry,
1340 ether_addr_to_u64(pfvf->mac_addr), 0,
1341 0xffffffffffffull, 0, intf);
1342
1343 write_req.hdr.pcifunc = rule->owner;
1344 write_req.entry = rule->entry;
1345 write_req.intf = pfvf->nix_rx_intf;
1346
1347 mutex_unlock(&mcam->lock);
1348 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp);
1349 mutex_lock(&mcam->lock);
1350
1351 return err;
1352 }
1353
npc_mcam_enable_flows(struct rvu * rvu,u16 target)1354 void npc_mcam_enable_flows(struct rvu *rvu, u16 target)
1355 {
1356 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target);
1357 struct rvu_npc_mcam_rule *def_ucast_rule;
1358 struct npc_mcam *mcam = &rvu->hw->mcam;
1359 struct rvu_npc_mcam_rule *rule;
1360 int blkaddr, bank, index;
1361 u64 def_action;
1362
1363 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1364 if (blkaddr < 0)
1365 return;
1366
1367 def_ucast_rule = pfvf->def_ucast_rule;
1368
1369 mutex_lock(&mcam->lock);
1370 list_for_each_entry(rule, &mcam->mcam_rules, list) {
1371 if (is_npc_intf_rx(rule->intf) &&
1372 rule->rx_action.pf_func == target && !rule->enable) {
1373 if (rule->default_rule) {
1374 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1375 rule->entry, true);
1376 rule->enable = true;
1377 continue;
1378 }
1379
1380 if (rule->vfvlan_cfg)
1381 npc_update_dmac_value(rvu, blkaddr, rule, pfvf);
1382
1383 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) {
1384 if (!def_ucast_rule)
1385 continue;
1386 /* Use default unicast entry action */
1387 rule->rx_action = def_ucast_rule->rx_action;
1388 def_action = *(u64 *)&def_ucast_rule->rx_action;
1389 bank = npc_get_bank(mcam, rule->entry);
1390 rvu_write64(rvu, blkaddr,
1391 NPC_AF_MCAMEX_BANKX_ACTION
1392 (rule->entry, bank), def_action);
1393 }
1394
1395 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1396 rule->entry, true);
1397 rule->enable = true;
1398 }
1399 }
1400
1401 /* Enable MCAM entries installed by PF with target as VF pcifunc */
1402 for (index = 0; index < mcam->bmap_entries; index++) {
1403 if (mcam->entry2target_pffunc[index] == target)
1404 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1405 index, true);
1406 }
1407 mutex_unlock(&mcam->lock);
1408 }
1409
npc_mcam_disable_flows(struct rvu * rvu,u16 target)1410 void npc_mcam_disable_flows(struct rvu *rvu, u16 target)
1411 {
1412 struct npc_mcam *mcam = &rvu->hw->mcam;
1413 int blkaddr, index;
1414
1415 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1416 if (blkaddr < 0)
1417 return;
1418
1419 mutex_lock(&mcam->lock);
1420 /* Disable MCAM entries installed by PF with target as VF pcifunc */
1421 for (index = 0; index < mcam->bmap_entries; index++) {
1422 if (mcam->entry2target_pffunc[index] == target)
1423 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1424 index, false);
1425 }
1426 mutex_unlock(&mcam->lock);
1427 }
1428