1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/devcoredump.h>
6
7 #include "main.h"
8 #include "regd.h"
9 #include "fw.h"
10 #include "ps.h"
11 #include "sec.h"
12 #include "mac.h"
13 #include "coex.h"
14 #include "phy.h"
15 #include "reg.h"
16 #include "efuse.h"
17 #include "tx.h"
18 #include "debug.h"
19 #include "bf.h"
20 #include "sar.h"
21
22 bool rtw_disable_lps_deep_mode;
23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
24 bool rtw_bf_support = true;
25 unsigned int rtw_debug_mask;
26 EXPORT_SYMBOL(rtw_debug_mask);
27 /* EDCCA is enabled during normal behavior. For debugging purpose in
28 * a noisy environment, it can be disabled via edcca debugfs. Because
29 * all rtw88 devices will probably be affected if environment is noisy,
30 * rtw_edcca_enabled is just declared by driver instead of by device.
31 * So, turning it off will take effect for all rtw88 devices before
32 * there is a tough reason to maintain rtw_edcca_enabled by device.
33 */
34 bool rtw_edcca_enabled = true;
35
36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
37 module_param_named(support_bf, rtw_bf_support, bool, 0644);
38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
39
40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
42 MODULE_PARM_DESC(debug_mask, "Debugging mask");
43
44 static struct ieee80211_channel rtw_channeltable_2g[] = {
45 {.center_freq = 2412, .hw_value = 1,},
46 {.center_freq = 2417, .hw_value = 2,},
47 {.center_freq = 2422, .hw_value = 3,},
48 {.center_freq = 2427, .hw_value = 4,},
49 {.center_freq = 2432, .hw_value = 5,},
50 {.center_freq = 2437, .hw_value = 6,},
51 {.center_freq = 2442, .hw_value = 7,},
52 {.center_freq = 2447, .hw_value = 8,},
53 {.center_freq = 2452, .hw_value = 9,},
54 {.center_freq = 2457, .hw_value = 10,},
55 {.center_freq = 2462, .hw_value = 11,},
56 {.center_freq = 2467, .hw_value = 12,},
57 {.center_freq = 2472, .hw_value = 13,},
58 {.center_freq = 2484, .hw_value = 14,},
59 };
60
61 static struct ieee80211_channel rtw_channeltable_5g[] = {
62 {.center_freq = 5180, .hw_value = 36,},
63 {.center_freq = 5200, .hw_value = 40,},
64 {.center_freq = 5220, .hw_value = 44,},
65 {.center_freq = 5240, .hw_value = 48,},
66 {.center_freq = 5260, .hw_value = 52,},
67 {.center_freq = 5280, .hw_value = 56,},
68 {.center_freq = 5300, .hw_value = 60,},
69 {.center_freq = 5320, .hw_value = 64,},
70 {.center_freq = 5500, .hw_value = 100,},
71 {.center_freq = 5520, .hw_value = 104,},
72 {.center_freq = 5540, .hw_value = 108,},
73 {.center_freq = 5560, .hw_value = 112,},
74 {.center_freq = 5580, .hw_value = 116,},
75 {.center_freq = 5600, .hw_value = 120,},
76 {.center_freq = 5620, .hw_value = 124,},
77 {.center_freq = 5640, .hw_value = 128,},
78 {.center_freq = 5660, .hw_value = 132,},
79 {.center_freq = 5680, .hw_value = 136,},
80 {.center_freq = 5700, .hw_value = 140,},
81 {.center_freq = 5720, .hw_value = 144,},
82 {.center_freq = 5745, .hw_value = 149,},
83 {.center_freq = 5765, .hw_value = 153,},
84 {.center_freq = 5785, .hw_value = 157,},
85 {.center_freq = 5805, .hw_value = 161,},
86 {.center_freq = 5825, .hw_value = 165,
87 .flags = IEEE80211_CHAN_NO_HT40MINUS},
88 };
89
90 static struct ieee80211_rate rtw_ratetable[] = {
91 {.bitrate = 10, .hw_value = 0x00,},
92 {.bitrate = 20, .hw_value = 0x01,},
93 {.bitrate = 55, .hw_value = 0x02,},
94 {.bitrate = 110, .hw_value = 0x03,},
95 {.bitrate = 60, .hw_value = 0x04,},
96 {.bitrate = 90, .hw_value = 0x05,},
97 {.bitrate = 120, .hw_value = 0x06,},
98 {.bitrate = 180, .hw_value = 0x07,},
99 {.bitrate = 240, .hw_value = 0x08,},
100 {.bitrate = 360, .hw_value = 0x09,},
101 {.bitrate = 480, .hw_value = 0x0a,},
102 {.bitrate = 540, .hw_value = 0x0b,},
103 };
104
rtw_desc_to_bitrate(u8 desc_rate)105 u16 rtw_desc_to_bitrate(u8 desc_rate)
106 {
107 struct ieee80211_rate rate;
108
109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
110 return 0;
111
112 rate = rtw_ratetable[desc_rate];
113
114 return rate.bitrate;
115 }
116
117 static struct ieee80211_supported_band rtw_band_2ghz = {
118 .band = NL80211_BAND_2GHZ,
119
120 .channels = rtw_channeltable_2g,
121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
122
123 .bitrates = rtw_ratetable,
124 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
125
126 .ht_cap = {0},
127 .vht_cap = {0},
128 };
129
130 static struct ieee80211_supported_band rtw_band_5ghz = {
131 .band = NL80211_BAND_5GHZ,
132
133 .channels = rtw_channeltable_5g,
134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
135
136 /* 5G has no CCK rates */
137 .bitrates = rtw_ratetable + 4,
138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
139
140 .ht_cap = {0},
141 .vht_cap = {0},
142 };
143
144 struct rtw_watch_dog_iter_data {
145 struct rtw_dev *rtwdev;
146 struct rtw_vif *rtwvif;
147 };
148
rtw_dynamic_csi_rate(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif)149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
150 {
151 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
152 u8 fix_rate_enable = 0;
153 u8 new_csi_rate_idx;
154
155 if (rtwvif->bfee.role != RTW_BFEE_SU &&
156 rtwvif->bfee.role != RTW_BFEE_MU)
157 return;
158
159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
160 bf_info->cur_csi_rpt_rate,
161 fix_rate_enable, &new_csi_rate_idx);
162
163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
165 }
166
rtw_vif_watch_dog_iter(void * data,u8 * mac,struct ieee80211_vif * vif)167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
168 struct ieee80211_vif *vif)
169 {
170 struct rtw_watch_dog_iter_data *iter_data = data;
171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
172
173 if (vif->type == NL80211_IFTYPE_STATION)
174 if (vif->cfg.assoc)
175 iter_data->rtwvif = rtwvif;
176
177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
178
179 rtwvif->stats.tx_unicast = 0;
180 rtwvif->stats.rx_unicast = 0;
181 rtwvif->stats.tx_cnt = 0;
182 rtwvif->stats.rx_cnt = 0;
183 }
184
185 /* process TX/RX statistics periodically for hardware,
186 * the information helps hardware to enhance performance
187 */
rtw_watch_dog_work(struct work_struct * work)188 static void rtw_watch_dog_work(struct work_struct *work)
189 {
190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
191 watch_dog_work.work);
192 struct rtw_traffic_stats *stats = &rtwdev->stats;
193 struct rtw_watch_dog_iter_data data = {};
194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
195 bool ps_active;
196
197 mutex_lock(&rtwdev->mutex);
198
199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
200 goto unlock;
201
202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
203 RTW_WATCH_DOG_DELAY_TIME);
204
205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
207 else
208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
209
210 rtw_coex_wl_status_check(rtwdev);
211 rtw_coex_query_bt_hid_list(rtwdev);
212
213 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
214 rtw_coex_wl_status_change_notify(rtwdev, 0);
215
216 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
217 stats->rx_cnt > RTW_LPS_THRESHOLD)
218 ps_active = true;
219 else
220 ps_active = false;
221
222 ewma_tp_add(&stats->tx_ewma_tp,
223 (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
224 ewma_tp_add(&stats->rx_ewma_tp,
225 (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
226 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
227 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
228
229 /* reset tx/rx statictics */
230 stats->tx_unicast = 0;
231 stats->rx_unicast = 0;
232 stats->tx_cnt = 0;
233 stats->rx_cnt = 0;
234
235 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
236 goto unlock;
237
238 /* make sure BB/RF is working for dynamic mech */
239 rtw_leave_lps(rtwdev);
240
241 rtw_phy_dynamic_mechanism(rtwdev);
242
243 data.rtwdev = rtwdev;
244 /* use atomic version to avoid taking local->iflist_mtx mutex */
245 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
246
247 /* fw supports only one station associated to enter lps, if there are
248 * more than two stations associated to the AP, then we can not enter
249 * lps, because fw does not handle the overlapped beacon interval
250 *
251 * mac80211 should iterate vifs and determine if driver can enter
252 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to
253 * get that vif and check if device is having traffic more than the
254 * threshold.
255 */
256 if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
257 !rtwdev->beacon_loss)
258 rtw_enter_lps(rtwdev, data.rtwvif->port);
259
260 rtwdev->watch_dog_cnt++;
261
262 unlock:
263 mutex_unlock(&rtwdev->mutex);
264 }
265
rtw_c2h_work(struct work_struct * work)266 static void rtw_c2h_work(struct work_struct *work)
267 {
268 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
269 struct sk_buff *skb, *tmp;
270
271 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
272 skb_unlink(skb, &rtwdev->c2h_queue);
273 rtw_fw_c2h_cmd_handle(rtwdev, skb);
274 dev_kfree_skb_any(skb);
275 }
276 }
277
rtw_ips_work(struct work_struct * work)278 static void rtw_ips_work(struct work_struct *work)
279 {
280 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
281
282 mutex_lock(&rtwdev->mutex);
283 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
284 rtw_enter_ips(rtwdev);
285 mutex_unlock(&rtwdev->mutex);
286 }
287
rtw_acquire_macid(struct rtw_dev * rtwdev)288 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
289 {
290 unsigned long mac_id;
291
292 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
293 if (mac_id < RTW_MAX_MAC_ID_NUM)
294 set_bit(mac_id, rtwdev->mac_id_map);
295
296 return mac_id;
297 }
298
rtw_sta_add(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,struct ieee80211_vif * vif)299 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
300 struct ieee80211_vif *vif)
301 {
302 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
303 int i;
304
305 si->mac_id = rtw_acquire_macid(rtwdev);
306 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
307 return -ENOSPC;
308
309 si->sta = sta;
310 si->vif = vif;
311 si->init_ra_lv = 1;
312 ewma_rssi_init(&si->avg_rssi);
313 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
314 rtw_txq_init(rtwdev, sta->txq[i]);
315
316 rtw_update_sta_info(rtwdev, si, true);
317 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
318
319 rtwdev->sta_cnt++;
320 rtwdev->beacon_loss = false;
321 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
322 sta->addr, si->mac_id);
323
324 return 0;
325 }
326
rtw_sta_remove(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,bool fw_exist)327 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
328 bool fw_exist)
329 {
330 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
331 int i;
332
333 rtw_release_macid(rtwdev, si->mac_id);
334 if (fw_exist)
335 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
336
337 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
338 rtw_txq_cleanup(rtwdev, sta->txq[i]);
339
340 kfree(si->mask);
341
342 rtwdev->sta_cnt--;
343 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
344 sta->addr, si->mac_id);
345 }
346
347 struct rtw_fwcd_hdr {
348 u32 item;
349 u32 size;
350 u32 padding1;
351 u32 padding2;
352 } __packed;
353
rtw_fwcd_prep(struct rtw_dev * rtwdev)354 static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
355 {
356 const struct rtw_chip_info *chip = rtwdev->chip;
357 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
358 const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
359 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
360 u8 i;
361
362 if (segs) {
363 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
364
365 for (i = 0; i < segs->num; i++)
366 prep_size += segs->segs[i];
367 }
368
369 desc->data = vmalloc(prep_size);
370 if (!desc->data)
371 return -ENOMEM;
372
373 desc->size = prep_size;
374 desc->next = desc->data;
375
376 return 0;
377 }
378
rtw_fwcd_next(struct rtw_dev * rtwdev,u32 item,u32 size)379 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
380 {
381 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
382 struct rtw_fwcd_hdr *hdr;
383 u8 *next;
384
385 if (!desc->data) {
386 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
387 return NULL;
388 }
389
390 next = desc->next + sizeof(struct rtw_fwcd_hdr);
391 if (next - desc->data + size > desc->size) {
392 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
393 return NULL;
394 }
395
396 hdr = (struct rtw_fwcd_hdr *)(desc->next);
397 hdr->item = item;
398 hdr->size = size;
399 hdr->padding1 = 0x01234567;
400 hdr->padding2 = 0x89abcdef;
401 desc->next = next + size;
402
403 return next;
404 }
405
rtw_fwcd_dump(struct rtw_dev * rtwdev)406 static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
407 {
408 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
409
410 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
411
412 /* Data will be freed after lifetime of device coredump. After calling
413 * dev_coredump, data is supposed to be handled by the device coredump
414 * framework. Note that a new dump will be discarded if a previous one
415 * hasn't been released yet.
416 */
417 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
418 }
419
rtw_fwcd_free(struct rtw_dev * rtwdev,bool free_self)420 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
421 {
422 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
423
424 if (free_self) {
425 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
426 vfree(desc->data);
427 }
428
429 desc->data = NULL;
430 desc->next = NULL;
431 }
432
rtw_fw_dump_crash_log(struct rtw_dev * rtwdev)433 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
434 {
435 u32 size = rtwdev->chip->fw_rxff_size;
436 u32 *buf;
437 u8 seq;
438
439 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
440 if (!buf)
441 return -ENOMEM;
442
443 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
444 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
445 return -EINVAL;
446 }
447
448 if (GET_FW_DUMP_LEN(buf) == 0) {
449 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
450 return -EINVAL;
451 }
452
453 seq = GET_FW_DUMP_SEQ(buf);
454 if (seq > 0) {
455 rtw_dbg(rtwdev, RTW_DBG_FW,
456 "fw crash dump's seq is wrong: %d\n", seq);
457 return -EINVAL;
458 }
459
460 return 0;
461 }
462
rtw_dump_fw(struct rtw_dev * rtwdev,const u32 ocp_src,u32 size,u32 fwcd_item)463 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
464 u32 fwcd_item)
465 {
466 u32 rxff = rtwdev->chip->fw_rxff_size;
467 u32 dump_size, done_size = 0;
468 u8 *buf;
469 int ret;
470
471 buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
472 if (!buf)
473 return -ENOMEM;
474
475 while (size) {
476 dump_size = size > rxff ? rxff : size;
477
478 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
479 dump_size);
480 if (ret) {
481 rtw_err(rtwdev,
482 "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
483 ocp_src, done_size);
484 return ret;
485 }
486
487 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
488 dump_size, (u32 *)(buf + done_size));
489 if (ret) {
490 rtw_err(rtwdev,
491 "dump fw 0x%x [+0x%x] from fw fifo fail\n",
492 ocp_src, done_size);
493 return ret;
494 }
495
496 size -= dump_size;
497 done_size += dump_size;
498 }
499
500 return 0;
501 }
502 EXPORT_SYMBOL(rtw_dump_fw);
503
rtw_dump_reg(struct rtw_dev * rtwdev,const u32 addr,const u32 size)504 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
505 {
506 u8 *buf;
507 u32 i;
508
509 if (addr & 0x3) {
510 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
511 return -EINVAL;
512 }
513
514 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
515 if (!buf)
516 return -ENOMEM;
517
518 for (i = 0; i < size; i += 4)
519 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
520
521 return 0;
522 }
523 EXPORT_SYMBOL(rtw_dump_reg);
524
rtw_vif_assoc_changed(struct rtw_vif * rtwvif,struct ieee80211_bss_conf * conf)525 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
526 struct ieee80211_bss_conf *conf)
527 {
528 struct ieee80211_vif *vif = NULL;
529
530 if (conf)
531 vif = container_of(conf, struct ieee80211_vif, bss_conf);
532
533 if (conf && vif->cfg.assoc) {
534 rtwvif->aid = vif->cfg.aid;
535 rtwvif->net_type = RTW_NET_MGD_LINKED;
536 } else {
537 rtwvif->aid = 0;
538 rtwvif->net_type = RTW_NET_NO_LINK;
539 }
540 }
541
rtw_reset_key_iter(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)542 static void rtw_reset_key_iter(struct ieee80211_hw *hw,
543 struct ieee80211_vif *vif,
544 struct ieee80211_sta *sta,
545 struct ieee80211_key_conf *key,
546 void *data)
547 {
548 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
549 struct rtw_sec_desc *sec = &rtwdev->sec;
550
551 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
552 }
553
rtw_reset_sta_iter(void * data,struct ieee80211_sta * sta)554 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
555 {
556 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
557
558 if (rtwdev->sta_cnt == 0) {
559 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
560 return;
561 }
562 rtw_sta_remove(rtwdev, sta, false);
563 }
564
rtw_reset_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)565 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
566 {
567 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
568 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
569
570 rtw_bf_disassoc(rtwdev, vif, NULL);
571 rtw_vif_assoc_changed(rtwvif, NULL);
572 rtw_txq_cleanup(rtwdev, vif->txq);
573 }
574
rtw_fw_recovery(struct rtw_dev * rtwdev)575 void rtw_fw_recovery(struct rtw_dev *rtwdev)
576 {
577 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
578 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
579 }
580
__fw_recovery_work(struct rtw_dev * rtwdev)581 static void __fw_recovery_work(struct rtw_dev *rtwdev)
582 {
583 int ret = 0;
584
585 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
586 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
587
588 ret = rtw_fwcd_prep(rtwdev);
589 if (ret)
590 goto free;
591 ret = rtw_fw_dump_crash_log(rtwdev);
592 if (ret)
593 goto free;
594 ret = rtw_chip_dump_fw_crash(rtwdev);
595 if (ret)
596 goto free;
597
598 rtw_fwcd_dump(rtwdev);
599 free:
600 rtw_fwcd_free(rtwdev, !!ret);
601 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
602
603 WARN(1, "firmware crash, start reset and recover\n");
604
605 rcu_read_lock();
606 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
607 rcu_read_unlock();
608 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
609 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
610 rtw_enter_ips(rtwdev);
611 }
612
rtw_fw_recovery_work(struct work_struct * work)613 static void rtw_fw_recovery_work(struct work_struct *work)
614 {
615 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
616 fw_recovery_work);
617
618 mutex_lock(&rtwdev->mutex);
619 __fw_recovery_work(rtwdev);
620 mutex_unlock(&rtwdev->mutex);
621
622 ieee80211_restart_hw(rtwdev->hw);
623 }
624
625 struct rtw_txq_ba_iter_data {
626 };
627
rtw_txq_ba_iter(void * data,struct ieee80211_sta * sta)628 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
629 {
630 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
631 int ret;
632 u8 tid;
633
634 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
635 while (tid != IEEE80211_NUM_TIDS) {
636 clear_bit(tid, si->tid_ba);
637 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
638 if (ret == -EINVAL) {
639 struct ieee80211_txq *txq;
640 struct rtw_txq *rtwtxq;
641
642 txq = sta->txq[tid];
643 rtwtxq = (struct rtw_txq *)txq->drv_priv;
644 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
645 }
646
647 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
648 }
649 }
650
rtw_txq_ba_work(struct work_struct * work)651 static void rtw_txq_ba_work(struct work_struct *work)
652 {
653 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
654 struct rtw_txq_ba_iter_data data;
655
656 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
657 }
658
rtw_set_rx_freq_band(struct rtw_rx_pkt_stat * pkt_stat,u8 channel)659 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
660 {
661 if (IS_CH_2G_BAND(channel))
662 pkt_stat->band = NL80211_BAND_2GHZ;
663 else if (IS_CH_5G_BAND(channel))
664 pkt_stat->band = NL80211_BAND_5GHZ;
665 else
666 return;
667
668 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
669 }
670 EXPORT_SYMBOL(rtw_set_rx_freq_band);
671
rtw_set_dtim_period(struct rtw_dev * rtwdev,int dtim_period)672 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
673 {
674 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
675 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
676 }
677
rtw_update_channel(struct rtw_dev * rtwdev,u8 center_channel,u8 primary_channel,enum rtw_supported_band band,enum rtw_bandwidth bandwidth)678 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
679 u8 primary_channel, enum rtw_supported_band band,
680 enum rtw_bandwidth bandwidth)
681 {
682 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
683 struct rtw_hal *hal = &rtwdev->hal;
684 u8 *cch_by_bw = hal->cch_by_bw;
685 u32 center_freq, primary_freq;
686 enum rtw_sar_bands sar_band;
687 u8 primary_channel_idx;
688
689 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
690 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
691
692 /* assign the center channel used while 20M bw is selected */
693 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
694
695 /* assign the center channel used while current bw is selected */
696 cch_by_bw[bandwidth] = center_channel;
697
698 switch (bandwidth) {
699 case RTW_CHANNEL_WIDTH_20:
700 default:
701 primary_channel_idx = RTW_SC_DONT_CARE;
702 break;
703 case RTW_CHANNEL_WIDTH_40:
704 if (primary_freq > center_freq)
705 primary_channel_idx = RTW_SC_20_UPPER;
706 else
707 primary_channel_idx = RTW_SC_20_LOWER;
708 break;
709 case RTW_CHANNEL_WIDTH_80:
710 if (primary_freq > center_freq) {
711 if (primary_freq - center_freq == 10)
712 primary_channel_idx = RTW_SC_20_UPPER;
713 else
714 primary_channel_idx = RTW_SC_20_UPMOST;
715
716 /* assign the center channel used
717 * while 40M bw is selected
718 */
719 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
720 } else {
721 if (center_freq - primary_freq == 10)
722 primary_channel_idx = RTW_SC_20_LOWER;
723 else
724 primary_channel_idx = RTW_SC_20_LOWEST;
725
726 /* assign the center channel used
727 * while 40M bw is selected
728 */
729 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
730 }
731 break;
732 }
733
734 switch (center_channel) {
735 case 1 ... 14:
736 sar_band = RTW_SAR_BAND_0;
737 break;
738 case 36 ... 64:
739 sar_band = RTW_SAR_BAND_1;
740 break;
741 case 100 ... 144:
742 sar_band = RTW_SAR_BAND_3;
743 break;
744 case 149 ... 177:
745 sar_band = RTW_SAR_BAND_4;
746 break;
747 default:
748 WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
749 sar_band = RTW_SAR_BAND_0;
750 break;
751 }
752
753 hal->current_primary_channel_index = primary_channel_idx;
754 hal->current_band_width = bandwidth;
755 hal->primary_channel = primary_channel;
756 hal->current_channel = center_channel;
757 hal->current_band_type = band;
758 hal->sar_band = sar_band;
759 }
760
rtw_get_channel_params(struct cfg80211_chan_def * chandef,struct rtw_channel_params * chan_params)761 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
762 struct rtw_channel_params *chan_params)
763 {
764 struct ieee80211_channel *channel = chandef->chan;
765 enum nl80211_chan_width width = chandef->width;
766 u32 primary_freq, center_freq;
767 u8 center_chan;
768 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
769
770 center_chan = channel->hw_value;
771 primary_freq = channel->center_freq;
772 center_freq = chandef->center_freq1;
773
774 switch (width) {
775 case NL80211_CHAN_WIDTH_20_NOHT:
776 case NL80211_CHAN_WIDTH_20:
777 bandwidth = RTW_CHANNEL_WIDTH_20;
778 break;
779 case NL80211_CHAN_WIDTH_40:
780 bandwidth = RTW_CHANNEL_WIDTH_40;
781 if (primary_freq > center_freq)
782 center_chan -= 2;
783 else
784 center_chan += 2;
785 break;
786 case NL80211_CHAN_WIDTH_80:
787 bandwidth = RTW_CHANNEL_WIDTH_80;
788 if (primary_freq > center_freq) {
789 if (primary_freq - center_freq == 10)
790 center_chan -= 2;
791 else
792 center_chan -= 6;
793 } else {
794 if (center_freq - primary_freq == 10)
795 center_chan += 2;
796 else
797 center_chan += 6;
798 }
799 break;
800 default:
801 center_chan = 0;
802 break;
803 }
804
805 chan_params->center_chan = center_chan;
806 chan_params->bandwidth = bandwidth;
807 chan_params->primary_chan = channel->hw_value;
808 }
809
rtw_set_channel(struct rtw_dev * rtwdev)810 void rtw_set_channel(struct rtw_dev *rtwdev)
811 {
812 const struct rtw_chip_info *chip = rtwdev->chip;
813 struct ieee80211_hw *hw = rtwdev->hw;
814 struct rtw_hal *hal = &rtwdev->hal;
815 struct rtw_channel_params ch_param;
816 u8 center_chan, primary_chan, bandwidth, band;
817
818 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
819 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
820 return;
821
822 center_chan = ch_param.center_chan;
823 primary_chan = ch_param.primary_chan;
824 bandwidth = ch_param.bandwidth;
825 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
826
827 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
828
829 chip->ops->set_channel(rtwdev, center_chan, bandwidth,
830 hal->current_primary_channel_index);
831
832 if (hal->current_band_type == RTW_BAND_5G) {
833 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
834 } else {
835 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
836 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
837 else
838 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
839 }
840
841 rtw_phy_set_tx_power_level(rtwdev, center_chan);
842
843 /* if the channel isn't set for scanning, we will do RF calibration
844 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
845 * during scanning on each channel takes too long.
846 */
847 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
848 rtwdev->need_rfk = true;
849 }
850
rtw_chip_prepare_tx(struct rtw_dev * rtwdev)851 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
852 {
853 const struct rtw_chip_info *chip = rtwdev->chip;
854
855 if (rtwdev->need_rfk) {
856 rtwdev->need_rfk = false;
857 chip->ops->phy_calibration(rtwdev);
858 }
859 }
860
rtw_vif_write_addr(struct rtw_dev * rtwdev,u32 start,u8 * addr)861 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
862 {
863 int i;
864
865 for (i = 0; i < ETH_ALEN; i++)
866 rtw_write8(rtwdev, start + i, addr[i]);
867 }
868
rtw_vif_port_config(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,u32 config)869 void rtw_vif_port_config(struct rtw_dev *rtwdev,
870 struct rtw_vif *rtwvif,
871 u32 config)
872 {
873 u32 addr, mask;
874
875 if (config & PORT_SET_MAC_ADDR) {
876 addr = rtwvif->conf->mac_addr.addr;
877 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
878 }
879 if (config & PORT_SET_BSSID) {
880 addr = rtwvif->conf->bssid.addr;
881 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
882 }
883 if (config & PORT_SET_NET_TYPE) {
884 addr = rtwvif->conf->net_type.addr;
885 mask = rtwvif->conf->net_type.mask;
886 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
887 }
888 if (config & PORT_SET_AID) {
889 addr = rtwvif->conf->aid.addr;
890 mask = rtwvif->conf->aid.mask;
891 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
892 }
893 if (config & PORT_SET_BCN_CTRL) {
894 addr = rtwvif->conf->bcn_ctrl.addr;
895 mask = rtwvif->conf->bcn_ctrl.mask;
896 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
897 }
898 }
899
hw_bw_cap_to_bitamp(u8 bw_cap)900 static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
901 {
902 u8 bw = 0;
903
904 switch (bw_cap) {
905 case EFUSE_HW_CAP_IGNORE:
906 case EFUSE_HW_CAP_SUPP_BW80:
907 bw |= BIT(RTW_CHANNEL_WIDTH_80);
908 fallthrough;
909 case EFUSE_HW_CAP_SUPP_BW40:
910 bw |= BIT(RTW_CHANNEL_WIDTH_40);
911 fallthrough;
912 default:
913 bw |= BIT(RTW_CHANNEL_WIDTH_20);
914 break;
915 }
916
917 return bw;
918 }
919
rtw_hw_config_rf_ant_num(struct rtw_dev * rtwdev,u8 hw_ant_num)920 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
921 {
922 const struct rtw_chip_info *chip = rtwdev->chip;
923 struct rtw_hal *hal = &rtwdev->hal;
924
925 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
926 hw_ant_num >= hal->rf_path_num)
927 return;
928
929 switch (hw_ant_num) {
930 case 1:
931 hal->rf_type = RF_1T1R;
932 hal->rf_path_num = 1;
933 if (!chip->fix_rf_phy_num)
934 hal->rf_phy_num = hal->rf_path_num;
935 hal->antenna_tx = BB_PATH_A;
936 hal->antenna_rx = BB_PATH_A;
937 break;
938 default:
939 WARN(1, "invalid hw configuration from efuse\n");
940 break;
941 }
942 }
943
get_vht_ra_mask(struct ieee80211_sta * sta)944 static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
945 {
946 u64 ra_mask = 0;
947 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
948 u8 vht_mcs_cap;
949 int i, nss;
950
951 /* 4SS, every two bits for MCS7/8/9 */
952 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
953 vht_mcs_cap = mcs_map & 0x3;
954 switch (vht_mcs_cap) {
955 case 2: /* MCS9 */
956 ra_mask |= 0x3ffULL << nss;
957 break;
958 case 1: /* MCS8 */
959 ra_mask |= 0x1ffULL << nss;
960 break;
961 case 0: /* MCS7 */
962 ra_mask |= 0x0ffULL << nss;
963 break;
964 default:
965 break;
966 }
967 }
968
969 return ra_mask;
970 }
971
get_rate_id(u8 wireless_set,enum rtw_bandwidth bw_mode,u8 tx_num)972 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
973 {
974 u8 rate_id = 0;
975
976 switch (wireless_set) {
977 case WIRELESS_CCK:
978 rate_id = RTW_RATEID_B_20M;
979 break;
980 case WIRELESS_OFDM:
981 rate_id = RTW_RATEID_G;
982 break;
983 case WIRELESS_CCK | WIRELESS_OFDM:
984 rate_id = RTW_RATEID_BG;
985 break;
986 case WIRELESS_OFDM | WIRELESS_HT:
987 if (tx_num == 1)
988 rate_id = RTW_RATEID_GN_N1SS;
989 else if (tx_num == 2)
990 rate_id = RTW_RATEID_GN_N2SS;
991 else if (tx_num == 3)
992 rate_id = RTW_RATEID_ARFR5_N_3SS;
993 break;
994 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
995 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
996 if (tx_num == 1)
997 rate_id = RTW_RATEID_BGN_40M_1SS;
998 else if (tx_num == 2)
999 rate_id = RTW_RATEID_BGN_40M_2SS;
1000 else if (tx_num == 3)
1001 rate_id = RTW_RATEID_ARFR5_N_3SS;
1002 else if (tx_num == 4)
1003 rate_id = RTW_RATEID_ARFR7_N_4SS;
1004 } else {
1005 if (tx_num == 1)
1006 rate_id = RTW_RATEID_BGN_20M_1SS;
1007 else if (tx_num == 2)
1008 rate_id = RTW_RATEID_BGN_20M_2SS;
1009 else if (tx_num == 3)
1010 rate_id = RTW_RATEID_ARFR5_N_3SS;
1011 else if (tx_num == 4)
1012 rate_id = RTW_RATEID_ARFR7_N_4SS;
1013 }
1014 break;
1015 case WIRELESS_OFDM | WIRELESS_VHT:
1016 if (tx_num == 1)
1017 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1018 else if (tx_num == 2)
1019 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1020 else if (tx_num == 3)
1021 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1022 else if (tx_num == 4)
1023 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1024 break;
1025 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
1026 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
1027 if (tx_num == 1)
1028 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1029 else if (tx_num == 2)
1030 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1031 else if (tx_num == 3)
1032 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1033 else if (tx_num == 4)
1034 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1035 } else {
1036 if (tx_num == 1)
1037 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
1038 else if (tx_num == 2)
1039 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
1040 else if (tx_num == 3)
1041 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1042 else if (tx_num == 4)
1043 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1044 }
1045 break;
1046 default:
1047 break;
1048 }
1049
1050 return rate_id;
1051 }
1052
1053 #define RA_MASK_CCK_RATES 0x0000f
1054 #define RA_MASK_OFDM_RATES 0x00ff0
1055 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
1056 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
1057 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
1058 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
1059 RA_MASK_HT_RATES_2SS | \
1060 RA_MASK_HT_RATES_3SS)
1061 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
1062 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
1063 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
1064 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
1065 RA_MASK_VHT_RATES_2SS | \
1066 RA_MASK_VHT_RATES_3SS)
1067 #define RA_MASK_CCK_IN_BG 0x00005
1068 #define RA_MASK_CCK_IN_HT 0x00005
1069 #define RA_MASK_CCK_IN_VHT 0x00005
1070 #define RA_MASK_OFDM_IN_VHT 0x00010
1071 #define RA_MASK_OFDM_IN_HT_2G 0x00010
1072 #define RA_MASK_OFDM_IN_HT_5G 0x00030
1073
rtw_rate_mask_rssi(struct rtw_sta_info * si,u8 wireless_set)1074 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
1075 {
1076 u8 rssi_level = si->rssi_level;
1077
1078 if (wireless_set == WIRELESS_CCK)
1079 return 0xffffffffffffffffULL;
1080
1081 if (rssi_level == 0)
1082 return 0xffffffffffffffffULL;
1083 else if (rssi_level == 1)
1084 return 0xfffffffffffffff0ULL;
1085 else if (rssi_level == 2)
1086 return 0xffffffffffffefe0ULL;
1087 else if (rssi_level == 3)
1088 return 0xffffffffffffcfc0ULL;
1089 else if (rssi_level == 4)
1090 return 0xffffffffffff8f80ULL;
1091 else
1092 return 0xffffffffffff0f00ULL;
1093 }
1094
rtw_rate_mask_recover(u64 ra_mask,u64 ra_mask_bak)1095 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
1096 {
1097 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
1098 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1099
1100 if (ra_mask == 0)
1101 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1102
1103 return ra_mask;
1104 }
1105
rtw_rate_mask_cfg(struct rtw_dev * rtwdev,struct rtw_sta_info * si,u64 ra_mask,bool is_vht_enable)1106 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1107 u64 ra_mask, bool is_vht_enable)
1108 {
1109 struct rtw_hal *hal = &rtwdev->hal;
1110 const struct cfg80211_bitrate_mask *mask = si->mask;
1111 u64 cfg_mask = GENMASK_ULL(63, 0);
1112 u8 band;
1113
1114 if (!si->use_cfg_mask)
1115 return ra_mask;
1116
1117 band = hal->current_band_type;
1118 if (band == RTW_BAND_2G) {
1119 band = NL80211_BAND_2GHZ;
1120 cfg_mask = mask->control[band].legacy;
1121 } else if (band == RTW_BAND_5G) {
1122 band = NL80211_BAND_5GHZ;
1123 cfg_mask = u64_encode_bits(mask->control[band].legacy,
1124 RA_MASK_OFDM_RATES);
1125 }
1126
1127 if (!is_vht_enable) {
1128 if (ra_mask & RA_MASK_HT_RATES_1SS)
1129 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1130 RA_MASK_HT_RATES_1SS);
1131 if (ra_mask & RA_MASK_HT_RATES_2SS)
1132 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1133 RA_MASK_HT_RATES_2SS);
1134 } else {
1135 if (ra_mask & RA_MASK_VHT_RATES_1SS)
1136 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1137 RA_MASK_VHT_RATES_1SS);
1138 if (ra_mask & RA_MASK_VHT_RATES_2SS)
1139 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1140 RA_MASK_VHT_RATES_2SS);
1141 }
1142
1143 ra_mask &= cfg_mask;
1144
1145 return ra_mask;
1146 }
1147
rtw_update_sta_info(struct rtw_dev * rtwdev,struct rtw_sta_info * si,bool reset_ra_mask)1148 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1149 bool reset_ra_mask)
1150 {
1151 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1152 struct ieee80211_sta *sta = si->sta;
1153 struct rtw_efuse *efuse = &rtwdev->efuse;
1154 struct rtw_hal *hal = &rtwdev->hal;
1155 u8 wireless_set;
1156 u8 bw_mode;
1157 u8 rate_id;
1158 u8 rf_type = RF_1T1R;
1159 u8 stbc_en = 0;
1160 u8 ldpc_en = 0;
1161 u8 tx_num = 1;
1162 u64 ra_mask = 0;
1163 u64 ra_mask_bak = 0;
1164 bool is_vht_enable = false;
1165 bool is_support_sgi = false;
1166
1167 if (sta->deflink.vht_cap.vht_supported) {
1168 is_vht_enable = true;
1169 ra_mask |= get_vht_ra_mask(sta);
1170 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1171 stbc_en = VHT_STBC_EN;
1172 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1173 ldpc_en = VHT_LDPC_EN;
1174 } else if (sta->deflink.ht_cap.ht_supported) {
1175 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1176 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1177 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1178 stbc_en = HT_STBC_EN;
1179 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1180 ldpc_en = HT_LDPC_EN;
1181 }
1182
1183 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1184 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1185
1186 if (hal->current_band_type == RTW_BAND_5G) {
1187 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1188 ra_mask_bak = ra_mask;
1189 if (sta->deflink.vht_cap.vht_supported) {
1190 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1191 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1192 } else if (sta->deflink.ht_cap.ht_supported) {
1193 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1194 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1195 } else {
1196 wireless_set = WIRELESS_OFDM;
1197 }
1198 dm_info->rrsr_val_init = RRSR_INIT_5G;
1199 } else if (hal->current_band_type == RTW_BAND_2G) {
1200 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1201 ra_mask_bak = ra_mask;
1202 if (sta->deflink.vht_cap.vht_supported) {
1203 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1204 RA_MASK_OFDM_IN_VHT;
1205 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1206 WIRELESS_HT | WIRELESS_VHT;
1207 } else if (sta->deflink.ht_cap.ht_supported) {
1208 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1209 RA_MASK_OFDM_IN_HT_2G;
1210 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1211 WIRELESS_HT;
1212 } else if (sta->deflink.supp_rates[0] <= 0xf) {
1213 wireless_set = WIRELESS_CCK;
1214 } else {
1215 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
1216 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1217 }
1218 dm_info->rrsr_val_init = RRSR_INIT_2G;
1219 } else {
1220 rtw_err(rtwdev, "Unknown band type\n");
1221 ra_mask_bak = ra_mask;
1222 wireless_set = 0;
1223 }
1224
1225 switch (sta->deflink.bandwidth) {
1226 case IEEE80211_STA_RX_BW_80:
1227 bw_mode = RTW_CHANNEL_WIDTH_80;
1228 is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1229 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1230 break;
1231 case IEEE80211_STA_RX_BW_40:
1232 bw_mode = RTW_CHANNEL_WIDTH_40;
1233 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1234 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1235 break;
1236 default:
1237 bw_mode = RTW_CHANNEL_WIDTH_20;
1238 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1239 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1240 break;
1241 }
1242
1243 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
1244 tx_num = 2;
1245 rf_type = RF_2T2R;
1246 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
1247 tx_num = 2;
1248 rf_type = RF_2T2R;
1249 }
1250
1251 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1252
1253 ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
1254 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
1255 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
1256
1257 si->bw_mode = bw_mode;
1258 si->stbc_en = stbc_en;
1259 si->ldpc_en = ldpc_en;
1260 si->rf_type = rf_type;
1261 si->wireless_set = wireless_set;
1262 si->sgi_enable = is_support_sgi;
1263 si->vht_enable = is_vht_enable;
1264 si->ra_mask = ra_mask;
1265 si->rate_id = rate_id;
1266
1267 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
1268 }
1269
rtw_wait_firmware_completion(struct rtw_dev * rtwdev)1270 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1271 {
1272 const struct rtw_chip_info *chip = rtwdev->chip;
1273 struct rtw_fw_state *fw;
1274
1275 fw = &rtwdev->fw;
1276 wait_for_completion(&fw->completion);
1277 if (!fw->firmware)
1278 return -EINVAL;
1279
1280 if (chip->wow_fw_name) {
1281 fw = &rtwdev->wow_fw;
1282 wait_for_completion(&fw->completion);
1283 if (!fw->firmware)
1284 return -EINVAL;
1285 }
1286
1287 return 0;
1288 }
1289
rtw_update_lps_deep_mode(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1290 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1291 struct rtw_fw_state *fw)
1292 {
1293 const struct rtw_chip_info *chip = rtwdev->chip;
1294
1295 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1296 !fw->feature)
1297 return LPS_DEEP_MODE_NONE;
1298
1299 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1300 rtw_fw_feature_check(fw, FW_FEATURE_PG))
1301 return LPS_DEEP_MODE_PG;
1302
1303 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1304 rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1305 return LPS_DEEP_MODE_LCLK;
1306
1307 return LPS_DEEP_MODE_NONE;
1308 }
1309
rtw_power_on(struct rtw_dev * rtwdev)1310 static int rtw_power_on(struct rtw_dev *rtwdev)
1311 {
1312 const struct rtw_chip_info *chip = rtwdev->chip;
1313 struct rtw_fw_state *fw = &rtwdev->fw;
1314 bool wifi_only;
1315 int ret;
1316
1317 ret = rtw_hci_setup(rtwdev);
1318 if (ret) {
1319 rtw_err(rtwdev, "failed to setup hci\n");
1320 goto err;
1321 }
1322
1323 /* power on MAC before firmware downloaded */
1324 ret = rtw_mac_power_on(rtwdev);
1325 if (ret) {
1326 rtw_err(rtwdev, "failed to power on mac\n");
1327 goto err;
1328 }
1329
1330 ret = rtw_wait_firmware_completion(rtwdev);
1331 if (ret) {
1332 rtw_err(rtwdev, "failed to wait firmware completion\n");
1333 goto err_off;
1334 }
1335
1336 ret = rtw_download_firmware(rtwdev, fw);
1337 if (ret) {
1338 rtw_err(rtwdev, "failed to download firmware\n");
1339 goto err_off;
1340 }
1341
1342 /* config mac after firmware downloaded */
1343 ret = rtw_mac_init(rtwdev);
1344 if (ret) {
1345 rtw_err(rtwdev, "failed to configure mac\n");
1346 goto err_off;
1347 }
1348
1349 chip->ops->phy_set_param(rtwdev);
1350
1351 ret = rtw_hci_start(rtwdev);
1352 if (ret) {
1353 rtw_err(rtwdev, "failed to start hci\n");
1354 goto err_off;
1355 }
1356
1357 /* send H2C after HCI has started */
1358 rtw_fw_send_general_info(rtwdev);
1359 rtw_fw_send_phydm_info(rtwdev);
1360
1361 wifi_only = !rtwdev->efuse.btcoex;
1362 rtw_coex_power_on_setting(rtwdev);
1363 rtw_coex_init_hw_config(rtwdev, wifi_only);
1364
1365 return 0;
1366
1367 err_off:
1368 rtw_mac_power_off(rtwdev);
1369
1370 err:
1371 return ret;
1372 }
1373
rtw_core_fw_scan_notify(struct rtw_dev * rtwdev,bool start)1374 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1375 {
1376 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1377 return;
1378
1379 if (start) {
1380 rtw_fw_scan_notify(rtwdev, true);
1381 } else {
1382 reinit_completion(&rtwdev->fw_scan_density);
1383 rtw_fw_scan_notify(rtwdev, false);
1384 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1385 SCAN_NOTIFY_TIMEOUT))
1386 rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1387 }
1388 }
1389
rtw_core_scan_start(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,const u8 * mac_addr,bool hw_scan)1390 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1391 const u8 *mac_addr, bool hw_scan)
1392 {
1393 u32 config = 0;
1394 int ret = 0;
1395
1396 rtw_leave_lps(rtwdev);
1397
1398 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1399 ret = rtw_leave_ips(rtwdev);
1400 if (ret) {
1401 rtw_err(rtwdev, "failed to leave idle state\n");
1402 return;
1403 }
1404 }
1405
1406 ether_addr_copy(rtwvif->mac_addr, mac_addr);
1407 config |= PORT_SET_MAC_ADDR;
1408 rtw_vif_port_config(rtwdev, rtwvif, config);
1409
1410 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
1411 rtw_core_fw_scan_notify(rtwdev, true);
1412
1413 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1414 set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1415 }
1416
rtw_core_scan_complete(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)1417 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
1418 bool hw_scan)
1419 {
1420 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1421 u32 config = 0;
1422
1423 if (!rtwvif)
1424 return;
1425
1426 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1427 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1428
1429 rtw_core_fw_scan_notify(rtwdev, false);
1430
1431 ether_addr_copy(rtwvif->mac_addr, vif->addr);
1432 config |= PORT_SET_MAC_ADDR;
1433 rtw_vif_port_config(rtwdev, rtwvif, config);
1434
1435 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
1436
1437 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1438 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1439 }
1440
rtw_core_start(struct rtw_dev * rtwdev)1441 int rtw_core_start(struct rtw_dev *rtwdev)
1442 {
1443 int ret;
1444
1445 ret = rtw_power_on(rtwdev);
1446 if (ret)
1447 return ret;
1448
1449 rtw_sec_enable_sec_engine(rtwdev);
1450
1451 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1452 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1453
1454 /* rcr reset after powered on */
1455 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1456
1457 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1458 RTW_WATCH_DOG_DELAY_TIME);
1459
1460 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1461
1462 return 0;
1463 }
1464
rtw_power_off(struct rtw_dev * rtwdev)1465 static void rtw_power_off(struct rtw_dev *rtwdev)
1466 {
1467 rtw_hci_stop(rtwdev);
1468 rtw_coex_power_off_setting(rtwdev);
1469 rtw_mac_power_off(rtwdev);
1470 }
1471
rtw_core_stop(struct rtw_dev * rtwdev)1472 void rtw_core_stop(struct rtw_dev *rtwdev)
1473 {
1474 struct rtw_coex *coex = &rtwdev->coex;
1475
1476 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1477 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1478
1479 mutex_unlock(&rtwdev->mutex);
1480
1481 cancel_work_sync(&rtwdev->c2h_work);
1482 cancel_work_sync(&rtwdev->update_beacon_work);
1483 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1484 cancel_delayed_work_sync(&coex->bt_relink_work);
1485 cancel_delayed_work_sync(&coex->bt_reenable_work);
1486 cancel_delayed_work_sync(&coex->defreeze_work);
1487 cancel_delayed_work_sync(&coex->wl_remain_work);
1488 cancel_delayed_work_sync(&coex->bt_remain_work);
1489 cancel_delayed_work_sync(&coex->wl_connecting_work);
1490 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1491 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1492
1493 mutex_lock(&rtwdev->mutex);
1494
1495 rtw_power_off(rtwdev);
1496 }
1497
rtw_init_ht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)1498 static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1499 struct ieee80211_sta_ht_cap *ht_cap)
1500 {
1501 const struct rtw_chip_info *chip = rtwdev->chip;
1502 struct rtw_efuse *efuse = &rtwdev->efuse;
1503
1504 ht_cap->ht_supported = true;
1505 ht_cap->cap = 0;
1506 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1507 IEEE80211_HT_CAP_MAX_AMSDU |
1508 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1509
1510 if (rtw_chip_has_rx_ldpc(rtwdev))
1511 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1512 if (rtw_chip_has_tx_stbc(rtwdev))
1513 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1514
1515 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1516 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1517 IEEE80211_HT_CAP_DSSSCCK40 |
1518 IEEE80211_HT_CAP_SGI_40;
1519 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1520 ht_cap->ampdu_density = chip->ampdu_density;
1521 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1522 if (efuse->hw_cap.nss > 1) {
1523 ht_cap->mcs.rx_mask[0] = 0xFF;
1524 ht_cap->mcs.rx_mask[1] = 0xFF;
1525 ht_cap->mcs.rx_mask[4] = 0x01;
1526 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1527 } else {
1528 ht_cap->mcs.rx_mask[0] = 0xFF;
1529 ht_cap->mcs.rx_mask[1] = 0x00;
1530 ht_cap->mcs.rx_mask[4] = 0x01;
1531 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1532 }
1533 }
1534
rtw_init_vht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)1535 static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1536 struct ieee80211_sta_vht_cap *vht_cap)
1537 {
1538 struct rtw_efuse *efuse = &rtwdev->efuse;
1539 u16 mcs_map;
1540 __le16 highest;
1541
1542 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1543 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1544 return;
1545
1546 vht_cap->vht_supported = true;
1547 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1548 IEEE80211_VHT_CAP_SHORT_GI_80 |
1549 IEEE80211_VHT_CAP_RXSTBC_1 |
1550 IEEE80211_VHT_CAP_HTC_VHT |
1551 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1552 0;
1553 if (rtwdev->hal.rf_path_num > 1)
1554 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1555 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1556 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1557 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1558 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1559
1560 if (rtw_chip_has_rx_ldpc(rtwdev))
1561 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1562
1563 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1564 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1565 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1566 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1567 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1568 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1569 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1570 if (efuse->hw_cap.nss > 1) {
1571 highest = cpu_to_le16(780);
1572 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1573 } else {
1574 highest = cpu_to_le16(390);
1575 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1576 }
1577
1578 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1579 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1580 vht_cap->vht_mcs.rx_highest = highest;
1581 vht_cap->vht_mcs.tx_highest = highest;
1582 }
1583
rtw_get_max_scan_ie_len(struct rtw_dev * rtwdev)1584 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
1585 {
1586 u16 len;
1587
1588 len = rtwdev->chip->max_scan_ie_len;
1589
1590 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
1591 rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
1592 len = IEEE80211_MAX_DATA_LEN;
1593 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
1594 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
1595
1596 return len;
1597 }
1598
rtw_set_supported_band(struct ieee80211_hw * hw,const struct rtw_chip_info * chip)1599 static void rtw_set_supported_band(struct ieee80211_hw *hw,
1600 const struct rtw_chip_info *chip)
1601 {
1602 struct rtw_dev *rtwdev = hw->priv;
1603 struct ieee80211_supported_band *sband;
1604
1605 if (chip->band & RTW_BAND_2G) {
1606 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1607 if (!sband)
1608 goto err_out;
1609 if (chip->ht_supported)
1610 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1611 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1612 }
1613
1614 if (chip->band & RTW_BAND_5G) {
1615 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1616 if (!sband)
1617 goto err_out;
1618 if (chip->ht_supported)
1619 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1620 if (chip->vht_supported)
1621 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1622 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1623 }
1624
1625 return;
1626
1627 err_out:
1628 rtw_err(rtwdev, "failed to set supported band\n");
1629 }
1630
rtw_unset_supported_band(struct ieee80211_hw * hw,const struct rtw_chip_info * chip)1631 static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1632 const struct rtw_chip_info *chip)
1633 {
1634 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1635 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1636 }
1637
rtw_vif_smps_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1638 static void rtw_vif_smps_iter(void *data, u8 *mac,
1639 struct ieee80211_vif *vif)
1640 {
1641 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
1642
1643 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1644 return;
1645
1646 if (rtwdev->hal.txrx_1ss)
1647 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
1648 else
1649 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
1650 }
1651
rtw_set_txrx_1ss(struct rtw_dev * rtwdev,bool txrx_1ss)1652 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
1653 {
1654 const struct rtw_chip_info *chip = rtwdev->chip;
1655 struct rtw_hal *hal = &rtwdev->hal;
1656
1657 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1658 return;
1659
1660 rtwdev->hal.txrx_1ss = txrx_1ss;
1661 if (txrx_1ss)
1662 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1663 else
1664 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1665 hal->antenna_rx, false);
1666 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
1667 }
1668
__update_firmware_feature(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1669 static void __update_firmware_feature(struct rtw_dev *rtwdev,
1670 struct rtw_fw_state *fw)
1671 {
1672 u32 feature;
1673 const struct rtw_fw_hdr *fw_hdr =
1674 (const struct rtw_fw_hdr *)fw->firmware->data;
1675
1676 feature = le32_to_cpu(fw_hdr->feature);
1677 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1678
1679 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
1680 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
1681 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
1682 }
1683
__update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1684 static void __update_firmware_info(struct rtw_dev *rtwdev,
1685 struct rtw_fw_state *fw)
1686 {
1687 const struct rtw_fw_hdr *fw_hdr =
1688 (const struct rtw_fw_hdr *)fw->firmware->data;
1689
1690 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1691 fw->version = le16_to_cpu(fw_hdr->version);
1692 fw->sub_version = fw_hdr->subversion;
1693 fw->sub_index = fw_hdr->subindex;
1694
1695 __update_firmware_feature(rtwdev, fw);
1696 }
1697
__update_firmware_info_legacy(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1698 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1699 struct rtw_fw_state *fw)
1700 {
1701 struct rtw_fw_hdr_legacy *legacy =
1702 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1703
1704 fw->h2c_version = 0;
1705 fw->version = le16_to_cpu(legacy->version);
1706 fw->sub_version = legacy->subversion1;
1707 fw->sub_index = legacy->subversion2;
1708 }
1709
update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1710 static void update_firmware_info(struct rtw_dev *rtwdev,
1711 struct rtw_fw_state *fw)
1712 {
1713 if (rtw_chip_wcpu_11n(rtwdev))
1714 __update_firmware_info_legacy(rtwdev, fw);
1715 else
1716 __update_firmware_info(rtwdev, fw);
1717 }
1718
rtw_load_firmware_cb(const struct firmware * firmware,void * context)1719 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1720 {
1721 struct rtw_fw_state *fw = context;
1722 struct rtw_dev *rtwdev = fw->rtwdev;
1723
1724 if (!firmware || !firmware->data) {
1725 rtw_err(rtwdev, "failed to request firmware\n");
1726 complete_all(&fw->completion);
1727 return;
1728 }
1729
1730 fw->firmware = firmware;
1731 update_firmware_info(rtwdev, fw);
1732 complete_all(&fw->completion);
1733
1734 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1735 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1736 }
1737
rtw_load_firmware(struct rtw_dev * rtwdev,enum rtw_fw_type type)1738 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1739 {
1740 const char *fw_name;
1741 struct rtw_fw_state *fw;
1742 int ret;
1743
1744 switch (type) {
1745 case RTW_WOWLAN_FW:
1746 fw = &rtwdev->wow_fw;
1747 fw_name = rtwdev->chip->wow_fw_name;
1748 break;
1749
1750 case RTW_NORMAL_FW:
1751 fw = &rtwdev->fw;
1752 fw_name = rtwdev->chip->fw_name;
1753 break;
1754
1755 default:
1756 rtw_warn(rtwdev, "unsupported firmware type\n");
1757 return -ENOENT;
1758 }
1759
1760 fw->rtwdev = rtwdev;
1761 init_completion(&fw->completion);
1762
1763 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1764 GFP_KERNEL, fw, rtw_load_firmware_cb);
1765 if (ret) {
1766 rtw_err(rtwdev, "failed to async firmware request\n");
1767 return ret;
1768 }
1769
1770 return 0;
1771 }
1772
rtw_chip_parameter_setup(struct rtw_dev * rtwdev)1773 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1774 {
1775 const struct rtw_chip_info *chip = rtwdev->chip;
1776 struct rtw_hal *hal = &rtwdev->hal;
1777 struct rtw_efuse *efuse = &rtwdev->efuse;
1778
1779 switch (rtw_hci_type(rtwdev)) {
1780 case RTW_HCI_TYPE_PCIE:
1781 rtwdev->hci.rpwm_addr = 0x03d9;
1782 rtwdev->hci.cpwm_addr = 0x03da;
1783 break;
1784 default:
1785 rtw_err(rtwdev, "unsupported hci type\n");
1786 return -EINVAL;
1787 }
1788
1789 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1790 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1791 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1792 if (hal->chip_version & BIT_RF_TYPE_ID) {
1793 hal->rf_type = RF_2T2R;
1794 hal->rf_path_num = 2;
1795 hal->antenna_tx = BB_PATH_AB;
1796 hal->antenna_rx = BB_PATH_AB;
1797 } else {
1798 hal->rf_type = RF_1T1R;
1799 hal->rf_path_num = 1;
1800 hal->antenna_tx = BB_PATH_A;
1801 hal->antenna_rx = BB_PATH_A;
1802 }
1803 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1804 hal->rf_path_num;
1805
1806 efuse->physical_size = chip->phy_efuse_size;
1807 efuse->logical_size = chip->log_efuse_size;
1808 efuse->protect_size = chip->ptct_efuse_size;
1809
1810 /* default use ack */
1811 rtwdev->hal.rcr |= BIT_VHT_DACK;
1812
1813 hal->bfee_sts_cap = 3;
1814
1815 return 0;
1816 }
1817
rtw_chip_efuse_enable(struct rtw_dev * rtwdev)1818 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1819 {
1820 struct rtw_fw_state *fw = &rtwdev->fw;
1821 int ret;
1822
1823 ret = rtw_hci_setup(rtwdev);
1824 if (ret) {
1825 rtw_err(rtwdev, "failed to setup hci\n");
1826 goto err;
1827 }
1828
1829 ret = rtw_mac_power_on(rtwdev);
1830 if (ret) {
1831 rtw_err(rtwdev, "failed to power on mac\n");
1832 goto err;
1833 }
1834
1835 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1836
1837 wait_for_completion(&fw->completion);
1838 if (!fw->firmware) {
1839 ret = -EINVAL;
1840 rtw_err(rtwdev, "failed to load firmware\n");
1841 goto err;
1842 }
1843
1844 ret = rtw_download_firmware(rtwdev, fw);
1845 if (ret) {
1846 rtw_err(rtwdev, "failed to download firmware\n");
1847 goto err_off;
1848 }
1849
1850 return 0;
1851
1852 err_off:
1853 rtw_mac_power_off(rtwdev);
1854
1855 err:
1856 return ret;
1857 }
1858
rtw_dump_hw_feature(struct rtw_dev * rtwdev)1859 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1860 {
1861 struct rtw_efuse *efuse = &rtwdev->efuse;
1862 u8 hw_feature[HW_FEATURE_LEN];
1863 u8 id;
1864 u8 bw;
1865 int i;
1866
1867 id = rtw_read8(rtwdev, REG_C2HEVT);
1868 if (id != C2H_HW_FEATURE_REPORT) {
1869 rtw_err(rtwdev, "failed to read hw feature report\n");
1870 return -EBUSY;
1871 }
1872
1873 for (i = 0; i < HW_FEATURE_LEN; i++)
1874 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1875
1876 rtw_write8(rtwdev, REG_C2HEVT, 0);
1877
1878 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1879 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1880 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1881 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1882 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1883 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1884
1885 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1886
1887 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1888 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1889 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1890
1891 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1892 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1893 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1894 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1895
1896 return 0;
1897 }
1898
rtw_chip_efuse_disable(struct rtw_dev * rtwdev)1899 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1900 {
1901 rtw_hci_stop(rtwdev);
1902 rtw_mac_power_off(rtwdev);
1903 }
1904
rtw_chip_efuse_info_setup(struct rtw_dev * rtwdev)1905 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1906 {
1907 struct rtw_efuse *efuse = &rtwdev->efuse;
1908 int ret;
1909
1910 mutex_lock(&rtwdev->mutex);
1911
1912 /* power on mac to read efuse */
1913 ret = rtw_chip_efuse_enable(rtwdev);
1914 if (ret)
1915 goto out_unlock;
1916
1917 ret = rtw_parse_efuse_map(rtwdev);
1918 if (ret)
1919 goto out_disable;
1920
1921 ret = rtw_dump_hw_feature(rtwdev);
1922 if (ret)
1923 goto out_disable;
1924
1925 ret = rtw_check_supported_rfe(rtwdev);
1926 if (ret)
1927 goto out_disable;
1928
1929 if (efuse->crystal_cap == 0xff)
1930 efuse->crystal_cap = 0;
1931 if (efuse->pa_type_2g == 0xff)
1932 efuse->pa_type_2g = 0;
1933 if (efuse->pa_type_5g == 0xff)
1934 efuse->pa_type_5g = 0;
1935 if (efuse->lna_type_2g == 0xff)
1936 efuse->lna_type_2g = 0;
1937 if (efuse->lna_type_5g == 0xff)
1938 efuse->lna_type_5g = 0;
1939 if (efuse->channel_plan == 0xff)
1940 efuse->channel_plan = 0x7f;
1941 if (efuse->rf_board_option == 0xff)
1942 efuse->rf_board_option = 0;
1943 if (efuse->bt_setting & BIT(0))
1944 efuse->share_ant = true;
1945 if (efuse->regd == 0xff)
1946 efuse->regd = 0;
1947 if (efuse->tx_bb_swing_setting_2g == 0xff)
1948 efuse->tx_bb_swing_setting_2g = 0;
1949 if (efuse->tx_bb_swing_setting_5g == 0xff)
1950 efuse->tx_bb_swing_setting_5g = 0;
1951
1952 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1953 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1954 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1955 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1956 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1957
1958 out_disable:
1959 rtw_chip_efuse_disable(rtwdev);
1960
1961 out_unlock:
1962 mutex_unlock(&rtwdev->mutex);
1963 return ret;
1964 }
1965
rtw_chip_board_info_setup(struct rtw_dev * rtwdev)1966 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1967 {
1968 struct rtw_hal *hal = &rtwdev->hal;
1969 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1970
1971 if (!rfe_def)
1972 return -ENODEV;
1973
1974 rtw_phy_setup_phy_cond(rtwdev, 0);
1975
1976 rtw_phy_init_tx_power(rtwdev);
1977 if (rfe_def->agc_btg_tbl)
1978 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
1979 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1980 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1981 rtw_phy_tx_power_by_rate_config(hal);
1982 rtw_phy_tx_power_limit_config(hal);
1983
1984 return 0;
1985 }
1986
rtw_chip_info_setup(struct rtw_dev * rtwdev)1987 int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1988 {
1989 int ret;
1990
1991 ret = rtw_chip_parameter_setup(rtwdev);
1992 if (ret) {
1993 rtw_err(rtwdev, "failed to setup chip parameters\n");
1994 goto err_out;
1995 }
1996
1997 ret = rtw_chip_efuse_info_setup(rtwdev);
1998 if (ret) {
1999 rtw_err(rtwdev, "failed to setup chip efuse info\n");
2000 goto err_out;
2001 }
2002
2003 ret = rtw_chip_board_info_setup(rtwdev);
2004 if (ret) {
2005 rtw_err(rtwdev, "failed to setup chip board info\n");
2006 goto err_out;
2007 }
2008
2009 return 0;
2010
2011 err_out:
2012 return ret;
2013 }
2014 EXPORT_SYMBOL(rtw_chip_info_setup);
2015
rtw_stats_init(struct rtw_dev * rtwdev)2016 static void rtw_stats_init(struct rtw_dev *rtwdev)
2017 {
2018 struct rtw_traffic_stats *stats = &rtwdev->stats;
2019 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2020 int i;
2021
2022 ewma_tp_init(&stats->tx_ewma_tp);
2023 ewma_tp_init(&stats->rx_ewma_tp);
2024
2025 for (i = 0; i < RTW_EVM_NUM; i++)
2026 ewma_evm_init(&dm_info->ewma_evm[i]);
2027 for (i = 0; i < RTW_SNR_NUM; i++)
2028 ewma_snr_init(&dm_info->ewma_snr[i]);
2029 }
2030
rtw_core_init(struct rtw_dev * rtwdev)2031 int rtw_core_init(struct rtw_dev *rtwdev)
2032 {
2033 const struct rtw_chip_info *chip = rtwdev->chip;
2034 struct rtw_coex *coex = &rtwdev->coex;
2035 int ret;
2036
2037 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
2038 INIT_LIST_HEAD(&rtwdev->txqs);
2039
2040 timer_setup(&rtwdev->tx_report.purge_timer,
2041 rtw_tx_report_purge_timer, 0);
2042 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
2043 if (!rtwdev->tx_wq) {
2044 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
2045 return -ENOMEM;
2046 }
2047
2048 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2049 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2050 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2051 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2052 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2053 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2054 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2055 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2056 rtw_coex_bt_multi_link_remain_work);
2057 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2058 INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2059 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2060 INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2061 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2062 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2063 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2064 skb_queue_head_init(&rtwdev->c2h_queue);
2065 skb_queue_head_init(&rtwdev->coex.queue);
2066 skb_queue_head_init(&rtwdev->tx_report.queue);
2067
2068 spin_lock_init(&rtwdev->rf_lock);
2069 spin_lock_init(&rtwdev->h2c.lock);
2070 spin_lock_init(&rtwdev->txq_lock);
2071 spin_lock_init(&rtwdev->tx_report.q_lock);
2072
2073 mutex_init(&rtwdev->mutex);
2074 mutex_init(&rtwdev->coex.mutex);
2075 mutex_init(&rtwdev->hal.tx_power_mutex);
2076
2077 init_waitqueue_head(&rtwdev->coex.wait);
2078 init_completion(&rtwdev->lps_leave_check);
2079 init_completion(&rtwdev->fw_scan_density);
2080
2081 rtwdev->sec.total_cam_num = 32;
2082 rtwdev->hal.current_channel = 1;
2083 rtwdev->dm_info.fix_rate = U8_MAX;
2084 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
2085
2086 rtw_stats_init(rtwdev);
2087
2088 /* default rx filter setting */
2089 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2090 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
2091 BIT_AB | BIT_AM | BIT_APM;
2092
2093 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
2094 if (ret) {
2095 rtw_warn(rtwdev, "no firmware loaded\n");
2096 goto out;
2097 }
2098
2099 if (chip->wow_fw_name) {
2100 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
2101 if (ret) {
2102 rtw_warn(rtwdev, "no wow firmware loaded\n");
2103 wait_for_completion(&rtwdev->fw.completion);
2104 if (rtwdev->fw.firmware)
2105 release_firmware(rtwdev->fw.firmware);
2106 goto out;
2107 }
2108 }
2109
2110 return 0;
2111
2112 out:
2113 destroy_workqueue(rtwdev->tx_wq);
2114 return ret;
2115 }
2116 EXPORT_SYMBOL(rtw_core_init);
2117
rtw_core_deinit(struct rtw_dev * rtwdev)2118 void rtw_core_deinit(struct rtw_dev *rtwdev)
2119 {
2120 struct rtw_fw_state *fw = &rtwdev->fw;
2121 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2122 struct rtw_rsvd_page *rsvd_pkt, *tmp;
2123 unsigned long flags;
2124
2125 rtw_wait_firmware_completion(rtwdev);
2126
2127 if (fw->firmware)
2128 release_firmware(fw->firmware);
2129
2130 if (wow_fw->firmware)
2131 release_firmware(wow_fw->firmware);
2132
2133 destroy_workqueue(rtwdev->tx_wq);
2134 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2135 skb_queue_purge(&rtwdev->tx_report.queue);
2136 skb_queue_purge(&rtwdev->coex.queue);
2137 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2138
2139 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2140 build_list) {
2141 list_del(&rsvd_pkt->build_list);
2142 kfree(rsvd_pkt);
2143 }
2144
2145 mutex_destroy(&rtwdev->mutex);
2146 mutex_destroy(&rtwdev->coex.mutex);
2147 mutex_destroy(&rtwdev->hal.tx_power_mutex);
2148 }
2149 EXPORT_SYMBOL(rtw_core_deinit);
2150
rtw_register_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)2151 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2152 {
2153 struct rtw_hal *hal = &rtwdev->hal;
2154 int max_tx_headroom = 0;
2155 int ret;
2156
2157 /* TODO: USB & SDIO may need extra room? */
2158 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2159
2160 hw->extra_tx_headroom = max_tx_headroom;
2161 hw->queues = IEEE80211_NUM_ACS;
2162 hw->txq_data_size = sizeof(struct rtw_txq);
2163 hw->sta_data_size = sizeof(struct rtw_sta_info);
2164 hw->vif_data_size = sizeof(struct rtw_vif);
2165
2166 ieee80211_hw_set(hw, SIGNAL_DBM);
2167 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2168 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2169 ieee80211_hw_set(hw, MFP_CAPABLE);
2170 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2171 ieee80211_hw_set(hw, SUPPORTS_PS);
2172 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
2173 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
2174 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
2175 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
2176 ieee80211_hw_set(hw, TX_AMSDU);
2177 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
2178
2179 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2180 BIT(NL80211_IFTYPE_AP) |
2181 BIT(NL80211_IFTYPE_ADHOC) |
2182 BIT(NL80211_IFTYPE_MESH_POINT);
2183 hw->wiphy->available_antennas_tx = hal->antenna_tx;
2184 hw->wiphy->available_antennas_rx = hal->antenna_rx;
2185
2186 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2187 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
2188
2189 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2190 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2191 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
2192
2193 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2194 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2195 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2196
2197 #ifdef CONFIG_PM
2198 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2199 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2200 #endif
2201 rtw_set_supported_band(hw, rtwdev->chip);
2202 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2203
2204 hw->wiphy->sar_capa = &rtw_sar_capa;
2205
2206 ret = rtw_regd_init(rtwdev);
2207 if (ret) {
2208 rtw_err(rtwdev, "failed to init regd\n");
2209 return ret;
2210 }
2211
2212 ret = ieee80211_register_hw(hw);
2213 if (ret) {
2214 rtw_err(rtwdev, "failed to register hw\n");
2215 return ret;
2216 }
2217
2218 ret = rtw_regd_hint(rtwdev);
2219 if (ret) {
2220 rtw_err(rtwdev, "failed to hint regd\n");
2221 return ret;
2222 }
2223
2224 rtw_debugfs_init(rtwdev);
2225
2226 rtwdev->bf_info.bfer_mu_cnt = 0;
2227 rtwdev->bf_info.bfer_su_cnt = 0;
2228
2229 return 0;
2230 }
2231 EXPORT_SYMBOL(rtw_register_hw);
2232
rtw_unregister_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)2233 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2234 {
2235 const struct rtw_chip_info *chip = rtwdev->chip;
2236
2237 ieee80211_unregister_hw(hw);
2238 rtw_unset_supported_band(hw, chip);
2239 }
2240 EXPORT_SYMBOL(rtw_unregister_hw);
2241
2242 MODULE_AUTHOR("Realtek Corporation");
2243 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
2244 MODULE_LICENSE("Dual BSD/GPL");
2245