1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation.
3 */
4
5 #include "main.h"
6 #include "reg.h"
7 #include "bf.h"
8 #include "debug.h"
9
rtw_bf_disassoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11 struct ieee80211_bss_conf *bss_conf)
12 {
13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14 struct rtw_bfee *bfee = &rtwvif->bfee;
15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16
17 if (bfee->role == RTW_BFEE_NONE)
18 return;
19
20 if (bfee->role == RTW_BFEE_MU)
21 bfinfo->bfer_mu_cnt--;
22 else if (bfee->role == RTW_BFEE_SU)
23 bfinfo->bfer_su_cnt--;
24
25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26
27 bfee->role = RTW_BFEE_NONE;
28 }
29
rtw_bf_assoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31 struct ieee80211_bss_conf *bss_conf)
32 {
33 const struct rtw_chip_info *chip = rtwdev->chip;
34 struct ieee80211_hw *hw = rtwdev->hw;
35 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
36 struct rtw_bfee *bfee = &rtwvif->bfee;
37 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
38 struct ieee80211_sta *sta;
39 struct ieee80211_sta_vht_cap *vht_cap;
40 struct ieee80211_sta_vht_cap *ic_vht_cap;
41 const u8 *bssid = bss_conf->bssid;
42 u32 sound_dim;
43 u8 i;
44
45 if (!(chip->band & RTW_BAND_5G))
46 return;
47
48 rcu_read_lock();
49
50 sta = ieee80211_find_sta(vif, bssid);
51 if (!sta) {
52 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
53 bssid);
54 goto out_unlock;
55 }
56
57 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
58 vht_cap = &sta->deflink.vht_cap;
59
60 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
61 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
62 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
63 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
64 goto out_unlock;
65 }
66
67 ether_addr_copy(bfee->mac_addr, bssid);
68 bfee->role = RTW_BFEE_MU;
69 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
70 bfee->aid = vif->cfg.aid;
71 bfinfo->bfer_mu_cnt++;
72
73 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
74 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
75 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
76 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
77 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
78 goto out_unlock;
79 }
80
81 sound_dim = vht_cap->cap &
82 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
83 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
84
85 ether_addr_copy(bfee->mac_addr, bssid);
86 bfee->role = RTW_BFEE_SU;
87 bfee->sound_dim = (u8)sound_dim;
88 bfee->g_id = 0;
89 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
90 bfinfo->bfer_su_cnt++;
91 for (i = 0; i < chip->bfer_su_max_num; i++) {
92 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
93 set_bit(i, bfinfo->bfer_su_reg_maping);
94 bfee->su_reg_index = i;
95 break;
96 }
97 }
98
99 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
100 }
101
102 out_unlock:
103 rcu_read_unlock();
104 }
105
rtw_bf_init_bfer_entry_mu(struct rtw_dev * rtwdev,struct mu_bfer_init_para * param)106 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
107 struct mu_bfer_init_para *param)
108 {
109 u16 mu_bf_ctl = 0;
110 u8 *addr = param->bfer_address;
111 int i;
112
113 for (i = 0; i < ETH_ALEN; i++)
114 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
115 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
116 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
117
118 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
119 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
120 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
121 }
122
rtw_bf_cfg_sounding(struct rtw_dev * rtwdev,struct rtw_vif * vif,enum rtw_trx_desc_rate rate)123 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
124 enum rtw_trx_desc_rate rate)
125 {
126 u32 psf_ctl = 0;
127 u8 csi_rsc = 0x1;
128
129 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
130 BIT_WMAC_USE_NDPARATE |
131 (csi_rsc << 13);
132
133 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
134 RTW_SND_CTRL_SOUNDING);
135 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
136 rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
137 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
138
139 if (vif->net_type == RTW_NET_AP_MODE)
140 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
141 else
142 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
143 }
144
rtw_bf_cfg_mu_bfee(struct rtw_dev * rtwdev,struct cfg_mumimo_para * param)145 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
146 {
147 u8 mu_tbl_sel;
148 u8 mu_valid;
149
150 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
151 ~BIT_MASK_R_MU_TABLE_VALID;
152
153 rtw_write8(rtwdev, REG_MU_TX_CTL,
154 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
155
156 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
157
158 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
159 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
160 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
161 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
162 param->given_user_pos[1]);
163
164 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
165 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
166 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
167 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
168 param->given_user_pos[3]);
169 }
170
rtw_bf_del_bfer_entry_mu(struct rtw_dev * rtwdev)171 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
172 {
173 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
174 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
175 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
176 rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
177 }
178
rtw_bf_del_sounding(struct rtw_dev * rtwdev)179 void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
180 {
181 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
182 }
183
rtw_bf_enable_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)184 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
185 struct rtw_bfee *bfee)
186 {
187 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
188 u8 nr_index = bfee->sound_dim;
189 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
190 u32 addr_bfer_info, addr_csi_rpt, csi_param;
191 u8 i;
192
193 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
194
195 switch (bfee->su_reg_index) {
196 case 1:
197 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
198 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
199 break;
200 case 0:
201 default:
202 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
203 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
204 break;
205 }
206
207 /* Sounding protocol control */
208 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
209 RTW_SND_CTRL_SOUNDING);
210
211 /* MAC address/Partial AID of Beamformer */
212 for (i = 0; i < ETH_ALEN; i++)
213 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
214
215 csi_param = (u16)((coefficientsize << 10) |
216 (codebookinfo << 8) |
217 (grouping << 6) |
218 (nr_index << 3) |
219 nc_index);
220 rtw_write16(rtwdev, addr_csi_rpt, csi_param);
221
222 /* ndp rx standby timer */
223 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
224 }
225 EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
226
227 /* nc index: 1 2T2R 0 1T1R
228 * nr index: 1 use Nsts 0 use reg setting
229 * codebookinfo: 1 802.11ac 3 802.11n
230 */
rtw_bf_enable_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)231 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
232 struct rtw_bfee *bfee)
233 {
234 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
235 struct mu_bfer_init_para param;
236 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
237 u8 nr_index = 1;
238 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
239 u32 csi_param;
240
241 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
242
243 csi_param = (u16)((coefficientsize << 10) |
244 (codebookinfo << 8) |
245 (grouping << 6) |
246 (nr_index << 3) |
247 nc_index);
248
249 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
250 nc_index, nr_index, grouping, codebookinfo,
251 coefficientsize);
252
253 param.paid = bfee->p_aid;
254 param.csi_para = csi_param;
255 param.my_aid = bfee->aid & 0xfff;
256 param.csi_length_sel = HAL_CSI_SEG_4K;
257 ether_addr_copy(param.bfer_address, bfee->mac_addr);
258
259 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m);
260
261 bf_info->cur_csi_rpt_rate = DESC_RATE6M;
262 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
263
264 /* accept action_no_ack */
265 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
266
267 /* accept NDPA and BF report poll */
268 rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
269 }
270 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
271
rtw_bf_remove_bfee_su(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)272 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
273 struct rtw_bfee *bfee)
274 {
275 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
276
277 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
278 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
279 RTW_SND_CTRL_REMOVE);
280
281 switch (bfee->su_reg_index) {
282 case 0:
283 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
284 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
285 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
286 break;
287 case 1:
288 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
289 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
290 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
291 break;
292 }
293
294 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
295 bfee->su_reg_index = 0xFF;
296 }
297 EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
298
rtw_bf_remove_bfee_mu(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)299 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
300 struct rtw_bfee *bfee)
301 {
302 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
303
304 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
305 RTW_SND_CTRL_REMOVE);
306
307 rtw_bf_del_bfer_entry_mu(rtwdev);
308
309 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
310 rtw_bf_del_sounding(rtwdev);
311 }
312 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
313
rtw_bf_set_gid_table(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)314 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
315 struct ieee80211_bss_conf *conf)
316 {
317 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
318 struct rtw_bfee *bfee = &rtwvif->bfee;
319 struct cfg_mumimo_para param;
320
321 if (bfee->role != RTW_BFEE_MU) {
322 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
323 return;
324 }
325
326 param.grouping_bitmap = 0;
327 param.mu_tx_en = 0;
328 memset(param.sounding_sts, 0, 6);
329 memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
330 memcpy(param.given_user_pos, conf->mu_group.position, 16);
331 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
332 param.given_gid_tab[0], param.given_user_pos[0],
333 param.given_user_pos[1]);
334
335 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
336 param.given_gid_tab[1], param.given_user_pos[2],
337 param.given_user_pos[3]);
338
339 rtw_bf_cfg_mu_bfee(rtwdev, ¶m);
340 }
341 EXPORT_SYMBOL(rtw_bf_set_gid_table);
342
rtw_bf_phy_init(struct rtw_dev * rtwdev)343 void rtw_bf_phy_init(struct rtw_dev *rtwdev)
344 {
345 u8 tmp8;
346 u32 tmp32;
347 u8 retry_limit = 0xA;
348 u8 ndpa_rate = 0x10;
349 u8 ack_policy = 3;
350
351 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
352 /* Enable P1 aggr new packet according to P0 transfer time */
353 tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
354 /* MU Retry Limit */
355 tmp32 &= ~BIT_MASK_R_MU_RL;
356 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
357 /* Disable Tx MU-MIMO until sounding done */
358 tmp32 &= ~BIT_EN_MU_MIMO;
359 /* Clear validity of MU STAs */
360 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
361 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
362
363 /* MU-MIMO Option as default value */
364 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
365 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
366 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
367
368 /* MU-MIMO Control as default value */
369 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
370 /* Set MU NDPA rate & BW source */
371 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
372 /* Set NDPA Rate */
373 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
374
375 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
376 DESC_RATE6M);
377 }
378 EXPORT_SYMBOL(rtw_bf_phy_init);
379
rtw_bf_cfg_csi_rate(struct rtw_dev * rtwdev,u8 rssi,u8 cur_rate,u8 fixrate_en,u8 * new_rate)380 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
381 u8 fixrate_en, u8 *new_rate)
382 {
383 u32 csi_cfg;
384 u16 cur_rrsr;
385
386 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
387 cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
388
389 if (rssi >= 40) {
390 if (cur_rate != DESC_RATE54M) {
391 cur_rrsr |= BIT(DESC_RATE54M);
392 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
393 BIT_SHIFT_CSI_RATE;
394 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
395 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
396 }
397 *new_rate = DESC_RATE54M;
398 } else {
399 if (cur_rate != DESC_RATE24M) {
400 cur_rrsr &= ~BIT(DESC_RATE54M);
401 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
402 BIT_SHIFT_CSI_RATE;
403 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
404 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
405 }
406 *new_rate = DESC_RATE24M;
407 }
408 }
409 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
410