1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "debug.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "ps.h"
10 #include "reg.h"
11 #include "sar.h"
12 #include "coex.h"
13
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
15 const struct rtw89_ra_report *report)
16 {
17 const struct rate_info *txrate = &report->txrate;
18 u32 bit_rate = report->bit_rate;
19 u8 mcs;
20
21 /* lower than ofdm, do not aggregate */
22 if (bit_rate < 550)
23 return 1;
24
25 /* prevent hardware rate fallback to G mode rate */
26 if (txrate->flags & RATE_INFO_FLAGS_MCS)
27 mcs = txrate->mcs & 0x07;
28 else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS))
29 mcs = txrate->mcs;
30 else
31 mcs = 0;
32
33 if (mcs <= 2)
34 return 1;
35
36 /* lower than 20M vht 2ss mcs8, make it small */
37 if (bit_rate < 1800)
38 return 1200;
39
40 /* lower than 40M vht 2ss mcs9, make it medium */
41 if (bit_rate < 4000)
42 return 2600;
43
44 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
45 if (bit_rate < 7000)
46 return 3500;
47
48 return rtwdev->chip->max_amsdu_limit;
49 }
50
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)51 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
52 {
53 u64 ra_mask = 0;
54 u8 mcs_cap;
55 int i, nss;
56
57 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
58 mcs_cap = mcs_map & 0x3;
59 switch (mcs_cap) {
60 case 2:
61 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
62 break;
63 case 1:
64 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
65 break;
66 case 0:
67 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
68 break;
69 default:
70 break;
71 }
72 }
73
74 return ra_mask;
75 }
76
get_he_ra_mask(struct ieee80211_sta * sta)77 static u64 get_he_ra_mask(struct ieee80211_sta *sta)
78 {
79 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap;
80 u16 mcs_map;
81
82 switch (sta->deflink.bandwidth) {
83 case IEEE80211_STA_RX_BW_160:
84 if (cap.he_cap_elem.phy_cap_info[0] &
85 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
86 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
87 else
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
89 break;
90 default:
91 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
92 }
93
94 /* MCS11, MCS9, MCS7 */
95 return get_mcs_ra_mask(mcs_map, 11, 2);
96 }
97
98 #define RA_FLOOR_TABLE_SIZE 7
99 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)100 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
101 u8 ratr_state)
102 {
103 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
104 u8 rssi_lv = 0;
105 u8 i;
106
107 rssi >>= 1;
108 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
109 if (i >= ratr_state)
110 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
111 if (rssi < rssi_lv_t[i]) {
112 rssi_lv = i;
113 break;
114 }
115 }
116 if (rssi_lv == 0)
117 return 0xffffffffffffffffULL;
118 else if (rssi_lv == 1)
119 return 0xfffffffffffffff0ULL;
120 else if (rssi_lv == 2)
121 return 0xffffffffffffefe0ULL;
122 else if (rssi_lv == 3)
123 return 0xffffffffffffcfc0ULL;
124 else if (rssi_lv == 4)
125 return 0xffffffffffff8f80ULL;
126 else if (rssi_lv >= 5)
127 return 0xffffffffffff0f00ULL;
128
129 return 0xffffffffffffffffULL;
130 }
131
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)132 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
133 {
134 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
135 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
136
137 if (ra_mask == 0)
138 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
139
140 return ra_mask;
141 }
142
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta)143 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
144 {
145 struct rtw89_hal *hal = &rtwdev->hal;
146 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
147 struct cfg80211_bitrate_mask *mask = &rtwsta->mask;
148 enum nl80211_band band;
149 u64 cfg_mask;
150
151 if (!rtwsta->use_cfg_mask)
152 return -1;
153
154 switch (hal->current_band_type) {
155 case RTW89_BAND_2G:
156 band = NL80211_BAND_2GHZ;
157 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
158 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
159 break;
160 case RTW89_BAND_5G:
161 band = NL80211_BAND_5GHZ;
162 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
163 RA_MASK_OFDM_RATES);
164 break;
165 case RTW89_BAND_6G:
166 band = NL80211_BAND_6GHZ;
167 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
168 RA_MASK_OFDM_RATES);
169 break;
170 default:
171 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type);
172 return -1;
173 }
174
175 if (sta->deflink.he_cap.has_he) {
176 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
177 RA_MASK_HE_1SS_RATES);
178 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
179 RA_MASK_HE_2SS_RATES);
180 } else if (sta->deflink.vht_cap.vht_supported) {
181 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
182 RA_MASK_VHT_1SS_RATES);
183 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
184 RA_MASK_VHT_2SS_RATES);
185 } else if (sta->deflink.ht_cap.ht_supported) {
186 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
187 RA_MASK_HT_1SS_RATES);
188 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
189 RA_MASK_HT_2SS_RATES);
190 }
191
192 return cfg_mask;
193 }
194
195 static const u64
196 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
197 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
198 static const u64
199 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
200 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
201 static const u64
202 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
203 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
204
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,bool csi)205 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
206 struct ieee80211_sta *sta, bool csi)
207 {
208 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
209 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
210 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
211 struct rtw89_ra_info *ra = &rtwsta->ra;
212 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
213 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
214 u64 ra_mask = 0;
215 u64 ra_mask_bak;
216 u8 mode = 0;
217 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
218 u8 bw_mode = 0;
219 u8 stbc_en = 0;
220 u8 ldpc_en = 0;
221 u8 i;
222 bool sgi = false;
223
224 memset(ra, 0, sizeof(*ra));
225 /* Set the ra mask from sta's capability */
226 if (sta->deflink.he_cap.has_he) {
227 mode |= RTW89_RA_MODE_HE;
228 csi_mode = RTW89_RA_RPT_MODE_HE;
229 ra_mask |= get_he_ra_mask(sta);
230 high_rate_masks = rtw89_ra_mask_he_rates;
231 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] &
232 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
233 stbc_en = 1;
234 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] &
235 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
236 ldpc_en = 1;
237 } else if (sta->deflink.vht_cap.vht_supported) {
238 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
239
240 mode |= RTW89_RA_MODE_VHT;
241 csi_mode = RTW89_RA_RPT_MODE_VHT;
242 /* MCS9, MCS8, MCS7 */
243 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
244 high_rate_masks = rtw89_ra_mask_vht_rates;
245 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
246 stbc_en = 1;
247 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
248 ldpc_en = 1;
249 } else if (sta->deflink.ht_cap.ht_supported) {
250 mode |= RTW89_RA_MODE_HT;
251 csi_mode = RTW89_RA_RPT_MODE_HT;
252 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) |
253 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) |
254 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) |
255 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
256 high_rate_masks = rtw89_ra_mask_ht_rates;
257 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
258 stbc_en = 1;
259 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
260 ldpc_en = 1;
261 }
262
263 switch (rtwdev->hal.current_band_type) {
264 case RTW89_BAND_2G:
265 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
266 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf)
267 mode |= RTW89_RA_MODE_CCK;
268 else
269 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM;
270 break;
271 case RTW89_BAND_5G:
272 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
273 mode |= RTW89_RA_MODE_OFDM;
274 break;
275 case RTW89_BAND_6G:
276 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4;
277 mode |= RTW89_RA_MODE_OFDM;
278 break;
279 default:
280 rtw89_err(rtwdev, "Unknown band type\n");
281 break;
282 }
283
284 ra_mask_bak = ra_mask;
285
286 if (mode >= RTW89_RA_MODE_HT) {
287 u64 mask = 0;
288 for (i = 0; i < rtwdev->hal.tx_nss; i++)
289 mask |= high_rate_masks[i];
290 if (mode & RTW89_RA_MODE_OFDM)
291 mask |= RA_MASK_SUBOFDM_RATES;
292 if (mode & RTW89_RA_MODE_CCK)
293 mask |= RA_MASK_SUBCCK_RATES;
294 ra_mask &= mask;
295 } else if (mode & RTW89_RA_MODE_OFDM) {
296 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
297 }
298
299 if (mode != RTW89_RA_MODE_CCK)
300 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
301
302 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
303 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
304
305 switch (sta->deflink.bandwidth) {
306 case IEEE80211_STA_RX_BW_160:
307 bw_mode = RTW89_CHANNEL_WIDTH_160;
308 sgi = sta->deflink.vht_cap.vht_supported &&
309 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
310 break;
311 case IEEE80211_STA_RX_BW_80:
312 bw_mode = RTW89_CHANNEL_WIDTH_80;
313 sgi = sta->deflink.vht_cap.vht_supported &&
314 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
315 break;
316 case IEEE80211_STA_RX_BW_40:
317 bw_mode = RTW89_CHANNEL_WIDTH_40;
318 sgi = sta->deflink.ht_cap.ht_supported &&
319 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
320 break;
321 default:
322 bw_mode = RTW89_CHANNEL_WIDTH_20;
323 sgi = sta->deflink.ht_cap.ht_supported &&
324 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
325 break;
326 }
327
328 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
329 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
330 ra->dcm_cap = 1;
331
332 if (rate_pattern->enable) {
333 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
334 ra_mask &= rate_pattern->ra_mask;
335 mode = rate_pattern->ra_mode;
336 }
337
338 ra->bw_cap = bw_mode;
339 ra->mode_ctrl = mode;
340 ra->macid = rtwsta->mac_id;
341 ra->stbc_cap = stbc_en;
342 ra->ldpc_cap = ldpc_en;
343 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
344 ra->en_sgi = sgi;
345 ra->ra_mask = ra_mask;
346
347 if (!csi)
348 return;
349
350 ra->fixed_csi_rate_en = false;
351 ra->ra_csi_rate_en = true;
352 ra->cr_tbl_sel = false;
353 ra->band_num = rtwvif->phy_idx;
354 ra->csi_bw = bw_mode;
355 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
356 ra->csi_mcs_ss_idx = 5;
357 ra->csi_mode = csi_mode;
358 }
359
rtw89_phy_ra_updata_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)360 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
361 u32 changed)
362 {
363 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
364 struct rtw89_ra_info *ra = &rtwsta->ra;
365
366 rtw89_phy_ra_sta_update(rtwdev, sta, false);
367
368 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
369 ra->upd_mask = 1;
370 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
371 ra->upd_bw_nss_mask = 1;
372
373 rtw89_debug(rtwdev, RTW89_DBG_RA,
374 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
375 ra->macid,
376 ra->bw_cap,
377 ra->ss_num,
378 ra->en_sgi,
379 ra->giltf);
380
381 rtw89_fw_h2c_ra(rtwdev, ra, false);
382 }
383
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)384 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
385 u16 rate_base, u64 ra_mask, u8 ra_mode,
386 u32 rate_ctrl, u32 ctrl_skip, bool force)
387 {
388 u8 n, c;
389
390 if (rate_ctrl == ctrl_skip)
391 return true;
392
393 n = hweight32(rate_ctrl);
394 if (n == 0)
395 return true;
396
397 if (force && n != 1)
398 return false;
399
400 if (next->enable)
401 return false;
402
403 c = __fls(rate_ctrl);
404 next->rate = rate_base + c;
405 next->ra_mode = ra_mode;
406 next->ra_mask = ra_mask;
407 next->enable = true;
408
409 return true;
410 }
411
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)412 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
413 struct ieee80211_vif *vif,
414 const struct cfg80211_bitrate_mask *mask)
415 {
416 struct ieee80211_supported_band *sband;
417 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
418 struct rtw89_phy_rate_pattern next_pattern = {0};
419 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0,
420 RTW89_HW_RATE_HE_NSS2_MCS0,
421 RTW89_HW_RATE_HE_NSS3_MCS0,
422 RTW89_HW_RATE_HE_NSS4_MCS0};
423 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0,
424 RTW89_HW_RATE_VHT_NSS2_MCS0,
425 RTW89_HW_RATE_VHT_NSS3_MCS0,
426 RTW89_HW_RATE_VHT_NSS4_MCS0};
427 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0,
428 RTW89_HW_RATE_MCS8,
429 RTW89_HW_RATE_MCS16,
430 RTW89_HW_RATE_MCS24};
431 u8 band = rtwdev->hal.current_band_type;
432 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
433 u8 tx_nss = rtwdev->hal.tx_nss;
434 u8 i;
435
436 for (i = 0; i < tx_nss; i++)
437 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i],
438 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
439 mask->control[nl_band].he_mcs[i],
440 0, true))
441 goto out;
442
443 for (i = 0; i < tx_nss; i++)
444 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i],
445 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
446 mask->control[nl_band].vht_mcs[i],
447 0, true))
448 goto out;
449
450 for (i = 0; i < tx_nss; i++)
451 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i],
452 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
453 mask->control[nl_band].ht_mcs[i],
454 0, true))
455 goto out;
456
457 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
458 * require at least one basic rate for ieee80211_set_bitrate_mask,
459 * so the decision just depends on if all bitrates are set or not.
460 */
461 sband = rtwdev->hw->wiphy->bands[nl_band];
462 if (band == RTW89_BAND_2G) {
463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
464 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
465 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
466 mask->control[nl_band].legacy,
467 BIT(sband->n_bitrates) - 1, false))
468 goto out;
469 } else {
470 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
471 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
472 mask->control[nl_band].legacy,
473 BIT(sband->n_bitrates) - 1, false))
474 goto out;
475 }
476
477 if (!next_pattern.enable)
478 goto out;
479
480 rtwvif->rate_pattern = next_pattern;
481 rtw89_debug(rtwdev, RTW89_DBG_RA,
482 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
483 next_pattern.rate,
484 next_pattern.ra_mask,
485 next_pattern.ra_mode);
486 return;
487
488 out:
489 rtwvif->rate_pattern.enable = false;
490 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
491 }
492
rtw89_phy_ra_updata_sta_iter(void * data,struct ieee80211_sta * sta)493 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta)
494 {
495 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
496
497 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
498 }
499
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)500 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
501 {
502 ieee80211_iterate_stations_atomic(rtwdev->hw,
503 rtw89_phy_ra_updata_sta_iter,
504 rtwdev);
505 }
506
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)507 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)
508 {
509 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
510 struct rtw89_ra_info *ra = &rtwsta->ra;
511 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR;
512 bool csi = rtw89_sta_has_beamformer_cap(sta);
513
514 rtw89_phy_ra_sta_update(rtwdev, sta, csi);
515
516 if (rssi > 40)
517 ra->init_rate_lv = 1;
518 else if (rssi > 20)
519 ra->init_rate_lv = 2;
520 else if (rssi > 1)
521 ra->init_rate_lv = 3;
522 else
523 ra->init_rate_lv = 0;
524 ra->upd_all = 1;
525 rtw89_debug(rtwdev, RTW89_DBG_RA,
526 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
527 ra->macid,
528 ra->mode_ctrl,
529 ra->bw_cap,
530 ra->ss_num,
531 ra->init_rate_lv);
532 rtw89_debug(rtwdev, RTW89_DBG_RA,
533 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
534 ra->dcm_cap,
535 ra->er_cap,
536 ra->ldpc_cap,
537 ra->stbc_cap,
538 ra->en_sgi,
539 ra->giltf);
540
541 rtw89_fw_h2c_ra(rtwdev, ra, csi);
542 }
543
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,struct rtw89_channel_params * param,enum rtw89_bandwidth dbw)544 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
545 struct rtw89_channel_params *param,
546 enum rtw89_bandwidth dbw)
547 {
548 enum rtw89_bandwidth cbw = param->bandwidth;
549 u8 pri_ch = param->primary_chan;
550 u8 central_ch = param->center_chan;
551 u8 txsc_idx = 0;
552 u8 tmp = 0;
553
554 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
555 return txsc_idx;
556
557 switch (cbw) {
558 case RTW89_CHANNEL_WIDTH_40:
559 txsc_idx = pri_ch > central_ch ? 1 : 2;
560 break;
561 case RTW89_CHANNEL_WIDTH_80:
562 if (dbw == RTW89_CHANNEL_WIDTH_20) {
563 if (pri_ch > central_ch)
564 txsc_idx = (pri_ch - central_ch) >> 1;
565 else
566 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
567 } else {
568 txsc_idx = pri_ch > central_ch ? 9 : 10;
569 }
570 break;
571 case RTW89_CHANNEL_WIDTH_160:
572 if (pri_ch > central_ch)
573 tmp = (pri_ch - central_ch) >> 1;
574 else
575 tmp = ((central_ch - pri_ch) >> 1) + 1;
576
577 if (dbw == RTW89_CHANNEL_WIDTH_20) {
578 txsc_idx = tmp;
579 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
580 if (tmp == 1 || tmp == 3)
581 txsc_idx = 9;
582 else if (tmp == 5 || tmp == 7)
583 txsc_idx = 11;
584 else if (tmp == 2 || tmp == 4)
585 txsc_idx = 10;
586 else if (tmp == 6 || tmp == 8)
587 txsc_idx = 12;
588 else
589 return 0xff;
590 } else {
591 txsc_idx = pri_ch > central_ch ? 13 : 14;
592 }
593 break;
594 case RTW89_CHANNEL_WIDTH_80_80:
595 if (dbw == RTW89_CHANNEL_WIDTH_20) {
596 if (pri_ch > central_ch)
597 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
598 else
599 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
600 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
601 txsc_idx = pri_ch > central_ch ? 10 : 12;
602 } else {
603 txsc_idx = 14;
604 }
605 break;
606 default:
607 break;
608 }
609
610 return txsc_idx;
611 }
612 EXPORT_SYMBOL(rtw89_phy_get_txsc);
613
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)614 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
615 {
616 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
617 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
618 }
619
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)620 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
621 u32 addr, u32 mask)
622 {
623 const struct rtw89_chip_info *chip = rtwdev->chip;
624 const u32 *base_addr = chip->rf_base_addr;
625 u32 val, direct_addr;
626
627 if (rf_path >= rtwdev->chip->rf_path_num) {
628 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
629 return INV_RF_DATA;
630 }
631
632 addr &= 0xff;
633 direct_addr = base_addr[rf_path] + (addr << 2);
634 mask &= RFREG_MASK;
635
636 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
637
638 return val;
639 }
640 EXPORT_SYMBOL(rtw89_phy_read_rf);
641
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)642 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
643 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
644 {
645 bool busy;
646 bool done;
647 u32 val;
648 int ret;
649
650 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
651 1, 30, false, rtwdev);
652 if (ret) {
653 rtw89_err(rtwdev, "read rf busy swsi\n");
654 return INV_RF_DATA;
655 }
656
657 mask &= RFREG_MASK;
658
659 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
660 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
661 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
662 udelay(2);
663
664 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
665 30, false, rtwdev, R_SWSI_V1,
666 B_SWSI_R_DATA_DONE_V1);
667 if (ret) {
668 rtw89_err(rtwdev, "read swsi busy\n");
669 return INV_RF_DATA;
670 }
671
672 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
673 }
674
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)675 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
676 u32 addr, u32 mask)
677 {
678 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
679
680 if (rf_path >= rtwdev->chip->rf_path_num) {
681 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
682 return INV_RF_DATA;
683 }
684
685 if (ad_sel)
686 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
687 else
688 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
689 }
690 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
691
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)692 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
693 u32 addr, u32 mask, u32 data)
694 {
695 const struct rtw89_chip_info *chip = rtwdev->chip;
696 const u32 *base_addr = chip->rf_base_addr;
697 u32 direct_addr;
698
699 if (rf_path >= rtwdev->chip->rf_path_num) {
700 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
701 return false;
702 }
703
704 addr &= 0xff;
705 direct_addr = base_addr[rf_path] + (addr << 2);
706 mask &= RFREG_MASK;
707
708 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
709
710 /* delay to ensure writing properly */
711 udelay(1);
712
713 return true;
714 }
715 EXPORT_SYMBOL(rtw89_phy_write_rf);
716
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)717 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
718 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
719 u32 data)
720 {
721 u8 bit_shift;
722 u32 val;
723 bool busy, b_msk_en = false;
724 int ret;
725
726 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
727 1, 30, false, rtwdev);
728 if (ret) {
729 rtw89_err(rtwdev, "write rf busy swsi\n");
730 return false;
731 }
732
733 data &= RFREG_MASK;
734 mask &= RFREG_MASK;
735
736 if (mask != RFREG_MASK) {
737 b_msk_en = true;
738 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
739 mask);
740 bit_shift = __ffs(mask);
741 data = (data << bit_shift) & RFREG_MASK;
742 }
743
744 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
745 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
746 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
747 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
748
749 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
750
751 return true;
752 }
753
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)754 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
755 u32 addr, u32 mask, u32 data)
756 {
757 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
758
759 if (rf_path >= rtwdev->chip->rf_path_num) {
760 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
761 return false;
762 }
763
764 if (ad_sel)
765 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
766 else
767 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
768 }
769 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
770
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)771 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
772 enum rtw89_phy_idx phy_idx)
773 {
774 const struct rtw89_chip_info *chip = rtwdev->chip;
775
776 chip->ops->bb_reset(rtwdev, phy_idx);
777 }
778
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)779 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
780 const struct rtw89_reg2_def *reg,
781 enum rtw89_rf_path rf_path,
782 void *extra_data)
783 {
784 if (reg->addr == 0xfe)
785 mdelay(50);
786 else if (reg->addr == 0xfd)
787 mdelay(5);
788 else if (reg->addr == 0xfc)
789 mdelay(1);
790 else if (reg->addr == 0xfb)
791 udelay(50);
792 else if (reg->addr == 0xfa)
793 udelay(5);
794 else if (reg->addr == 0xf9)
795 udelay(1);
796 else
797 rtw89_phy_write32(rtwdev, reg->addr, reg->data);
798 }
799
800 union rtw89_phy_bb_gain_arg {
801 u32 addr;
802 struct {
803 union {
804 u8 type;
805 struct {
806 u8 rxsc_start:4;
807 u8 bw:4;
808 };
809 };
810 u8 path;
811 u8 gain_band;
812 u8 cfg_type;
813 };
814 } __packed;
815
816 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)817 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
818 union rtw89_phy_bb_gain_arg arg, u32 data)
819 {
820 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
821 u8 type = arg.type;
822 u8 path = arg.path;
823 u8 gband = arg.gain_band;
824 int i;
825
826 switch (type) {
827 case 0:
828 for (i = 0; i < 4; i++, data >>= 8)
829 gain->lna_gain[gband][path][i] = data & 0xff;
830 break;
831 case 1:
832 for (i = 4; i < 7; i++, data >>= 8)
833 gain->lna_gain[gband][path][i] = data & 0xff;
834 break;
835 case 2:
836 for (i = 0; i < 2; i++, data >>= 8)
837 gain->tia_gain[gband][path][i] = data & 0xff;
838 break;
839 default:
840 rtw89_warn(rtwdev,
841 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
842 arg.addr, data, type);
843 break;
844 }
845 }
846
847 enum rtw89_phy_bb_rxsc_start_idx {
848 RTW89_BB_RXSC_START_IDX_FULL = 0,
849 RTW89_BB_RXSC_START_IDX_20 = 1,
850 RTW89_BB_RXSC_START_IDX_20_1 = 5,
851 RTW89_BB_RXSC_START_IDX_40 = 9,
852 RTW89_BB_RXSC_START_IDX_80 = 13,
853 };
854
855 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)856 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
857 union rtw89_phy_bb_gain_arg arg, u32 data)
858 {
859 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
860 u8 rxsc_start = arg.rxsc_start;
861 u8 bw = arg.bw;
862 u8 path = arg.path;
863 u8 gband = arg.gain_band;
864 u8 rxsc;
865 s8 ofst;
866 int i;
867
868 switch (bw) {
869 case RTW89_CHANNEL_WIDTH_20:
870 gain->rpl_ofst_20[gband][path] = (s8)data;
871 break;
872 case RTW89_CHANNEL_WIDTH_40:
873 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
874 gain->rpl_ofst_40[gband][path][0] = (s8)data;
875 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
876 for (i = 0; i < 2; i++, data >>= 8) {
877 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
878 ofst = (s8)(data & 0xff);
879 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
880 }
881 }
882 break;
883 case RTW89_CHANNEL_WIDTH_80:
884 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
885 gain->rpl_ofst_80[gband][path][0] = (s8)data;
886 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
887 for (i = 0; i < 4; i++, data >>= 8) {
888 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
889 ofst = (s8)(data & 0xff);
890 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
891 }
892 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
893 for (i = 0; i < 2; i++, data >>= 8) {
894 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
895 ofst = (s8)(data & 0xff);
896 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
897 }
898 }
899 break;
900 case RTW89_CHANNEL_WIDTH_160:
901 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
902 gain->rpl_ofst_160[gband][path][0] = (s8)data;
903 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
904 for (i = 0; i < 4; i++, data >>= 8) {
905 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
906 ofst = (s8)(data & 0xff);
907 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
908 }
909 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
910 for (i = 0; i < 4; i++, data >>= 8) {
911 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
912 ofst = (s8)(data & 0xff);
913 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
914 }
915 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
916 for (i = 0; i < 4; i++, data >>= 8) {
917 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
918 ofst = (s8)(data & 0xff);
919 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
920 }
921 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
922 for (i = 0; i < 2; i++, data >>= 8) {
923 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
924 ofst = (s8)(data & 0xff);
925 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
926 }
927 }
928 break;
929 default:
930 rtw89_warn(rtwdev,
931 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
932 arg.addr, data, bw);
933 break;
934 }
935 }
936
937 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)938 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
939 union rtw89_phy_bb_gain_arg arg, u32 data)
940 {
941 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
942 u8 type = arg.type;
943 u8 path = arg.path;
944 u8 gband = arg.gain_band;
945 int i;
946
947 switch (type) {
948 case 0:
949 for (i = 0; i < 4; i++, data >>= 8)
950 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
951 break;
952 case 1:
953 for (i = 4; i < 7; i++, data >>= 8)
954 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
955 break;
956 default:
957 rtw89_warn(rtwdev,
958 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
959 arg.addr, data, type);
960 break;
961 }
962 }
963
964 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)965 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
966 union rtw89_phy_bb_gain_arg arg, u32 data)
967 {
968 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
969 u8 type = arg.type;
970 u8 path = arg.path;
971 u8 gband = arg.gain_band;
972 int i;
973
974 switch (type) {
975 case 0:
976 for (i = 0; i < 4; i++, data >>= 8)
977 gain->lna_op1db[gband][path][i] = data & 0xff;
978 break;
979 case 1:
980 for (i = 4; i < 7; i++, data >>= 8)
981 gain->lna_op1db[gband][path][i] = data & 0xff;
982 break;
983 case 2:
984 for (i = 0; i < 4; i++, data >>= 8)
985 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
986 break;
987 case 3:
988 for (i = 4; i < 8; i++, data >>= 8)
989 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
990 break;
991 default:
992 rtw89_warn(rtwdev,
993 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
994 arg.addr, data, type);
995 break;
996 }
997 }
998
rtw89_phy_config_bb_gain(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)999 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev,
1000 const struct rtw89_reg2_def *reg,
1001 enum rtw89_rf_path rf_path,
1002 void *extra_data)
1003 {
1004 const struct rtw89_chip_info *chip = rtwdev->chip;
1005 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1006
1007 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1008 return;
1009
1010 if (arg.path >= chip->rf_path_num)
1011 return;
1012
1013 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1014 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1015 return;
1016 }
1017
1018 switch (arg.cfg_type) {
1019 case 0:
1020 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1021 break;
1022 case 1:
1023 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1024 break;
1025 case 2:
1026 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1027 break;
1028 case 3:
1029 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1030 break;
1031 default:
1032 rtw89_warn(rtwdev,
1033 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1034 arg.addr, reg->data, arg.cfg_type);
1035 break;
1036 }
1037 }
1038
1039 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1040 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1041 const struct rtw89_reg2_def *reg,
1042 enum rtw89_rf_path rf_path,
1043 struct rtw89_fw_h2c_rf_reg_info *info)
1044 {
1045 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1046 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1047
1048 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1049 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1050 rf_path, info->curr_idx);
1051 return;
1052 }
1053
1054 info->rtw89_phy_config_rf_h2c[page][idx] =
1055 cpu_to_le32((reg->addr << 20) | reg->data);
1056 info->curr_idx++;
1057 }
1058
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1059 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1060 struct rtw89_fw_h2c_rf_reg_info *info)
1061 {
1062 u16 remain = info->curr_idx;
1063 u16 len = 0;
1064 u8 i;
1065 int ret = 0;
1066
1067 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1068 rtw89_warn(rtwdev,
1069 "rf reg h2c total len %d larger than %d\n",
1070 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1071 ret = -EINVAL;
1072 goto out;
1073 }
1074
1075 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1076 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1077 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1078 if (ret)
1079 goto out;
1080 }
1081 out:
1082 info->curr_idx = 0;
1083
1084 return ret;
1085 }
1086
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1087 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1088 const struct rtw89_reg2_def *reg,
1089 enum rtw89_rf_path rf_path,
1090 void *extra_data)
1091 {
1092 if (reg->addr == 0xfe) {
1093 mdelay(50);
1094 } else if (reg->addr == 0xfd) {
1095 mdelay(5);
1096 } else if (reg->addr == 0xfc) {
1097 mdelay(1);
1098 } else if (reg->addr == 0xfb) {
1099 udelay(50);
1100 } else if (reg->addr == 0xfa) {
1101 udelay(5);
1102 } else if (reg->addr == 0xf9) {
1103 udelay(1);
1104 } else {
1105 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1106 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1107 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1108 }
1109 }
1110
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1111 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1112 const struct rtw89_reg2_def *reg,
1113 enum rtw89_rf_path rf_path,
1114 void *extra_data)
1115 {
1116 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1117
1118 if (reg->addr < 0x100)
1119 return;
1120
1121 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1122 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1123 }
1124 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1125
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1126 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1127 const struct rtw89_phy_table *table,
1128 u32 *headline_size, u32 *headline_idx,
1129 u8 rfe, u8 cv)
1130 {
1131 const struct rtw89_reg2_def *reg;
1132 u32 headline;
1133 u32 compare, target;
1134 u8 rfe_para, cv_para;
1135 u8 cv_max = 0;
1136 bool case_matched = false;
1137 u32 i;
1138
1139 for (i = 0; i < table->n_regs; i++) {
1140 reg = &table->regs[i];
1141 headline = get_phy_headline(reg->addr);
1142 if (headline != PHY_HEADLINE_VALID)
1143 break;
1144 }
1145 *headline_size = i;
1146 if (*headline_size == 0)
1147 return 0;
1148
1149 /* case 1: RFE match, CV match */
1150 compare = get_phy_compare(rfe, cv);
1151 for (i = 0; i < *headline_size; i++) {
1152 reg = &table->regs[i];
1153 target = get_phy_target(reg->addr);
1154 if (target == compare) {
1155 *headline_idx = i;
1156 return 0;
1157 }
1158 }
1159
1160 /* case 2: RFE match, CV don't care */
1161 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1162 for (i = 0; i < *headline_size; i++) {
1163 reg = &table->regs[i];
1164 target = get_phy_target(reg->addr);
1165 if (target == compare) {
1166 *headline_idx = i;
1167 return 0;
1168 }
1169 }
1170
1171 /* case 3: RFE match, CV max in table */
1172 for (i = 0; i < *headline_size; i++) {
1173 reg = &table->regs[i];
1174 rfe_para = get_phy_cond_rfe(reg->addr);
1175 cv_para = get_phy_cond_cv(reg->addr);
1176 if (rfe_para == rfe) {
1177 if (cv_para >= cv_max) {
1178 cv_max = cv_para;
1179 *headline_idx = i;
1180 case_matched = true;
1181 }
1182 }
1183 }
1184
1185 if (case_matched)
1186 return 0;
1187
1188 /* case 4: RFE don't care, CV max in table */
1189 for (i = 0; i < *headline_size; i++) {
1190 reg = &table->regs[i];
1191 rfe_para = get_phy_cond_rfe(reg->addr);
1192 cv_para = get_phy_cond_cv(reg->addr);
1193 if (rfe_para == PHY_COND_DONT_CARE) {
1194 if (cv_para >= cv_max) {
1195 cv_max = cv_para;
1196 *headline_idx = i;
1197 case_matched = true;
1198 }
1199 }
1200 }
1201
1202 if (case_matched)
1203 return 0;
1204
1205 return -EINVAL;
1206 }
1207
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1208 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1209 const struct rtw89_phy_table *table,
1210 void (*config)(struct rtw89_dev *rtwdev,
1211 const struct rtw89_reg2_def *reg,
1212 enum rtw89_rf_path rf_path,
1213 void *data),
1214 void *extra_data)
1215 {
1216 const struct rtw89_reg2_def *reg;
1217 enum rtw89_rf_path rf_path = table->rf_path;
1218 u8 rfe = rtwdev->efuse.rfe_type;
1219 u8 cv = rtwdev->hal.cv;
1220 u32 i;
1221 u32 headline_size = 0, headline_idx = 0;
1222 u32 target = 0, cfg_target;
1223 u8 cond;
1224 bool is_matched = true;
1225 bool target_found = false;
1226 int ret;
1227
1228 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1229 &headline_idx, rfe, cv);
1230 if (ret) {
1231 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1232 return;
1233 }
1234
1235 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1236 for (i = headline_size; i < table->n_regs; i++) {
1237 reg = &table->regs[i];
1238 cond = get_phy_cond(reg->addr);
1239 switch (cond) {
1240 case PHY_COND_BRANCH_IF:
1241 case PHY_COND_BRANCH_ELIF:
1242 target = get_phy_target(reg->addr);
1243 break;
1244 case PHY_COND_BRANCH_ELSE:
1245 is_matched = false;
1246 if (!target_found) {
1247 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1248 reg->addr, reg->data);
1249 return;
1250 }
1251 break;
1252 case PHY_COND_BRANCH_END:
1253 is_matched = true;
1254 target_found = false;
1255 break;
1256 case PHY_COND_CHECK:
1257 if (target_found) {
1258 is_matched = false;
1259 break;
1260 }
1261
1262 if (target == cfg_target) {
1263 is_matched = true;
1264 target_found = true;
1265 } else {
1266 is_matched = false;
1267 target_found = false;
1268 }
1269 break;
1270 default:
1271 if (is_matched)
1272 config(rtwdev, reg, rf_path, extra_data);
1273 break;
1274 }
1275 }
1276 }
1277
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1278 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1279 {
1280 const struct rtw89_chip_info *chip = rtwdev->chip;
1281 const struct rtw89_phy_table *bb_table = chip->bb_table;
1282 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table;
1283
1284 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1285 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
1286 if (bb_gain_table)
1287 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1288 rtw89_phy_config_bb_gain, NULL);
1289 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1290 }
1291
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1292 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1293 {
1294 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1295 udelay(1);
1296 return rtw89_phy_read32(rtwdev, 0x8080);
1297 }
1298
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev)1299 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)
1300 {
1301 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1302 enum rtw89_rf_path rf_path, void *data);
1303 const struct rtw89_chip_info *chip = rtwdev->chip;
1304 const struct rtw89_phy_table *rf_table;
1305 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1306 u8 path;
1307
1308 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1309 if (!rf_reg_info)
1310 return;
1311
1312 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1313 rf_table = chip->rf_table[path];
1314 rf_reg_info->rf_path = rf_table->rf_path;
1315 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg;
1316 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1317 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1318 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1319 rf_reg_info->rf_path);
1320 }
1321 kfree(rf_reg_info);
1322 }
1323
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1324 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1325 {
1326 const struct rtw89_chip_info *chip = rtwdev->chip;
1327 const struct rtw89_phy_table *nctl_table;
1328 u32 val;
1329 int ret;
1330
1331 /* IQK/DPK clock & reset */
1332 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
1333 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
1334 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
1335 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
1336
1337 /* check 0x8080 */
1338 rtw89_phy_write32(rtwdev, 0x8000, 0x8);
1339
1340 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1341 1000, false, rtwdev);
1342 if (ret)
1343 rtw89_err(rtwdev, "failed to poll nctl block\n");
1344
1345 nctl_table = chip->nctl_table;
1346 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1347 }
1348
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)1349 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
1350 {
1351 u32 phy_page = addr >> 8;
1352 u32 ofst = 0;
1353
1354 switch (phy_page) {
1355 case 0x6:
1356 case 0x7:
1357 case 0x8:
1358 case 0x9:
1359 case 0xa:
1360 case 0xb:
1361 case 0xc:
1362 case 0xd:
1363 case 0x19:
1364 case 0x1a:
1365 case 0x1b:
1366 ofst = 0x2000;
1367 break;
1368 default:
1369 /* warning case */
1370 ofst = 0;
1371 break;
1372 }
1373
1374 if (phy_page >= 0x40 && phy_page <= 0x4f)
1375 ofst = 0x2000;
1376
1377 return ofst;
1378 }
1379
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1380 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1381 u32 data, enum rtw89_phy_idx phy_idx)
1382 {
1383 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1384 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1385 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1386 }
1387 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1388
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1389 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1390 u32 val)
1391 {
1392 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1393
1394 if (!rtwdev->dbcc_en)
1395 return;
1396
1397 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1398 }
1399
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1400 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1401 const struct rtw89_phy_reg3_tbl *tbl)
1402 {
1403 const struct rtw89_reg3_def *reg3;
1404 int i;
1405
1406 for (i = 0; i < tbl->size; i++) {
1407 reg3 = &tbl->reg3[i];
1408 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1409 }
1410 }
1411 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1412
1413 const u8 rtw89_rs_idx_max[] = {
1414 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
1415 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
1416 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
1417 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
1418 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
1419 };
1420 EXPORT_SYMBOL(rtw89_rs_idx_max);
1421
1422 const u8 rtw89_rs_nss_max[] = {
1423 [RTW89_RS_CCK] = 1,
1424 [RTW89_RS_OFDM] = 1,
1425 [RTW89_RS_MCS] = RTW89_NSS_MAX,
1426 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
1427 [RTW89_RS_OFFSET] = 1,
1428 };
1429 EXPORT_SYMBOL(rtw89_rs_nss_max);
1430
1431 static const u8 _byr_of_rs[] = {
1432 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
1433 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm),
1434 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs),
1435 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm),
1436 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset),
1437 };
1438
1439 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs])
1440 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx))
1441 #define _byr_chk(rs, nss, idx) \
1442 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs])
1443
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)1444 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1445 const struct rtw89_txpwr_table *tbl)
1446 {
1447 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
1448 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
1449 s8 *byr;
1450 u32 data;
1451 u8 i, idx;
1452
1453 for (; cfg < end; cfg++) {
1454 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]);
1455 data = cfg->data;
1456
1457 for (i = 0; i < cfg->len; i++, data >>= 8) {
1458 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i));
1459 byr[idx] = (s8)(data & 0xff);
1460 }
1461 }
1462 }
1463 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
1464
1465 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \
1466 ({ \
1467 const struct rtw89_chip_info *__c = (rtwdev)->chip; \
1468 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
1469 })
1470
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_rate_desc * rate_desc)1471 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
1472 const struct rtw89_rate_desc *rate_desc)
1473 {
1474 enum rtw89_band band = rtwdev->hal.current_band_type;
1475 s8 *byr;
1476 u8 idx;
1477
1478 if (rate_desc->rs == RTW89_RS_CCK)
1479 band = RTW89_BAND_2G;
1480
1481 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) {
1482 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1483 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n",
1484 rate_desc->rs, rate_desc->nss, rate_desc->idx);
1485
1486 return 0;
1487 }
1488
1489 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]);
1490 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx);
1491
1492 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
1493 }
1494 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
1495
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)1496 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
1497 {
1498 switch (channel_6g) {
1499 case 1 ... 29:
1500 return (channel_6g - 1) / 2;
1501 case 33 ... 61:
1502 return (channel_6g - 3) / 2;
1503 case 65 ... 93:
1504 return (channel_6g - 5) / 2;
1505 case 97 ... 125:
1506 return (channel_6g - 7) / 2;
1507 case 129 ... 157:
1508 return (channel_6g - 9) / 2;
1509 case 161 ... 189:
1510 return (channel_6g - 11) / 2;
1511 case 193 ... 221:
1512 return (channel_6g - 13) / 2;
1513 case 225 ... 253:
1514 return (channel_6g - 15) / 2;
1515 default:
1516 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
1517 return 0;
1518 }
1519 }
1520
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)1521 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
1522 {
1523 if (band == RTW89_BAND_6G)
1524 return rtw89_channel_6g_to_idx(rtwdev, channel);
1525
1526 switch (channel) {
1527 case 1 ... 14:
1528 return channel - 1;
1529 case 36 ... 64:
1530 return (channel - 36) / 2;
1531 case 100 ... 144:
1532 return ((channel - 100) / 2) + 15;
1533 case 149 ... 177:
1534 return ((channel - 149) / 2) + 38;
1535 default:
1536 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
1537 return 0;
1538 }
1539 }
1540
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)1541 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
1542 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
1543 {
1544 const struct rtw89_chip_info *chip = rtwdev->chip;
1545 u8 band = rtwdev->hal.current_band_type;
1546 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
1547 u8 regd = rtw89_regd_get(rtwdev, band);
1548 s8 lmt = 0, sar;
1549
1550 switch (band) {
1551 case RTW89_BAND_2G:
1552 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx];
1553 if (!lmt)
1554 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf]
1555 [RTW89_WW][ch_idx];
1556 break;
1557 case RTW89_BAND_5G:
1558 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx];
1559 if (!lmt)
1560 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf]
1561 [RTW89_WW][ch_idx];
1562 break;
1563 case RTW89_BAND_6G:
1564 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx];
1565 if (!lmt)
1566 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf]
1567 [RTW89_WW][ch_idx];
1568 break;
1569 default:
1570 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1571 return 0;
1572 }
1573
1574 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt);
1575 sar = rtw89_query_sar(rtwdev);
1576
1577 return min(lmt, sar);
1578 }
1579 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
1580
1581 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \
1582 do { \
1583 u8 __i; \
1584 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
1585 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
1586 bw, ntx, \
1587 rs, __i, \
1588 (ch)); \
1589 } while (0)
1590
rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 ntx,u8 ch)1591 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev,
1592 struct rtw89_txpwr_limit *lmt,
1593 u8 ntx, u8 ch)
1594 {
1595 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20,
1596 ntx, RTW89_RS_CCK, ch);
1597 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40,
1598 ntx, RTW89_RS_CCK, ch);
1599 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1600 ntx, RTW89_RS_OFDM, ch);
1601 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1602 ntx, RTW89_RS_MCS, ch);
1603 }
1604
rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 ntx,u8 ch,u8 pri_ch)1605 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev,
1606 struct rtw89_txpwr_limit *lmt,
1607 u8 ntx, u8 ch, u8 pri_ch)
1608 {
1609 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20,
1610 ntx, RTW89_RS_CCK, ch - 2);
1611 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40,
1612 ntx, RTW89_RS_CCK, ch);
1613 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1614 ntx, RTW89_RS_OFDM, pri_ch);
1615 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1616 ntx, RTW89_RS_MCS, ch - 2);
1617 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20,
1618 ntx, RTW89_RS_MCS, ch + 2);
1619 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40,
1620 ntx, RTW89_RS_MCS, ch);
1621 }
1622
rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 ntx,u8 ch,u8 pri_ch)1623 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev,
1624 struct rtw89_txpwr_limit *lmt,
1625 u8 ntx, u8 ch, u8 pri_ch)
1626 {
1627 s8 val_0p5_n[RTW89_BF_NUM];
1628 s8 val_0p5_p[RTW89_BF_NUM];
1629 u8 i;
1630
1631 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1632 ntx, RTW89_RS_OFDM, pri_ch);
1633 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1634 ntx, RTW89_RS_MCS, ch - 6);
1635 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20,
1636 ntx, RTW89_RS_MCS, ch - 2);
1637 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20,
1638 ntx, RTW89_RS_MCS, ch + 2);
1639 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20,
1640 ntx, RTW89_RS_MCS, ch + 6);
1641 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40,
1642 ntx, RTW89_RS_MCS, ch - 4);
1643 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40,
1644 ntx, RTW89_RS_MCS, ch + 4);
1645 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80,
1646 ntx, RTW89_RS_MCS, ch);
1647
1648 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40,
1649 ntx, RTW89_RS_MCS, ch - 4);
1650 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40,
1651 ntx, RTW89_RS_MCS, ch + 4);
1652
1653 for (i = 0; i < RTW89_BF_NUM; i++)
1654 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
1655 }
1656
rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 ntx,u8 ch,u8 pri_ch)1657 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev,
1658 struct rtw89_txpwr_limit *lmt,
1659 u8 ntx, u8 ch, u8 pri_ch)
1660 {
1661 s8 val_0p5_n[RTW89_BF_NUM];
1662 s8 val_0p5_p[RTW89_BF_NUM];
1663 s8 val_2p5_n[RTW89_BF_NUM];
1664 s8 val_2p5_p[RTW89_BF_NUM];
1665 u8 i;
1666
1667 /* fill ofdm section */
1668 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1669 ntx, RTW89_RS_OFDM, pri_ch);
1670
1671 /* fill mcs 20m section */
1672 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1673 ntx, RTW89_RS_MCS, ch - 14);
1674 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20,
1675 ntx, RTW89_RS_MCS, ch - 10);
1676 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20,
1677 ntx, RTW89_RS_MCS, ch - 6);
1678 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20,
1679 ntx, RTW89_RS_MCS, ch - 2);
1680 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], RTW89_CHANNEL_WIDTH_20,
1681 ntx, RTW89_RS_MCS, ch + 2);
1682 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], RTW89_CHANNEL_WIDTH_20,
1683 ntx, RTW89_RS_MCS, ch + 6);
1684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], RTW89_CHANNEL_WIDTH_20,
1685 ntx, RTW89_RS_MCS, ch + 10);
1686 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], RTW89_CHANNEL_WIDTH_20,
1687 ntx, RTW89_RS_MCS, ch + 14);
1688
1689 /* fill mcs 40m section */
1690 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40,
1691 ntx, RTW89_RS_MCS, ch - 12);
1692 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40,
1693 ntx, RTW89_RS_MCS, ch - 4);
1694 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], RTW89_CHANNEL_WIDTH_40,
1695 ntx, RTW89_RS_MCS, ch + 4);
1696 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], RTW89_CHANNEL_WIDTH_40,
1697 ntx, RTW89_RS_MCS, ch + 12);
1698
1699 /* fill mcs 80m section */
1700 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80,
1701 ntx, RTW89_RS_MCS, ch - 8);
1702 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], RTW89_CHANNEL_WIDTH_80,
1703 ntx, RTW89_RS_MCS, ch + 8);
1704
1705 /* fill mcs 160m section */
1706 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, RTW89_CHANNEL_WIDTH_160,
1707 ntx, RTW89_RS_MCS, ch);
1708
1709 /* fill mcs 40m 0p5 section */
1710 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40,
1711 ntx, RTW89_RS_MCS, ch - 4);
1712 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40,
1713 ntx, RTW89_RS_MCS, ch + 4);
1714
1715 for (i = 0; i < RTW89_BF_NUM; i++)
1716 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
1717
1718 /* fill mcs 40m 2p5 section */
1719 __fill_txpwr_limit_nonbf_bf(val_2p5_n, RTW89_CHANNEL_WIDTH_40,
1720 ntx, RTW89_RS_MCS, ch - 8);
1721 __fill_txpwr_limit_nonbf_bf(val_2p5_p, RTW89_CHANNEL_WIDTH_40,
1722 ntx, RTW89_RS_MCS, ch + 8);
1723
1724 for (i = 0; i < RTW89_BF_NUM; i++)
1725 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
1726 }
1727
rtw89_phy_fill_txpwr_limit(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 ntx)1728 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
1729 struct rtw89_txpwr_limit *lmt,
1730 u8 ntx)
1731 {
1732 u8 pri_ch = rtwdev->hal.current_primary_channel;
1733 u8 ch = rtwdev->hal.current_channel;
1734 u8 bw = rtwdev->hal.current_band_width;
1735
1736 memset(lmt, 0, sizeof(*lmt));
1737
1738 switch (bw) {
1739 case RTW89_CHANNEL_WIDTH_20:
1740 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch);
1741 break;
1742 case RTW89_CHANNEL_WIDTH_40:
1743 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch, pri_ch);
1744 break;
1745 case RTW89_CHANNEL_WIDTH_80:
1746 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch, pri_ch);
1747 break;
1748 case RTW89_CHANNEL_WIDTH_160:
1749 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, ntx, ch, pri_ch);
1750 break;
1751 }
1752 }
1753 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
1754
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 ru,u8 ntx,u8 ch)1755 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1756 u8 ru, u8 ntx, u8 ch)
1757 {
1758 const struct rtw89_chip_info *chip = rtwdev->chip;
1759 u8 band = rtwdev->hal.current_band_type;
1760 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
1761 u8 regd = rtw89_regd_get(rtwdev, band);
1762 s8 lmt_ru = 0, sar;
1763
1764 switch (band) {
1765 case RTW89_BAND_2G:
1766 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx];
1767 if (!lmt_ru)
1768 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx]
1769 [RTW89_WW][ch_idx];
1770 break;
1771 case RTW89_BAND_5G:
1772 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx];
1773 if (!lmt_ru)
1774 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx]
1775 [RTW89_WW][ch_idx];
1776 break;
1777 case RTW89_BAND_6G:
1778 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx];
1779 if (!lmt_ru)
1780 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx]
1781 [RTW89_WW][ch_idx];
1782 break;
1783 default:
1784 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1785 return 0;
1786 }
1787
1788 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
1789 sar = rtw89_query_sar(rtwdev);
1790
1791 return min(lmt_ru, sar);
1792 }
1793
1794 static void
rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx,u8 ch)1795 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev,
1796 struct rtw89_txpwr_limit_ru *lmt_ru,
1797 u8 ntx, u8 ch)
1798 {
1799 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1800 ntx, ch);
1801 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1802 ntx, ch);
1803 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1804 ntx, ch);
1805 }
1806
1807 static void
rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx,u8 ch)1808 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev,
1809 struct rtw89_txpwr_limit_ru *lmt_ru,
1810 u8 ntx, u8 ch)
1811 {
1812 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1813 ntx, ch - 2);
1814 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1815 ntx, ch + 2);
1816 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1817 ntx, ch - 2);
1818 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1819 ntx, ch + 2);
1820 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1821 ntx, ch - 2);
1822 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1823 ntx, ch + 2);
1824 }
1825
1826 static void
rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx,u8 ch)1827 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev,
1828 struct rtw89_txpwr_limit_ru *lmt_ru,
1829 u8 ntx, u8 ch)
1830 {
1831 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1832 ntx, ch - 6);
1833 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1834 ntx, ch - 2);
1835 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1836 ntx, ch + 2);
1837 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1838 ntx, ch + 6);
1839 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1840 ntx, ch - 6);
1841 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1842 ntx, ch - 2);
1843 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1844 ntx, ch + 2);
1845 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1846 ntx, ch + 6);
1847 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1848 ntx, ch - 6);
1849 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1850 ntx, ch - 2);
1851 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1852 ntx, ch + 2);
1853 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1854 ntx, ch + 6);
1855 }
1856
1857 static void
rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx,u8 ch)1858 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev,
1859 struct rtw89_txpwr_limit_ru *lmt_ru,
1860 u8 ntx, u8 ch)
1861 {
1862 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
1863 int i;
1864
1865 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM);
1866 for (i = 0; i < RTW89_RU_SEC_NUM; i++) {
1867 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev,
1868 RTW89_RU26,
1869 ntx,
1870 ch + ofst[i]);
1871 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev,
1872 RTW89_RU52,
1873 ntx,
1874 ch + ofst[i]);
1875 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev,
1876 RTW89_RU106,
1877 ntx,
1878 ch + ofst[i]);
1879 }
1880 }
1881
rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx)1882 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1883 struct rtw89_txpwr_limit_ru *lmt_ru,
1884 u8 ntx)
1885 {
1886 u8 ch = rtwdev->hal.current_channel;
1887 u8 bw = rtwdev->hal.current_band_width;
1888
1889 memset(lmt_ru, 0, sizeof(*lmt_ru));
1890
1891 switch (bw) {
1892 case RTW89_CHANNEL_WIDTH_20:
1893 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch);
1894 break;
1895 case RTW89_CHANNEL_WIDTH_40:
1896 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch);
1897 break;
1898 case RTW89_CHANNEL_WIDTH_80:
1899 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch);
1900 break;
1901 case RTW89_CHANNEL_WIDTH_160:
1902 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, ntx, ch);
1903 break;
1904 }
1905 }
1906 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
1907
1908 struct rtw89_phy_iter_ra_data {
1909 struct rtw89_dev *rtwdev;
1910 struct sk_buff *c2h;
1911 };
1912
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)1913 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
1914 {
1915 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
1916 struct rtw89_dev *rtwdev = ra_data->rtwdev;
1917 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1918 struct rtw89_ra_report *ra_report = &rtwsta->ra_report;
1919 struct sk_buff *c2h = ra_data->c2h;
1920 u8 mode, rate, bw, giltf, mac_id;
1921
1922 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data);
1923 if (mac_id != rtwsta->mac_id)
1924 return;
1925
1926 memset(ra_report, 0, sizeof(*ra_report));
1927
1928 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data);
1929 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data);
1930 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data);
1931 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data);
1932
1933 switch (mode) {
1934 case RTW89_RA_RPT_MODE_LEGACY:
1935 ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate);
1936 break;
1937 case RTW89_RA_RPT_MODE_HT:
1938 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
1939 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
1940 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
1941 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
1942 else
1943 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
1944 ra_report->txrate.mcs = rate;
1945 if (giltf)
1946 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1947 break;
1948 case RTW89_RA_RPT_MODE_VHT:
1949 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
1950 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
1951 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
1952 if (giltf)
1953 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1954 break;
1955 case RTW89_RA_RPT_MODE_HE:
1956 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
1957 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
1958 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
1959 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
1960 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
1961 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
1962 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
1963 else
1964 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
1965 break;
1966 }
1967
1968 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
1969 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
1970 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) |
1971 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate);
1972 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
1973 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1;
1974 }
1975
1976 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)1977 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
1978 {
1979 struct rtw89_phy_iter_ra_data ra_data;
1980
1981 ra_data.rtwdev = rtwdev;
1982 ra_data.c2h = c2h;
1983 ieee80211_iterate_stations_atomic(rtwdev->hw,
1984 rtw89_phy_c2h_ra_rpt_iter,
1985 &ra_data);
1986 }
1987
1988 static
1989 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
1990 struct sk_buff *c2h, u32 len) = {
1991 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
1992 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
1993 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
1994 };
1995
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)1996 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1997 u32 len, u8 class, u8 func)
1998 {
1999 void (*handler)(struct rtw89_dev *rtwdev,
2000 struct sk_buff *c2h, u32 len) = NULL;
2001
2002 switch (class) {
2003 case RTW89_PHY_C2H_CLASS_RA:
2004 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
2005 handler = rtw89_phy_c2h_ra_handler[func];
2006 break;
2007 default:
2008 rtw89_info(rtwdev, "c2h class %d not support\n", class);
2009 return;
2010 }
2011 if (!handler) {
2012 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
2013 func);
2014 return;
2015 }
2016 handler(rtwdev, skb, len);
2017 }
2018
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)2019 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
2020 {
2021 u32 reg_mask;
2022
2023 if (sc_xo)
2024 reg_mask = B_AX_XTAL_SC_XO_MASK;
2025 else
2026 reg_mask = B_AX_XTAL_SC_XI_MASK;
2027
2028 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask);
2029 }
2030
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)2031 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
2032 u8 val)
2033 {
2034 u32 reg_mask;
2035
2036 if (sc_xo)
2037 reg_mask = B_AX_XTAL_SC_XO_MASK;
2038 else
2039 reg_mask = B_AX_XTAL_SC_XI_MASK;
2040
2041 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val);
2042 }
2043
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)2044 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
2045 u8 crystal_cap, bool force)
2046 {
2047 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2048 const struct rtw89_chip_info *chip = rtwdev->chip;
2049 u8 sc_xi_val, sc_xo_val;
2050
2051 if (!force && cfo->crystal_cap == crystal_cap)
2052 return;
2053 crystal_cap = clamp_t(u8, crystal_cap, 0, 127);
2054 if (chip->chip_id == RTL8852A) {
2055 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
2056 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
2057 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
2058 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
2059 } else {
2060 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
2061 crystal_cap, XTAL_SC_XO_MASK);
2062 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
2063 crystal_cap, XTAL_SC_XI_MASK);
2064 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
2065 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
2066 }
2067 cfo->crystal_cap = sc_xi_val;
2068 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
2069
2070 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
2071 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
2072 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
2073 cfo->x_cap_ofst);
2074 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
2075 }
2076
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)2077 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
2078 {
2079 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2080 u8 cap;
2081
2082 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
2083 cfo->is_adjust = false;
2084 if (cfo->crystal_cap == cfo->def_x_cap)
2085 return;
2086 cap = cfo->crystal_cap;
2087 cap += (cap > cfo->def_x_cap ? -1 : 1);
2088 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
2089 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2090 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
2091 cfo->def_x_cap);
2092 }
2093
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)2094 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
2095 {
2096 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
2097 bool is_linked = rtwdev->total_sta_assoc > 0;
2098 s32 cfo_avg_312;
2099 s32 dcfo_comp_val;
2100 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
2101 int sign;
2102
2103 if (!is_linked) {
2104 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
2105 is_linked);
2106 return;
2107 }
2108 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
2109 if (curr_cfo == 0)
2110 return;
2111 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
2112 sign = curr_cfo > 0 ? 1 : -1;
2113 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val;
2114 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312);
2115 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
2116 cfo_avg_312 = -cfo_avg_312;
2117 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
2118 cfo_avg_312);
2119 }
2120
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)2121 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
2122 {
2123 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1);
2124 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8);
2125 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK);
2126 }
2127
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)2128 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
2129 {
2130 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2131 struct rtw89_efuse *efuse = &rtwdev->efuse;
2132
2133 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
2134 cfo->crystal_cap = cfo->crystal_cap_default;
2135 cfo->def_x_cap = cfo->crystal_cap;
2136 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
2137 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
2138 cfo->is_adjust = false;
2139 cfo->divergence_lock_en = false;
2140 cfo->x_cap_ofst = 0;
2141 cfo->lock_cnt = 0;
2142 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
2143 cfo->apply_compensation = false;
2144 cfo->residual_cfo_acc = 0;
2145 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
2146 cfo->crystal_cap_default);
2147 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
2148 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
2149 rtw89_dcfo_comp_init(rtwdev);
2150 cfo->cfo_timer_ms = 2000;
2151 cfo->cfo_trig_by_timer_en = false;
2152 cfo->phy_cfo_trk_cnt = 0;
2153 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2154 }
2155
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)2156 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
2157 s32 curr_cfo)
2158 {
2159 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2160 s8 crystal_cap = cfo->crystal_cap;
2161 s32 cfo_abs = abs(curr_cfo);
2162 int sign;
2163
2164 if (!cfo->is_adjust) {
2165 if (cfo_abs > CFO_TRK_ENABLE_TH)
2166 cfo->is_adjust = true;
2167 } else {
2168 if (cfo_abs < CFO_TRK_STOP_TH)
2169 cfo->is_adjust = false;
2170 }
2171 if (!cfo->is_adjust) {
2172 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
2173 return;
2174 }
2175 sign = curr_cfo > 0 ? 1 : -1;
2176 if (cfo_abs > CFO_TRK_STOP_TH_4)
2177 crystal_cap += 7 * sign;
2178 else if (cfo_abs > CFO_TRK_STOP_TH_3)
2179 crystal_cap += 5 * sign;
2180 else if (cfo_abs > CFO_TRK_STOP_TH_2)
2181 crystal_cap += 3 * sign;
2182 else if (cfo_abs > CFO_TRK_STOP_TH_1)
2183 crystal_cap += 1 * sign;
2184 else
2185 return;
2186 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
2187 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2188 "X_cap{Curr,Default}={0x%x,0x%x}\n",
2189 cfo->crystal_cap, cfo->def_x_cap);
2190 }
2191
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)2192 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
2193 {
2194 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2195 s32 cfo_khz_all = 0;
2196 s32 cfo_cnt_all = 0;
2197 s32 cfo_all_avg = 0;
2198 u8 i;
2199
2200 if (rtwdev->total_sta_assoc != 1)
2201 return 0;
2202 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
2203 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2204 if (cfo->cfo_cnt[i] == 0)
2205 continue;
2206 cfo_khz_all += cfo->cfo_tail[i];
2207 cfo_cnt_all += cfo->cfo_cnt[i];
2208 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
2209 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
2210 }
2211 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2212 "CFO track for macid = %d\n", i);
2213 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2214 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
2215 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
2216 return cfo_all_avg;
2217 }
2218
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)2219 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
2220 {
2221 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2222 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2223 s32 target_cfo = 0;
2224 s32 cfo_khz_all = 0;
2225 s32 cfo_khz_all_tp_wgt = 0;
2226 s32 cfo_avg = 0;
2227 s32 max_cfo_lb = BIT(31);
2228 s32 min_cfo_ub = GENMASK(30, 0);
2229 u16 cfo_cnt_all = 0;
2230 u8 active_entry_cnt = 0;
2231 u8 sta_cnt = 0;
2232 u32 tp_all = 0;
2233 u8 i;
2234 u8 cfo_tol = 0;
2235
2236 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
2237 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
2238 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
2239 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2240 if (cfo->cfo_cnt[i] == 0)
2241 continue;
2242 cfo_khz_all += cfo->cfo_tail[i];
2243 cfo_cnt_all += cfo->cfo_cnt[i];
2244 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
2245 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2246 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
2247 cfo_khz_all, cfo_cnt_all, cfo_avg);
2248 target_cfo = cfo_avg;
2249 }
2250 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
2251 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
2252 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2253 if (cfo->cfo_cnt[i] == 0)
2254 continue;
2255 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
2256 (s32)cfo->cfo_cnt[i]);
2257 cfo_khz_all += cfo->cfo_avg[i];
2258 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2259 "Macid=%d, cfo_avg=%d\n", i,
2260 cfo->cfo_avg[i]);
2261 }
2262 sta_cnt = rtwdev->total_sta_assoc;
2263 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
2264 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2265 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
2266 cfo_khz_all, sta_cnt, cfo_avg);
2267 target_cfo = cfo_avg;
2268 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
2269 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
2270 cfo_tol = cfo->sta_cfo_tolerance;
2271 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2272 sta_cnt++;
2273 if (cfo->cfo_cnt[i] != 0) {
2274 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
2275 (s32)cfo->cfo_cnt[i]);
2276 active_entry_cnt++;
2277 } else {
2278 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
2279 }
2280 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
2281 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
2282 cfo_khz_all += cfo->cfo_avg[i];
2283 /* need tp for each entry */
2284 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2285 "[%d] cfo_avg=%d, tp=tbd\n",
2286 i, cfo->cfo_avg[i]);
2287 if (sta_cnt >= rtwdev->total_sta_assoc)
2288 break;
2289 }
2290 tp_all = stats->rx_throughput; /* need tp for each entry */
2291 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
2292
2293 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
2294 sta_cnt);
2295 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
2296 active_entry_cnt);
2297 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2298 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
2299 cfo_khz_all_tp_wgt, cfo_avg);
2300 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
2301 max_cfo_lb, min_cfo_ub);
2302 if (max_cfo_lb <= min_cfo_ub) {
2303 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2304 "cfo win_size=%d\n",
2305 min_cfo_ub - max_cfo_lb);
2306 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
2307 } else {
2308 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2309 "No intersection of cfo tolerance windows\n");
2310 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
2311 }
2312 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
2313 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
2314 }
2315 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
2316 return target_cfo;
2317 }
2318
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)2319 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
2320 {
2321 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2322
2323 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
2324 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
2325 cfo->packet_count = 0;
2326 cfo->packet_count_pre = 0;
2327 cfo->cfo_avg_pre = 0;
2328 }
2329
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)2330 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
2331 {
2332 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2333 s32 new_cfo = 0;
2334 bool x_cap_update = false;
2335 u8 pre_x_cap = cfo->crystal_cap;
2336
2337 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
2338 rtwdev->total_sta_assoc);
2339 if (rtwdev->total_sta_assoc == 0) {
2340 rtw89_phy_cfo_reset(rtwdev);
2341 return;
2342 }
2343 if (cfo->packet_count == 0) {
2344 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
2345 return;
2346 }
2347 if (cfo->packet_count == cfo->packet_count_pre) {
2348 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
2349 return;
2350 }
2351 if (rtwdev->total_sta_assoc == 1)
2352 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
2353 else
2354 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
2355 if (new_cfo == 0) {
2356 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
2357 return;
2358 }
2359 if (cfo->divergence_lock_en) {
2360 cfo->lock_cnt++;
2361 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
2362 cfo->divergence_lock_en = false;
2363 cfo->lock_cnt = 0;
2364 } else {
2365 rtw89_phy_cfo_reset(rtwdev);
2366 }
2367 return;
2368 }
2369 if (cfo->crystal_cap >= cfo->x_cap_ub ||
2370 cfo->crystal_cap <= cfo->x_cap_lb) {
2371 cfo->divergence_lock_en = true;
2372 rtw89_phy_cfo_reset(rtwdev);
2373 return;
2374 }
2375
2376 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
2377 cfo->cfo_avg_pre = new_cfo;
2378 x_cap_update = cfo->crystal_cap != pre_x_cap;
2379 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
2380 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
2381 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
2382 cfo->x_cap_ofst);
2383 if (x_cap_update) {
2384 if (new_cfo > 0)
2385 new_cfo -= CFO_SW_COMP_FINE_TUNE;
2386 else
2387 new_cfo += CFO_SW_COMP_FINE_TUNE;
2388 }
2389 rtw89_dcfo_comp(rtwdev, new_cfo);
2390 rtw89_phy_cfo_statistics_reset(rtwdev);
2391 }
2392
rtw89_phy_cfo_track_work(struct work_struct * work)2393 void rtw89_phy_cfo_track_work(struct work_struct *work)
2394 {
2395 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2396 cfo_track_work.work);
2397 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2398
2399 mutex_lock(&rtwdev->mutex);
2400 if (!cfo->cfo_trig_by_timer_en)
2401 goto out;
2402 rtw89_leave_ps_mode(rtwdev);
2403 rtw89_phy_cfo_dm(rtwdev);
2404 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
2405 msecs_to_jiffies(cfo->cfo_timer_ms));
2406 out:
2407 mutex_unlock(&rtwdev->mutex);
2408 }
2409
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)2410 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
2411 {
2412 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2413
2414 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
2415 msecs_to_jiffies(cfo->cfo_timer_ms));
2416 }
2417
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)2418 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
2419 {
2420 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2421 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2422
2423 switch (cfo->phy_cfo_status) {
2424 case RTW89_PHY_DCFO_STATE_NORMAL:
2425 if (stats->tx_throughput >= CFO_TP_UPPER) {
2426 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
2427 cfo->cfo_trig_by_timer_en = true;
2428 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
2429 rtw89_phy_cfo_start_work(rtwdev);
2430 }
2431 break;
2432 case RTW89_PHY_DCFO_STATE_ENHANCE:
2433 if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) {
2434 cfo->phy_cfo_trk_cnt = 0;
2435 cfo->cfo_trig_by_timer_en = false;
2436 }
2437 if (cfo->cfo_trig_by_timer_en == 1)
2438 cfo->phy_cfo_trk_cnt++;
2439 if (stats->tx_throughput <= CFO_TP_LOWER) {
2440 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2441 cfo->phy_cfo_trk_cnt = 0;
2442 cfo->cfo_trig_by_timer_en = false;
2443 }
2444 break;
2445 default:
2446 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2447 cfo->phy_cfo_trk_cnt = 0;
2448 break;
2449 }
2450 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2451 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
2452 stats->tx_throughput, cfo->phy_cfo_status,
2453 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
2454 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
2455 if (cfo->cfo_trig_by_timer_en)
2456 return;
2457 rtw89_phy_cfo_dm(rtwdev);
2458 }
2459
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)2460 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
2461 struct rtw89_rx_phy_ppdu *phy_ppdu)
2462 {
2463 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2464 u8 macid = phy_ppdu->mac_id;
2465
2466 if (macid >= CFO_TRACK_MAX_USER) {
2467 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
2468 return;
2469 }
2470
2471 cfo->cfo_tail[macid] += cfo_val;
2472 cfo->cfo_cnt[macid]++;
2473 cfo->packet_count++;
2474 }
2475
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)2476 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
2477 {
2478 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2479 int i;
2480 u8 th;
2481
2482 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
2483 th = rtw89_chip_get_thermal(rtwdev, i);
2484 if (th)
2485 ewma_thermal_add(&phystat->avg_thermal[i], th);
2486
2487 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2488 "path(%d) thermal cur=%u avg=%ld", i, th,
2489 ewma_thermal_read(&phystat->avg_thermal[i]));
2490 }
2491 }
2492
2493 struct rtw89_phy_iter_rssi_data {
2494 struct rtw89_dev *rtwdev;
2495 struct rtw89_phy_ch_info *ch_info;
2496 bool rssi_changed;
2497 };
2498
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)2499 static void rtw89_phy_stat_rssi_update_iter(void *data,
2500 struct ieee80211_sta *sta)
2501 {
2502 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2503 struct rtw89_phy_iter_rssi_data *rssi_data =
2504 (struct rtw89_phy_iter_rssi_data *)data;
2505 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
2506 unsigned long rssi_curr;
2507
2508 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi);
2509
2510 if (rssi_curr < ch_info->rssi_min) {
2511 ch_info->rssi_min = rssi_curr;
2512 ch_info->rssi_min_macid = rtwsta->mac_id;
2513 }
2514
2515 if (rtwsta->prev_rssi == 0) {
2516 rtwsta->prev_rssi = rssi_curr;
2517 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) {
2518 rtwsta->prev_rssi = rssi_curr;
2519 rssi_data->rssi_changed = true;
2520 }
2521 }
2522
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)2523 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
2524 {
2525 struct rtw89_phy_iter_rssi_data rssi_data = {0};
2526
2527 rssi_data.rtwdev = rtwdev;
2528 rssi_data.ch_info = &rtwdev->ch_info;
2529 rssi_data.ch_info->rssi_min = U8_MAX;
2530 ieee80211_iterate_stations_atomic(rtwdev->hw,
2531 rtw89_phy_stat_rssi_update_iter,
2532 &rssi_data);
2533 if (rssi_data.rssi_changed)
2534 rtw89_btc_ntfy_wl_sta(rtwdev);
2535 }
2536
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)2537 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
2538 {
2539 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2540 int i;
2541
2542 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2543 ewma_thermal_init(&phystat->avg_thermal[i]);
2544
2545 rtw89_phy_stat_thermal_update(rtwdev);
2546
2547 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
2548 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
2549 }
2550
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)2551 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
2552 {
2553 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2554
2555 rtw89_phy_stat_thermal_update(rtwdev);
2556 rtw89_phy_stat_rssi_update(rtwdev);
2557
2558 phystat->last_pkt_stat = phystat->cur_pkt_stat;
2559 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
2560 }
2561
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,u32 time_us)2562 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
2563 {
2564 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2565
2566 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
2567 }
2568
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,u16 idx)2569 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
2570 {
2571 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2572
2573 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
2574 }
2575
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev)2576 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
2577 {
2578 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2579
2580 env->ccx_manual_ctrl = false;
2581 env->ccx_ongoing = false;
2582 env->ccx_rac_lv = RTW89_RAC_RELEASE;
2583 env->ccx_rpt_stamp = 0;
2584 env->ccx_period = 0;
2585 env->ccx_unit_idx = RTW89_CCX_32_US;
2586 env->ccx_trigger_time = 0;
2587 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0;
2588
2589 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1);
2590 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1);
2591 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2592 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK,
2593 RTW89_CCX_EDCCA_BW20_0);
2594 }
2595
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,u16 report,u16 score)2596 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
2597 u16 score)
2598 {
2599 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2600 u32 numer = 0;
2601 u16 ret = 0;
2602
2603 numer = report * score + (env->ccx_period >> 1);
2604 if (env->ccx_period)
2605 ret = numer / env->ccx_period;
2606
2607 return ret >= score ? score - 1 : ret;
2608 }
2609
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)2610 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
2611 u16 time_ms, u32 *period,
2612 u32 *unit_idx)
2613 {
2614 u32 idx;
2615 u8 quotient;
2616
2617 if (time_ms >= CCX_MAX_PERIOD)
2618 time_ms = CCX_MAX_PERIOD;
2619
2620 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
2621
2622 if (quotient < 4)
2623 idx = RTW89_CCX_4_US;
2624 else if (quotient < 8)
2625 idx = RTW89_CCX_8_US;
2626 else if (quotient < 16)
2627 idx = RTW89_CCX_16_US;
2628 else
2629 idx = RTW89_CCX_32_US;
2630
2631 *unit_idx = idx;
2632 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
2633
2634 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2635 "[Trigger Time] period:%d, unit_idx:%d\n",
2636 *period, *unit_idx);
2637 }
2638
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev)2639 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
2640 {
2641 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2642
2643 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2644 "lv:(%d)->(0)\n", env->ccx_rac_lv);
2645
2646 env->ccx_ongoing = false;
2647 env->ccx_rac_lv = RTW89_RAC_RELEASE;
2648 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2649 }
2650
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)2651 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
2652 struct rtw89_ccx_para_info *para)
2653 {
2654 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2655 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
2656 u8 i = 0;
2657 u16 *ifs_th_l = env->ifs_clm_th_l;
2658 u16 *ifs_th_h = env->ifs_clm_th_h;
2659 u32 ifs_th0_us = 0, ifs_th_times = 0;
2660 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
2661
2662 if (!is_update)
2663 goto ifs_update_finished;
2664
2665 switch (para->ifs_clm_app) {
2666 case RTW89_IFS_CLM_INIT:
2667 case RTW89_IFS_CLM_BACKGROUND:
2668 case RTW89_IFS_CLM_ACS:
2669 case RTW89_IFS_CLM_DBG:
2670 case RTW89_IFS_CLM_DIG:
2671 case RTW89_IFS_CLM_TDMA_DIG:
2672 ifs_th0_us = IFS_CLM_TH0_UPPER;
2673 ifs_th_times = IFS_CLM_TH_MUL;
2674 break;
2675 case RTW89_IFS_CLM_DBG_MANUAL:
2676 ifs_th0_us = para->ifs_clm_manual_th0;
2677 ifs_th_times = para->ifs_clm_manual_th_times;
2678 break;
2679 default:
2680 break;
2681 }
2682
2683 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
2684 * low[i] = high[i-1] + 1
2685 * high[i] = high[i-1] * ifs_th_times
2686 */
2687 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
2688 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
2689 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
2690 ifs_th0_us);
2691 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
2692 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
2693 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
2694 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
2695 }
2696
2697 ifs_update_finished:
2698 if (!is_update)
2699 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2700 "No need to update IFS_TH\n");
2701
2702 return is_update;
2703 }
2704
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev)2705 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
2706 {
2707 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2708 u8 i = 0;
2709
2710 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK,
2711 env->ifs_clm_th_l[0]);
2712 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK,
2713 env->ifs_clm_th_l[1]);
2714 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK,
2715 env->ifs_clm_th_l[2]);
2716 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK,
2717 env->ifs_clm_th_l[3]);
2718
2719 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK,
2720 env->ifs_clm_th_h[0]);
2721 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK,
2722 env->ifs_clm_th_h[1]);
2723 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK,
2724 env->ifs_clm_th_h[2]);
2725 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK,
2726 env->ifs_clm_th_h[3]);
2727
2728 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2729 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2730 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
2731 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
2732 }
2733
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev)2734 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
2735 {
2736 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2737 struct rtw89_ccx_para_info para = {0};
2738
2739 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2740 env->ifs_clm_mntr_time = 0;
2741
2742 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
2743 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
2744 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
2745
2746 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN,
2747 true);
2748 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true);
2749 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true);
2750 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true);
2751 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true);
2752 }
2753
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,enum rtw89_env_racing_lv level)2754 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
2755 enum rtw89_env_racing_lv level)
2756 {
2757 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2758 int ret = 0;
2759
2760 if (level >= RTW89_RAC_MAX_NUM) {
2761 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2762 "[WARNING] Wrong LV=%d\n", level);
2763 return -EINVAL;
2764 }
2765
2766 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2767 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
2768 env->ccx_rac_lv, level);
2769
2770 if (env->ccx_ongoing) {
2771 if (level <= env->ccx_rac_lv)
2772 ret = -EINVAL;
2773 else
2774 env->ccx_ongoing = false;
2775 }
2776
2777 if (ret == 0)
2778 env->ccx_rac_lv = level;
2779
2780 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
2781 !ret);
2782
2783 return ret;
2784 }
2785
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev)2786 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
2787 {
2788 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2789
2790 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0);
2791 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0);
2792 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1);
2793 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2794
2795 env->ccx_rpt_stamp++;
2796 env->ccx_ongoing = true;
2797 }
2798
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev)2799 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
2800 {
2801 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2802 u8 i = 0;
2803 u32 res = 0;
2804
2805 env->ifs_clm_tx_ratio =
2806 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
2807 env->ifs_clm_edcca_excl_cca_ratio =
2808 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
2809 PERCENT);
2810 env->ifs_clm_cck_fa_ratio =
2811 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
2812 env->ifs_clm_ofdm_fa_ratio =
2813 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
2814 env->ifs_clm_cck_cca_excl_fa_ratio =
2815 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
2816 PERCENT);
2817 env->ifs_clm_ofdm_cca_excl_fa_ratio =
2818 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
2819 PERCENT);
2820 env->ifs_clm_cck_fa_permil =
2821 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
2822 env->ifs_clm_ofdm_fa_permil =
2823 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
2824
2825 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
2826 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
2827 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
2828 } else {
2829 env->ifs_clm_ifs_avg[i] =
2830 rtw89_phy_ccx_idx_to_us(rtwdev,
2831 env->ifs_clm_avg[i]);
2832 }
2833
2834 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
2835 res += env->ifs_clm_his[i] >> 1;
2836 if (env->ifs_clm_his[i])
2837 res /= env->ifs_clm_his[i];
2838 else
2839 res = 0;
2840 env->ifs_clm_cca_avg[i] = res;
2841 }
2842
2843 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2844 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
2845 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
2846 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2847 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
2848 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
2849 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2850 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
2851 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
2852 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2853 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
2854 env->ifs_clm_cck_cca_excl_fa_ratio,
2855 env->ifs_clm_ofdm_cca_excl_fa_ratio);
2856 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2857 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
2858 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2859 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
2860 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
2861 env->ifs_clm_cca_avg[i]);
2862 }
2863
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev)2864 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
2865 {
2866 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2867 u8 i = 0;
2868
2869 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) {
2870 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2871 "Get IFS_CLM report Fail\n");
2872 return false;
2873 }
2874
2875 env->ifs_clm_tx =
2876 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2877 B_IFS_CLM_TX_CNT_MSK);
2878 env->ifs_clm_edcca_excl_cca =
2879 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2880 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK);
2881 env->ifs_clm_cckcca_excl_fa =
2882 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2883 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK);
2884 env->ifs_clm_ofdmcca_excl_fa =
2885 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2886 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK);
2887 env->ifs_clm_cckfa =
2888 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2889 B_IFS_CLM_CCK_FA_MSK);
2890 env->ifs_clm_ofdmfa =
2891 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2892 B_IFS_CLM_OFDM_FA_MSK);
2893
2894 env->ifs_clm_his[0] =
2895 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK);
2896 env->ifs_clm_his[1] =
2897 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK);
2898 env->ifs_clm_his[2] =
2899 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK);
2900 env->ifs_clm_his[3] =
2901 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK);
2902
2903 env->ifs_clm_avg[0] =
2904 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK);
2905 env->ifs_clm_avg[1] =
2906 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK);
2907 env->ifs_clm_avg[2] =
2908 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK);
2909 env->ifs_clm_avg[3] =
2910 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK);
2911
2912 env->ifs_clm_cca[0] =
2913 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK);
2914 env->ifs_clm_cca[1] =
2915 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK);
2916 env->ifs_clm_cca[2] =
2917 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK);
2918 env->ifs_clm_cca[3] =
2919 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK);
2920
2921 env->ifs_clm_total_ifs =
2922 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK);
2923
2924 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
2925 env->ifs_clm_total_ifs);
2926 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2927 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
2928 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
2929 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2930 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
2931 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
2932 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2933 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
2934 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
2935
2936 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
2937 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2938 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2939 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
2940 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
2941
2942 rtw89_phy_ifs_clm_get_utility(rtwdev);
2943
2944 return true;
2945 }
2946
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)2947 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
2948 struct rtw89_ccx_para_info *para)
2949 {
2950 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2951 u32 period = 0;
2952 u32 unit_idx = 0;
2953
2954 if (para->mntr_time == 0) {
2955 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2956 "[WARN] MNTR_TIME is 0\n");
2957 return -EINVAL;
2958 }
2959
2960 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
2961 return -EINVAL;
2962
2963 if (para->mntr_time != env->ifs_clm_mntr_time) {
2964 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
2965 &period, &unit_idx);
2966 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
2967 B_IFS_CLM_PERIOD_MSK, period);
2968 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
2969 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx);
2970
2971 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2972 "Update IFS-CLM time ((%d)) -> ((%d))\n",
2973 env->ifs_clm_mntr_time, para->mntr_time);
2974
2975 env->ifs_clm_mntr_time = para->mntr_time;
2976 env->ccx_period = (u16)period;
2977 env->ccx_unit_idx = (u8)unit_idx;
2978 }
2979
2980 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
2981 env->ifs_clm_app = para->ifs_clm_app;
2982 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
2983 }
2984
2985 return 0;
2986 }
2987
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)2988 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
2989 {
2990 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2991 struct rtw89_ccx_para_info para = {0};
2992 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
2993
2994 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
2995 if (env->ccx_manual_ctrl) {
2996 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2997 "CCX in manual ctrl\n");
2998 return;
2999 }
3000
3001 /* only ifs_clm for now */
3002 if (rtw89_phy_ifs_clm_get_result(rtwdev))
3003 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
3004
3005 rtw89_phy_ccx_racing_release(rtwdev);
3006 para.mntr_time = 1900;
3007 para.rac_lv = RTW89_RAC_LV_1;
3008 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
3009
3010 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0)
3011 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
3012 if (chk_result)
3013 rtw89_phy_ccx_trigger(rtwdev);
3014
3015 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3016 "get_result=0x%x, chk_result:0x%x\n",
3017 env->ccx_watchdog_result, chk_result);
3018 }
3019
rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap * ie_page)3020 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
3021 {
3022 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM ||
3023 *ie_page == RTW89_RSVD_9)
3024 return false;
3025 else if (*ie_page > RTW89_RSVD_9)
3026 *ie_page -= 1;
3027
3028 return true;
3029 }
3030
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)3031 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
3032 {
3033 static const u8 ie_page_shift = 2;
3034
3035 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
3036 }
3037
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page)3038 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
3039 enum rtw89_phy_status_bitmap ie_page)
3040 {
3041 u32 addr;
3042
3043 if (!rtw89_physts_ie_page_valid(&ie_page))
3044 return 0;
3045
3046 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3047
3048 return rtw89_phy_read32(rtwdev, addr);
3049 }
3050
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val)3051 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
3052 enum rtw89_phy_status_bitmap ie_page,
3053 u32 val)
3054 {
3055 const struct rtw89_chip_info *chip = rtwdev->chip;
3056 u32 addr;
3057
3058 if (!rtw89_physts_ie_page_valid(&ie_page))
3059 return;
3060
3061 if (chip->chip_id == RTL8852A)
3062 val &= B_PHY_STS_BITMAP_MSK_52A;
3063
3064 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3065 rtw89_phy_write32(rtwdev, addr, val);
3066 }
3067
rtw89_physts_enable_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap bitmap,enum rtw89_phy_status_ie_type ie,bool enable)3068 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
3069 enum rtw89_phy_status_bitmap bitmap,
3070 enum rtw89_phy_status_ie_type ie,
3071 bool enable)
3072 {
3073 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap);
3074
3075 if (enable)
3076 val |= BIT(ie);
3077 else
3078 val &= ~BIT(ie);
3079
3080 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val);
3081 }
3082
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)3083 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
3084 bool enable,
3085 enum rtw89_phy_idx phy_idx)
3086 {
3087 if (enable) {
3088 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
3089 B_STS_DIS_TRIG_BY_FAIL);
3090 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
3091 B_STS_DIS_TRIG_BY_BRK);
3092 } else {
3093 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
3094 B_STS_DIS_TRIG_BY_FAIL);
3095 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
3096 B_STS_DIS_TRIG_BY_BRK);
3097 }
3098 }
3099
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)3100 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
3101 {
3102 const struct rtw89_chip_info *chip = rtwdev->chip;
3103 u8 i;
3104
3105 if (chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
3106 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0);
3107
3108 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
3109 if (i >= RTW89_CCK_PKT)
3110 rtw89_physts_enable_ie_bitmap(rtwdev, i,
3111 RTW89_PHYSTS_IE09_FTR_0,
3112 true);
3113 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
3114 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
3115 continue;
3116 rtw89_physts_enable_ie_bitmap(rtwdev, i,
3117 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
3118 true);
3119 }
3120 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
3121 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
3122 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
3123 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
3124
3125 /* force IE01 for channel index, only channel field is valid */
3126 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
3127 RTW89_PHYSTS_IE01_CMN_OFDM, true);
3128 }
3129
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,int type)3130 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
3131 {
3132 const struct rtw89_chip_info *chip = rtwdev->chip;
3133 struct rtw89_dig_info *dig = &rtwdev->dig;
3134 const struct rtw89_phy_dig_gain_cfg *cfg;
3135 const char *msg;
3136 u8 i;
3137 s8 gain_base;
3138 s8 *gain_arr;
3139 u32 tmp;
3140
3141 switch (type) {
3142 case RTW89_DIG_GAIN_LNA_G:
3143 gain_arr = dig->lna_gain_g;
3144 gain_base = LNA0_GAIN;
3145 cfg = chip->dig_table->cfg_lna_g;
3146 msg = "lna_gain_g";
3147 break;
3148 case RTW89_DIG_GAIN_TIA_G:
3149 gain_arr = dig->tia_gain_g;
3150 gain_base = TIA0_GAIN_G;
3151 cfg = chip->dig_table->cfg_tia_g;
3152 msg = "tia_gain_g";
3153 break;
3154 case RTW89_DIG_GAIN_LNA_A:
3155 gain_arr = dig->lna_gain_a;
3156 gain_base = LNA0_GAIN;
3157 cfg = chip->dig_table->cfg_lna_a;
3158 msg = "lna_gain_a";
3159 break;
3160 case RTW89_DIG_GAIN_TIA_A:
3161 gain_arr = dig->tia_gain_a;
3162 gain_base = TIA0_GAIN_A;
3163 cfg = chip->dig_table->cfg_tia_a;
3164 msg = "tia_gain_a";
3165 break;
3166 default:
3167 return;
3168 }
3169
3170 for (i = 0; i < cfg->size; i++) {
3171 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
3172 cfg->table[i].mask);
3173 tmp >>= DIG_GAIN_SHIFT;
3174 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
3175 gain_base += DIG_GAIN;
3176
3177 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
3178 msg, i, gain_arr[i]);
3179 }
3180 }
3181
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev)3182 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
3183 {
3184 struct rtw89_dig_info *dig = &rtwdev->dig;
3185 u32 tmp;
3186 u8 i;
3187
3188 if (!rtwdev->hal.support_igi)
3189 return;
3190
3191 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
3192 B_PATH0_IB_PKPW_MSK);
3193 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
3194 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
3195 B_PATH0_IB_PBK_MSK);
3196 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
3197 dig->ib_pkpwr, dig->ib_pbk);
3198
3199 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
3200 rtw89_phy_dig_read_gain_table(rtwdev, i);
3201 }
3202
3203 static const u8 rssi_nolink = 22;
3204 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
3205 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
3206 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
3207 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
3208
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev)3209 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
3210 {
3211 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
3212 struct rtw89_dig_info *dig = &rtwdev->dig;
3213 bool is_linked = rtwdev->total_sta_assoc > 0;
3214
3215 if (is_linked) {
3216 dig->igi_rssi = ch_info->rssi_min >> 1;
3217 } else {
3218 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
3219 dig->igi_rssi = rssi_nolink;
3220 }
3221 }
3222
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev)3223 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
3224 {
3225 struct rtw89_dig_info *dig = &rtwdev->dig;
3226 bool is_linked = rtwdev->total_sta_assoc > 0;
3227 const u16 *fa_th_src = NULL;
3228
3229 switch (rtwdev->hal.current_band_type) {
3230 case RTW89_BAND_2G:
3231 dig->lna_gain = dig->lna_gain_g;
3232 dig->tia_gain = dig->tia_gain_g;
3233 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
3234 dig->force_gaincode_idx_en = false;
3235 dig->dyn_pd_th_en = true;
3236 break;
3237 case RTW89_BAND_5G:
3238 default:
3239 dig->lna_gain = dig->lna_gain_a;
3240 dig->tia_gain = dig->tia_gain_a;
3241 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
3242 dig->force_gaincode_idx_en = true;
3243 dig->dyn_pd_th_en = true;
3244 break;
3245 }
3246 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
3247 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
3248 }
3249
3250 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20;
3251 static const u8 igi_max_performance_mode = 0x5a;
3252 static const u8 dynamic_pd_threshold_max;
3253
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev)3254 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
3255 {
3256 struct rtw89_dig_info *dig = &rtwdev->dig;
3257
3258 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
3259 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
3260 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
3261 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
3262 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
3263 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
3264
3265 dig->dyn_igi_max = igi_max_performance_mode;
3266 dig->dyn_igi_min = dynamic_igi_min;
3267 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
3268 dig->pd_low_th_ofst = pd_low_th_offset;
3269 dig->is_linked_pre = false;
3270 }
3271
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)3272 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
3273 {
3274 rtw89_phy_dig_update_gain_para(rtwdev);
3275 rtw89_phy_dig_reset(rtwdev);
3276 }
3277
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)3278 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
3279 {
3280 struct rtw89_dig_info *dig = &rtwdev->dig;
3281 u8 lna_idx;
3282
3283 if (rssi < dig->igi_rssi_th[0])
3284 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
3285 else if (rssi < dig->igi_rssi_th[1])
3286 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
3287 else if (rssi < dig->igi_rssi_th[2])
3288 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
3289 else if (rssi < dig->igi_rssi_th[3])
3290 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
3291 else if (rssi < dig->igi_rssi_th[4])
3292 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
3293 else
3294 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
3295
3296 return lna_idx;
3297 }
3298
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)3299 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
3300 {
3301 struct rtw89_dig_info *dig = &rtwdev->dig;
3302 u8 tia_idx;
3303
3304 if (rssi < dig->igi_rssi_th[0])
3305 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
3306 else
3307 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
3308
3309 return tia_idx;
3310 }
3311
3312 #define IB_PBK_BASE 110
3313 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)3314 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
3315 struct rtw89_agc_gaincode_set *set)
3316 {
3317 struct rtw89_dig_info *dig = &rtwdev->dig;
3318 s8 lna_gain = dig->lna_gain[set->lna_idx];
3319 s8 tia_gain = dig->tia_gain[set->tia_idx];
3320 s32 wb_rssi = rssi + lna_gain + tia_gain;
3321 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
3322 u8 rxb_idx;
3323
3324 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
3325 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
3326
3327 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
3328 wb_rssi, rxb_idx_tmp);
3329
3330 return rxb_idx;
3331 }
3332
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)3333 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
3334 struct rtw89_agc_gaincode_set *set)
3335 {
3336 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
3337 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
3338 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
3339
3340 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3341 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
3342 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
3343 }
3344
3345 #define IGI_OFFSET_MAX 25
3346 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev)3347 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
3348 {
3349 struct rtw89_dig_info *dig = &rtwdev->dig;
3350 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
3351 enum rtw89_dig_noisy_level noisy_lv;
3352 u8 igi_offset = dig->fa_rssi_ofst;
3353 u16 fa_ratio = 0;
3354
3355 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
3356
3357 if (fa_ratio < dig->fa_th[0])
3358 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
3359 else if (fa_ratio < dig->fa_th[1])
3360 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
3361 else if (fa_ratio < dig->fa_th[2])
3362 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
3363 else if (fa_ratio < dig->fa_th[3])
3364 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
3365 else
3366 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
3367
3368 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
3369 igi_offset = 0;
3370 else
3371 igi_offset += noisy_lv * IGI_OFFSET_MUL;
3372
3373 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
3374 dig->fa_rssi_ofst = igi_offset;
3375
3376 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3377 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
3378 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
3379
3380 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3381 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
3382 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
3383 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
3384 noisy_lv, igi_offset);
3385 }
3386
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,u8 lna_idx)3387 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
3388 {
3389 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT,
3390 B_PATH0_LNA_INIT_IDX_MSK, lna_idx);
3391 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT,
3392 B_PATH1_LNA_INIT_IDX_MSK, lna_idx);
3393 }
3394
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,u8 tia_idx)3395 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
3396 {
3397 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT,
3398 B_PATH0_TIA_INIT_IDX_MSK, tia_idx);
3399 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT,
3400 B_PATH1_TIA_INIT_IDX_MSK, tia_idx);
3401 }
3402
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,u8 rxb_idx)3403 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
3404 {
3405 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT,
3406 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx);
3407 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT,
3408 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx);
3409 }
3410
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,const struct rtw89_agc_gaincode_set set)3411 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
3412 const struct rtw89_agc_gaincode_set set)
3413 {
3414 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
3415 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
3416 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
3417
3418 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
3419 set.lna_idx, set.tia_idx, set.rxb_idx);
3420 }
3421
3422 static const struct rtw89_reg_def sdagc_config[4] = {
3423 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
3424 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
3425 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
3426 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
3427 };
3428
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,bool enable)3429 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
3430 bool enable)
3431 {
3432 u8 i = 0;
3433
3434 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++)
3435 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr,
3436 sdagc_config[i].mask, enable);
3437
3438 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
3439 }
3440
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev)3441 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev)
3442 {
3443 struct rtw89_dig_info *dig = &rtwdev->dig;
3444
3445 if (!rtwdev->hal.support_igi)
3446 return;
3447
3448 if (dig->force_gaincode_idx_en) {
3449 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
3450 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3451 "Force gaincode index enabled.\n");
3452 } else {
3453 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
3454 &dig->cur_gaincode);
3455 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
3456 }
3457 }
3458
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,u8 rssi,bool enable)3459 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
3460 bool enable)
3461 {
3462 enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width;
3463 struct rtw89_dig_info *dig = &rtwdev->dig;
3464 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
3465 u8 ofdm_cca_th;
3466 s8 cck_cca_th;
3467 u32 pd_val = 0;
3468
3469 under_region += PD_TH_SB_FLTR_CMP_VAL;
3470
3471 switch (cbw) {
3472 case RTW89_CHANNEL_WIDTH_40:
3473 under_region += PD_TH_BW40_CMP_VAL;
3474 break;
3475 case RTW89_CHANNEL_WIDTH_80:
3476 under_region += PD_TH_BW80_CMP_VAL;
3477 break;
3478 case RTW89_CHANNEL_WIDTH_160:
3479 under_region += PD_TH_BW160_CMP_VAL;
3480 break;
3481 case RTW89_CHANNEL_WIDTH_20:
3482 fallthrough;
3483 default:
3484 under_region += PD_TH_BW20_CMP_VAL;
3485 break;
3486 }
3487
3488 dig->dyn_pd_th_max = dig->igi_rssi;
3489
3490 final_rssi = min_t(u8, rssi, dig->igi_rssi);
3491 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
3492 PD_TH_MAX_RSSI + under_region);
3493
3494 if (enable) {
3495 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
3496 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3497 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
3498 final_rssi, ofdm_cca_th, under_region, pd_val);
3499 } else {
3500 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3501 "Dynamic PD th disabled, Set PD_low_bd=0\n");
3502 }
3503
3504 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK,
3505 pd_val);
3506 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD,
3507 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable);
3508
3509 if (!rtwdev->hal.support_cckpd)
3510 return;
3511
3512 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
3513 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
3514
3515 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3516 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
3517 final_rssi, cck_cca_th, under_region, pd_val);
3518
3519 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1,
3520 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable);
3521 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1,
3522 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val);
3523 }
3524
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev)3525 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
3526 {
3527 struct rtw89_dig_info *dig = &rtwdev->dig;
3528
3529 dig->bypass_dig = false;
3530 rtw89_phy_dig_para_reset(rtwdev);
3531 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
3532 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
3533 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
3534 rtw89_phy_dig_update_para(rtwdev);
3535 }
3536
3537 #define IGI_RSSI_MIN 10
rtw89_phy_dig(struct rtw89_dev * rtwdev)3538 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
3539 {
3540 struct rtw89_dig_info *dig = &rtwdev->dig;
3541 bool is_linked = rtwdev->total_sta_assoc > 0;
3542
3543 if (unlikely(dig->bypass_dig)) {
3544 dig->bypass_dig = false;
3545 return;
3546 }
3547
3548 if (!dig->is_linked_pre && is_linked) {
3549 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
3550 rtw89_phy_dig_update_para(rtwdev);
3551 } else if (dig->is_linked_pre && !is_linked) {
3552 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
3553 rtw89_phy_dig_update_para(rtwdev);
3554 }
3555 dig->is_linked_pre = is_linked;
3556
3557 rtw89_phy_dig_igi_offset_by_env(rtwdev);
3558 rtw89_phy_dig_update_rssi_info(rtwdev);
3559
3560 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ?
3561 dig->igi_rssi - IGI_RSSI_MIN : 0;
3562 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX;
3563 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst;
3564
3565 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
3566 dig->dyn_igi_max);
3567
3568 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3569 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n",
3570 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
3571 dig->igi_fa_rssi);
3572
3573 rtw89_phy_dig_config_igi(rtwdev);
3574
3575 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
3576
3577 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
3578 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
3579 else
3580 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
3581 }
3582
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)3583 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
3584 {
3585 rtw89_phy_ccx_top_setting_init(rtwdev);
3586 rtw89_phy_ifs_clm_setting_init(rtwdev);
3587 }
3588
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)3589 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
3590 {
3591 const struct rtw89_chip_info *chip = rtwdev->chip;
3592
3593 rtw89_phy_stat_init(rtwdev);
3594
3595 rtw89_chip_bb_sethw(rtwdev);
3596
3597 rtw89_phy_env_monitor_init(rtwdev);
3598 rtw89_physts_parsing_init(rtwdev);
3599 rtw89_phy_dig_init(rtwdev);
3600 rtw89_phy_cfo_init(rtwdev);
3601
3602 rtw89_phy_init_rf_nctl(rtwdev);
3603 rtw89_chip_rfk_init(rtwdev);
3604 rtw89_load_txpwr_table(rtwdev, chip->byr_table);
3605 rtw89_chip_set_txpwr_ctrl(rtwdev);
3606 rtw89_chip_power_trim(rtwdev);
3607 rtw89_chip_cfg_txrx_path(rtwdev);
3608 }
3609
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3610 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
3611 {
3612 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
3613 u8 bss_color;
3614
3615 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc)
3616 return;
3617
3618 bss_color = vif->bss_conf.he_bss_color.color;
3619
3620 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1,
3621 phy_idx);
3622 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color,
3623 phy_idx);
3624 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID,
3625 vif->bss_conf.aid, phy_idx);
3626 }
3627
3628 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3629 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3630 {
3631 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
3632 }
3633
3634 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3635 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3636 {
3637 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
3638 }
3639
3640 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3641 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3642 {
3643 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
3644 }
3645
3646 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3647 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3648 {
3649 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
3650 }
3651
3652 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3653 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3654 {
3655 udelay(def->data);
3656 }
3657
3658 static void
3659 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
3660 [RTW89_RFK_F_WRF] = _rfk_write_rf,
3661 [RTW89_RFK_F_WM] = _rfk_write32_mask,
3662 [RTW89_RFK_F_WS] = _rfk_write32_set,
3663 [RTW89_RFK_F_WC] = _rfk_write32_clr,
3664 [RTW89_RFK_F_DELAY] = _rfk_delay,
3665 };
3666
3667 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
3668
3669 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)3670 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
3671 {
3672 const struct rtw89_reg5_def *p = tbl->defs;
3673 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
3674
3675 for (; p < end; p++)
3676 _rfk_handler[p->flag](rtwdev, p);
3677 }
3678 EXPORT_SYMBOL(rtw89_rfk_parser);
3679
3680 #define RTW89_TSSI_FAST_MODE_NUM 4
3681
3682 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
3683 {0xD934, 0xff0000},
3684 {0xD934, 0xff000000},
3685 {0xD938, 0xff},
3686 {0xD934, 0xff00},
3687 };
3688
3689 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
3690 {0xD930, 0xff0000},
3691 {0xD930, 0xff000000},
3692 {0xD934, 0xff},
3693 {0xD930, 0xff00},
3694 };
3695
3696 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)3697 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
3698 enum rtw89_mac_idx mac_idx,
3699 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
3700 u32 val)
3701 {
3702 const struct rtw89_reg_def *regs;
3703 u32 reg;
3704 int i;
3705
3706 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
3707 regs = rtw89_tssi_fastmode_regs_flat;
3708 else
3709 regs = rtw89_tssi_fastmode_regs_level;
3710
3711 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
3712 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx);
3713 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
3714 }
3715 }
3716
3717 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
3718 {0xD91C, 0xff000000},
3719 {0xD920, 0xff},
3720 {0xD920, 0xff00},
3721 {0xD920, 0xff0000},
3722 {0xD920, 0xff000000},
3723 {0xD924, 0xff},
3724 {0xD924, 0xff00},
3725 {0xD914, 0xff000000},
3726 {0xD918, 0xff},
3727 {0xD918, 0xff00},
3728 {0xD918, 0xff0000},
3729 {0xD918, 0xff000000},
3730 {0xD91C, 0xff},
3731 {0xD91C, 0xff00},
3732 {0xD91C, 0xff0000},
3733 };
3734
3735 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
3736 {0xD910, 0xff},
3737 {0xD910, 0xff00},
3738 {0xD910, 0xff0000},
3739 {0xD910, 0xff000000},
3740 {0xD914, 0xff},
3741 {0xD914, 0xff00},
3742 {0xD914, 0xff0000},
3743 {0xD908, 0xff},
3744 {0xD908, 0xff00},
3745 {0xD908, 0xff0000},
3746 {0xD908, 0xff000000},
3747 {0xD90C, 0xff},
3748 {0xD90C, 0xff00},
3749 {0xD90C, 0xff0000},
3750 {0xD90C, 0xff000000},
3751 };
3752
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)3753 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
3754 enum rtw89_mac_idx mac_idx,
3755 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
3756 {
3757 const struct rtw89_chip_info *chip = rtwdev->chip;
3758 const struct rtw89_reg_def *regs;
3759 const u32 *data;
3760 u32 reg;
3761 int i;
3762
3763 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
3764 return;
3765
3766 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
3767 regs = rtw89_tssi_bandedge_regs_flat;
3768 else
3769 regs = rtw89_tssi_bandedge_regs_level;
3770
3771 data = chip->tssi_dbw_table->data[bandedge_cfg];
3772
3773 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
3774 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx);
3775 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
3776 }
3777
3778 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx);
3779 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
3780
3781 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
3782 data[RTW89_TSSI_SBW20]);
3783 }
3784 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
3785