1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "cam.h"
6 #include "chan.h"
7 #include "debug.h"
8 #include "fw.h"
9 #include "mac.h"
10 #include "ps.h"
11 #include "reg.h"
12 #include "util.h"
13
14 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = {
15 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR,
16 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR,
17 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR,
18 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR,
19 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR,
20 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR,
21 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR,
22 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR,
23 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR,
24 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR,
25 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR,
26 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR,
27 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR,
28 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR,
29 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR,
30 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR,
31 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
32 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
33 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR,
34 };
35
rtw89_mac_mem_write(struct rtw89_dev * rtwdev,u32 offset,u32 val,enum rtw89_mac_mem_sel sel)36 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
37 u32 val, enum rtw89_mac_mem_sel sel)
38 {
39 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
40
41 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
42 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val);
43 }
44
rtw89_mac_mem_read(struct rtw89_dev * rtwdev,u32 offset,enum rtw89_mac_mem_sel sel)45 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
46 enum rtw89_mac_mem_sel sel)
47 {
48 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
49
50 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
51 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY);
52 }
53
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)54 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
55 enum rtw89_mac_hwmod_sel sel)
56 {
57 u32 val, r_val;
58
59 if (sel == RTW89_DMAC_SEL) {
60 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
61 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
62 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) {
63 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
64 val = B_AX_CMAC_EN;
65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) {
66 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
67 val = B_AX_CMAC1_FEN;
68 } else {
69 return -EINVAL;
70 }
71 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD ||
72 (val & r_val) != val)
73 return -EFAULT;
74
75 return 0;
76 }
77
rtw89_mac_write_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 val)78 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
79 {
80 u8 lte_ctrl;
81 int ret;
82
83 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
84 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
85 if (ret)
86 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
87
88 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
89 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
90
91 return ret;
92 }
93
rtw89_mac_read_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 * val)94 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
95 {
96 u8 lte_ctrl;
97 int ret;
98
99 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
100 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
101 if (ret)
102 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
103
104 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
105 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
106
107 return ret;
108 }
109
110 static
dle_dfi_ctrl(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_ctrl * ctrl)111 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
112 {
113 u32 ctrl_reg, data_reg, ctrl_data;
114 u32 val;
115 int ret;
116
117 switch (ctrl->type) {
118 case DLE_CTRL_TYPE_WDE:
119 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;
120 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA;
121 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
122 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
123 B_AX_WDE_DFI_ACTIVE;
124 break;
125 case DLE_CTRL_TYPE_PLE:
126 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;
127 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA;
128 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
129 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
130 B_AX_PLE_DFI_ACTIVE;
131 break;
132 default:
133 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
134 return -EINVAL;
135 }
136
137 rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
138
139 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
140 1, 1000, false, rtwdev, ctrl_reg);
141 if (ret) {
142 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
143 ctrl_reg, ctrl_data);
144 return ret;
145 }
146
147 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
148 return 0;
149 }
150
dle_dfi_quota(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_quota * quota)151 static int dle_dfi_quota(struct rtw89_dev *rtwdev,
152 struct rtw89_mac_dle_dfi_quota *quota)
153 {
154 struct rtw89_mac_dle_dfi_ctrl ctrl;
155 int ret;
156
157 ctrl.type = quota->dle_type;
158 ctrl.target = DLE_DFI_TYPE_QUOTA;
159 ctrl.addr = quota->qtaid;
160 ret = dle_dfi_ctrl(rtwdev, &ctrl);
161 if (ret) {
162 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
163 return ret;
164 }
165
166 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
167 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
168 return 0;
169 }
170
dle_dfi_qempty(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_qempty * qempty)171 static int dle_dfi_qempty(struct rtw89_dev *rtwdev,
172 struct rtw89_mac_dle_dfi_qempty *qempty)
173 {
174 struct rtw89_mac_dle_dfi_ctrl ctrl;
175 u32 ret;
176
177 ctrl.type = qempty->dle_type;
178 ctrl.target = DLE_DFI_TYPE_QEMPTY;
179 ctrl.addr = qempty->grpsel;
180 ret = dle_dfi_ctrl(rtwdev, &ctrl);
181 if (ret) {
182 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
183 return ret;
184 }
185
186 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
187 return 0;
188 }
189
dump_err_status_dispatcher(struct rtw89_dev * rtwdev)190 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)
191 {
192 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
193 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
194 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
195 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
196 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
197 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
198 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
199 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
200 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
201 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
202 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
203 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
204 }
205
rtw89_mac_dump_qta_lost(struct rtw89_dev * rtwdev)206 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)
207 {
208 struct rtw89_mac_dle_dfi_qempty qempty;
209 struct rtw89_mac_dle_dfi_quota quota;
210 struct rtw89_mac_dle_dfi_ctrl ctrl;
211 u32 val, not_empty, i;
212 int ret;
213
214 qempty.dle_type = DLE_CTRL_TYPE_PLE;
215 qempty.grpsel = 0;
216 qempty.qempty = ~(u32)0;
217 ret = dle_dfi_qempty(rtwdev, &qempty);
218 if (ret)
219 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
220 else
221 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
222
223 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
224 if (!(not_empty & BIT(0)))
225 continue;
226 ctrl.type = DLE_CTRL_TYPE_PLE;
227 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
228 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
229 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i);
230 ret = dle_dfi_ctrl(rtwdev, &ctrl);
231 if (ret)
232 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
233 else
234 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,
235 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK,
236 ctrl.out_data));
237 }
238
239 quota.dle_type = DLE_CTRL_TYPE_PLE;
240 quota.qtaid = 6;
241 ret = dle_dfi_quota(rtwdev, "a);
242 if (ret)
243 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
244 else
245 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
246 quota.rsv_pgnum, quota.use_pgnum);
247
248 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
249 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",
250 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val));
251 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",
252 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val));
253
254 dump_err_status_dispatcher(rtwdev);
255 }
256
rtw89_mac_dump_l0_to_l1(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)257 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
258 enum mac_ax_err_info err)
259 {
260 u32 dbg, event;
261
262 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
263 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg);
264
265 switch (event) {
266 case MAC_AX_L0_TO_L1_RX_QTA_LOST:
267 rtw89_info(rtwdev, "quota lost!\n");
268 rtw89_mac_dump_qta_lost(rtwdev);
269 break;
270 default:
271 break;
272 }
273 }
274
rtw89_mac_dump_err_status(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)275 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
276 enum mac_ax_err_info err)
277 {
278 u32 dmac_err, cmac_err;
279
280 if (err != MAC_AX_ERR_L1_ERR_DMAC &&
281 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
282 err != MAC_AX_ERR_L0_ERR_CMAC0 &&
283 err != MAC_AX_ERR_L0_ERR_CMAC1)
284 return;
285
286 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
287 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
288 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
289
290 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR);
291 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
294
295 if (dmac_err) {
296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ",
297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG));
298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG));
300 }
301
302 if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
303 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ",
304 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
305 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n",
306 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
307 }
308
309 if (dmac_err & B_AX_WSEC_ERR_FLAG) {
310 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
311 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
312 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n",
313 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
314 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n",
315 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
316 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n",
317 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
318 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n",
319 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
320 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n",
321 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
322 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n",
323 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
324 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n",
325 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
326 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n",
327 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
328 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n",
329 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
330 }
331
332 if (dmac_err & B_AX_MPDU_ERR_FLAG) {
333 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ",
334 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
335 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
336 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
337 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ",
338 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
339 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
340 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
341 }
342
343 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
344 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ",
345 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
346 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
347 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
348 }
349
350 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
351 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
352 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
353 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
354 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
355 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
356 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
357 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
358 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
359 dump_err_status_dispatcher(rtwdev);
360 }
361
362 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
363 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
364 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
365 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
366 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
367 }
368
369 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
370 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
371 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
372 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
373 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
374 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
375 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
376 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
377 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
378 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
379 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
380 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
381 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
382 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
383 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
384 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
385 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
386 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
387 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
388 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
389 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
390 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
391 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
392 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
393 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
394 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
395 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
396 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
397 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
398 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
399 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
400 dump_err_status_dispatcher(rtwdev);
401 }
402
403 if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
404 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
405 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
406 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
407 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
408 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
409 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
410 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
411 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
412 }
413
414 if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
415 dump_err_status_dispatcher(rtwdev);
416
417 if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
418 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ",
419 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR));
420 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n",
421 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
422 }
423
424 if (dmac_err & BIT(11)) {
425 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
426 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
427 }
428
429 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
430 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ",
431 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR));
432 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
433 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR));
434 }
435
436 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
437 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ",
438 rtw89_read32(rtwdev, R_AX_PTCL_IMR0));
439 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n",
440 rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
441 }
442
443 if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
444 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n",
445 rtw89_read32(rtwdev, R_AX_DLE_CTRL));
446 }
447
448 if (cmac_err & B_AX_PHYINTF_ERR_IND) {
449 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n",
450 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR));
451 }
452
453 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
454 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ",
455 rtw89_read32(rtwdev, R_AX_TXPWR_IMR));
456 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n",
457 rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
458 }
459
460 if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
461 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ",
462 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
463 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n",
464 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
465 }
466
467 if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
468 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ",
469 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
470 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n",
471 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
472 }
473
474 rtwdev->hci.ops->dump_err_status(rtwdev);
475
476 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
477 rtw89_mac_dump_l0_to_l1(rtwdev, err);
478
479 rtw89_info(rtwdev, "<---\n");
480 }
481
rtw89_mac_get_err_status(struct rtw89_dev * rtwdev)482 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
483 {
484 u32 err, err_scnr;
485 int ret;
486
487 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000,
488 false, rtwdev, R_AX_HALT_C2H_CTRL);
489 if (ret) {
490 rtw89_warn(rtwdev, "Polling FW err status fail\n");
491 return ret;
492 }
493
494 err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
495 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
496
497 err_scnr = RTW89_ERROR_SCENARIO(err);
498 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION)
499 err = MAC_AX_ERR_CPU_EXCEPTION;
500 else if (err_scnr == RTW89_WCPU_ASSERTION)
501 err = MAC_AX_ERR_ASSERTION;
502
503 rtw89_fw_st_dbg_dump(rtwdev);
504 rtw89_mac_dump_err_status(rtwdev, err);
505
506 return err;
507 }
508 EXPORT_SYMBOL(rtw89_mac_get_err_status);
509
rtw89_mac_set_err_status(struct rtw89_dev * rtwdev,u32 err)510 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
511 {
512 u32 halt;
513 int ret = 0;
514
515 if (err > MAC_AX_SET_ERR_MAX) {
516 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
517 return -EINVAL;
518 }
519
520 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000,
521 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
522 if (ret) {
523 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
524 return -EFAULT;
525 }
526
527 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
528 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
529
530 return 0;
531 }
532 EXPORT_SYMBOL(rtw89_mac_set_err_status);
533
hfc_reset_param(struct rtw89_dev * rtwdev)534 static int hfc_reset_param(struct rtw89_dev *rtwdev)
535 {
536 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
537 struct rtw89_hfc_param_ini param_ini = {NULL};
538 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
539
540 switch (rtwdev->hci.type) {
541 case RTW89_HCI_TYPE_PCIE:
542 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
543 param->en = 0;
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 if (param_ini.pub_cfg)
550 param->pub_cfg = *param_ini.pub_cfg;
551
552 if (param_ini.prec_cfg) {
553 param->prec_cfg = *param_ini.prec_cfg;
554 rtwdev->hal.sw_amsdu_max_size =
555 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT;
556 }
557
558 if (param_ini.ch_cfg)
559 param->ch_cfg = param_ini.ch_cfg;
560
561 memset(¶m->ch_info, 0, sizeof(param->ch_info));
562 memset(¶m->pub_info, 0, sizeof(param->pub_info));
563 param->mode = param_ini.mode;
564
565 return 0;
566 }
567
hfc_ch_cfg_chk(struct rtw89_dev * rtwdev,u8 ch)568 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
569 {
570 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
571 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
572 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
573 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
574
575 if (ch >= RTW89_DMA_CH_NUM)
576 return -EINVAL;
577
578 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
579 ch_cfg[ch].max > pub_cfg->pub_max)
580 return -EINVAL;
581 if (ch_cfg[ch].grp >= grp_num)
582 return -EINVAL;
583
584 return 0;
585 }
586
hfc_pub_info_chk(struct rtw89_dev * rtwdev)587 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
588 {
589 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
590 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg;
591 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
592
593 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
594 if (rtwdev->chip->chip_id == RTL8852A)
595 return 0;
596 else
597 return -EFAULT;
598 }
599
600 return 0;
601 }
602
hfc_pub_cfg_chk(struct rtw89_dev * rtwdev)603 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
604 {
605 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
606 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
607
608 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
609 return -EFAULT;
610
611 return 0;
612 }
613
hfc_ch_ctrl(struct rtw89_dev * rtwdev,u8 ch)614 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
615 {
616 const struct rtw89_chip_info *chip = rtwdev->chip;
617 const struct rtw89_page_regs *regs = chip->page_regs;
618 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
619 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
620 int ret = 0;
621 u32 val = 0;
622
623 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
624 if (ret)
625 return ret;
626
627 ret = hfc_ch_cfg_chk(rtwdev, ch);
628 if (ret)
629 return ret;
630
631 if (ch > RTW89_DMA_B1HI)
632 return -EINVAL;
633
634 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
635 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) |
636 (cfg[ch].grp ? B_AX_GRP : 0);
637 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
638
639 return 0;
640 }
641
hfc_upd_ch_info(struct rtw89_dev * rtwdev,u8 ch)642 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
643 {
644 const struct rtw89_chip_info *chip = rtwdev->chip;
645 const struct rtw89_page_regs *regs = chip->page_regs;
646 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
647 struct rtw89_hfc_ch_info *info = param->ch_info;
648 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
649 u32 val;
650 u32 ret;
651
652 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
653 if (ret)
654 return ret;
655
656 if (ch > RTW89_DMA_H2C)
657 return -EINVAL;
658
659 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
660 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
661 if (ch < RTW89_DMA_H2C)
662 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
663 else
664 info[ch].used = cfg[ch].min - info[ch].aval;
665
666 return 0;
667 }
668
hfc_pub_ctrl(struct rtw89_dev * rtwdev)669 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
670 {
671 const struct rtw89_chip_info *chip = rtwdev->chip;
672 const struct rtw89_page_regs *regs = chip->page_regs;
673 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
674 u32 val;
675 int ret;
676
677 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
678 if (ret)
679 return ret;
680
681 ret = hfc_pub_cfg_chk(rtwdev);
682 if (ret)
683 return ret;
684
685 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
686 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
687 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
688
689 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
690 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
691
692 return 0;
693 }
694
hfc_upd_mix_info(struct rtw89_dev * rtwdev)695 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
696 {
697 const struct rtw89_chip_info *chip = rtwdev->chip;
698 const struct rtw89_page_regs *regs = chip->page_regs;
699 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
700 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
701 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
702 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
703 u32 val;
704 int ret;
705
706 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
707 if (ret)
708 return ret;
709
710 val = rtw89_read32(rtwdev, regs->pub_page_info1);
711 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
712 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
713 val = rtw89_read32(rtwdev, regs->pub_page_info3);
714 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
715 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
716 info->pub_aval =
717 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
718 B_AX_PUB_AVAL_PG_MASK);
719 info->wp_aval =
720 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
721 B_AX_WP_AVAL_PG_MASK);
722
723 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
724 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
725 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
726 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
727 prec_cfg->ch011_full_cond =
728 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
729 prec_cfg->h2c_full_cond =
730 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
731 prec_cfg->wp_ch07_full_cond =
732 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
733 prec_cfg->wp_ch811_full_cond =
734 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
735
736 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
737 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
738 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
739
740 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
741 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
742
743 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
744 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
745 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
746
747 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
748 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
749
750 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
751 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
752 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
753
754 ret = hfc_pub_info_chk(rtwdev);
755 if (param->en && ret)
756 return ret;
757
758 return 0;
759 }
760
hfc_h2c_cfg(struct rtw89_dev * rtwdev)761 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)
762 {
763 const struct rtw89_chip_info *chip = rtwdev->chip;
764 const struct rtw89_page_regs *regs = chip->page_regs;
765 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
766 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
767 u32 val;
768
769 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
770 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
771
772 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
773 B_AX_HCI_FC_CH12_FULL_COND_MASK,
774 prec_cfg->h2c_full_cond);
775 }
776
hfc_mix_cfg(struct rtw89_dev * rtwdev)777 static void hfc_mix_cfg(struct rtw89_dev *rtwdev)
778 {
779 const struct rtw89_chip_info *chip = rtwdev->chip;
780 const struct rtw89_page_regs *regs = chip->page_regs;
781 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
782 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
783 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
784 u32 val;
785
786 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
787 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
788 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
789
790 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
791 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
792
793 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
794 B_AX_PREC_PAGE_WP_CH07_MASK) |
795 u32_encode_bits(prec_cfg->wp_ch811_prec,
796 B_AX_PREC_PAGE_WP_CH811_MASK);
797 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
798
799 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
800 param->mode, B_AX_HCI_FC_MODE_MASK);
801 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
802 B_AX_HCI_FC_WD_FULL_COND_MASK);
803 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
804 B_AX_HCI_FC_CH12_FULL_COND_MASK);
805 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
806 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
807 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
808 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
809 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
810 }
811
hfc_func_en(struct rtw89_dev * rtwdev,bool en,bool h2c_en)812 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
813 {
814 const struct rtw89_chip_info *chip = rtwdev->chip;
815 const struct rtw89_page_regs *regs = chip->page_regs;
816 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
817 u32 val;
818
819 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
820 param->en = en;
821 param->h2c_en = h2c_en;
822 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
823 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
824 (val & ~B_AX_HCI_FC_CH12_EN);
825 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
826 }
827
hfc_init(struct rtw89_dev * rtwdev,bool reset,bool en,bool h2c_en)828 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
829 {
830 const struct rtw89_chip_info *chip = rtwdev->chip;
831 u32 dma_ch_mask = chip->dma_ch_mask;
832 u8 ch;
833 u32 ret = 0;
834
835 if (reset)
836 ret = hfc_reset_param(rtwdev);
837 if (ret)
838 return ret;
839
840 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
841 if (ret)
842 return ret;
843
844 hfc_func_en(rtwdev, false, false);
845
846 if (!en && h2c_en) {
847 hfc_h2c_cfg(rtwdev);
848 hfc_func_en(rtwdev, en, h2c_en);
849 return ret;
850 }
851
852 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
853 if (dma_ch_mask & BIT(ch))
854 continue;
855 ret = hfc_ch_ctrl(rtwdev, ch);
856 if (ret)
857 return ret;
858 }
859
860 ret = hfc_pub_ctrl(rtwdev);
861 if (ret)
862 return ret;
863
864 hfc_mix_cfg(rtwdev);
865 if (en || h2c_en) {
866 hfc_func_en(rtwdev, en, h2c_en);
867 udelay(10);
868 }
869 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
870 if (dma_ch_mask & BIT(ch))
871 continue;
872 ret = hfc_upd_ch_info(rtwdev, ch);
873 if (ret)
874 return ret;
875 }
876 ret = hfc_upd_mix_info(rtwdev);
877
878 return ret;
879 }
880
881 #define PWR_POLL_CNT 2000
pwr_cmd_poll(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * cfg)882 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
883 const struct rtw89_pwr_cfg *cfg)
884 {
885 u8 val = 0;
886 int ret;
887 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
888 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
889
890 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
891 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
892
893 if (!ret)
894 return 0;
895
896 rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
897 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
898 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
899
900 return -EBUSY;
901 }
902
rtw89_mac_sub_pwr_seq(struct rtw89_dev * rtwdev,u8 cv_msk,u8 intf_msk,const struct rtw89_pwr_cfg * cfg)903 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
904 u8 intf_msk, const struct rtw89_pwr_cfg *cfg)
905 {
906 const struct rtw89_pwr_cfg *cur_cfg;
907 u32 addr;
908 u8 val;
909
910 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
911 if (!(cur_cfg->intf_msk & intf_msk) ||
912 !(cur_cfg->cv_msk & cv_msk))
913 continue;
914
915 switch (cur_cfg->cmd) {
916 case PWR_CMD_WRITE:
917 addr = cur_cfg->addr;
918
919 if (cur_cfg->base == PWR_BASE_SDIO)
920 addr |= SDIO_LOCAL_BASE_ADDR;
921
922 val = rtw89_read8(rtwdev, addr);
923 val &= ~(cur_cfg->msk);
924 val |= (cur_cfg->val & cur_cfg->msk);
925
926 rtw89_write8(rtwdev, addr, val);
927 break;
928 case PWR_CMD_POLL:
929 if (pwr_cmd_poll(rtwdev, cur_cfg))
930 return -EBUSY;
931 break;
932 case PWR_CMD_DELAY:
933 if (cur_cfg->val == PWR_DELAY_US)
934 udelay(cur_cfg->addr);
935 else
936 fsleep(cur_cfg->addr * 1000);
937 break;
938 default:
939 return -EINVAL;
940 }
941 }
942
943 return 0;
944 }
945
rtw89_mac_pwr_seq(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * const * cfg_seq)946 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
947 const struct rtw89_pwr_cfg * const *cfg_seq)
948 {
949 int ret;
950
951 for (; *cfg_seq; cfg_seq++) {
952 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
953 PWR_INTF_MSK_PCIE, *cfg_seq);
954 if (ret)
955 return -EBUSY;
956 }
957
958 return 0;
959 }
960
961 static enum rtw89_rpwm_req_pwr_state
rtw89_mac_get_req_pwr_state(struct rtw89_dev * rtwdev)962 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
963 {
964 enum rtw89_rpwm_req_pwr_state state;
965
966 switch (rtwdev->ps_mode) {
967 case RTW89_PS_MODE_RFOFF:
968 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF;
969 break;
970 case RTW89_PS_MODE_CLK_GATED:
971 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED;
972 break;
973 case RTW89_PS_MODE_PWR_GATED:
974 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED;
975 break;
976 default:
977 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
978 break;
979 }
980 return state;
981 }
982
rtw89_mac_send_rpwm(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state,bool notify_wake)983 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
984 enum rtw89_rpwm_req_pwr_state req_pwr_state,
985 bool notify_wake)
986 {
987 u16 request;
988
989 spin_lock_bh(&rtwdev->rpwm_lock);
990
991 request = rtw89_read16(rtwdev, R_AX_RPWM);
992 request ^= request | PS_RPWM_TOGGLE;
993 request |= req_pwr_state;
994
995 if (notify_wake) {
996 request |= PS_RPWM_NOTIFY_WAKE;
997 } else {
998 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
999 RPWM_SEQ_NUM_MAX;
1000 request |= FIELD_PREP(PS_RPWM_SEQ_NUM,
1001 rtwdev->mac.rpwm_seq_num);
1002
1003 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1004 request |= PS_RPWM_ACK;
1005 }
1006 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1007
1008 spin_unlock_bh(&rtwdev->rpwm_lock);
1009 }
1010
rtw89_mac_check_cpwm_state(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state)1011 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1012 enum rtw89_rpwm_req_pwr_state req_pwr_state)
1013 {
1014 bool request_deep_mode;
1015 bool in_deep_mode;
1016 u8 rpwm_req_num;
1017 u8 cpwm_rsp_seq;
1018 u8 cpwm_seq;
1019 u8 cpwm_status;
1020
1021 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1022 request_deep_mode = true;
1023 else
1024 request_deep_mode = false;
1025
1026 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1027 in_deep_mode = true;
1028 else
1029 in_deep_mode = false;
1030
1031 if (request_deep_mode != in_deep_mode)
1032 return -EPERM;
1033
1034 if (request_deep_mode)
1035 return 0;
1036
1037 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1038 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1039 PS_CPWM_RSP_SEQ_NUM);
1040
1041 if (rpwm_req_num != cpwm_rsp_seq)
1042 return -EPERM;
1043
1044 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1045 CPWM_SEQ_NUM_MAX;
1046
1047 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1048 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1049 return -EPERM;
1050
1051 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1052 if (cpwm_status != req_pwr_state)
1053 return -EPERM;
1054
1055 return 0;
1056 }
1057
rtw89_mac_power_mode_change(struct rtw89_dev * rtwdev,bool enter)1058 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1059 {
1060 enum rtw89_rpwm_req_pwr_state state;
1061 unsigned long delay = enter ? 10 : 150;
1062 int ret;
1063 int i;
1064
1065 if (enter)
1066 state = rtw89_mac_get_req_pwr_state(rtwdev);
1067 else
1068 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
1069
1070 for (i = 0; i < RPWM_TRY_CNT; i++) {
1071 rtw89_mac_send_rpwm(rtwdev, state, false);
1072 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret,
1073 !ret, delay, 15000, false,
1074 rtwdev, state);
1075 if (!ret)
1076 break;
1077
1078 if (i == RPWM_TRY_CNT - 1)
1079 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1080 enter ? "entering" : "leaving");
1081 else
1082 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1083 "%d time firmware failed to ack for %s ps mode\n",
1084 i + 1, enter ? "entering" : "leaving");
1085 }
1086 }
1087
rtw89_mac_notify_wake(struct rtw89_dev * rtwdev)1088 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1089 {
1090 enum rtw89_rpwm_req_pwr_state state;
1091
1092 state = rtw89_mac_get_req_pwr_state(rtwdev);
1093 rtw89_mac_send_rpwm(rtwdev, state, true);
1094 }
1095
rtw89_mac_power_switch(struct rtw89_dev * rtwdev,bool on)1096 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1097 {
1098 #define PWR_ACT 1
1099 const struct rtw89_chip_info *chip = rtwdev->chip;
1100 const struct rtw89_pwr_cfg * const *cfg_seq;
1101 int (*cfg_func)(struct rtw89_dev *rtwdev);
1102 int ret;
1103 u8 val;
1104
1105 if (on) {
1106 cfg_seq = chip->pwr_on_seq;
1107 cfg_func = chip->ops->pwr_on_func;
1108 } else {
1109 cfg_seq = chip->pwr_off_seq;
1110 cfg_func = chip->ops->pwr_off_func;
1111 }
1112
1113 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1114 __rtw89_leave_ps_mode(rtwdev);
1115
1116 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1117 if (on && val == PWR_ACT) {
1118 rtw89_err(rtwdev, "MAC has already powered on\n");
1119 return -EBUSY;
1120 }
1121
1122 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1123 if (ret)
1124 return ret;
1125
1126 if (on) {
1127 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1128 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1129 } else {
1130 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1131 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1132 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1133 rtw89_set_entity_state(rtwdev, false);
1134 }
1135
1136 return 0;
1137 #undef PWR_ACT
1138 }
1139
rtw89_mac_pwr_off(struct rtw89_dev * rtwdev)1140 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1141 {
1142 rtw89_mac_power_switch(rtwdev, false);
1143 }
1144
cmac_func_en(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)1145 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1146 {
1147 u32 func_en = 0;
1148 u32 ck_en = 0;
1149 u32 c1pc_en = 0;
1150 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1};
1151 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1};
1152
1153 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
1154 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN |
1155 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN |
1156 B_AX_CMAC_CRPRT;
1157 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN |
1158 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN |
1159 B_AX_RMAC_CKEN;
1160 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN |
1161 B_AX_R_SYM_WLCMAC1_P1_PC_EN |
1162 B_AX_R_SYM_WLCMAC1_P2_PC_EN |
1163 B_AX_R_SYM_WLCMAC1_P3_PC_EN |
1164 B_AX_R_SYM_WLCMAC1_P4_PC_EN;
1165
1166 if (en) {
1167 if (mac_idx == RTW89_MAC_1) {
1168 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1169 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1170 B_AX_R_SYM_ISO_CMAC12PP);
1171 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1172 B_AX_CMAC1_FEN);
1173 }
1174 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1175 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1176 } else {
1177 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1178 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1179 if (mac_idx == RTW89_MAC_1) {
1180 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1181 B_AX_CMAC1_FEN);
1182 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1183 B_AX_R_SYM_ISO_CMAC12PP);
1184 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1185 }
1186 }
1187
1188 return 0;
1189 }
1190
dmac_func_en(struct rtw89_dev * rtwdev)1191 static int dmac_func_en(struct rtw89_dev *rtwdev)
1192 {
1193 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1194 u32 val32;
1195
1196 if (chip_id == RTL8852C)
1197 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1198 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1199 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1200 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1201 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1202 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1203 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN);
1204 else
1205 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1206 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1207 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1208 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1209 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1210 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1211 B_AX_DMAC_CRPRT);
1212 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1213
1214 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN |
1215 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN |
1216 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN |
1217 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN);
1218 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1219
1220 return 0;
1221 }
1222
chip_func_en(struct rtw89_dev * rtwdev)1223 static int chip_func_en(struct rtw89_dev *rtwdev)
1224 {
1225 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1226
1227 if (chip_id == RTL8852A || chip_id == RTL8852B)
1228 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1229 B_AX_OCP_L1_MASK);
1230
1231 return 0;
1232 }
1233
rtw89_mac_sys_init(struct rtw89_dev * rtwdev)1234 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)
1235 {
1236 int ret;
1237
1238 ret = dmac_func_en(rtwdev);
1239 if (ret)
1240 return ret;
1241
1242 ret = cmac_func_en(rtwdev, 0, true);
1243 if (ret)
1244 return ret;
1245
1246 ret = chip_func_en(rtwdev);
1247 if (ret)
1248 return ret;
1249
1250 return ret;
1251 }
1252
1253 const struct rtw89_mac_size_set rtw89_mac_size = {
1254 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
1255 /* PCIE 64 */
1256 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
1257 /* DLFW */
1258 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},
1259 /* PCIE 64 */
1260 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,},
1261 /* DLFW */
1262 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
1263 /* 8852C DLFW */
1264 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
1265 /* 8852C PCIE SCC */
1266 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
1267 /* PCIE */
1268 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
1269 /* DLFW */
1270 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},
1271 /* PCIE 64 */
1272 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,},
1273 /* DLFW */
1274 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
1275 /* 8852C DLFW */
1276 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
1277 /* 8852C PCIE SCC */
1278 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
1279 /* PCIE 64 */
1280 .wde_qt0 = {3792, 196, 0, 107,},
1281 /* DLFW */
1282 .wde_qt4 = {0, 0, 0, 0,},
1283 /* PCIE 64 */
1284 .wde_qt6 = {448, 48, 0, 16,},
1285 /* 8852C DLFW */
1286 .wde_qt17 = {0, 0, 0, 0,},
1287 /* 8852C PCIE SCC */
1288 .wde_qt18 = {3228, 60, 0, 40,},
1289 /* PCIE SCC */
1290 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,},
1291 /* PCIE SCC */
1292 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},
1293 /* DLFW */
1294 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
1295 /* PCIE 64 */
1296 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
1297 /* DLFW 52C */
1298 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1299 /* DLFW 52C */
1300 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1301 /* 8852C PCIE SCC */
1302 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,},
1303 /* 8852C PCIE SCC */
1304 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
1305 /* PCIE 64 */
1306 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
1307 };
1308 EXPORT_SYMBOL(rtw89_mac_size);
1309
get_dle_mem_cfg(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1310 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1311 enum rtw89_qta_mode mode)
1312 {
1313 struct rtw89_mac_info *mac = &rtwdev->mac;
1314 const struct rtw89_dle_mem *cfg;
1315
1316 cfg = &rtwdev->chip->dle_mem[mode];
1317 if (!cfg)
1318 return NULL;
1319
1320 if (cfg->mode != mode) {
1321 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1322 return NULL;
1323 }
1324
1325 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size;
1326 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1327 mac->dle_info.qta_mode = mode;
1328 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
1329 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
1330
1331 return cfg;
1332 }
1333
dle_used_size(const struct rtw89_dle_size * wde,const struct rtw89_dle_size * ple)1334 static inline u32 dle_used_size(const struct rtw89_dle_size *wde,
1335 const struct rtw89_dle_size *ple)
1336 {
1337 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) +
1338 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num);
1339 }
1340
dle_expected_used_size(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1341 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1342 enum rtw89_qta_mode mode)
1343 {
1344 u32 size = rtwdev->chip->fifo_size;
1345
1346 if (mode == RTW89_QTA_SCC)
1347 size -= rtwdev->chip->dle_scc_rsvd_size;
1348
1349 return size;
1350 }
1351
dle_func_en(struct rtw89_dev * rtwdev,bool enable)1352 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)
1353 {
1354 if (enable)
1355 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1356 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1357 else
1358 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1359 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1360 }
1361
dle_clk_en(struct rtw89_dev * rtwdev,bool enable)1362 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)
1363 {
1364 if (enable)
1365 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN,
1366 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
1367 else
1368 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN,
1369 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
1370 }
1371
dle_mix_cfg(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)1372 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1373 {
1374 const struct rtw89_dle_size *size_cfg;
1375 u32 val;
1376 u8 bound = 0;
1377
1378 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1379 size_cfg = cfg->wde_size;
1380
1381 switch (size_cfg->pge_size) {
1382 default:
1383 case RTW89_WDE_PG_64:
1384 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
1385 B_AX_WDE_PAGE_SEL_MASK);
1386 break;
1387 case RTW89_WDE_PG_128:
1388 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
1389 B_AX_WDE_PAGE_SEL_MASK);
1390 break;
1391 case RTW89_WDE_PG_256:
1392 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1393 return -EINVAL;
1394 }
1395
1396 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK);
1397 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1398 B_AX_WDE_FREE_PAGE_NUM_MASK);
1399 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1400
1401 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1402 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
1403 * size_cfg->pge_size / DLE_BOUND_UNIT;
1404 size_cfg = cfg->ple_size;
1405
1406 switch (size_cfg->pge_size) {
1407 default:
1408 case RTW89_PLE_PG_64:
1409 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1410 return -EINVAL;
1411 case RTW89_PLE_PG_128:
1412 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
1413 B_AX_PLE_PAGE_SEL_MASK);
1414 break;
1415 case RTW89_PLE_PG_256:
1416 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
1417 B_AX_PLE_PAGE_SEL_MASK);
1418 break;
1419 }
1420
1421 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK);
1422 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1423 B_AX_PLE_FREE_PAGE_NUM_MASK);
1424 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1425
1426 return 0;
1427 }
1428
1429 #define INVALID_QT_WCPU U16_MAX
1430 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
1431 do { \
1432 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \
1433 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \
1434 rtw89_write32(rtwdev, \
1435 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \
1436 val); \
1437 } while (0)
1438 #define SET_QUOTA(_x, _module, _idx) \
1439 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
1440
wde_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)1441 static void wde_quota_cfg(struct rtw89_dev *rtwdev,
1442 const struct rtw89_wde_quota *min_cfg,
1443 const struct rtw89_wde_quota *max_cfg,
1444 u16 ext_wde_min_qt_wcpu)
1445 {
1446 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
1447 ext_wde_min_qt_wcpu : min_cfg->wcpu;
1448 u32 val;
1449
1450 SET_QUOTA(hif, WDE, 0);
1451 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1);
1452 SET_QUOTA(pkt_in, WDE, 3);
1453 SET_QUOTA(cpu_io, WDE, 4);
1454 }
1455
ple_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)1456 static void ple_quota_cfg(struct rtw89_dev *rtwdev,
1457 const struct rtw89_ple_quota *min_cfg,
1458 const struct rtw89_ple_quota *max_cfg)
1459 {
1460 u32 val;
1461
1462 SET_QUOTA(cma0_tx, PLE, 0);
1463 SET_QUOTA(cma1_tx, PLE, 1);
1464 SET_QUOTA(c2h, PLE, 2);
1465 SET_QUOTA(h2c, PLE, 3);
1466 SET_QUOTA(wcpu, PLE, 4);
1467 SET_QUOTA(mpdu_proc, PLE, 5);
1468 SET_QUOTA(cma0_dma, PLE, 6);
1469 SET_QUOTA(cma1_dma, PLE, 7);
1470 SET_QUOTA(bb_rpt, PLE, 8);
1471 SET_QUOTA(wd_rel, PLE, 9);
1472 SET_QUOTA(cpu_io, PLE, 10);
1473 if (rtwdev->chip->chip_id == RTL8852C)
1474 SET_QUOTA(tx_rpt, PLE, 11);
1475 }
1476
1477 #undef SET_QUOTA
1478
dle_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg,u16 ext_wde_min_qt_wcpu)1479 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
1480 const struct rtw89_dle_mem *cfg,
1481 u16 ext_wde_min_qt_wcpu)
1482 {
1483 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
1484 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
1485 }
1486
dle_init(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode,enum rtw89_qta_mode ext_mode)1487 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1488 enum rtw89_qta_mode ext_mode)
1489 {
1490 const struct rtw89_dle_mem *cfg, *ext_cfg;
1491 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU;
1492 int ret = 0;
1493 u32 ini;
1494
1495 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1496 if (ret)
1497 return ret;
1498
1499 cfg = get_dle_mem_cfg(rtwdev, mode);
1500 if (!cfg) {
1501 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1502 ret = -EINVAL;
1503 goto error;
1504 }
1505
1506 if (mode == RTW89_QTA_DLFW) {
1507 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
1508 if (!ext_cfg) {
1509 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
1510 ext_mode);
1511 ret = -EINVAL;
1512 goto error;
1513 }
1514 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu;
1515 }
1516
1517 if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
1518 dle_expected_used_size(rtwdev, mode)) {
1519 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
1520 ret = -EINVAL;
1521 goto error;
1522 }
1523
1524 dle_func_en(rtwdev, false);
1525 dle_clk_en(rtwdev, true);
1526
1527 ret = dle_mix_cfg(rtwdev, cfg);
1528 if (ret) {
1529 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
1530 goto error;
1531 }
1532 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
1533
1534 dle_func_en(rtwdev, true);
1535
1536 ret = read_poll_timeout(rtw89_read32, ini,
1537 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1538 2000, false, rtwdev, R_AX_WDE_INI_STATUS);
1539 if (ret) {
1540 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
1541 return ret;
1542 }
1543
1544 ret = read_poll_timeout(rtw89_read32, ini,
1545 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1546 2000, false, rtwdev, R_AX_PLE_INI_STATUS);
1547 if (ret) {
1548 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
1549 return ret;
1550 }
1551
1552 return 0;
1553 error:
1554 dle_func_en(rtwdev, false);
1555 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
1556 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
1557 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
1558 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
1559
1560 return ret;
1561 }
1562
preload_init_set(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)1563 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1564 enum rtw89_qta_mode mode)
1565 {
1566 u32 reg, max_preld_size, min_rsvd_size;
1567
1568 max_preld_size = (mac_idx == RTW89_MAC_0 ?
1569 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE;
1570 reg = mac_idx == RTW89_MAC_0 ?
1571 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0;
1572 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
1573 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
1574
1575 min_rsvd_size = PRELD_AMSDU_SIZE;
1576 reg = mac_idx == RTW89_MAC_0 ?
1577 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1;
1578 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
1579 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
1580
1581 return 0;
1582 }
1583
is_qta_poh(struct rtw89_dev * rtwdev)1584 static bool is_qta_poh(struct rtw89_dev *rtwdev)
1585 {
1586 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
1587 }
1588
preload_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)1589 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1590 enum rtw89_qta_mode mode)
1591 {
1592 const struct rtw89_chip_info *chip = rtwdev->chip;
1593
1594 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev))
1595 return 0;
1596
1597 return preload_init_set(rtwdev, mac_idx, mode);
1598 }
1599
dle_is_txq_empty(struct rtw89_dev * rtwdev)1600 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
1601 {
1602 u32 msk32;
1603 u32 val32;
1604
1605 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH |
1606 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 |
1607 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS |
1608 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
1609 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN |
1610 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU |
1611 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO |
1612 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL |
1613 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
1614 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX |
1615 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
1616 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
1617 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU;
1618 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1619
1620 if ((val32 & msk32) == msk32)
1621 return true;
1622
1623 return false;
1624 }
1625
_patch_ss2f_path(struct rtw89_dev * rtwdev)1626 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
1627 {
1628 const struct rtw89_chip_info *chip = rtwdev->chip;
1629
1630 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
1631 return;
1632
1633 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
1634 SS2F_PATH_WLCPU);
1635 }
1636
sta_sch_init(struct rtw89_dev * rtwdev)1637 static int sta_sch_init(struct rtw89_dev *rtwdev)
1638 {
1639 u32 p_val;
1640 u8 val;
1641 int ret;
1642
1643 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1644 if (ret)
1645 return ret;
1646
1647 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
1648 val |= B_AX_SS_EN;
1649 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
1650
1651 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1,
1652 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
1653 if (ret) {
1654 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
1655 return ret;
1656 }
1657
1658 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
1659 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
1660
1661 _patch_ss2f_path(rtwdev);
1662
1663 return 0;
1664 }
1665
mpdu_proc_init(struct rtw89_dev * rtwdev)1666 static int mpdu_proc_init(struct rtw89_dev *rtwdev)
1667 {
1668 int ret;
1669
1670 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1671 if (ret)
1672 return ret;
1673
1674 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
1675 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
1676 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
1677 B_AX_APPEND_FCS | B_AX_A_ICV_ERR);
1678 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
1679
1680 return 0;
1681 }
1682
sec_eng_init(struct rtw89_dev * rtwdev)1683 static int sec_eng_init(struct rtw89_dev *rtwdev)
1684 {
1685 const struct rtw89_chip_info *chip = rtwdev->chip;
1686 u32 val = 0;
1687 int ret;
1688
1689 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1690 if (ret)
1691 return ret;
1692
1693 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
1694 /* init clock */
1695 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
1696 /* init TX encryption */
1697 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
1698 val |= (B_AX_MC_DEC | B_AX_BC_DEC);
1699 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
1700 val &= ~B_AX_TX_PARTIAL_MODE;
1701 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
1702
1703 /* init MIC ICV append */
1704 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
1705 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
1706
1707 /* option init */
1708 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
1709
1710 if (chip->chip_id == RTL8852C)
1711 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
1712 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL);
1713
1714 return 0;
1715 }
1716
dmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)1717 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1718 {
1719 int ret;
1720
1721 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
1722 if (ret) {
1723 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
1724 return ret;
1725 }
1726
1727 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
1728 if (ret) {
1729 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
1730 return ret;
1731 }
1732
1733 ret = hfc_init(rtwdev, true, true, true);
1734 if (ret) {
1735 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
1736 return ret;
1737 }
1738
1739 ret = sta_sch_init(rtwdev);
1740 if (ret) {
1741 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
1742 return ret;
1743 }
1744
1745 ret = mpdu_proc_init(rtwdev);
1746 if (ret) {
1747 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
1748 return ret;
1749 }
1750
1751 ret = sec_eng_init(rtwdev);
1752 if (ret) {
1753 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
1754 return ret;
1755 }
1756
1757 return ret;
1758 }
1759
addr_cam_init(struct rtw89_dev * rtwdev,u8 mac_idx)1760 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1761 {
1762 u32 val, reg;
1763 u16 p_val;
1764 int ret;
1765
1766 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1767 if (ret)
1768 return ret;
1769
1770 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx);
1771
1772 val = rtw89_read32(rtwdev, reg);
1773 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
1774 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN;
1775 rtw89_write32(rtwdev, reg, val);
1776
1777 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR),
1778 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
1779 if (ret) {
1780 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
1781 return ret;
1782 }
1783
1784 return 0;
1785 }
1786
scheduler_init(struct rtw89_dev * rtwdev,u8 mac_idx)1787 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1788 {
1789 u32 ret;
1790 u32 reg;
1791 u32 val;
1792
1793 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1794 if (ret)
1795 return ret;
1796
1797 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
1798 if (rtwdev->chip->chip_id == RTL8852C)
1799 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
1800 SIFS_MACTXEN_T1_V1);
1801 else
1802 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
1803 SIFS_MACTXEN_T1);
1804
1805 if (rtwdev->chip->chip_id == RTL8852B) {
1806 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);
1807 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
1808 }
1809
1810 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx);
1811 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
1812
1813 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx);
1814 if (rtwdev->chip->chip_id == RTL8852C) {
1815 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
1816 B_AX_TX_PARTIAL_MODE);
1817 if (!val)
1818 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
1819 SCH_PREBKF_24US);
1820 } else {
1821 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
1822 SCH_PREBKF_24US);
1823 }
1824
1825 return 0;
1826 }
1827
rtw89_mac_typ_fltr_opt(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)1828 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
1829 enum rtw89_machdr_frame_type type,
1830 enum rtw89_mac_fwd_target fwd_target,
1831 u8 mac_idx)
1832 {
1833 u32 reg;
1834 u32 val;
1835
1836 switch (fwd_target) {
1837 case RTW89_FWD_DONT_CARE:
1838 val = RX_FLTR_FRAME_DROP;
1839 break;
1840 case RTW89_FWD_TO_HOST:
1841 val = RX_FLTR_FRAME_TO_HOST;
1842 break;
1843 case RTW89_FWD_TO_WLAN_CPU:
1844 val = RX_FLTR_FRAME_TO_WLCPU;
1845 break;
1846 default:
1847 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
1848 return -EINVAL;
1849 }
1850
1851 switch (type) {
1852 case RTW89_MGNT:
1853 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx);
1854 break;
1855 case RTW89_CTRL:
1856 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx);
1857 break;
1858 case RTW89_DATA:
1859 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx);
1860 break;
1861 default:
1862 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
1863 return -EINVAL;
1864 }
1865 rtw89_write32(rtwdev, reg, val);
1866
1867 return 0;
1868 }
1869
rx_fltr_init(struct rtw89_dev * rtwdev,u8 mac_idx)1870 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1871 {
1872 int ret, i;
1873 u32 mac_ftlr, plcp_ftlr;
1874
1875 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1876 if (ret)
1877 return ret;
1878
1879 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) {
1880 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST,
1881 mac_idx);
1882 if (ret)
1883 return ret;
1884 }
1885 mac_ftlr = rtwdev->hal.rx_fltr;
1886 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK |
1887 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK |
1888 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK |
1889 B_AX_HE_SIGB_CRC_CHK;
1890 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx),
1891 mac_ftlr);
1892 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx),
1893 plcp_ftlr);
1894
1895 return 0;
1896 }
1897
_patch_dis_resp_chk(struct rtw89_dev * rtwdev,u8 mac_idx)1898 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
1899 {
1900 u32 reg, val32;
1901 u32 b_rsp_chk_nav, b_rsp_chk_cca;
1902
1903 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV |
1904 B_AX_RSP_CHK_BASIC_NAV;
1905 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 |
1906 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA |
1907 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA;
1908
1909 switch (rtwdev->chip->chip_id) {
1910 case RTL8852A:
1911 case RTL8852B:
1912 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);
1913 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
1914 rtw89_write32(rtwdev, reg, val32);
1915
1916 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
1917 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
1918 rtw89_write32(rtwdev, reg, val32);
1919 break;
1920 default:
1921 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);
1922 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
1923 rtw89_write32(rtwdev, reg, val32);
1924
1925 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
1926 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
1927 rtw89_write32(rtwdev, reg, val32);
1928 break;
1929 }
1930 }
1931
cca_ctrl_init(struct rtw89_dev * rtwdev,u8 mac_idx)1932 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1933 {
1934 u32 val, reg;
1935 int ret;
1936
1937 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1938 if (ret)
1939 return ret;
1940
1941 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx);
1942 val = rtw89_read32(rtwdev, reg);
1943 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
1944 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 |
1945 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 |
1946 B_AX_CTN_CHK_INTRA_NAV |
1947 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
1948 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
1949 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
1950 B_AX_CTN_CHK_CCA_P20);
1951 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
1952 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
1953 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
1954 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
1955 B_AX_SIFS_CHK_EDCCA);
1956
1957 rtw89_write32(rtwdev, reg, val);
1958
1959 _patch_dis_resp_chk(rtwdev, mac_idx);
1960
1961 return 0;
1962 }
1963
nav_ctrl_init(struct rtw89_dev * rtwdev)1964 static int nav_ctrl_init(struct rtw89_dev *rtwdev)
1965 {
1966 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
1967 B_AX_WMAC_TF_UP_NAV_EN |
1968 B_AX_WMAC_NAV_UPPER_EN);
1969 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
1970
1971 return 0;
1972 }
1973
spatial_reuse_init(struct rtw89_dev * rtwdev,u8 mac_idx)1974 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1975 {
1976 u32 reg;
1977 int ret;
1978
1979 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1980 if (ret)
1981 return ret;
1982 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx);
1983 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
1984
1985 return 0;
1986 }
1987
tmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)1988 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1989 {
1990 u32 reg;
1991 int ret;
1992
1993 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1994 if (ret)
1995 return ret;
1996
1997 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx);
1998 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
1999
2000 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx);
2001 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2002
2003 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx);
2004 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2005 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2006
2007 return 0;
2008 }
2009
trxptcl_init(struct rtw89_dev * rtwdev,u8 mac_idx)2010 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2011 {
2012 const struct rtw89_chip_info *chip = rtwdev->chip;
2013 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
2014 u32 reg, val, sifs;
2015 int ret;
2016
2017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2018 if (ret)
2019 return ret;
2020
2021 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
2022 val = rtw89_read32(rtwdev, reg);
2023 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
2024 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
2025
2026 switch (rtwdev->chip->chip_id) {
2027 case RTL8852A:
2028 sifs = WMAC_SPEC_SIFS_OFDM_52A;
2029 break;
2030 case RTL8852B:
2031 sifs = WMAC_SPEC_SIFS_OFDM_52B;
2032 break;
2033 default:
2034 sifs = WMAC_SPEC_SIFS_OFDM_52C;
2035 break;
2036 }
2037 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK;
2038 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);
2039 rtw89_write32(rtwdev, reg, val);
2040
2041 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx);
2042 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2043
2044 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx);
2045 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2046 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx);
2047 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2048
2049 return 0;
2050 }
2051
rst_bacam(struct rtw89_dev * rtwdev)2052 static void rst_bacam(struct rtw89_dev *rtwdev)
2053 {
2054 u32 val32;
2055 int ret;
2056
2057 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2058 S_AX_BACAM_RST_ALL);
2059
2060 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0,
2061 1, 1000, false,
2062 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2063 if (ret)
2064 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2065 }
2066
rmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)2067 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2068 {
2069 #define TRXCFG_RMAC_CCA_TO 32
2070 #define TRXCFG_RMAC_DATA_TO 15
2071 #define RX_MAX_LEN_UNIT 512
2072 #define PLD_RLS_MAX_PG 127
2073 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
2074 int ret;
2075 u32 reg, rx_max_len, rx_qta;
2076 u16 val;
2077
2078 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2079 if (ret)
2080 return ret;
2081
2082 if (mac_idx == RTW89_MAC_0)
2083 rst_bacam(rtwdev);
2084
2085 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx);
2086 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2087
2088 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx);
2089 val = rtw89_read16(rtwdev, reg);
2090 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,
2091 B_AX_RX_DLK_DATA_TIME_MASK);
2092 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
2093 B_AX_RX_DLK_CCA_TIME_MASK);
2094 rtw89_write16(rtwdev, reg, val);
2095
2096 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx);
2097 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2098
2099 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx);
2100 if (mac_idx == RTW89_MAC_0)
2101 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2102 else
2103 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2104 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG);
2105 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2106 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
2107 rx_max_len /= RX_MAX_LEN_UNIT;
2108 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2109
2110 if (rtwdev->chip->chip_id == RTL8852A &&
2111 rtwdev->hal.cv == CHIP_CBV) {
2112 rtw89_write16_mask(rtwdev,
2113 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx),
2114 B_AX_RX_DLK_CCA_TIME_MASK, 0);
2115 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx),
2116 BIT(12));
2117 }
2118
2119 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx);
2120 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2121
2122 return ret;
2123 }
2124
cmac_com_init(struct rtw89_dev * rtwdev,u8 mac_idx)2125 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2126 {
2127 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2128 u32 val, reg;
2129 int ret;
2130
2131 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2132 if (ret)
2133 return ret;
2134
2135 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2136 val = rtw89_read32(rtwdev, reg);
2137 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);
2138 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
2139 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
2140 rtw89_write32(rtwdev, reg, val);
2141
2142 if (chip_id == RTL8852A || chip_id == RTL8852B) {
2143 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx);
2144 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2145 }
2146
2147 return 0;
2148 }
2149
is_qta_dbcc(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)2150 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2151 {
2152 const struct rtw89_dle_mem *cfg;
2153
2154 cfg = get_dle_mem_cfg(rtwdev, mode);
2155 if (!cfg) {
2156 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2157 return false;
2158 }
2159
2160 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma);
2161 }
2162
ptcl_init(struct rtw89_dev * rtwdev,u8 mac_idx)2163 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2164 {
2165 u32 val, reg;
2166 int ret;
2167
2168 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2169 if (ret)
2170 return ret;
2171
2172 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2173 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx);
2174 val = rtw89_read32(rtwdev, reg);
2175 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
2176 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK);
2177 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
2178 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
2179 val |= B_AX_HW_CTS2SELF_EN;
2180 rtw89_write32(rtwdev, reg, val);
2181
2182 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx);
2183 val = rtw89_read32(rtwdev, reg);
2184 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);
2185 val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
2186 rtw89_write32(rtwdev, reg, val);
2187 }
2188
2189 if (mac_idx == RTW89_MAC_0) {
2190 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2191 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1);
2192 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2193 B_AX_PTCL_TRIGGER_SS_EN_0 |
2194 B_AX_PTCL_TRIGGER_SS_EN_1 |
2195 B_AX_PTCL_TRIGGER_SS_EN_UL);
2196 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2197 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2198 } else if (mac_idx == RTW89_MAC_1) {
2199 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2200 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2201 }
2202
2203 return 0;
2204 }
2205
cmac_dma_init(struct rtw89_dev * rtwdev,u8 mac_idx)2206 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2207 {
2208 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2209 u32 reg;
2210 int ret;
2211
2212 if (chip_id != RTL8852A && chip_id != RTL8852B)
2213 return 0;
2214
2215 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2216 if (ret)
2217 return ret;
2218
2219 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx);
2220 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2221
2222 return 0;
2223 }
2224
cmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)2225 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2226 {
2227 int ret;
2228
2229 ret = scheduler_init(rtwdev, mac_idx);
2230 if (ret) {
2231 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2232 return ret;
2233 }
2234
2235 ret = addr_cam_init(rtwdev, mac_idx);
2236 if (ret) {
2237 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2238 ret);
2239 return ret;
2240 }
2241
2242 ret = rx_fltr_init(rtwdev, mac_idx);
2243 if (ret) {
2244 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2245 ret);
2246 return ret;
2247 }
2248
2249 ret = cca_ctrl_init(rtwdev, mac_idx);
2250 if (ret) {
2251 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2252 ret);
2253 return ret;
2254 }
2255
2256 ret = nav_ctrl_init(rtwdev);
2257 if (ret) {
2258 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2259 ret);
2260 return ret;
2261 }
2262
2263 ret = spatial_reuse_init(rtwdev, mac_idx);
2264 if (ret) {
2265 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2266 mac_idx, ret);
2267 return ret;
2268 }
2269
2270 ret = tmac_init(rtwdev, mac_idx);
2271 if (ret) {
2272 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2273 return ret;
2274 }
2275
2276 ret = trxptcl_init(rtwdev, mac_idx);
2277 if (ret) {
2278 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2279 return ret;
2280 }
2281
2282 ret = rmac_init(rtwdev, mac_idx);
2283 if (ret) {
2284 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2285 return ret;
2286 }
2287
2288 ret = cmac_com_init(rtwdev, mac_idx);
2289 if (ret) {
2290 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2291 return ret;
2292 }
2293
2294 ret = ptcl_init(rtwdev, mac_idx);
2295 if (ret) {
2296 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2297 return ret;
2298 }
2299
2300 ret = cmac_dma_init(rtwdev, mac_idx);
2301 if (ret) {
2302 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2303 return ret;
2304 }
2305
2306 return ret;
2307 }
2308
rtw89_mac_read_phycap(struct rtw89_dev * rtwdev,struct rtw89_mac_c2h_info * c2h_info)2309 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2310 struct rtw89_mac_c2h_info *c2h_info)
2311 {
2312 struct rtw89_mac_h2c_info h2c_info = {0};
2313 u32 ret;
2314
2315 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE;
2316 h2c_info.content_len = 0;
2317
2318 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2319 if (ret)
2320 return ret;
2321
2322 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP)
2323 return -EINVAL;
2324
2325 return 0;
2326 }
2327
rtw89_mac_setup_phycap(struct rtw89_dev * rtwdev)2328 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
2329 {
2330 struct rtw89_hal *hal = &rtwdev->hal;
2331 const struct rtw89_chip_info *chip = rtwdev->chip;
2332 struct rtw89_mac_c2h_info c2h_info = {0};
2333 u8 tx_nss;
2334 u8 rx_nss;
2335 u8 tx_ant;
2336 u8 rx_ant;
2337 u32 ret;
2338
2339 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
2340 if (ret)
2341 return ret;
2342
2343 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg);
2344 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg);
2345 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg);
2346 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg);
2347
2348 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
2349 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
2350
2351 if (tx_ant == 1)
2352 hal->antenna_tx = RF_B;
2353 if (rx_ant == 1)
2354 hal->antenna_rx = RF_B;
2355
2356 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) {
2357 hal->antenna_tx = RF_B;
2358 hal->tx_path_diversity = true;
2359 }
2360
2361 rtw89_debug(rtwdev, RTW89_DBG_FW,
2362 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n",
2363 hal->tx_nss, tx_nss, chip->tx_nss,
2364 hal->rx_nss, rx_nss, chip->rx_nss);
2365 rtw89_debug(rtwdev, RTW89_DBG_FW,
2366 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n",
2367 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
2368 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2369
2370 return 0;
2371 }
2372
rtw89_hw_sch_tx_en_h2c(struct rtw89_dev * rtwdev,u8 band,u16 tx_en_u16,u16 mask_u16)2373 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
2374 u16 tx_en_u16, u16 mask_u16)
2375 {
2376 u32 ret;
2377 struct rtw89_mac_c2h_info c2h_info = {0};
2378 struct rtw89_mac_h2c_info h2c_info = {0};
2379 struct rtw89_h2creg_sch_tx_en *h2creg =
2380 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg;
2381
2382 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN;
2383 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN;
2384 h2creg->tx_en = tx_en_u16;
2385 h2creg->mask = mask_u16;
2386 h2creg->band = band;
2387
2388 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
2389 if (ret)
2390 return ret;
2391
2392 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT)
2393 return -EINVAL;
2394
2395 return 0;
2396 }
2397
rtw89_set_hw_sch_tx_en(struct rtw89_dev * rtwdev,u8 mac_idx,u16 tx_en,u16 tx_en_mask)2398 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
2399 u16 tx_en, u16 tx_en_mask)
2400 {
2401 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx);
2402 u16 val;
2403 int ret;
2404
2405 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2406 if (ret)
2407 return ret;
2408
2409 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
2410 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
2411 tx_en, tx_en_mask);
2412
2413 val = rtw89_read16(rtwdev, reg);
2414 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2415 rtw89_write16(rtwdev, reg, val);
2416
2417 return 0;
2418 }
2419
rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)2420 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2421 u32 tx_en, u32 tx_en_mask)
2422 {
2423 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx);
2424 u32 val;
2425 int ret;
2426
2427 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2428 if (ret)
2429 return ret;
2430
2431 val = rtw89_read32(rtwdev, reg);
2432 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2433 rtw89_write32(rtwdev, reg, val);
2434
2435 return 0;
2436 }
2437
rtw89_mac_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2438 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
2439 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2440 {
2441 int ret;
2442
2443 *tx_en = rtw89_read16(rtwdev,
2444 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx));
2445
2446 switch (sel) {
2447 case RTW89_SCH_TX_SEL_ALL:
2448 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2449 B_AX_CTN_TXEN_ALL_MASK);
2450 if (ret)
2451 return ret;
2452 break;
2453 case RTW89_SCH_TX_SEL_HIQ:
2454 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2455 0, B_AX_CTN_TXEN_HGQ);
2456 if (ret)
2457 return ret;
2458 break;
2459 case RTW89_SCH_TX_SEL_MG0:
2460 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2461 0, B_AX_CTN_TXEN_MGQ);
2462 if (ret)
2463 return ret;
2464 break;
2465 case RTW89_SCH_TX_SEL_MACID:
2466 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2467 B_AX_CTN_TXEN_ALL_MASK);
2468 if (ret)
2469 return ret;
2470 break;
2471 default:
2472 return 0;
2473 }
2474
2475 return 0;
2476 }
2477 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx);
2478
rtw89_mac_stop_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2479 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2480 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2481 {
2482 int ret;
2483
2484 *tx_en = rtw89_read32(rtwdev,
2485 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx));
2486
2487 switch (sel) {
2488 case RTW89_SCH_TX_SEL_ALL:
2489 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2490 B_AX_CTN_TXEN_ALL_MASK_V1);
2491 if (ret)
2492 return ret;
2493 break;
2494 case RTW89_SCH_TX_SEL_HIQ:
2495 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2496 0, B_AX_CTN_TXEN_HGQ);
2497 if (ret)
2498 return ret;
2499 break;
2500 case RTW89_SCH_TX_SEL_MG0:
2501 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2502 0, B_AX_CTN_TXEN_MGQ);
2503 if (ret)
2504 return ret;
2505 break;
2506 case RTW89_SCH_TX_SEL_MACID:
2507 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2508 B_AX_CTN_TXEN_ALL_MASK_V1);
2509 if (ret)
2510 return ret;
2511 break;
2512 default:
2513 return 0;
2514 }
2515
2516 return 0;
2517 }
2518 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1);
2519
rtw89_mac_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2520 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2521 {
2522 int ret;
2523
2524 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
2525 if (ret)
2526 return ret;
2527
2528 return 0;
2529 }
2530 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx);
2531
rtw89_mac_resume_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2532 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2533 {
2534 int ret;
2535
2536 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
2537 B_AX_CTN_TXEN_ALL_MASK_V1);
2538 if (ret)
2539 return ret;
2540
2541 return 0;
2542 }
2543 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1);
2544
rtw89_mac_dle_buf_req(struct rtw89_dev * rtwdev,u16 buf_len,bool wd)2545 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd)
2546 {
2547 u32 val, reg;
2548 int ret;
2549
2550 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ;
2551 val = buf_len;
2552 val |= B_AX_WD_BUF_REQ_EXEC;
2553 rtw89_write32(rtwdev, reg, val);
2554
2555 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS;
2556
2557 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE,
2558 1, 2000, false, rtwdev, reg);
2559 if (ret)
2560 return 0xffff;
2561
2562 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val);
2563 }
2564
rtw89_mac_set_cpuio(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)2565 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
2566 struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
2567 {
2568 u32 val, cmd_type, reg;
2569 int ret;
2570
2571 cmd_type = ctrl_para->cmd_type;
2572
2573 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2;
2574 val = 0;
2575 val = u32_replace_bits(val, ctrl_para->start_pktid,
2576 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK);
2577 val = u32_replace_bits(val, ctrl_para->end_pktid,
2578 B_AX_WD_CPUQ_OP_END_PKTID_MASK);
2579 rtw89_write32(rtwdev, reg, val);
2580
2581 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1;
2582 val = 0;
2583 val = u32_replace_bits(val, ctrl_para->src_pid,
2584 B_AX_CPUQ_OP_SRC_PID_MASK);
2585 val = u32_replace_bits(val, ctrl_para->src_qid,
2586 B_AX_CPUQ_OP_SRC_QID_MASK);
2587 val = u32_replace_bits(val, ctrl_para->dst_pid,
2588 B_AX_CPUQ_OP_DST_PID_MASK);
2589 val = u32_replace_bits(val, ctrl_para->dst_qid,
2590 B_AX_CPUQ_OP_DST_QID_MASK);
2591 rtw89_write32(rtwdev, reg, val);
2592
2593 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0;
2594 val = 0;
2595 val = u32_replace_bits(val, cmd_type,
2596 B_AX_CPUQ_OP_CMD_TYPE_MASK);
2597 val = u32_replace_bits(val, ctrl_para->macid,
2598 B_AX_CPUQ_OP_MACID_MASK);
2599 val = u32_replace_bits(val, ctrl_para->pkt_num,
2600 B_AX_CPUQ_OP_PKTNUM_MASK);
2601 val |= B_AX_WD_CPUQ_OP_EXEC;
2602 rtw89_write32(rtwdev, reg, val);
2603
2604 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS;
2605
2606 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE,
2607 1, 2000, false, rtwdev, reg);
2608 if (ret)
2609 return ret;
2610
2611 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID ||
2612 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID)
2613 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
2614
2615 return 0;
2616 }
2617
dle_quota_change(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)2618 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2619 {
2620 const struct rtw89_dle_mem *cfg;
2621 struct rtw89_cpuio_ctrl ctrl_para = {0};
2622 u16 pkt_id;
2623 int ret;
2624
2625 cfg = get_dle_mem_cfg(rtwdev, mode);
2626 if (!cfg) {
2627 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2628 return -EINVAL;
2629 }
2630
2631 if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
2632 dle_expected_used_size(rtwdev, mode)) {
2633 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2634 return -EINVAL;
2635 }
2636
2637 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
2638
2639 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true);
2640 if (pkt_id == 0xffff) {
2641 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
2642 return -ENOMEM;
2643 }
2644
2645 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2646 ctrl_para.start_pktid = pkt_id;
2647 ctrl_para.end_pktid = pkt_id;
2648 ctrl_para.pkt_num = 0;
2649 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
2650 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
2651 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true);
2652 if (ret) {
2653 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
2654 return -EFAULT;
2655 }
2656
2657 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false);
2658 if (pkt_id == 0xffff) {
2659 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
2660 return -ENOMEM;
2661 }
2662
2663 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2664 ctrl_para.start_pktid = pkt_id;
2665 ctrl_para.end_pktid = pkt_id;
2666 ctrl_para.pkt_num = 0;
2667 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS;
2668 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT;
2669 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false);
2670 if (ret) {
2671 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
2672 return -EFAULT;
2673 }
2674
2675 return 0;
2676 }
2677
band_idle_ck_b(struct rtw89_dev * rtwdev,u8 mac_idx)2678 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
2679 {
2680 int ret;
2681 u32 reg;
2682 u8 val;
2683
2684 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2685 if (ret)
2686 return ret;
2687
2688 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx);
2689
2690 ret = read_poll_timeout(rtw89_read8, val,
2691 (val & B_AX_PTCL_TX_ON_STAT) == 0,
2692 SW_CVR_DUR_US,
2693 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT,
2694 false, rtwdev, reg);
2695 if (ret)
2696 return ret;
2697
2698 return 0;
2699 }
2700
band1_enable(struct rtw89_dev * rtwdev)2701 static int band1_enable(struct rtw89_dev *rtwdev)
2702 {
2703 int ret, i;
2704 u32 sleep_bak[4] = {0};
2705 u32 pause_bak[4] = {0};
2706 u32 tx_en;
2707
2708 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
2709 if (ret) {
2710 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
2711 return ret;
2712 }
2713
2714 for (i = 0; i < 4; i++) {
2715 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
2716 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
2717 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
2718 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
2719 }
2720
2721 ret = band_idle_ck_b(rtwdev, 0);
2722 if (ret) {
2723 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
2724 return ret;
2725 }
2726
2727 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
2728 if (ret) {
2729 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2730 return ret;
2731 }
2732
2733 for (i = 0; i < 4; i++) {
2734 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
2735 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
2736 }
2737
2738 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
2739 if (ret) {
2740 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
2741 return ret;
2742 }
2743
2744 ret = cmac_func_en(rtwdev, 1, true);
2745 if (ret) {
2746 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
2747 return ret;
2748 }
2749
2750 ret = cmac_init(rtwdev, 1);
2751 if (ret) {
2752 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
2753 return ret;
2754 }
2755
2756 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
2757 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1);
2758
2759 return 0;
2760 }
2761
rtw89_wdrls_imr_enable(struct rtw89_dev * rtwdev)2762 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
2763 {
2764 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2765
2766 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
2767 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
2768 }
2769
rtw89_wsec_imr_enable(struct rtw89_dev * rtwdev)2770 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
2771 {
2772 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2773
2774 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
2775 }
2776
rtw89_mpdu_trx_imr_enable(struct rtw89_dev * rtwdev)2777 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
2778 {
2779 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2780 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2781
2782 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2783 B_AX_TX_GET_ERRPKTID_INT_EN |
2784 B_AX_TX_NXT_ERRPKTID_INT_EN |
2785 B_AX_TX_MPDU_SIZE_ZERO_INT_EN |
2786 B_AX_TX_OFFSET_ERR_INT_EN |
2787 B_AX_TX_HDR3_SIZE_ERR_INT_EN);
2788 if (chip_id == RTL8852C)
2789 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2790 B_AX_TX_ETH_TYPE_ERR_EN |
2791 B_AX_TX_LLC_PRE_ERR_EN |
2792 B_AX_TX_NW_TYPE_ERR_EN |
2793 B_AX_TX_KSRCH_ERR_EN);
2794 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2795 imr->mpdu_tx_imr_set);
2796
2797 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
2798 B_AX_GETPKTID_ERR_INT_EN |
2799 B_AX_MHDRLEN_ERR_INT_EN |
2800 B_AX_RPT_ERR_INT_EN);
2801 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
2802 imr->mpdu_rx_imr_set);
2803 }
2804
rtw89_sta_sch_imr_enable(struct rtw89_dev * rtwdev)2805 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
2806 {
2807 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2808
2809 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
2810 B_AX_SEARCH_HANG_TIMEOUT_INT_EN |
2811 B_AX_RPT_HANG_TIMEOUT_INT_EN |
2812 B_AX_PLE_B_PKTID_ERR_INT_EN);
2813 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
2814 imr->sta_sch_imr_set);
2815 }
2816
rtw89_txpktctl_imr_enable(struct rtw89_dev * rtwdev)2817 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
2818 {
2819 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2820
2821 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
2822 imr->txpktctl_imr_b0_clr);
2823 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
2824 imr->txpktctl_imr_b0_set);
2825 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
2826 imr->txpktctl_imr_b1_clr);
2827 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
2828 imr->txpktctl_imr_b1_set);
2829 }
2830
rtw89_wde_imr_enable(struct rtw89_dev * rtwdev)2831 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
2832 {
2833 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2834
2835 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
2836 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
2837 }
2838
rtw89_ple_imr_enable(struct rtw89_dev * rtwdev)2839 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
2840 {
2841 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2842
2843 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
2844 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
2845 }
2846
rtw89_pktin_imr_enable(struct rtw89_dev * rtwdev)2847 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
2848 {
2849 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
2850 B_AX_PKTIN_GETPKTID_ERR_INT_EN);
2851 }
2852
rtw89_dispatcher_imr_enable(struct rtw89_dev * rtwdev)2853 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
2854 {
2855 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2856
2857 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
2858 imr->host_disp_imr_clr);
2859 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
2860 imr->host_disp_imr_set);
2861 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
2862 imr->cpu_disp_imr_clr);
2863 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
2864 imr->cpu_disp_imr_set);
2865 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
2866 imr->other_disp_imr_clr);
2867 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
2868 imr->other_disp_imr_set);
2869 }
2870
rtw89_cpuio_imr_enable(struct rtw89_dev * rtwdev)2871 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
2872 {
2873 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
2874 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
2875 }
2876
rtw89_bbrpt_imr_enable(struct rtw89_dev * rtwdev)2877 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
2878 {
2879 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2880
2881 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
2882 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
2883 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
2884 B_AX_BBRPT_CHINFO_IMR_CLR);
2885 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
2886 imr->bbrpt_err_imr_set);
2887 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
2888 B_AX_BBRPT_DFS_TO_ERR_INT_EN);
2889 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
2890 }
2891
rtw89_scheduler_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2892 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2893 {
2894 u32 reg;
2895
2896 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx);
2897 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
2898 B_AX_FSM_TIMEOUT_ERR_INT_EN);
2899 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
2900 }
2901
rtw89_ptcl_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2902 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2903 {
2904 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2905 u32 reg;
2906
2907 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx);
2908 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
2909 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
2910 }
2911
rtw89_cdma_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2912 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2913 {
2914 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2915 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2916 u32 reg;
2917
2918 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx);
2919 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
2920 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
2921
2922 if (chip_id == RTL8852C) {
2923 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx);
2924 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
2925 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
2926 }
2927 }
2928
rtw89_phy_intf_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2929 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2930 {
2931 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2932 u32 reg;
2933
2934 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx);
2935 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
2936 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
2937 }
2938
rtw89_rmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2939 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2940 {
2941 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2942 u32 reg;
2943
2944 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx);
2945 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
2946 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
2947 }
2948
rtw89_tmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2949 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2950 {
2951 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2952 u32 reg;
2953
2954 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx);
2955 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
2956 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
2957 }
2958
rtw89_mac_enable_imr(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)2959 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
2960 enum rtw89_mac_hwmod_sel sel)
2961 {
2962 int ret;
2963
2964 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
2965 if (ret) {
2966 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
2967 sel, mac_idx);
2968 return ret;
2969 }
2970
2971 if (sel == RTW89_DMAC_SEL) {
2972 rtw89_wdrls_imr_enable(rtwdev);
2973 rtw89_wsec_imr_enable(rtwdev);
2974 rtw89_mpdu_trx_imr_enable(rtwdev);
2975 rtw89_sta_sch_imr_enable(rtwdev);
2976 rtw89_txpktctl_imr_enable(rtwdev);
2977 rtw89_wde_imr_enable(rtwdev);
2978 rtw89_ple_imr_enable(rtwdev);
2979 rtw89_pktin_imr_enable(rtwdev);
2980 rtw89_dispatcher_imr_enable(rtwdev);
2981 rtw89_cpuio_imr_enable(rtwdev);
2982 rtw89_bbrpt_imr_enable(rtwdev);
2983 } else if (sel == RTW89_CMAC_SEL) {
2984 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
2985 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
2986 rtw89_cdma_imr_enable(rtwdev, mac_idx);
2987 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
2988 rtw89_rmac_imr_enable(rtwdev, mac_idx);
2989 rtw89_tmac_imr_enable(rtwdev, mac_idx);
2990 } else {
2991 return -EINVAL;
2992 }
2993
2994 return 0;
2995 }
2996
rtw89_mac_err_imr_ctrl(struct rtw89_dev * rtwdev,bool en)2997 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en)
2998 {
2999 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3000
3001 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3002 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS);
3003 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3004 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS);
3005 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)
3006 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3007 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS);
3008 }
3009
rtw89_mac_dbcc_enable(struct rtw89_dev * rtwdev,bool enable)3010 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)
3011 {
3012 int ret = 0;
3013
3014 if (enable) {
3015 ret = band1_enable(rtwdev);
3016 if (ret) {
3017 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3018 return ret;
3019 }
3020
3021 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3022 if (ret) {
3023 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3024 return ret;
3025 }
3026 } else {
3027 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3028 return -EINVAL;
3029 }
3030
3031 return 0;
3032 }
3033
set_host_rpr(struct rtw89_dev * rtwdev)3034 static int set_host_rpr(struct rtw89_dev *rtwdev)
3035 {
3036 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3037 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3038 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH);
3039 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3040 B_AX_RLSRPT0_FLTR_MAP_MASK);
3041 } else {
3042 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3043 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF);
3044 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3045 B_AX_RLSRPT0_FLTR_MAP_MASK);
3046 }
3047
3048 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3049 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3050
3051 return 0;
3052 }
3053
rtw89_mac_trx_init(struct rtw89_dev * rtwdev)3054 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)
3055 {
3056 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3057 int ret;
3058
3059 ret = dmac_init(rtwdev, 0);
3060 if (ret) {
3061 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3062 return ret;
3063 }
3064
3065 ret = cmac_init(rtwdev, 0);
3066 if (ret) {
3067 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3068 return ret;
3069 }
3070
3071 if (is_qta_dbcc(rtwdev, qta_mode)) {
3072 ret = rtw89_mac_dbcc_enable(rtwdev, true);
3073 if (ret) {
3074 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3075 return ret;
3076 }
3077 }
3078
3079 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3080 if (ret) {
3081 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3082 return ret;
3083 }
3084
3085 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3086 if (ret) {
3087 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3088 return ret;
3089 }
3090
3091 rtw89_mac_err_imr_ctrl(rtwdev, true);
3092
3093 ret = set_host_rpr(rtwdev);
3094 if (ret) {
3095 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3096 return ret;
3097 }
3098
3099 return 0;
3100 }
3101
rtw89_disable_fw_watchdog(struct rtw89_dev * rtwdev)3102 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3103 {
3104 u32 val32;
3105
3106 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3107 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL);
3108
3109 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3110 val32 |= B_AX_FS_WDT_INT;
3111 val32 &= ~B_AX_FS_WDT_INT_MSK;
3112 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3113 }
3114
rtw89_mac_disable_cpu(struct rtw89_dev * rtwdev)3115 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
3116 {
3117 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3118
3119 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3120 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3121 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3122 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3123
3124 rtw89_disable_fw_watchdog(rtwdev);
3125
3126 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3127 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3128 }
3129
rtw89_mac_enable_cpu(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw)3130 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason,
3131 bool dlfw)
3132 {
3133 u32 val;
3134 int ret;
3135
3136 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3137 return -EFAULT;
3138
3139 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3140 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3141 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3142 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3143
3144 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3145
3146 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3147 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3148 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE,
3149 B_AX_WCPU_FWDL_STS_MASK);
3150
3151 if (dlfw)
3152 val |= B_AX_WCPU_FWDL_EN;
3153
3154 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3155 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3156 boot_reason);
3157 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3158
3159 if (!dlfw) {
3160 mdelay(5);
3161
3162 ret = rtw89_fw_check_rdy(rtwdev);
3163 if (ret)
3164 return ret;
3165 }
3166
3167 return 0;
3168 }
3169
rtw89_mac_dmac_pre_init(struct rtw89_dev * rtwdev)3170 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3171 {
3172 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3173 u32 val;
3174 int ret;
3175
3176 if (chip_id == RTL8852C)
3177 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3178 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN;
3179 else
3180 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3181 B_AX_PKT_BUF_EN;
3182 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3183
3184 val = B_AX_DISPATCHER_CLK_EN;
3185 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3186
3187 if (chip_id != RTL8852C)
3188 goto dle;
3189
3190 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3191 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
3192 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
3193 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1;
3194 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3195
3196 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3197 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 |
3198 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 |
3199 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 |
3200 B_AX_STOP_CH12 | B_AX_STOP_ACH2);
3201 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3202 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3203
3204 dle:
3205 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3206 if (ret) {
3207 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3208 return ret;
3209 }
3210
3211 ret = hfc_init(rtwdev, true, false, true);
3212 if (ret) {
3213 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3214 return ret;
3215 }
3216
3217 return ret;
3218 }
3219
rtw89_mac_enable_bb_rf(struct rtw89_dev * rtwdev)3220 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3221 {
3222 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3223 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3224 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3225 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3226 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3227 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3228
3229 return 0;
3230 }
3231 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);
3232
rtw89_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3233 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3234 {
3235 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3236 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3237 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3238 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3239 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3240 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3241
3242 return 0;
3243 }
3244 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);
3245
rtw89_mac_partial_init(struct rtw89_dev * rtwdev)3246 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
3247 {
3248 int ret;
3249
3250 ret = rtw89_mac_power_switch(rtwdev, true);
3251 if (ret) {
3252 rtw89_mac_power_switch(rtwdev, false);
3253 ret = rtw89_mac_power_switch(rtwdev, true);
3254 if (ret)
3255 return ret;
3256 }
3257
3258 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
3259
3260 ret = rtw89_mac_dmac_pre_init(rtwdev);
3261 if (ret)
3262 return ret;
3263
3264 if (rtwdev->hci.ops->mac_pre_init) {
3265 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3266 if (ret)
3267 return ret;
3268 }
3269
3270 rtw89_mac_disable_cpu(rtwdev);
3271 ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
3272 if (ret)
3273 return ret;
3274
3275 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
3276 if (ret)
3277 return ret;
3278
3279 return 0;
3280 }
3281
rtw89_mac_init(struct rtw89_dev * rtwdev)3282 int rtw89_mac_init(struct rtw89_dev *rtwdev)
3283 {
3284 int ret;
3285
3286 ret = rtw89_mac_partial_init(rtwdev);
3287 if (ret)
3288 goto fail;
3289
3290 ret = rtw89_chip_enable_bb_rf(rtwdev);
3291 if (ret)
3292 goto fail;
3293
3294 ret = rtw89_mac_sys_init(rtwdev);
3295 if (ret)
3296 goto fail;
3297
3298 ret = rtw89_mac_trx_init(rtwdev);
3299 if (ret)
3300 goto fail;
3301
3302 if (rtwdev->hci.ops->mac_post_init) {
3303 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3304 if (ret)
3305 goto fail;
3306 }
3307
3308 rtw89_fw_send_all_early_h2c(rtwdev);
3309 rtw89_fw_h2c_set_ofld_cfg(rtwdev);
3310
3311 return ret;
3312 fail:
3313 rtw89_mac_power_switch(rtwdev, false);
3314
3315 return ret;
3316 }
3317
rtw89_mac_dmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)3318 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3319 {
3320 u8 i;
3321
3322 for (i = 0; i < 4; i++) {
3323 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3324 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2));
3325 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
3326 }
3327 }
3328
rtw89_mac_cmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)3329 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3330 {
3331 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3332 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE);
3333 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
3334 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
3335 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
3336 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
3337 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
3338 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
3339 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
3340 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
3341 }
3342
rtw89_mac_set_macid_pause(struct rtw89_dev * rtwdev,u8 macid,bool pause)3343 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
3344 {
3345 u8 sh = FIELD_GET(GENMASK(4, 0), macid);
3346 u8 grp = macid >> 5;
3347 int ret;
3348
3349 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3350 if (ret)
3351 return ret;
3352
3353 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
3354
3355 return 0;
3356 }
3357
3358 static const struct rtw89_port_reg rtw_port_base = {
3359 .port_cfg = R_AX_PORT_CFG_P0,
3360 .tbtt_prohib = R_AX_TBTT_PROHIB_P0,
3361 .bcn_area = R_AX_BCN_AREA_P0,
3362 .bcn_early = R_AX_BCNERLYINT_CFG_P0,
3363 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0,
3364 .tbtt_agg = R_AX_TBTT_AGG_P0,
3365 .bcn_space = R_AX_BCN_SPACE_CFG_P0,
3366 .bcn_forcetx = R_AX_BCN_FORCETX_P0,
3367 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0,
3368 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0,
3369 .dtim_ctrl = R_AX_DTIM_CTRL_P0,
3370 .tbtt_shift = R_AX_TBTT_SHIFT_P0,
3371 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0,
3372 .tsftr_l = R_AX_TSFTR_LOW_P0,
3373 .tsftr_h = R_AX_TSFTR_HIGH_P0
3374 };
3375
3376 #define BCN_INTERVAL 100
3377 #define BCN_ERLY_DEF 160
3378 #define BCN_SETUP_DEF 2
3379 #define BCN_HOLD_DEF 200
3380 #define BCN_MASK_DEF 0
3381 #define TBTT_ERLY_DEF 5
3382 #define BCN_SET_UNIT 32
3383 #define BCN_ERLY_SET_DLY (10 * 2)
3384
rtw89_mac_port_cfg_func_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3385 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
3386 struct rtw89_vif *rtwvif)
3387 {
3388 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3389 const struct rtw89_port_reg *p = &rtw_port_base;
3390
3391 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
3392 return;
3393
3394 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
3395 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
3396 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
3397 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
3398
3399 msleep(vif->bss_conf.beacon_int + 1);
3400
3401 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
3402 B_AX_BRK_SETUP);
3403 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
3404 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
3405 }
3406
rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)3407 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
3408 struct rtw89_vif *rtwvif, bool en)
3409 {
3410 const struct rtw89_port_reg *p = &rtw_port_base;
3411
3412 if (en)
3413 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3414 else
3415 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3416 }
3417
rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)3418 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
3419 struct rtw89_vif *rtwvif, bool en)
3420 {
3421 const struct rtw89_port_reg *p = &rtw_port_base;
3422
3423 if (en)
3424 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3425 else
3426 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3427 }
3428
rtw89_mac_port_cfg_net_type(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3429 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
3430 struct rtw89_vif *rtwvif)
3431 {
3432 const struct rtw89_port_reg *p = &rtw_port_base;
3433
3434 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
3435 rtwvif->net_type);
3436 }
3437
rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3438 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
3439 struct rtw89_vif *rtwvif)
3440 {
3441 const struct rtw89_port_reg *p = &rtw_port_base;
3442 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK;
3443 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP;
3444
3445 if (en)
3446 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
3447 else
3448 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
3449 }
3450
rtw89_mac_port_cfg_rx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3451 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
3452 struct rtw89_vif *rtwvif)
3453 {
3454 const struct rtw89_port_reg *p = &rtw_port_base;
3455 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3456 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3457 u32 bit = B_AX_RX_BSSID_FIT_EN;
3458
3459 if (en)
3460 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
3461 else
3462 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
3463 }
3464
rtw89_mac_port_cfg_rx_sync(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3465 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
3466 struct rtw89_vif *rtwvif)
3467 {
3468 const struct rtw89_port_reg *p = &rtw_port_base;
3469 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3470 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3471
3472 if (en)
3473 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3474 else
3475 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3476 }
3477
rtw89_mac_port_cfg_tx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3478 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
3479 struct rtw89_vif *rtwvif)
3480 {
3481 const struct rtw89_port_reg *p = &rtw_port_base;
3482 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ||
3483 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3484
3485 if (en)
3486 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3487 else
3488 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3489 }
3490
rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3491 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
3492 struct rtw89_vif *rtwvif)
3493 {
3494 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3495 const struct rtw89_port_reg *p = &rtw_port_base;
3496 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL;
3497
3498 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
3499 bcn_int);
3500 }
3501
rtw89_mac_port_cfg_hiq_win(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3502 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
3503 struct rtw89_vif *rtwvif)
3504 {
3505 static const u32 hiq_win_addr[RTW89_PORT_NUM] = {
3506 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG,
3507 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2,
3508 R_AX_PORT_HGQ_WINDOW_CFG + 3,
3509 };
3510 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
3511 u8 port = rtwvif->port;
3512 u32 reg;
3513
3514 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx);
3515 rtw89_write8(rtwdev, reg, win);
3516 }
3517
rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3518 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
3519 struct rtw89_vif *rtwvif)
3520 {
3521 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3522 const struct rtw89_port_reg *p = &rtw_port_base;
3523 u32 addr;
3524
3525 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
3526 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
3527
3528 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
3529 vif->bss_conf.dtim_period);
3530 }
3531
rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3532 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
3533 struct rtw89_vif *rtwvif)
3534 {
3535 const struct rtw89_port_reg *p = &rtw_port_base;
3536
3537 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3538 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF);
3539 }
3540
rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3541 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
3542 struct rtw89_vif *rtwvif)
3543 {
3544 const struct rtw89_port_reg *p = &rtw_port_base;
3545
3546 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3547 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF);
3548 }
3549
rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3550 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
3551 struct rtw89_vif *rtwvif)
3552 {
3553 const struct rtw89_port_reg *p = &rtw_port_base;
3554
3555 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
3556 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF);
3557 }
3558
rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3559 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
3560 struct rtw89_vif *rtwvif)
3561 {
3562 const struct rtw89_port_reg *p = &rtw_port_base;
3563
3564 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
3565 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF);
3566 }
3567
rtw89_mac_port_cfg_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3568 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
3569 struct rtw89_vif *rtwvif)
3570 {
3571 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3572 static const u32 masks[RTW89_PORT_NUM] = {
3573 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK,
3574 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK,
3575 B_AX_BSS_COLOB_AX_PORT_4_MASK,
3576 };
3577 u8 port = rtwvif->port;
3578 u32 reg_base;
3579 u32 reg;
3580 u8 bss_color;
3581
3582 bss_color = vif->bss_conf.he_bss_color.color;
3583 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0;
3584 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx);
3585 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
3586 }
3587
rtw89_mac_port_cfg_mbssid(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3588 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
3589 struct rtw89_vif *rtwvif)
3590 {
3591 u8 port = rtwvif->port;
3592 u32 reg;
3593
3594 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
3595 return;
3596
3597 if (port == 0) {
3598 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx);
3599 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
3600 }
3601 }
3602
rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3603 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
3604 struct rtw89_vif *rtwvif)
3605 {
3606 u8 port = rtwvif->port;
3607 u32 reg;
3608 u32 val;
3609
3610 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx);
3611 val = rtw89_read32(rtwdev, reg);
3612 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));
3613 if (port == 0)
3614 val &= ~BIT(0);
3615 rtw89_write32(rtwdev, reg, val);
3616 }
3617
rtw89_mac_port_cfg_func_en(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3618 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
3619 struct rtw89_vif *rtwvif)
3620 {
3621 const struct rtw89_port_reg *p = &rtw_port_base;
3622
3623 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN);
3624 }
3625
rtw89_mac_port_cfg_bcn_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3626 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
3627 struct rtw89_vif *rtwvif)
3628 {
3629 const struct rtw89_port_reg *p = &rtw_port_base;
3630
3631 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
3632 BCN_ERLY_DEF);
3633 }
3634
rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3635 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
3636 struct rtw89_vif *rtwvif)
3637 {
3638 const struct rtw89_port_reg *p = &rtw_port_base;
3639 u16 val;
3640
3641 if (rtwdev->chip->chip_id != RTL8852C)
3642 return;
3643
3644 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT &&
3645 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
3646 return;
3647
3648 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) |
3649 B_AX_TBTT_SHIFT_OFST_SIGN;
3650
3651 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
3652 B_AX_TBTT_SHIFT_OFST_MASK, val);
3653 }
3654
rtw89_mac_vif_init(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3655 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3656 {
3657 int ret;
3658
3659 ret = rtw89_mac_port_update(rtwdev, rtwvif);
3660 if (ret)
3661 return ret;
3662
3663 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
3664 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
3665
3666 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
3667 if (ret)
3668 return ret;
3669
3670 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);
3671 if (ret)
3672 return ret;
3673
3674 ret = rtw89_cam_init(rtwdev, rtwvif);
3675 if (ret)
3676 return ret;
3677
3678 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3679 if (ret)
3680 return ret;
3681
3682 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif);
3683 if (ret)
3684 return ret;
3685
3686 return 0;
3687 }
3688
rtw89_mac_vif_deinit(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3689 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3690 {
3691 int ret;
3692
3693 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);
3694 if (ret)
3695 return ret;
3696
3697 rtw89_cam_deinit(rtwdev, rtwvif);
3698
3699 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3700 if (ret)
3701 return ret;
3702
3703 return 0;
3704 }
3705
rtw89_mac_port_update(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3706 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3707 {
3708 u8 port = rtwvif->port;
3709
3710 if (port >= RTW89_PORT_NUM)
3711 return -EINVAL;
3712
3713 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
3714 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);
3715 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);
3716 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);
3717 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);
3718 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);
3719 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);
3720 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif);
3721 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
3722 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
3723 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
3724 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
3725 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
3726 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
3727 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
3728 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
3729 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
3730 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
3731 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
3732 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif);
3733 fsleep(BCN_ERLY_SET_DLY);
3734 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
3735
3736 return 0;
3737 }
3738
rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy * wiphy,struct cfg80211_bss * bss,void * data)3739 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy,
3740 struct cfg80211_bss *bss,
3741 void *data)
3742 {
3743 const struct cfg80211_bss_ies *ies;
3744 const struct element *elem;
3745 bool *tolerated = data;
3746
3747 rcu_read_lock();
3748 ies = rcu_dereference(bss->ies);
3749 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data,
3750 ies->len);
3751
3752 if (!elem || elem->datalen < 10 ||
3753 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
3754 *tolerated = false;
3755 rcu_read_unlock();
3756 }
3757
rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3758 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
3759 struct ieee80211_vif *vif)
3760 {
3761 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3762 struct ieee80211_hw *hw = rtwdev->hw;
3763 bool tolerated = true;
3764 u32 reg;
3765
3766 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION)
3767 return;
3768
3769 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR))
3770 return;
3771
3772 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef,
3773 rtw89_mac_check_he_obss_narrow_bw_ru_iter,
3774 &tolerated);
3775
3776 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);
3777 if (tolerated)
3778 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
3779 else
3780 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
3781 }
3782
rtw89_mac_add_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3783 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3784 {
3785 int ret;
3786
3787 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
3788 RTW89_MAX_MAC_ID_NUM);
3789 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM)
3790 return -ENOSPC;
3791
3792 ret = rtw89_mac_vif_init(rtwdev, rtwvif);
3793 if (ret)
3794 goto release_mac_id;
3795
3796 return 0;
3797
3798 release_mac_id:
3799 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
3800
3801 return ret;
3802 }
3803
rtw89_mac_remove_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3804 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3805 {
3806 int ret;
3807
3808 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);
3809 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
3810
3811 return ret;
3812 }
3813
3814 static void
rtw89_mac_c2h_macid_pause(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3815 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3816 {
3817 }
3818
rtw89_is_op_chan(struct rtw89_dev * rtwdev,u8 band,u8 channel)3819 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
3820 {
3821 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
3822
3823 return band == scan_info->op_band && channel == scan_info->op_pri_ch;
3824 }
3825
3826 static void
rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3827 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3828 u32 len)
3829 {
3830 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
3831 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
3832 struct rtw89_chan new;
3833 u8 reason, status, tx_fail, band, actual_period;
3834 u32 last_chan = rtwdev->scan_info.last_chan_idx;
3835 u16 chan;
3836 int ret;
3837
3838 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data);
3839 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data);
3840 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data);
3841 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data);
3842 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data);
3843 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data);
3844
3845 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
3846 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
3847
3848 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
3849 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n",
3850 band, chan, reason, status, tx_fail, actual_period);
3851
3852 switch (reason) {
3853 case RTW89_SCAN_LEAVE_CH_NOTIFY:
3854 if (rtw89_is_op_chan(rtwdev, band, chan))
3855 ieee80211_stop_queues(rtwdev->hw);
3856 return;
3857 case RTW89_SCAN_END_SCAN_NOTIFY:
3858 if (rtwvif && rtwvif->scan_req &&
3859 last_chan < rtwvif->scan_req->n_channels) {
3860 ret = rtw89_hw_scan_offload(rtwdev, vif, true);
3861 if (ret) {
3862 rtw89_hw_scan_abort(rtwdev, vif);
3863 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
3864 }
3865 } else {
3866 rtw89_hw_scan_complete(rtwdev, vif, false);
3867 }
3868 break;
3869 case RTW89_SCAN_ENTER_CH_NOTIFY:
3870 rtw89_chan_create(&new, chan, chan, band, RTW89_CHANNEL_WIDTH_20);
3871 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new);
3872 if (rtw89_is_op_chan(rtwdev, band, chan)) {
3873 rtw89_store_op_chan(rtwdev, false);
3874 ieee80211_wake_queues(rtwdev->hw);
3875 }
3876 break;
3877 default:
3878 return;
3879 }
3880 }
3881
3882 static void
rtw89_mac_c2h_rec_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3883 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3884 {
3885 rtw89_debug(rtwdev, RTW89_DBG_FW,
3886 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n",
3887 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
3888 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
3889 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
3890 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
3891 }
3892
3893 static void
rtw89_mac_c2h_done_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3894 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3895 {
3896 rtw89_debug(rtwdev, RTW89_DBG_FW,
3897 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n",
3898 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data),
3899 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data),
3900 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data),
3901 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data),
3902 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data));
3903 }
3904
3905 static void
rtw89_mac_c2h_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3906 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3907 {
3908 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len),
3909 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data));
3910 }
3911
3912 static void
rtw89_mac_c2h_bcn_cnt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3913 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3914 {
3915 }
3916
3917 static void
rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3918 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3919 u32 len)
3920 {
3921 }
3922
3923 static void
rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3924 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3925 u32 len)
3926 {
3927 }
3928
3929 static
3930 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
3931 struct sk_buff *c2h, u32 len) = {
3932 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL,
3933 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL,
3934 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp,
3935 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL,
3936 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause,
3937 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp,
3938 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt,
3939 };
3940
3941 static
3942 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
3943 struct sk_buff *c2h, u32 len) = {
3944 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack,
3945 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack,
3946 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log,
3947 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt,
3948 };
3949
rtw89_mac_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3950 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3951 u32 len, u8 class, u8 func)
3952 {
3953 void (*handler)(struct rtw89_dev *rtwdev,
3954 struct sk_buff *c2h, u32 len) = NULL;
3955
3956 switch (class) {
3957 case RTW89_MAC_C2H_CLASS_INFO:
3958 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX)
3959 handler = rtw89_mac_c2h_info_handler[func];
3960 break;
3961 case RTW89_MAC_C2H_CLASS_OFLD:
3962 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX)
3963 handler = rtw89_mac_c2h_ofld_handler[func];
3964 break;
3965 case RTW89_MAC_C2H_CLASS_FWDBG:
3966 return;
3967 default:
3968 rtw89_info(rtwdev, "c2h class %d not support\n", class);
3969 return;
3970 }
3971 if (!handler) {
3972 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
3973 func);
3974 return;
3975 }
3976 handler(rtwdev, skb, len);
3977 }
3978
rtw89_mac_get_txpwr_cr(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)3979 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
3980 enum rtw89_phy_idx phy_idx,
3981 u32 reg_base, u32 *cr)
3982 {
3983 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;
3984 enum rtw89_qta_mode mode = dle_mem->mode;
3985 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx);
3986
3987 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {
3988 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
3989 addr);
3990 goto error;
3991 }
3992
3993 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR)
3994 if (mode == RTW89_QTA_SCC) {
3995 rtw89_err(rtwdev,
3996 "[TXPWR] addr=0x%x but hw not enable\n",
3997 addr);
3998 goto error;
3999 }
4000
4001 *cr = addr;
4002 return true;
4003
4004 error:
4005 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
4006 addr, phy_idx);
4007
4008 return false;
4009 }
4010 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);
4011
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)4012 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
4013 {
4014 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx);
4015 int ret = 0;
4016
4017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4018 if (ret)
4019 return ret;
4020
4021 if (!enable) {
4022 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
4023 return ret;
4024 }
4025
4026 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
4027 B_AX_APP_MAC_INFO_RPT |
4028 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT |
4029 B_AX_PPDU_STAT_RPT_CRC32);
4030 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
4031 RTW89_PRPT_DEST_HOST);
4032
4033 return ret;
4034 }
4035 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status);
4036
rtw89_mac_update_rts_threshold(struct rtw89_dev * rtwdev,u8 mac_idx)4037 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
4038 {
4039 #define MAC_AX_TIME_TH_SH 5
4040 #define MAC_AX_LEN_TH_SH 4
4041 #define MAC_AX_TIME_TH_MAX 255
4042 #define MAC_AX_LEN_TH_MAX 255
4043 #define MAC_AX_TIME_TH_DEF 88
4044 #define MAC_AX_LEN_TH_DEF 4080
4045 struct ieee80211_hw *hw = rtwdev->hw;
4046 u32 rts_threshold = hw->wiphy->rts_threshold;
4047 u32 time_th, len_th;
4048 u32 reg;
4049
4050 if (rts_threshold == (u32)-1) {
4051 time_th = MAC_AX_TIME_TH_DEF;
4052 len_th = MAC_AX_LEN_TH_DEF;
4053 } else {
4054 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH;
4055 len_th = rts_threshold;
4056 }
4057
4058 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX);
4059 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX);
4060
4061 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx);
4062 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
4063 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
4064 }
4065
rtw89_mac_flush_txq(struct rtw89_dev * rtwdev,u32 queues,bool drop)4066 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
4067 {
4068 bool empty;
4069 int ret;
4070
4071 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4072 return;
4073
4074 ret = read_poll_timeout(dle_is_txq_empty, empty, empty,
4075 10000, 200000, false, rtwdev);
4076 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
4077 rtw89_info(rtwdev, "timed out to flush queues\n");
4078 }
4079
rtw89_mac_coex_init(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)4080 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
4081 {
4082 u8 val;
4083 u16 val16;
4084 u32 val32;
4085 int ret;
4086
4087 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
4088 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
4089 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
4090 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
4091 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
4092 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
4093
4094 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
4095 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN;
4096 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
4097
4098 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
4099 if (ret) {
4100 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
4101 return ret;
4102 }
4103 val32 = val32 & B_AX_WL_RX_CTRL;
4104 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
4105 if (ret) {
4106 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
4107 return ret;
4108 }
4109
4110 switch (coex->pta_mode) {
4111 case RTW89_MAC_AX_COEX_RTK_MODE:
4112 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4113 val &= ~B_AX_BTMODE_MASK;
4114 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3);
4115 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4116
4117 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
4118 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
4119
4120 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
4121 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK;
4122 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE);
4123 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
4124 break;
4125 case RTW89_MAC_AX_COEX_CSR_MODE:
4126 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4127 val &= ~B_AX_BTMODE_MASK;
4128 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2);
4129 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4130
4131 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
4132 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK;
4133 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO);
4134 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK;
4135 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO);
4136 val16 &= ~B_AX_BT_STAT_DELAY_MASK;
4137 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY);
4138 val16 |= B_AX_ENHANCED_BT;
4139 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
4140
4141 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
4142 break;
4143 default:
4144 return -EINVAL;
4145 }
4146
4147 switch (coex->direction) {
4148 case RTW89_MAC_AX_COEX_INNER:
4149 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4150 val = (val & ~BIT(2)) | BIT(1);
4151 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4152 break;
4153 case RTW89_MAC_AX_COEX_OUTPUT:
4154 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4155 val = val | BIT(1) | BIT(0);
4156 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4157 break;
4158 case RTW89_MAC_AX_COEX_INPUT:
4159 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4160 val = val & ~(BIT(2) | BIT(1));
4161 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4162 break;
4163 default:
4164 return -EINVAL;
4165 }
4166
4167 return 0;
4168 }
4169 EXPORT_SYMBOL(rtw89_mac_coex_init);
4170
rtw89_mac_coex_init_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)4171 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
4172 const struct rtw89_mac_ax_coex *coex)
4173 {
4174 rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
4175 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL);
4176 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
4177 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
4178 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
4179
4180 switch (coex->pta_mode) {
4181 case RTW89_MAC_AX_COEX_RTK_MODE:
4182 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4183 MAC_AX_RTK_MODE);
4184 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
4185 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE);
4186 break;
4187 case RTW89_MAC_AX_COEX_CSR_MODE:
4188 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4189 MAC_AX_CSR_MODE);
4190 break;
4191 default:
4192 return -EINVAL;
4193 }
4194
4195 return 0;
4196 }
4197 EXPORT_SYMBOL(rtw89_mac_coex_init_v1);
4198
rtw89_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)4199 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
4200 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4201 {
4202 u32 val = 0, ret;
4203
4204 if (gnt_cfg->band[0].gnt_bt)
4205 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL;
4206
4207 if (gnt_cfg->band[0].gnt_bt_sw_en)
4208 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL;
4209
4210 if (gnt_cfg->band[0].gnt_wl)
4211 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL;
4212
4213 if (gnt_cfg->band[0].gnt_wl_sw_en)
4214 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL;
4215
4216 if (gnt_cfg->band[1].gnt_bt)
4217 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL;
4218
4219 if (gnt_cfg->band[1].gnt_bt_sw_en)
4220 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL;
4221
4222 if (gnt_cfg->band[1].gnt_wl)
4223 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL;
4224
4225 if (gnt_cfg->band[1].gnt_wl_sw_en)
4226 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL;
4227
4228 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
4229 if (ret) {
4230 rtw89_err(rtwdev, "Write LTE fail!\n");
4231 return ret;
4232 }
4233
4234 return 0;
4235 }
4236 EXPORT_SYMBOL(rtw89_mac_cfg_gnt);
4237
rtw89_mac_cfg_gnt_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)4238 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
4239 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4240 {
4241 u32 val = 0;
4242
4243 if (gnt_cfg->band[0].gnt_bt)
4244 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL |
4245 B_AX_GNT_BT_TX_VAL;
4246 else
4247 val |= B_AX_WL_ACT_VAL;
4248
4249 if (gnt_cfg->band[0].gnt_bt_sw_en)
4250 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
4251 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
4252
4253 if (gnt_cfg->band[0].gnt_wl)
4254 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL |
4255 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
4256
4257 if (gnt_cfg->band[0].gnt_wl_sw_en)
4258 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
4259 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
4260
4261 if (gnt_cfg->band[1].gnt_bt)
4262 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL |
4263 B_AX_GNT_BT_TX_VAL;
4264 else
4265 val |= B_AX_WL_ACT_VAL;
4266
4267 if (gnt_cfg->band[1].gnt_bt_sw_en)
4268 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
4269 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
4270
4271 if (gnt_cfg->band[1].gnt_wl)
4272 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL |
4273 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
4274
4275 if (gnt_cfg->band[1].gnt_wl_sw_en)
4276 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
4277 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
4278
4279 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
4280
4281 return 0;
4282 }
4283 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1);
4284
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)4285 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
4286 {
4287 u32 reg;
4288 u16 val;
4289 int ret;
4290
4291 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
4292 if (ret)
4293 return ret;
4294
4295 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band);
4296 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
4297 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
4298 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
4299 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
4300 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
4301 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
4302 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
4303 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
4304 B_AX_PLT_EN;
4305 rtw89_write16(rtwdev, reg, val);
4306
4307 return 0;
4308 }
4309
rtw89_mac_cfg_sb(struct rtw89_dev * rtwdev,u32 val)4310 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
4311 {
4312 u32 fw_sb;
4313
4314 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
4315 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb);
4316 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY;
4317 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4318 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR;
4319 else
4320 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR;
4321 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val);
4322 val = B_AX_TOGGLE |
4323 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
4324 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb);
4325 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
4326 fsleep(1000); /* avoid BT FW loss information */
4327 }
4328
rtw89_mac_get_sb(struct rtw89_dev * rtwdev)4329 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
4330 {
4331 return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
4332 }
4333
rtw89_mac_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)4334 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
4335 {
4336 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
4337
4338 val = wl ? val | BIT(2) : val & ~BIT(2);
4339 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
4340
4341 return 0;
4342 }
4343 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path);
4344
rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev * rtwdev,bool wl)4345 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
4346 {
4347 struct rtw89_btc *btc = &rtwdev->btc;
4348 struct rtw89_btc_dm *dm = &btc->dm;
4349 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
4350 int i;
4351
4352 if (wl)
4353 return 0;
4354
4355 for (i = 0; i < RTW89_PHY_MAX; i++) {
4356 g[i].gnt_bt_sw_en = 1;
4357 g[i].gnt_bt = 1;
4358 g[i].gnt_wl_sw_en = 1;
4359 g[i].gnt_wl = 0;
4360 }
4361
4362 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
4363 }
4364 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1);
4365
rtw89_mac_get_ctrl_path(struct rtw89_dev * rtwdev)4366 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
4367 {
4368 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
4369
4370 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val);
4371 }
4372
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)4373 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
4374 {
4375 u32 reg;
4376 u16 cnt;
4377
4378 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band);
4379 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
4380 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
4381
4382 return cnt;
4383 }
4384
rtw89_mac_bfee_ctrl(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)4385 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
4386 {
4387 u32 reg;
4388 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
4389 B_AX_BFMEE_HE_NDPA_EN;
4390
4391 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
4392 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
4393 if (en) {
4394 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4395 rtw89_write32_set(rtwdev, reg, mask);
4396 } else {
4397 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4398 rtw89_write32_clr(rtwdev, reg, mask);
4399 }
4400 }
4401
rtw89_mac_init_bfee(struct rtw89_dev * rtwdev,u8 mac_idx)4402 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)
4403 {
4404 u32 reg;
4405 u32 val32;
4406 int ret;
4407
4408 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4409 if (ret)
4410 return ret;
4411
4412 /* AP mode set tx gid to 63 */
4413 /* STA mode set tx gid to 0(default) */
4414 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx);
4415 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
4416
4417 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
4418 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
4419
4420 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
4421 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER);
4422 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);
4423 rtw89_write32(rtwdev, reg, val32);
4424 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
4425
4426 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4427 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
4428 B_AX_BFMEE_USE_NSTS |
4429 B_AX_BFMEE_CSI_GID_SEL |
4430 B_AX_BFMEE_CSI_FORCE_RETE_EN);
4431 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
4432 rtw89_write32(rtwdev, reg,
4433 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) |
4434 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) |
4435 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK));
4436
4437 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx);
4438 rtw89_write32_set(rtwdev, reg,
4439 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN);
4440
4441 return 0;
4442 }
4443
rtw89_mac_set_csi_para_reg(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4444 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,
4445 struct ieee80211_vif *vif,
4446 struct ieee80211_sta *sta)
4447 {
4448 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4449 u8 mac_idx = rtwvif->mac_idx;
4450 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
4451 u8 port_sel = rtwvif->port;
4452 u8 sound_dim = 3, t;
4453 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info;
4454 u32 reg;
4455 u16 val;
4456 int ret;
4457
4458 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4459 if (ret)
4460 return ret;
4461
4462 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
4463 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
4464 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
4465 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
4466 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
4467 phy_cap[5]);
4468 sound_dim = min(sound_dim, t);
4469 }
4470 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
4471 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
4472 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
4473 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
4474 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
4475 sta->deflink.vht_cap.cap);
4476 sound_dim = min(sound_dim, t);
4477 }
4478 nc = min(nc, sound_dim);
4479 nr = min(nr, sound_dim);
4480
4481 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4482 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
4483
4484 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
4485 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) |
4486 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) |
4487 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) |
4488 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) |
4489 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) |
4490 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en);
4491
4492 if (port_sel == 0)
4493 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4494 else
4495 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
4496
4497 rtw89_write16(rtwdev, reg, val);
4498
4499 return 0;
4500 }
4501
rtw89_mac_csi_rrsc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4502 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,
4503 struct ieee80211_vif *vif,
4504 struct ieee80211_sta *sta)
4505 {
4506 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4507 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
4508 u32 reg;
4509 u8 mac_idx = rtwvif->mac_idx;
4510 int ret;
4511
4512 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4513 if (ret)
4514 return ret;
4515
4516 if (sta->deflink.he_cap.has_he) {
4517 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
4518 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
4519 BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
4520 }
4521 if (sta->deflink.vht_cap.vht_supported) {
4522 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
4523 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
4524 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
4525 }
4526 if (sta->deflink.ht_cap.ht_supported) {
4527 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
4528 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
4529 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
4530 }
4531 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4532 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
4533 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
4534 rtw89_write32(rtwdev,
4535 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
4536 rrsc);
4537
4538 return 0;
4539 }
4540
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4541 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4542 struct ieee80211_sta *sta)
4543 {
4544 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4545
4546 if (rtw89_sta_has_beamformer_cap(sta)) {
4547 rtw89_debug(rtwdev, RTW89_DBG_BF,
4548 "initialize bfee for new association\n");
4549 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx);
4550 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta);
4551 rtw89_mac_csi_rrsc(rtwdev, vif, sta);
4552 }
4553 }
4554
rtw89_mac_bf_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4555 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4556 struct ieee80211_sta *sta)
4557 {
4558 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4559
4560 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
4561 }
4562
rtw89_mac_bf_set_gid_table(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)4563 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4564 struct ieee80211_bss_conf *conf)
4565 {
4566 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4567 u8 mac_idx = rtwvif->mac_idx;
4568 __le32 *p;
4569
4570 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
4571
4572 p = (__le32 *)conf->mu_group.membership;
4573 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx),
4574 le32_to_cpu(p[0]));
4575 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx),
4576 le32_to_cpu(p[1]));
4577
4578 p = (__le32 *)conf->mu_group.position;
4579 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx),
4580 le32_to_cpu(p[0]));
4581 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx),
4582 le32_to_cpu(p[1]));
4583 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx),
4584 le32_to_cpu(p[2]));
4585 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx),
4586 le32_to_cpu(p[3]));
4587 }
4588
4589 struct rtw89_mac_bf_monitor_iter_data {
4590 struct rtw89_dev *rtwdev;
4591 struct ieee80211_sta *down_sta;
4592 int count;
4593 };
4594
4595 static
rtw89_mac_bf_monitor_calc_iter(void * data,struct ieee80211_sta * sta)4596 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta)
4597 {
4598 struct rtw89_mac_bf_monitor_iter_data *iter_data =
4599 (struct rtw89_mac_bf_monitor_iter_data *)data;
4600 struct ieee80211_sta *down_sta = iter_data->down_sta;
4601 int *count = &iter_data->count;
4602
4603 if (down_sta == sta)
4604 return;
4605
4606 if (rtw89_sta_has_beamformer_cap(sta))
4607 (*count)++;
4608 }
4609
rtw89_mac_bf_monitor_calc(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,bool disconnect)4610 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
4611 struct ieee80211_sta *sta, bool disconnect)
4612 {
4613 struct rtw89_mac_bf_monitor_iter_data data;
4614
4615 data.rtwdev = rtwdev;
4616 data.down_sta = disconnect ? sta : NULL;
4617 data.count = 0;
4618 ieee80211_iterate_stations_atomic(rtwdev->hw,
4619 rtw89_mac_bf_monitor_calc_iter,
4620 &data);
4621
4622 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
4623 if (data.count)
4624 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
4625 else
4626 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
4627 }
4628
_rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)4629 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
4630 {
4631 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4632 struct rtw89_vif *rtwvif;
4633 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
4634 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4635
4636 if (en == old)
4637 return;
4638
4639 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4640 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
4641 }
4642
4643 static int
__rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 tx_time)4644 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4645 u32 tx_time)
4646 {
4647 #define MAC_AX_DFLT_TX_TIME 5280
4648 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4649 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time;
4650 u32 reg;
4651 int ret = 0;
4652
4653 if (rtwsta->cctl_tx_time) {
4654 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9;
4655 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4656 } else {
4657 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4658 if (ret) {
4659 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
4660 return ret;
4661 }
4662
4663 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);
4664 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
4665 max_tx_time >> 5);
4666 }
4667
4668 return ret;
4669 }
4670
rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u32 tx_time)4671 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4672 bool resume, u32 tx_time)
4673 {
4674 int ret = 0;
4675
4676 if (!resume) {
4677 rtwsta->cctl_tx_time = true;
4678 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
4679 } else {
4680 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
4681 rtwsta->cctl_tx_time = false;
4682 }
4683
4684 return ret;
4685 }
4686
rtw89_mac_get_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 * tx_time)4687 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4688 u32 *tx_time)
4689 {
4690 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4691 u32 reg;
4692 int ret = 0;
4693
4694 if (rtwsta->cctl_tx_time) {
4695 *tx_time = (rtwsta->ampdu_max_time + 1) << 9;
4696 } else {
4697 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4698 if (ret) {
4699 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
4700 return ret;
4701 }
4702
4703 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);
4704 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
4705 }
4706
4707 return ret;
4708 }
4709
rtw89_mac_set_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u8 tx_retry)4710 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
4711 struct rtw89_sta *rtwsta,
4712 bool resume, u8 tx_retry)
4713 {
4714 int ret = 0;
4715
4716 rtwsta->data_tx_cnt_lmt = tx_retry;
4717
4718 if (!resume) {
4719 rtwsta->cctl_tx_retry_limit = true;
4720 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4721 } else {
4722 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4723 rtwsta->cctl_tx_retry_limit = false;
4724 }
4725
4726 return ret;
4727 }
4728
rtw89_mac_get_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 * tx_retry)4729 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
4730 struct rtw89_sta *rtwsta, u8 *tx_retry)
4731 {
4732 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4733 u32 reg;
4734 int ret = 0;
4735
4736 if (rtwsta->cctl_tx_retry_limit) {
4737 *tx_retry = rtwsta->data_tx_cnt_lmt;
4738 } else {
4739 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4740 if (ret) {
4741 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
4742 return ret;
4743 }
4744
4745 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx);
4746 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
4747 }
4748
4749 return ret;
4750 }
4751
rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4752 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
4753 struct rtw89_vif *rtwvif, bool en)
4754 {
4755 u8 mac_idx = rtwvif->mac_idx;
4756 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0;
4757 u32 reg;
4758 u32 ret;
4759
4760 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4761 if (ret)
4762 return ret;
4763
4764 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx);
4765 if (en)
4766 rtw89_write16_set(rtwdev, reg, set);
4767 else
4768 rtw89_write16_clr(rtwdev, reg, set);
4769
4770 return 0;
4771 }
4772
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)4773 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
4774 {
4775 u32 val32;
4776 int ret;
4777
4778 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
4779 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) |
4780 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) |
4781 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) |
4782 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
4783 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
4784
4785 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
4786 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
4787 if (ret) {
4788 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
4789 offset, val, mask);
4790 return ret;
4791 }
4792
4793 return 0;
4794 }
4795 EXPORT_SYMBOL(rtw89_mac_write_xtal_si);
4796
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)4797 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
4798 {
4799 u32 val32;
4800 int ret;
4801
4802 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
4803 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) |
4804 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) |
4805 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) |
4806 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
4807 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
4808
4809 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
4810 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
4811 if (ret) {
4812 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
4813 return ret;
4814 }
4815
4816 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
4817
4818 return 0;
4819 }
4820
4821 static
rtw89_mac_pkt_drop_sta(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta)4822 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
4823 {
4824 static const enum rtw89_pkt_drop_sel sels[] = {
4825 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4826 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4827 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4828 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4829 };
4830 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4831 struct rtw89_pkt_drop_params params = {0};
4832 int i;
4833
4834 params.mac_band = RTW89_MAC_0;
4835 params.macid = rtwsta->mac_id;
4836 params.port = rtwvif->port;
4837 params.mbssid = 0;
4838 params.tf_trs = rtwvif->trigger;
4839
4840 for (i = 0; i < ARRAY_SIZE(sels); i++) {
4841 params.sel = sels[i];
4842 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
4843 }
4844 }
4845
rtw89_mac_pkt_drop_vif_iter(void * data,struct ieee80211_sta * sta)4846 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta)
4847 {
4848 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
4849 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4850 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
4851 struct rtw89_vif *target = data;
4852
4853 if (rtwvif != target)
4854 return;
4855
4856 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);
4857 }
4858
rtw89_mac_pkt_drop_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4859 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4860 {
4861 ieee80211_iterate_stations_atomic(rtwdev->hw,
4862 rtw89_mac_pkt_drop_vif_iter,
4863 rtwvif);
4864 }
4865