1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 #include <linux/ip.h>
5 #include <linux/udp.h>
6 
7 #include "cam.h"
8 #include "chan.h"
9 #include "coex.h"
10 #include "core.h"
11 #include "efuse.h"
12 #include "fw.h"
13 #include "mac.h"
14 #include "phy.h"
15 #include "ps.h"
16 #include "reg.h"
17 #include "sar.h"
18 #include "ser.h"
19 #include "txrx.h"
20 #include "util.h"
21 
22 static bool rtw89_disable_ps_mode;
23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
25 
26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band)	\
27 	{ .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val)	\
29 	RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val)	\
31 	RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val)	\
33 	RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val)	\
35 	RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
36 
37 static struct ieee80211_channel rtw89_channels_2ghz[] = {
38 	RTW89_DEF_CHAN_2G(2412, 1),
39 	RTW89_DEF_CHAN_2G(2417, 2),
40 	RTW89_DEF_CHAN_2G(2422, 3),
41 	RTW89_DEF_CHAN_2G(2427, 4),
42 	RTW89_DEF_CHAN_2G(2432, 5),
43 	RTW89_DEF_CHAN_2G(2437, 6),
44 	RTW89_DEF_CHAN_2G(2442, 7),
45 	RTW89_DEF_CHAN_2G(2447, 8),
46 	RTW89_DEF_CHAN_2G(2452, 9),
47 	RTW89_DEF_CHAN_2G(2457, 10),
48 	RTW89_DEF_CHAN_2G(2462, 11),
49 	RTW89_DEF_CHAN_2G(2467, 12),
50 	RTW89_DEF_CHAN_2G(2472, 13),
51 	RTW89_DEF_CHAN_2G(2484, 14),
52 };
53 
54 static struct ieee80211_channel rtw89_channels_5ghz[] = {
55 	RTW89_DEF_CHAN_5G(5180, 36),
56 	RTW89_DEF_CHAN_5G(5200, 40),
57 	RTW89_DEF_CHAN_5G(5220, 44),
58 	RTW89_DEF_CHAN_5G(5240, 48),
59 	RTW89_DEF_CHAN_5G(5260, 52),
60 	RTW89_DEF_CHAN_5G(5280, 56),
61 	RTW89_DEF_CHAN_5G(5300, 60),
62 	RTW89_DEF_CHAN_5G(5320, 64),
63 	RTW89_DEF_CHAN_5G(5500, 100),
64 	RTW89_DEF_CHAN_5G(5520, 104),
65 	RTW89_DEF_CHAN_5G(5540, 108),
66 	RTW89_DEF_CHAN_5G(5560, 112),
67 	RTW89_DEF_CHAN_5G(5580, 116),
68 	RTW89_DEF_CHAN_5G(5600, 120),
69 	RTW89_DEF_CHAN_5G(5620, 124),
70 	RTW89_DEF_CHAN_5G(5640, 128),
71 	RTW89_DEF_CHAN_5G(5660, 132),
72 	RTW89_DEF_CHAN_5G(5680, 136),
73 	RTW89_DEF_CHAN_5G(5700, 140),
74 	RTW89_DEF_CHAN_5G(5720, 144),
75 	RTW89_DEF_CHAN_5G(5745, 149),
76 	RTW89_DEF_CHAN_5G(5765, 153),
77 	RTW89_DEF_CHAN_5G(5785, 157),
78 	RTW89_DEF_CHAN_5G(5805, 161),
79 	RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
80 };
81 
82 static struct ieee80211_channel rtw89_channels_6ghz[] = {
83 	RTW89_DEF_CHAN_6G(5955, 1),
84 	RTW89_DEF_CHAN_6G(5975, 5),
85 	RTW89_DEF_CHAN_6G(5995, 9),
86 	RTW89_DEF_CHAN_6G(6015, 13),
87 	RTW89_DEF_CHAN_6G(6035, 17),
88 	RTW89_DEF_CHAN_6G(6055, 21),
89 	RTW89_DEF_CHAN_6G(6075, 25),
90 	RTW89_DEF_CHAN_6G(6095, 29),
91 	RTW89_DEF_CHAN_6G(6115, 33),
92 	RTW89_DEF_CHAN_6G(6135, 37),
93 	RTW89_DEF_CHAN_6G(6155, 41),
94 	RTW89_DEF_CHAN_6G(6175, 45),
95 	RTW89_DEF_CHAN_6G(6195, 49),
96 	RTW89_DEF_CHAN_6G(6215, 53),
97 	RTW89_DEF_CHAN_6G(6235, 57),
98 	RTW89_DEF_CHAN_6G(6255, 61),
99 	RTW89_DEF_CHAN_6G(6275, 65),
100 	RTW89_DEF_CHAN_6G(6295, 69),
101 	RTW89_DEF_CHAN_6G(6315, 73),
102 	RTW89_DEF_CHAN_6G(6335, 77),
103 	RTW89_DEF_CHAN_6G(6355, 81),
104 	RTW89_DEF_CHAN_6G(6375, 85),
105 	RTW89_DEF_CHAN_6G(6395, 89),
106 	RTW89_DEF_CHAN_6G(6415, 93),
107 	RTW89_DEF_CHAN_6G(6435, 97),
108 	RTW89_DEF_CHAN_6G(6455, 101),
109 	RTW89_DEF_CHAN_6G(6475, 105),
110 	RTW89_DEF_CHAN_6G(6495, 109),
111 	RTW89_DEF_CHAN_6G(6515, 113),
112 	RTW89_DEF_CHAN_6G(6535, 117),
113 	RTW89_DEF_CHAN_6G(6555, 121),
114 	RTW89_DEF_CHAN_6G(6575, 125),
115 	RTW89_DEF_CHAN_6G(6595, 129),
116 	RTW89_DEF_CHAN_6G(6615, 133),
117 	RTW89_DEF_CHAN_6G(6635, 137),
118 	RTW89_DEF_CHAN_6G(6655, 141),
119 	RTW89_DEF_CHAN_6G(6675, 145),
120 	RTW89_DEF_CHAN_6G(6695, 149),
121 	RTW89_DEF_CHAN_6G(6715, 153),
122 	RTW89_DEF_CHAN_6G(6735, 157),
123 	RTW89_DEF_CHAN_6G(6755, 161),
124 	RTW89_DEF_CHAN_6G(6775, 165),
125 	RTW89_DEF_CHAN_6G(6795, 169),
126 	RTW89_DEF_CHAN_6G(6815, 173),
127 	RTW89_DEF_CHAN_6G(6835, 177),
128 	RTW89_DEF_CHAN_6G(6855, 181),
129 	RTW89_DEF_CHAN_6G(6875, 185),
130 	RTW89_DEF_CHAN_6G(6895, 189),
131 	RTW89_DEF_CHAN_6G(6915, 193),
132 	RTW89_DEF_CHAN_6G(6935, 197),
133 	RTW89_DEF_CHAN_6G(6955, 201),
134 	RTW89_DEF_CHAN_6G(6975, 205),
135 	RTW89_DEF_CHAN_6G(6995, 209),
136 	RTW89_DEF_CHAN_6G(7015, 213),
137 	RTW89_DEF_CHAN_6G(7035, 217),
138 	RTW89_DEF_CHAN_6G(7055, 221),
139 	RTW89_DEF_CHAN_6G(7075, 225),
140 	RTW89_DEF_CHAN_6G(7095, 229),
141 	RTW89_DEF_CHAN_6G(7115, 233),
142 };
143 
144 static struct ieee80211_rate rtw89_bitrates[] = {
145 	{ .bitrate = 10,  .hw_value = 0x00, },
146 	{ .bitrate = 20,  .hw_value = 0x01, },
147 	{ .bitrate = 55,  .hw_value = 0x02, },
148 	{ .bitrate = 110, .hw_value = 0x03, },
149 	{ .bitrate = 60,  .hw_value = 0x04, },
150 	{ .bitrate = 90,  .hw_value = 0x05, },
151 	{ .bitrate = 120, .hw_value = 0x06, },
152 	{ .bitrate = 180, .hw_value = 0x07, },
153 	{ .bitrate = 240, .hw_value = 0x08, },
154 	{ .bitrate = 360, .hw_value = 0x09, },
155 	{ .bitrate = 480, .hw_value = 0x0a, },
156 	{ .bitrate = 540, .hw_value = 0x0b, },
157 };
158 
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)159 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
160 {
161 	struct ieee80211_rate rate;
162 
163 	if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
164 		rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
165 		return false;
166 	}
167 
168 	rate = rtw89_bitrates[rpt_rate];
169 	*bitrate = rate.bitrate;
170 
171 	return true;
172 }
173 
174 static struct ieee80211_supported_band rtw89_sband_2ghz = {
175 	.band		= NL80211_BAND_2GHZ,
176 	.channels	= rtw89_channels_2ghz,
177 	.n_channels	= ARRAY_SIZE(rtw89_channels_2ghz),
178 	.bitrates	= rtw89_bitrates,
179 	.n_bitrates	= ARRAY_SIZE(rtw89_bitrates),
180 	.ht_cap		= {0},
181 	.vht_cap	= {0},
182 };
183 
184 static struct ieee80211_supported_band rtw89_sband_5ghz = {
185 	.band		= NL80211_BAND_5GHZ,
186 	.channels	= rtw89_channels_5ghz,
187 	.n_channels	= ARRAY_SIZE(rtw89_channels_5ghz),
188 
189 	/* 5G has no CCK rates, 1M/2M/5.5M/11M */
190 	.bitrates	= rtw89_bitrates + 4,
191 	.n_bitrates	= ARRAY_SIZE(rtw89_bitrates) - 4,
192 	.ht_cap		= {0},
193 	.vht_cap	= {0},
194 };
195 
196 static struct ieee80211_supported_band rtw89_sband_6ghz = {
197 	.band		= NL80211_BAND_6GHZ,
198 	.channels	= rtw89_channels_6ghz,
199 	.n_channels	= ARRAY_SIZE(rtw89_channels_6ghz),
200 
201 	/* 6G has no CCK rates, 1M/2M/5.5M/11M */
202 	.bitrates	= rtw89_bitrates + 4,
203 	.n_bitrates	= ARRAY_SIZE(rtw89_bitrates) - 4,
204 };
205 
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)206 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
207 				     struct rtw89_traffic_stats *stats,
208 				     struct sk_buff *skb, bool tx)
209 {
210 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
211 
212 	if (!ieee80211_is_data(hdr->frame_control))
213 		return;
214 
215 	if (is_broadcast_ether_addr(hdr->addr1) ||
216 	    is_multicast_ether_addr(hdr->addr1))
217 		return;
218 
219 	if (tx) {
220 		stats->tx_cnt++;
221 		stats->tx_unicast += skb->len;
222 	} else {
223 		stats->rx_cnt++;
224 		stats->rx_unicast += skb->len;
225 	}
226 }
227 
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)228 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
229 {
230 	cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
231 				NL80211_CHAN_NO_HT);
232 }
233 
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)234 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
235 				     struct rtw89_chan *chan)
236 {
237 	struct ieee80211_channel *channel = chandef->chan;
238 	enum nl80211_chan_width width = chandef->width;
239 	u32 primary_freq, center_freq;
240 	u8 center_chan;
241 	u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
242 	u32 offset;
243 	u8 band;
244 
245 	center_chan = channel->hw_value;
246 	primary_freq = channel->center_freq;
247 	center_freq = chandef->center_freq1;
248 
249 	switch (width) {
250 	case NL80211_CHAN_WIDTH_20_NOHT:
251 	case NL80211_CHAN_WIDTH_20:
252 		bandwidth = RTW89_CHANNEL_WIDTH_20;
253 		break;
254 	case NL80211_CHAN_WIDTH_40:
255 		bandwidth = RTW89_CHANNEL_WIDTH_40;
256 		if (primary_freq > center_freq) {
257 			center_chan -= 2;
258 		} else {
259 			center_chan += 2;
260 		}
261 		break;
262 	case NL80211_CHAN_WIDTH_80:
263 	case NL80211_CHAN_WIDTH_160:
264 		bandwidth = nl_to_rtw89_bandwidth(width);
265 		if (primary_freq > center_freq) {
266 			offset = (primary_freq - center_freq - 10) / 20;
267 			center_chan -= 2 + offset * 4;
268 		} else {
269 			offset = (center_freq - primary_freq - 10) / 20;
270 			center_chan += 2 + offset * 4;
271 		}
272 		break;
273 	default:
274 		center_chan = 0;
275 		break;
276 	}
277 
278 	switch (channel->band) {
279 	default:
280 	case NL80211_BAND_2GHZ:
281 		band = RTW89_BAND_2G;
282 		break;
283 	case NL80211_BAND_5GHZ:
284 		band = RTW89_BAND_5G;
285 		break;
286 	case NL80211_BAND_6GHZ:
287 		band = RTW89_BAND_6G;
288 		break;
289 	}
290 
291 	rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
292 }
293 
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)294 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
295 {
296 	const struct rtw89_chip_info *chip = rtwdev->chip;
297 	const struct rtw89_chan *chan;
298 	enum rtw89_sub_entity_idx sub_entity_idx;
299 	enum rtw89_phy_idx phy_idx;
300 	enum rtw89_entity_mode mode;
301 	bool entity_active;
302 
303 	entity_active = rtw89_get_entity_state(rtwdev);
304 	if (!entity_active)
305 		return;
306 
307 	mode = rtw89_get_entity_mode(rtwdev);
308 	if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode))
309 		return;
310 
311 	sub_entity_idx = RTW89_SUB_ENTITY_0;
312 	phy_idx = RTW89_PHY_0;
313 	chan = rtw89_chan_get(rtwdev, sub_entity_idx);
314 	if (chip->ops->set_txpwr)
315 		chip->ops->set_txpwr(rtwdev, chan, phy_idx);
316 }
317 
rtw89_set_channel(struct rtw89_dev * rtwdev)318 void rtw89_set_channel(struct rtw89_dev *rtwdev)
319 {
320 	const struct rtw89_chip_info *chip = rtwdev->chip;
321 	const struct cfg80211_chan_def *chandef;
322 	enum rtw89_sub_entity_idx sub_entity_idx;
323 	enum rtw89_mac_idx mac_idx;
324 	enum rtw89_phy_idx phy_idx;
325 	struct rtw89_chan chan;
326 	struct rtw89_channel_help_params bak;
327 	enum rtw89_entity_mode mode;
328 	bool band_changed;
329 	bool entity_active;
330 
331 	entity_active = rtw89_get_entity_state(rtwdev);
332 
333 	mode = rtw89_entity_recalc(rtwdev);
334 	if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode))
335 		return;
336 
337 	sub_entity_idx = RTW89_SUB_ENTITY_0;
338 	mac_idx = RTW89_MAC_0;
339 	phy_idx = RTW89_PHY_0;
340 	chandef = rtw89_chandef_get(rtwdev, sub_entity_idx);
341 	rtw89_get_channel_params(chandef, &chan);
342 	if (WARN(chan.channel == 0, "Invalid channel\n"))
343 		return;
344 
345 	band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan);
346 
347 	rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx);
348 
349 	chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx);
350 
351 	rtw89_core_set_chip_txpwr(rtwdev);
352 
353 	rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx);
354 
355 	if (!entity_active || band_changed) {
356 		rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type);
357 		rtw89_chip_rfk_band_changed(rtwdev, phy_idx);
358 	}
359 
360 	rtw89_set_entity_state(rtwdev, true);
361 }
362 
363 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)364 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
365 		       struct sk_buff *skb)
366 {
367 	struct ieee80211_hdr *hdr = (void *)skb->data;
368 	__le16 fc = hdr->frame_control;
369 
370 	if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
371 		return RTW89_CORE_TX_TYPE_MGMT;
372 
373 	return RTW89_CORE_TX_TYPE_DATA;
374 }
375 
376 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)377 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
378 				struct rtw89_core_tx_request *tx_req,
379 				enum btc_pkt_type pkt_type)
380 {
381 	struct ieee80211_sta *sta = tx_req->sta;
382 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
383 	struct sk_buff *skb = tx_req->skb;
384 	struct rtw89_sta *rtwsta;
385 	u8 ampdu_num;
386 	u8 tid;
387 
388 	if (pkt_type == PACKET_EAPOL) {
389 		desc_info->bk = true;
390 		return;
391 	}
392 
393 	if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
394 		return;
395 
396 	if (!sta) {
397 		rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
398 		return;
399 	}
400 
401 	tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
402 	rtwsta = (struct rtw89_sta *)sta->drv_priv;
403 
404 	ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
405 			  rtwsta->ampdu_params[tid].agg_num :
406 			  4 << sta->deflink.ht_cap.ampdu_factor) - 1);
407 
408 	desc_info->agg_en = true;
409 	desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density;
410 	desc_info->ampdu_num = ampdu_num;
411 }
412 
413 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)414 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
415 			     struct rtw89_core_tx_request *tx_req)
416 {
417 	const struct rtw89_chip_info *chip = rtwdev->chip;
418 	struct ieee80211_vif *vif = tx_req->vif;
419 	struct ieee80211_sta *sta = tx_req->sta;
420 	struct ieee80211_tx_info *info;
421 	struct ieee80211_key_conf *key;
422 	struct rtw89_vif *rtwvif;
423 	struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
424 	struct rtw89_addr_cam_entry *addr_cam;
425 	struct rtw89_sec_cam_entry *sec_cam;
426 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
427 	struct sk_buff *skb = tx_req->skb;
428 	u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
429 	u64 pn64;
430 
431 	if (!vif) {
432 		rtw89_warn(rtwdev, "cannot set sec key without vif\n");
433 		return;
434 	}
435 
436 	rtwvif = (struct rtw89_vif *)vif->drv_priv;
437 	addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta);
438 
439 	info = IEEE80211_SKB_CB(skb);
440 	key = info->control.hw_key;
441 	sec_cam = addr_cam->sec_entries[key->hw_key_idx];
442 	if (!sec_cam) {
443 		rtw89_warn(rtwdev, "sec cam entry is empty\n");
444 		return;
445 	}
446 
447 	switch (key->cipher) {
448 	case WLAN_CIPHER_SUITE_WEP40:
449 		sec_type = RTW89_SEC_KEY_TYPE_WEP40;
450 		break;
451 	case WLAN_CIPHER_SUITE_WEP104:
452 		sec_type = RTW89_SEC_KEY_TYPE_WEP104;
453 		break;
454 	case WLAN_CIPHER_SUITE_TKIP:
455 		sec_type = RTW89_SEC_KEY_TYPE_TKIP;
456 		break;
457 	case WLAN_CIPHER_SUITE_CCMP:
458 		sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
459 		break;
460 	case WLAN_CIPHER_SUITE_CCMP_256:
461 		sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
462 		break;
463 	case WLAN_CIPHER_SUITE_GCMP:
464 		sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
465 		break;
466 	case WLAN_CIPHER_SUITE_GCMP_256:
467 		sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
468 		break;
469 	default:
470 		rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
471 		return;
472 	}
473 
474 	desc_info->sec_en = true;
475 	desc_info->sec_keyid = key->keyidx;
476 	desc_info->sec_type = sec_type;
477 	desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
478 
479 	if (!chip->hw_sec_hdr)
480 		return;
481 
482 	pn64 = atomic64_inc_return(&key->tx_pn);
483 	desc_info->sec_seq[0] = pn64;
484 	desc_info->sec_seq[1] = pn64 >> 8;
485 	desc_info->sec_seq[2] = pn64 >> 16;
486 	desc_info->sec_seq[3] = pn64 >> 24;
487 	desc_info->sec_seq[4] = pn64 >> 32;
488 	desc_info->sec_seq[5] = pn64 >> 40;
489 	desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
490 }
491 
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)492 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
493 				    struct rtw89_core_tx_request *tx_req)
494 {
495 	struct sk_buff *skb = tx_req->skb;
496 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
497 	struct ieee80211_vif *vif = tx_info->control.vif;
498 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
499 	u16 lowest_rate;
500 
501 	if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || vif->p2p)
502 		lowest_rate = RTW89_HW_RATE_OFDM6;
503 	else if (chan->band_type == RTW89_BAND_2G)
504 		lowest_rate = RTW89_HW_RATE_CCK1;
505 	else
506 		lowest_rate = RTW89_HW_RATE_OFDM6;
507 
508 	if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta)
509 		return lowest_rate;
510 
511 	return __ffs(vif->bss_conf.basic_rates) + lowest_rate;
512 }
513 
514 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)515 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
516 			       struct rtw89_core_tx_request *tx_req)
517 {
518 	struct ieee80211_vif *vif = tx_req->vif;
519 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
520 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
521 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
522 	u8 qsel, ch_dma;
523 
524 	qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
525 	ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
526 
527 	desc_info->qsel = qsel;
528 	desc_info->ch_dma = ch_dma;
529 	desc_info->port = desc_info->hiq ? rtwvif->port : 0;
530 	desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
531 	desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
532 
533 	/* fixed data rate for mgmt frames */
534 	desc_info->en_wd_info = true;
535 	desc_info->use_rate = true;
536 	desc_info->dis_data_fb = true;
537 	desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req);
538 
539 	rtw89_debug(rtwdev, RTW89_DBG_TXRX,
540 		    "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
541 		    desc_info->data_rate, chan->channel, chan->band_type,
542 		    chan->band_width);
543 }
544 
545 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)546 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
547 			      struct rtw89_core_tx_request *tx_req)
548 {
549 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
550 
551 	desc_info->is_bmc = false;
552 	desc_info->wd_page = false;
553 	desc_info->ch_dma = RTW89_DMA_H2C;
554 }
555 
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc)556 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc)
557 {
558 	static const u8 rtw89_bandwidth_to_om[] = {
559 		[RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
560 		[RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
561 		[RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
562 		[RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
563 		[RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
564 	};
565 	const struct rtw89_chip_info *chip = rtwdev->chip;
566 	struct rtw89_hal *hal = &rtwdev->hal;
567 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
568 	u8 om_bandwidth;
569 
570 	if (!chip->dis_2g_40m_ul_ofdma ||
571 	    chan->band_type != RTW89_BAND_2G ||
572 	    chan->band_width != RTW89_CHANNEL_WIDTH_40)
573 		return;
574 
575 	om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
576 		       rtw89_bandwidth_to_om[chan->band_width] : 0;
577 	*htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
578 	       le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
579 	       le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
580 	       le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
581 	       le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
582 	       le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
583 	       le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
584 	       le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
585 	       le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
586 }
587 
588 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)589 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
590 				 struct rtw89_core_tx_request *tx_req,
591 				 enum btc_pkt_type pkt_type)
592 {
593 	struct ieee80211_sta *sta = tx_req->sta;
594 	struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
595 	struct sk_buff *skb = tx_req->skb;
596 	struct ieee80211_hdr *hdr = (void *)skb->data;
597 	__le16 fc = hdr->frame_control;
598 
599 	/* AP IOT issue with EAPoL, ARP and DHCP */
600 	if (pkt_type < PACKET_MAX)
601 		return false;
602 
603 	if (!sta || !sta->deflink.he_cap.has_he)
604 		return false;
605 
606 	if (!ieee80211_is_data_qos(fc))
607 		return false;
608 
609 	if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
610 		return false;
611 
612 	if (rtwsta && rtwsta->ra_report.might_fallback_legacy)
613 		return false;
614 
615 	return true;
616 }
617 
618 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)619 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
620 				  struct rtw89_core_tx_request *tx_req)
621 {
622 	struct ieee80211_sta *sta = tx_req->sta;
623 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
624 	struct sk_buff *skb = tx_req->skb;
625 	struct ieee80211_hdr *hdr = (void *)skb->data;
626 	__le16 fc = hdr->frame_control;
627 	void *data;
628 	__le32 *htc;
629 	u8 *qc;
630 	int hdr_len;
631 
632 	hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
633 	data = skb_push(skb, IEEE80211_HT_CTL_LEN);
634 	memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
635 
636 	hdr = data;
637 	htc = data + hdr_len;
638 	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
639 	*htc = rtwsta->htc_template ? rtwsta->htc_template :
640 	       le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
641 	       le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
642 
643 	qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
644 	qc[0] |= IEEE80211_QOS_CTL_EOSP;
645 }
646 
647 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)648 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
649 				struct rtw89_core_tx_request *tx_req,
650 				enum btc_pkt_type pkt_type)
651 {
652 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
653 	struct ieee80211_vif *vif = tx_req->vif;
654 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
655 
656 	if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
657 		goto desc_bk;
658 
659 	__rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
660 
661 	desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
662 	desc_info->a_ctrl_bsr = true;
663 
664 desc_bk:
665 	if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr)
666 		return;
667 
668 	rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr;
669 	desc_info->bk = true;
670 }
671 
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)672 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
673 				   struct rtw89_core_tx_request *tx_req)
674 {
675 	struct ieee80211_vif *vif = tx_req->vif;
676 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
677 	struct ieee80211_sta *sta = tx_req->sta;
678 	struct rtw89_sta *rtwsta;
679 
680 	if (!sta)
681 		return rtwvif->mac_id;
682 
683 	rtwsta = (struct rtw89_sta *)sta->drv_priv;
684 	return rtwsta->mac_id;
685 }
686 
687 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)688 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
689 			       struct rtw89_core_tx_request *tx_req)
690 {
691 	struct ieee80211_vif *vif = tx_req->vif;
692 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
693 	struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
694 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
695 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
696 	struct sk_buff *skb = tx_req->skb;
697 	u8 tid, tid_indicate;
698 	u8 qsel, ch_dma;
699 
700 	tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
701 	tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
702 	qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
703 	ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
704 
705 	desc_info->ch_dma = ch_dma;
706 	desc_info->tid_indicate = tid_indicate;
707 	desc_info->qsel = qsel;
708 	desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
709 	desc_info->port = desc_info->hiq ? rtwvif->port : 0;
710 
711 	/* enable wd_info for AMPDU */
712 	desc_info->en_wd_info = true;
713 
714 	if (IEEE80211_SKB_CB(skb)->control.hw_key)
715 		rtw89_core_tx_update_sec_key(rtwdev, tx_req);
716 
717 	if (vif->p2p)
718 		desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6;
719 	else if (rate_pattern->enable)
720 		desc_info->data_retry_lowest_rate = rate_pattern->rate;
721 	else if (chan->band_type == RTW89_BAND_2G)
722 		desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1;
723 	else
724 		desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6;
725 }
726 
727 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)728 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
729 				  struct rtw89_core_tx_request *tx_req)
730 {
731 	struct sk_buff *skb = tx_req->skb;
732 	struct udphdr *udphdr;
733 
734 	if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
735 		ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
736 		return PACKET_EAPOL;
737 	}
738 
739 	if (skb->protocol == htons(ETH_P_ARP)) {
740 		ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
741 		return PACKET_ARP;
742 	}
743 
744 	if (skb->protocol == htons(ETH_P_IP) &&
745 	    ip_hdr(skb)->protocol == IPPROTO_UDP) {
746 		udphdr = udp_hdr(skb);
747 		if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
748 		     (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
749 		    skb->len > 282) {
750 			ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
751 			return PACKET_DHCP;
752 		}
753 	}
754 
755 	if (skb->protocol == htons(ETH_P_IP) &&
756 	    ip_hdr(skb)->protocol == IPPROTO_ICMP) {
757 		ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
758 		return PACKET_ICMP;
759 	}
760 
761 	return PACKET_MAX;
762 }
763 
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)764 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
765 					 struct rtw89_tx_desc_info *desc_info,
766 					 struct sk_buff *skb)
767 {
768 	struct ieee80211_hdr *hdr = (void *)skb->data;
769 	__le16 fc = hdr->frame_control;
770 
771 	desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
772 	desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
773 }
774 
775 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)776 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
777 		   struct rtw89_core_tx_request *tx_req)
778 {
779 	const struct rtw89_chip_info *chip = rtwdev->chip;
780 
781 	if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
782 		return;
783 
784 	if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
785 		return;
786 
787 	if (chip->chip_id != RTL8852C &&
788 	    tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
789 		return;
790 
791 	rtw89_mac_notify_wake(rtwdev);
792 }
793 
794 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)795 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
796 			       struct rtw89_core_tx_request *tx_req)
797 {
798 	struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
799 	struct sk_buff *skb = tx_req->skb;
800 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
801 	struct ieee80211_hdr *hdr = (void *)skb->data;
802 	enum rtw89_core_tx_type tx_type;
803 	enum btc_pkt_type pkt_type;
804 	bool is_bmc;
805 	u16 seq;
806 
807 	seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
808 	if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
809 		tx_type = rtw89_core_get_tx_type(rtwdev, skb);
810 		tx_req->tx_type = tx_type;
811 	}
812 	is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
813 		  is_multicast_ether_addr(hdr->addr1));
814 
815 	desc_info->seq = seq;
816 	desc_info->pkt_size = skb->len;
817 	desc_info->is_bmc = is_bmc;
818 	desc_info->wd_page = true;
819 	desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
820 
821 	switch (tx_req->tx_type) {
822 	case RTW89_CORE_TX_TYPE_MGMT:
823 		rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
824 		break;
825 	case RTW89_CORE_TX_TYPE_DATA:
826 		rtw89_core_tx_update_data_info(rtwdev, tx_req);
827 		pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
828 		rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
829 		rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
830 		rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
831 		break;
832 	case RTW89_CORE_TX_TYPE_FWCMD:
833 		rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
834 		break;
835 	}
836 }
837 
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)838 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
839 {
840 	u8 ch_dma;
841 
842 	ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
843 
844 	rtw89_hci_tx_kick_off(rtwdev, ch_dma);
845 }
846 
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)847 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
848 		 struct sk_buff *skb, bool fwdl)
849 {
850 	struct rtw89_core_tx_request tx_req = {0};
851 	u32 cnt;
852 	int ret;
853 
854 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
855 		rtw89_debug(rtwdev, RTW89_DBG_FW,
856 			    "ignore h2c due to power is off with firmware state=%d\n",
857 			    test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
858 		dev_kfree_skb(skb);
859 		return 0;
860 	}
861 
862 	tx_req.skb = skb;
863 	tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
864 	if (fwdl)
865 		tx_req.desc_info.fw_dl = true;
866 
867 	rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
868 
869 	if (!fwdl)
870 		rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
871 
872 	cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
873 	if (cnt == 0) {
874 		rtw89_err(rtwdev, "no tx fwcmd resource\n");
875 		return -ENOSPC;
876 	}
877 
878 	ret = rtw89_hci_tx_write(rtwdev, &tx_req);
879 	if (ret) {
880 		rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
881 		return ret;
882 	}
883 	rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
884 
885 	return 0;
886 }
887 
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)888 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
889 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
890 {
891 	struct rtw89_core_tx_request tx_req = {0};
892 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
893 	int ret;
894 
895 	tx_req.skb = skb;
896 	tx_req.sta = sta;
897 	tx_req.vif = vif;
898 
899 	rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
900 	rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
901 	rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
902 	rtw89_core_tx_wake(rtwdev, &tx_req);
903 
904 	ret = rtw89_hci_tx_write(rtwdev, &tx_req);
905 	if (ret) {
906 		rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
907 		return ret;
908 	}
909 
910 	if (qsel)
911 		*qsel = tx_req.desc_info.qsel;
912 
913 	return 0;
914 }
915 
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)916 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
917 {
918 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
919 		    FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
920 		    FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
921 		    FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
922 		    FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
923 		    FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
924 		    FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
925 		    FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
926 
927 	return cpu_to_le32(dword);
928 }
929 
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)930 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
931 {
932 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
933 		    FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
934 		    FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
935 		    FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
936 		    FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
937 		    FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
938 
939 	return cpu_to_le32(dword);
940 }
941 
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)942 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
943 {
944 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
945 		    FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
946 		    FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
947 
948 	return cpu_to_le32(dword);
949 }
950 
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)951 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
952 {
953 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
954 		    FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
955 		    FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
956 		    FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
957 
958 	return cpu_to_le32(dword);
959 }
960 
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)961 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
962 {
963 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
964 		    FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
965 		    FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
966 
967 	return cpu_to_le32(dword);
968 }
969 
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)970 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
971 {
972 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
973 		    FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
974 
975 	return cpu_to_le32(dword);
976 }
977 
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)978 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
979 {
980 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
981 		    FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
982 		    FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
983 		    FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
984 
985 	return cpu_to_le32(dword);
986 }
987 
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)988 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
989 {
990 	u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
991 		    FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
992 
993 	return cpu_to_le32(dword);
994 }
995 
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)996 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
997 {
998 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
999 		    FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1000 		    FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1001 		    FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1002 
1003 	return cpu_to_le32(dword);
1004 }
1005 
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1006 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1007 {
1008 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1009 		    FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1010 
1011 	return cpu_to_le32(dword);
1012 }
1013 
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1014 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1015 {
1016 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1017 		    FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1018 		    FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1019 			       desc_info->data_retry_lowest_rate);
1020 
1021 	return cpu_to_le32(dword);
1022 }
1023 
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1024 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1025 {
1026 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1027 		    FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1028 		    FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1029 		    FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1030 
1031 	return cpu_to_le32(dword);
1032 }
1033 
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1034 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1035 {
1036 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1037 		    FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1038 		    FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1039 
1040 	return cpu_to_le32(dword);
1041 }
1042 
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1043 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1044 {
1045 	u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) |
1046 		    FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1047 
1048 	return cpu_to_le32(dword);
1049 }
1050 
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1051 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1052 			    struct rtw89_tx_desc_info *desc_info,
1053 			    void *txdesc)
1054 {
1055 	struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1056 	struct rtw89_txwd_info *txwd_info;
1057 
1058 	txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1059 	txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1060 	txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1061 
1062 	if (!desc_info->en_wd_info)
1063 		return;
1064 
1065 	txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1066 	txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1067 	txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1068 	txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1069 	txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1070 
1071 }
1072 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1073 
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1074 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1075 			       struct rtw89_tx_desc_info *desc_info,
1076 			       void *txdesc)
1077 {
1078 	struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1079 	struct rtw89_txwd_info *txwd_info;
1080 
1081 	txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1082 	txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1083 	txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1084 	txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1085 	if (desc_info->sec_en) {
1086 		txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1087 		txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1088 	}
1089 	txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1090 
1091 	if (!desc_info->en_wd_info)
1092 		return;
1093 
1094 	txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1095 	txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1096 	txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1097 	txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1098 	txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1099 }
1100 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1101 
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1102 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1103 {
1104 	u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1105 		    FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1106 						      RTW89_CORE_RX_TYPE_FWDL :
1107 						      RTW89_CORE_RX_TYPE_H2C);
1108 
1109 	return cpu_to_le32(dword);
1110 }
1111 
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1112 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1113 				     struct rtw89_tx_desc_info *desc_info,
1114 				     void *txdesc)
1115 {
1116 	struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1117 
1118 	txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1119 }
1120 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1121 
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1122 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1123 					  struct sk_buff *skb,
1124 					  struct rtw89_rx_phy_ppdu *phy_ppdu)
1125 {
1126 	bool rx_cnt_valid = false;
1127 	u8 plcp_size = 0;
1128 	u8 usr_num = 0;
1129 	u8 *phy_sts;
1130 
1131 	rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data);
1132 	plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3;
1133 	usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data);
1134 	if (usr_num > RTW89_PPDU_MAX_USR) {
1135 		rtw89_warn(rtwdev, "Invalid user number in mac info\n");
1136 		return -EINVAL;
1137 	}
1138 
1139 	phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1140 	phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1141 	/* 8-byte alignment */
1142 	if (usr_num & BIT(0))
1143 		phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1144 	if (rx_cnt_valid)
1145 		phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE;
1146 	phy_sts += plcp_size;
1147 
1148 	phy_ppdu->buf = phy_sts;
1149 	phy_ppdu->len = skb->data + skb->len - phy_sts;
1150 
1151 	return 0;
1152 }
1153 
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1154 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1155 						struct ieee80211_sta *sta)
1156 {
1157 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1158 	struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1159 	struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1160 	int i;
1161 
1162 	if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) {
1163 		ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg);
1164 		for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1165 			ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]);
1166 	}
1167 }
1168 
1169 #define VAR_LEN 0xff
1170 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,u8 * addr)1171 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr)
1172 {
1173 	static const u8 physts_ie_len_tab[32] = {
1174 		16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1175 		VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1176 		VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1177 	};
1178 	u16 ie_len;
1179 	u8 ie;
1180 
1181 	ie = RTW89_GET_PHY_STS_IE_TYPE(addr);
1182 	if (physts_ie_len_tab[ie] != VAR_LEN)
1183 		ie_len = physts_ie_len_tab[ie];
1184 	else
1185 		ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT;
1186 
1187 	return ie_len;
1188 }
1189 
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,u8 * addr,struct rtw89_rx_phy_ppdu * phy_ppdu)1190 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr,
1191 					     struct rtw89_rx_phy_ppdu *phy_ppdu)
1192 {
1193 	s16 cfo;
1194 
1195 	phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr);
1196 	if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1197 		return;
1198 	/* sign conversion for S(12,2) */
1199 	cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11);
1200 	rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1201 }
1202 
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,u8 * addr,struct rtw89_rx_phy_ppdu * phy_ppdu)1203 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr,
1204 					    struct rtw89_rx_phy_ppdu *phy_ppdu)
1205 {
1206 	u8 ie;
1207 
1208 	ie = RTW89_GET_PHY_STS_IE_TYPE(addr);
1209 	switch (ie) {
1210 	case RTW89_PHYSTS_IE01_CMN_OFDM:
1211 		rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu);
1212 		break;
1213 	default:
1214 		break;
1215 	}
1216 
1217 	return 0;
1218 }
1219 
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1220 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1221 {
1222 	u8 *rssi = phy_ppdu->rssi;
1223 	u8 *buf = phy_ppdu->buf;
1224 
1225 	phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf);
1226 	phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf);
1227 	rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf);
1228 	rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf);
1229 	rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf);
1230 	rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf);
1231 }
1232 
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1233 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1234 					  struct rtw89_rx_phy_ppdu *phy_ppdu)
1235 {
1236 	if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) {
1237 		rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1238 		return -EINVAL;
1239 	}
1240 	rtw89_core_update_phy_ppdu(phy_ppdu);
1241 	ieee80211_iterate_stations_atomic(rtwdev->hw,
1242 					  rtw89_core_rx_process_phy_ppdu_iter,
1243 					  phy_ppdu);
1244 
1245 	return 0;
1246 }
1247 
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1248 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1249 				       struct rtw89_rx_phy_ppdu *phy_ppdu)
1250 {
1251 	u16 ie_len;
1252 	u8 *pos, *end;
1253 
1254 	/* mark invalid reports and bypass them */
1255 	if (phy_ppdu->ie < RTW89_CCK_PKT)
1256 		return -EINVAL;
1257 
1258 	pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
1259 	end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
1260 	while (pos < end) {
1261 		ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos);
1262 		rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu);
1263 		pos += ie_len;
1264 		if (pos > end || ie_len == 0) {
1265 			rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1266 				    "phy status parse failed\n");
1267 			return -EINVAL;
1268 		}
1269 	}
1270 
1271 	return 0;
1272 }
1273 
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1274 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1275 					  struct rtw89_rx_phy_ppdu *phy_ppdu)
1276 {
1277 	int ret;
1278 
1279 	ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1280 	if (ret)
1281 		rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1282 	else
1283 		phy_ppdu->valid = true;
1284 }
1285 
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,const struct rtw89_rx_desc_info * desc_info,bool rx_status)1286 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
1287 				   const struct rtw89_rx_desc_info *desc_info,
1288 				   bool rx_status)
1289 {
1290 	switch (desc_info->gi_ltf) {
1291 	case RTW89_GILTF_SGI_4XHE08:
1292 	case RTW89_GILTF_2XHE08:
1293 	case RTW89_GILTF_1XHE08:
1294 		return NL80211_RATE_INFO_HE_GI_0_8;
1295 	case RTW89_GILTF_2XHE16:
1296 	case RTW89_GILTF_1XHE16:
1297 		return NL80211_RATE_INFO_HE_GI_1_6;
1298 	case RTW89_GILTF_LGI_4XHE32:
1299 		return NL80211_RATE_INFO_HE_GI_3_2;
1300 	default:
1301 		rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf);
1302 		return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX;
1303 	}
1304 }
1305 
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1306 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1307 				     struct rtw89_rx_desc_info *desc_info,
1308 				     struct ieee80211_rx_status *status)
1309 {
1310 	u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1311 	u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1312 	u16 data_rate;
1313 	bool ret;
1314 
1315 	data_rate = desc_info->data_rate;
1316 	data_rate_mode = GET_DATA_RATE_MODE(data_rate);
1317 	if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1318 		rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate);
1319 		/* rate_idx is still hardware value here */
1320 	} else if (data_rate_mode == DATA_RATE_MODE_HT) {
1321 		rate_idx = GET_DATA_RATE_HT_IDX(data_rate);
1322 	} else if (data_rate_mode == DATA_RATE_MODE_VHT) {
1323 		rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate);
1324 	} else if (data_rate_mode == DATA_RATE_MODE_HE) {
1325 		rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate);
1326 	} else {
1327 		rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1328 	}
1329 
1330 	bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1331 	gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false);
1332 	ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
1333 	      status->rate_idx == rate_idx &&
1334 	      status->he_gi == gi_ltf &&
1335 	      status->bw == bw;
1336 
1337 	return ret;
1338 }
1339 
1340 struct rtw89_vif_rx_stats_iter_data {
1341 	struct rtw89_dev *rtwdev;
1342 	struct rtw89_rx_phy_ppdu *phy_ppdu;
1343 	struct rtw89_rx_desc_info *desc_info;
1344 	struct sk_buff *skb;
1345 	const u8 *bssid;
1346 };
1347 
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct sk_buff * skb)1348 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
1349 				      struct ieee80211_vif *vif,
1350 				      struct sk_buff *skb)
1351 {
1352 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1353 	struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
1354 	u8 *pos, *end, type;
1355 	u16 aid;
1356 
1357 	if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) ||
1358 	    rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION ||
1359 	    rtwvif->net_type == RTW89_NET_TYPE_NO_LINK)
1360 		return;
1361 
1362 	type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
1363 	if (type != IEEE80211_TRIGGER_TYPE_BASIC)
1364 		return;
1365 
1366 	end = (u8 *)tf + skb->len;
1367 	pos = tf->variable;
1368 
1369 	while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
1370 		aid = RTW89_GET_TF_USER_INFO_AID12(pos);
1371 		rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1372 			    "[TF] aid: %d, ul_mcs: %d, rua: %d\n",
1373 			    aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
1374 			    RTW89_GET_TF_USER_INFO_RUA(pos));
1375 
1376 		if (aid == RTW89_TF_PAD)
1377 			break;
1378 
1379 		if (aid == vif->cfg.aid) {
1380 			rtwvif->stats.rx_tf_acc++;
1381 			rtwdev->stats.rx_tf_acc++;
1382 			break;
1383 		}
1384 
1385 		pos += RTW89_TF_BASIC_USER_INFO_SZ;
1386 	}
1387 }
1388 
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1389 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
1390 				    struct ieee80211_vif *vif)
1391 {
1392 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1393 	struct rtw89_vif_rx_stats_iter_data *iter_data = data;
1394 	struct rtw89_dev *rtwdev = iter_data->rtwdev;
1395 	struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
1396 	struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
1397 	struct sk_buff *skb = iter_data->skb;
1398 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1399 	const u8 *bssid = iter_data->bssid;
1400 
1401 	if (ieee80211_is_trigger(hdr->frame_control)) {
1402 		rtw89_stats_trigger_frame(rtwdev, vif, skb);
1403 		return;
1404 	}
1405 
1406 	if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
1407 		return;
1408 
1409 	if (ieee80211_is_beacon(hdr->frame_control))
1410 		pkt_stat->beacon_nr++;
1411 
1412 	if (!ether_addr_equal(vif->addr, hdr->addr1))
1413 		return;
1414 
1415 	if (desc_info->data_rate < RTW89_HW_RATE_NR)
1416 		pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
1417 
1418 	rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
1419 }
1420 
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1421 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
1422 				struct rtw89_rx_phy_ppdu *phy_ppdu,
1423 				struct rtw89_rx_desc_info *desc_info,
1424 				struct sk_buff *skb)
1425 {
1426 	struct rtw89_vif_rx_stats_iter_data iter_data;
1427 
1428 	rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
1429 
1430 	iter_data.rtwdev = rtwdev;
1431 	iter_data.phy_ppdu = phy_ppdu;
1432 	iter_data.desc_info = desc_info;
1433 	iter_data.skb = skb;
1434 	iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
1435 	rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
1436 }
1437 
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)1438 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
1439 				   struct ieee80211_rx_status *status)
1440 {
1441 	const struct rtw89_chan_rcd *rcd =
1442 		rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0);
1443 	u16 chan = rcd->prev_primary_channel;
1444 	u8 band = rcd->prev_band_type == RTW89_BAND_2G ?
1445 		  NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1446 
1447 	if (status->band != NL80211_BAND_2GHZ &&
1448 	    status->encoding == RX_ENC_LEGACY &&
1449 	    status->rate_idx < RTW89_HW_RATE_OFDM6) {
1450 		status->freq = ieee80211_channel_to_frequency(chan, band);
1451 		status->band = band;
1452 	}
1453 }
1454 
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)1455 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
1456 {
1457 	if (rx_status->band == NL80211_BAND_2GHZ ||
1458 	    rx_status->encoding != RX_ENC_LEGACY)
1459 		return;
1460 
1461 	/* Some control frames' freq(ACKs in this case) are reported wrong due
1462 	 * to FW notify timing, set to lowest rate to prevent overflow.
1463 	 */
1464 	if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
1465 		rx_status->rate_idx = 0;
1466 		return;
1467 	}
1468 
1469 	/* No 4 CCK rates for non-2G */
1470 	rx_status->rate_idx -= 4;
1471 }
1472 
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)1473 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
1474 				      struct rtw89_rx_phy_ppdu *phy_ppdu,
1475 				      struct rtw89_rx_desc_info *desc_info,
1476 				      struct sk_buff *skb_ppdu,
1477 				      struct ieee80211_rx_status *rx_status)
1478 {
1479 	struct napi_struct *napi = &rtwdev->napi;
1480 
1481 	/* In low power mode, napi isn't scheduled. Receive it to netif. */
1482 	if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state)))
1483 		napi = NULL;
1484 
1485 	rtw89_core_hw_to_sband_rate(rx_status);
1486 	rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
1487 	/* In low power mode, it does RX in thread context. */
1488 	local_bh_disable();
1489 	ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
1490 	local_bh_enable();
1491 	rtwdev->napi_budget_countdown--;
1492 }
1493 
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1494 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
1495 				      struct rtw89_rx_phy_ppdu *phy_ppdu,
1496 				      struct rtw89_rx_desc_info *desc_info,
1497 				      struct sk_buff *skb)
1498 {
1499 	u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1500 	int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
1501 	struct sk_buff *skb_ppdu = NULL, *tmp;
1502 	struct ieee80211_rx_status *rx_status;
1503 
1504 	if (curr > RTW89_MAX_PPDU_CNT)
1505 		return;
1506 
1507 	skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
1508 		skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
1509 		rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
1510 		if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
1511 			rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
1512 		rtw89_correct_cck_chan(rtwdev, rx_status);
1513 		rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
1514 	}
1515 }
1516 
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1517 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
1518 					   struct rtw89_rx_desc_info *desc_info,
1519 					   struct sk_buff *skb)
1520 {
1521 	struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
1522 					     .len = skb->len,
1523 					     .to_self = desc_info->addr1_match,
1524 					     .rate = desc_info->data_rate,
1525 					     .mac_id = desc_info->mac_id};
1526 	int ret;
1527 
1528 	if (desc_info->mac_info_valid)
1529 		rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
1530 	ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
1531 	if (ret)
1532 		rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n");
1533 
1534 	rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
1535 	rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
1536 	dev_kfree_skb_any(skb);
1537 }
1538 
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1539 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
1540 					 struct rtw89_rx_desc_info *desc_info,
1541 					 struct sk_buff *skb)
1542 {
1543 	switch (desc_info->pkt_type) {
1544 	case RTW89_CORE_RX_TYPE_C2H:
1545 		rtw89_fw_c2h_irqsafe(rtwdev, skb);
1546 		break;
1547 	case RTW89_CORE_RX_TYPE_PPDU_STAT:
1548 		rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
1549 		break;
1550 	default:
1551 		rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
1552 			    desc_info->pkt_type);
1553 		dev_kfree_skb_any(skb);
1554 		break;
1555 	}
1556 }
1557 
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)1558 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
1559 			     struct rtw89_rx_desc_info *desc_info,
1560 			     u8 *data, u32 data_offset)
1561 {
1562 	const struct rtw89_chip_info *chip = rtwdev->chip;
1563 	struct rtw89_rxdesc_short *rxd_s;
1564 	struct rtw89_rxdesc_long *rxd_l;
1565 	u8 shift_len, drv_info_len;
1566 
1567 	rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
1568 	desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s);
1569 	desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s);
1570 	desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s);
1571 	desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s);
1572 	desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s);
1573 	if (chip->chip_id == RTL8852C)
1574 		desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s);
1575 	else
1576 		desc_info->bw = RTW89_GET_RXWD_BW(rxd_s);
1577 	desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s);
1578 	desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s);
1579 	desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s);
1580 	desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s);
1581 	desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s);
1582 	desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s);
1583 	desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s);
1584 	desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s);
1585 	desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s);
1586 	desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s);
1587 	desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s);
1588 	desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s);
1589 
1590 	shift_len = desc_info->shift << 1; /* 2-byte unit */
1591 	drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
1592 	desc_info->offset = data_offset + shift_len + drv_info_len;
1593 	desc_info->ready = true;
1594 
1595 	if (!desc_info->long_rxdesc)
1596 		return;
1597 
1598 	rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
1599 	desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l);
1600 	desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l);
1601 	desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l);
1602 	desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l);
1603 	desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l);
1604 	desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l);
1605 }
1606 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
1607 
1608 struct rtw89_core_iter_rx_status {
1609 	struct rtw89_dev *rtwdev;
1610 	struct ieee80211_rx_status *rx_status;
1611 	struct rtw89_rx_desc_info *desc_info;
1612 	u8 mac_id;
1613 };
1614 
1615 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)1616 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
1617 {
1618 	struct rtw89_core_iter_rx_status *iter_data =
1619 				(struct rtw89_core_iter_rx_status *)data;
1620 	struct ieee80211_rx_status *rx_status = iter_data->rx_status;
1621 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1622 	struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
1623 	u8 mac_id = iter_data->mac_id;
1624 
1625 	if (mac_id != rtwsta->mac_id)
1626 		return;
1627 
1628 	rtwsta->rx_status = *rx_status;
1629 	rtwsta->rx_hw_rate = desc_info->data_rate;
1630 }
1631 
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1632 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
1633 					   struct rtw89_rx_desc_info *desc_info,
1634 					   struct ieee80211_rx_status *rx_status)
1635 {
1636 	struct rtw89_core_iter_rx_status iter_data;
1637 
1638 	if (!desc_info->addr1_match || !desc_info->long_rxdesc)
1639 		return;
1640 
1641 	if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
1642 		return;
1643 
1644 	iter_data.rtwdev = rtwdev;
1645 	iter_data.rx_status = rx_status;
1646 	iter_data.desc_info = desc_info;
1647 	iter_data.mac_id = desc_info->mac_id;
1648 	ieee80211_iterate_stations_atomic(rtwdev->hw,
1649 					  rtw89_core_stats_sta_rx_status_iter,
1650 					  &iter_data);
1651 }
1652 
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1653 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
1654 					struct rtw89_rx_desc_info *desc_info,
1655 					struct ieee80211_rx_status *rx_status)
1656 {
1657 	const struct cfg80211_chan_def *chandef =
1658 		rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0);
1659 	const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1660 	u16 data_rate;
1661 	u8 data_rate_mode;
1662 
1663 	/* currently using single PHY */
1664 	rx_status->freq = chandef->chan->center_freq;
1665 	rx_status->band = chandef->chan->band;
1666 
1667 	if (rtwdev->scanning &&
1668 	    RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
1669 		u8 chan = cur->primary_channel;
1670 		u8 band = cur->band_type;
1671 		enum nl80211_band nl_band;
1672 
1673 		nl_band = rtw89_hw_to_nl80211_band(band);
1674 		rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
1675 		rx_status->band = nl_band;
1676 	}
1677 
1678 	if (desc_info->icv_err || desc_info->crc32_err)
1679 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
1680 
1681 	if (desc_info->hw_dec &&
1682 	    !(desc_info->sw_dec || desc_info->icv_err))
1683 		rx_status->flag |= RX_FLAG_DECRYPTED;
1684 
1685 	rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1686 
1687 	data_rate = desc_info->data_rate;
1688 	data_rate_mode = GET_DATA_RATE_MODE(data_rate);
1689 	if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1690 		rx_status->encoding = RX_ENC_LEGACY;
1691 		rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate);
1692 		/* convert rate_idx after we get the correct band */
1693 	} else if (data_rate_mode == DATA_RATE_MODE_HT) {
1694 		rx_status->encoding = RX_ENC_HT;
1695 		rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate);
1696 		if (desc_info->gi_ltf)
1697 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1698 	} else if (data_rate_mode == DATA_RATE_MODE_VHT) {
1699 		rx_status->encoding = RX_ENC_VHT;
1700 		rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate);
1701 		rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1;
1702 		if (desc_info->gi_ltf)
1703 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1704 	} else if (data_rate_mode == DATA_RATE_MODE_HE) {
1705 		rx_status->encoding = RX_ENC_HE;
1706 		rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate);
1707 		rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1;
1708 	} else {
1709 		rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1710 	}
1711 
1712 	/* he_gi is used to match ppdu, so we always fill it. */
1713 	rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true);
1714 	rx_status->flag |= RX_FLAG_MACTIME_START;
1715 	rx_status->mactime = desc_info->free_run_cnt;
1716 
1717 	rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
1718 }
1719 
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)1720 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
1721 {
1722 	const struct rtw89_chip_info *chip = rtwdev->chip;
1723 
1724 	if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
1725 	    RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
1726 		return RTW89_PS_MODE_NONE;
1727 
1728 	if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED))
1729 		return RTW89_PS_MODE_PWR_GATED;
1730 
1731 	if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
1732 		return RTW89_PS_MODE_CLK_GATED;
1733 
1734 	if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
1735 		return RTW89_PS_MODE_RFOFF;
1736 
1737 	return RTW89_PS_MODE_NONE;
1738 }
1739 
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)1740 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
1741 					   struct rtw89_rx_desc_info *desc_info)
1742 {
1743 	struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
1744 	u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1745 	struct ieee80211_rx_status *rx_status;
1746 	struct sk_buff *skb_ppdu, *tmp;
1747 
1748 	skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
1749 		skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
1750 		rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
1751 		rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
1752 	}
1753 }
1754 
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1755 void rtw89_core_rx(struct rtw89_dev *rtwdev,
1756 		   struct rtw89_rx_desc_info *desc_info,
1757 		   struct sk_buff *skb)
1758 {
1759 	struct ieee80211_rx_status *rx_status;
1760 	struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
1761 	u8 ppdu_cnt = desc_info->ppdu_cnt;
1762 	u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1763 
1764 	if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
1765 		rtw89_core_rx_process_report(rtwdev, desc_info, skb);
1766 		return;
1767 	}
1768 
1769 	if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
1770 		rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
1771 		ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
1772 	}
1773 
1774 	rx_status = IEEE80211_SKB_RXCB(skb);
1775 	memset(rx_status, 0, sizeof(*rx_status));
1776 	rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
1777 	if (desc_info->long_rxdesc &&
1778 	    BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
1779 		skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
1780 	else
1781 		rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
1782 }
1783 EXPORT_SYMBOL(rtw89_core_rx);
1784 
rtw89_core_napi_start(struct rtw89_dev * rtwdev)1785 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
1786 {
1787 	if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
1788 		return;
1789 
1790 	napi_enable(&rtwdev->napi);
1791 }
1792 EXPORT_SYMBOL(rtw89_core_napi_start);
1793 
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)1794 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
1795 {
1796 	if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
1797 		return;
1798 
1799 	napi_synchronize(&rtwdev->napi);
1800 	napi_disable(&rtwdev->napi);
1801 }
1802 EXPORT_SYMBOL(rtw89_core_napi_stop);
1803 
rtw89_core_napi_init(struct rtw89_dev * rtwdev)1804 void rtw89_core_napi_init(struct rtw89_dev *rtwdev)
1805 {
1806 	init_dummy_netdev(&rtwdev->netdev);
1807 	netif_napi_add(&rtwdev->netdev, &rtwdev->napi,
1808 		       rtwdev->hci.ops->napi_poll);
1809 }
1810 EXPORT_SYMBOL(rtw89_core_napi_init);
1811 
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)1812 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
1813 {
1814 	rtw89_core_napi_stop(rtwdev);
1815 	netif_napi_del(&rtwdev->napi);
1816 }
1817 EXPORT_SYMBOL(rtw89_core_napi_deinit);
1818 
rtw89_core_ba_work(struct work_struct * work)1819 static void rtw89_core_ba_work(struct work_struct *work)
1820 {
1821 	struct rtw89_dev *rtwdev =
1822 		container_of(work, struct rtw89_dev, ba_work);
1823 	struct rtw89_txq *rtwtxq, *tmp;
1824 	int ret;
1825 
1826 	spin_lock_bh(&rtwdev->ba_lock);
1827 	list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
1828 		struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1829 		struct ieee80211_sta *sta = txq->sta;
1830 		struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
1831 		u8 tid = txq->tid;
1832 
1833 		if (!sta) {
1834 			rtw89_warn(rtwdev, "cannot start BA without sta\n");
1835 			goto skip_ba_work;
1836 		}
1837 
1838 		if (rtwsta->disassoc) {
1839 			rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1840 				    "cannot start BA with disassoc sta\n");
1841 			goto skip_ba_work;
1842 		}
1843 
1844 		ret = ieee80211_start_tx_ba_session(sta, tid, 0);
1845 		if (ret) {
1846 			rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1847 				    "failed to setup BA session for %pM:%2d: %d\n",
1848 				    sta->addr, tid, ret);
1849 			if (ret == -EINVAL)
1850 				set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
1851 		}
1852 skip_ba_work:
1853 		list_del_init(&rtwtxq->list);
1854 	}
1855 	spin_unlock_bh(&rtwdev->ba_lock);
1856 }
1857 
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)1858 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
1859 					   struct ieee80211_sta *sta)
1860 {
1861 	struct rtw89_txq *rtwtxq, *tmp;
1862 
1863 	spin_lock_bh(&rtwdev->ba_lock);
1864 	list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
1865 		struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1866 
1867 		if (sta == txq->sta)
1868 			list_del_init(&rtwtxq->list);
1869 	}
1870 	spin_unlock_bh(&rtwdev->ba_lock);
1871 }
1872 
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)1873 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
1874 						  struct ieee80211_sta *sta)
1875 {
1876 	struct rtw89_txq *rtwtxq, *tmp;
1877 
1878 	spin_lock_bh(&rtwdev->ba_lock);
1879 	list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
1880 		struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1881 
1882 		if (sta == txq->sta) {
1883 			clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
1884 			list_del_init(&rtwtxq->list);
1885 		}
1886 	}
1887 	spin_unlock_bh(&rtwdev->ba_lock);
1888 }
1889 
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)1890 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
1891 					  struct rtw89_txq *rtwtxq)
1892 {
1893 	struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1894 	struct ieee80211_sta *sta = txq->sta;
1895 	struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1896 
1897 	if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
1898 		return;
1899 
1900 	if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
1901 	    test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
1902 		return;
1903 
1904 	spin_lock_bh(&rtwdev->ba_lock);
1905 	if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
1906 		list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
1907 	spin_unlock_bh(&rtwdev->ba_lock);
1908 
1909 	ieee80211_stop_tx_ba_session(sta, txq->tid);
1910 	cancel_delayed_work(&rtwdev->forbid_ba_work);
1911 	ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
1912 				     RTW89_FORBID_BA_TIMER);
1913 }
1914 
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)1915 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
1916 				     struct rtw89_txq *rtwtxq,
1917 				     struct sk_buff *skb)
1918 {
1919 	struct ieee80211_hw *hw = rtwdev->hw;
1920 	struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1921 	struct ieee80211_sta *sta = txq->sta;
1922 	struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
1923 
1924 	if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
1925 		return;
1926 
1927 	if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1928 		rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
1929 		return;
1930 	}
1931 
1932 	if (unlikely(!sta))
1933 		return;
1934 
1935 	if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
1936 		return;
1937 
1938 	if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
1939 		IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
1940 		return;
1941 	}
1942 
1943 	spin_lock_bh(&rtwdev->ba_lock);
1944 	if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
1945 		list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
1946 		ieee80211_queue_work(hw, &rtwdev->ba_work);
1947 	}
1948 	spin_unlock_bh(&rtwdev->ba_lock);
1949 }
1950 
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)1951 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
1952 				struct rtw89_txq *rtwtxq,
1953 				unsigned long frame_cnt,
1954 				unsigned long byte_cnt)
1955 {
1956 	struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
1957 	struct ieee80211_vif *vif = txq->vif;
1958 	struct ieee80211_sta *sta = txq->sta;
1959 	struct sk_buff *skb;
1960 	unsigned long i;
1961 	int ret;
1962 
1963 	rcu_read_lock();
1964 	for (i = 0; i < frame_cnt; i++) {
1965 		skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
1966 		if (!skb) {
1967 			rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
1968 			goto out;
1969 		}
1970 		rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
1971 		ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
1972 		if (ret) {
1973 			rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
1974 			ieee80211_free_txskb(rtwdev->hw, skb);
1975 			break;
1976 		}
1977 	}
1978 out:
1979 	rcu_read_unlock();
1980 }
1981 
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)1982 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
1983 {
1984 	u8 qsel, ch_dma;
1985 
1986 	qsel = rtw89_core_get_qsel(rtwdev, tid);
1987 	ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
1988 
1989 	return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
1990 }
1991 
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)1992 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
1993 				    struct ieee80211_txq *txq,
1994 				    unsigned long *frame_cnt,
1995 				    bool *sched_txq, bool *reinvoke)
1996 {
1997 	struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
1998 	struct ieee80211_sta *sta = txq->sta;
1999 	struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2000 
2001 	if (!sta || rtwsta->max_agg_wait <= 0)
2002 		return false;
2003 
2004 	if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
2005 		return false;
2006 
2007 	if (*frame_cnt > 1) {
2008 		*frame_cnt -= 1;
2009 		*sched_txq = true;
2010 		*reinvoke = true;
2011 		rtwtxq->wait_cnt = 1;
2012 		return false;
2013 	}
2014 
2015 	if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) {
2016 		*reinvoke = true;
2017 		rtwtxq->wait_cnt++;
2018 		return true;
2019 	}
2020 
2021 	rtwtxq->wait_cnt = 0;
2022 	return false;
2023 }
2024 
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2025 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
2026 {
2027 	struct ieee80211_hw *hw = rtwdev->hw;
2028 	struct ieee80211_txq *txq;
2029 	struct rtw89_txq *rtwtxq;
2030 	unsigned long frame_cnt;
2031 	unsigned long byte_cnt;
2032 	u32 tx_resource;
2033 	bool sched_txq;
2034 
2035 	ieee80211_txq_schedule_start(hw, ac);
2036 	while ((txq = ieee80211_next_txq(hw, ac))) {
2037 		rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2038 		tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
2039 		sched_txq = false;
2040 
2041 		ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
2042 		if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
2043 			ieee80211_return_txq(hw, txq, true);
2044 			continue;
2045 		}
2046 		frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
2047 		rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
2048 		ieee80211_return_txq(hw, txq, sched_txq);
2049 		if (frame_cnt != 0)
2050 			rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
2051 
2052 		/* bound of tx_resource could get stuck due to burst traffic */
2053 		if (frame_cnt == tx_resource)
2054 			*reinvoke = true;
2055 	}
2056 	ieee80211_txq_schedule_end(hw, ac);
2057 }
2058 
rtw89_ips_work(struct work_struct * work)2059 static void rtw89_ips_work(struct work_struct *work)
2060 {
2061 	struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2062 						ips_work);
2063 	mutex_lock(&rtwdev->mutex);
2064 	if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
2065 		rtw89_enter_ips(rtwdev);
2066 	mutex_unlock(&rtwdev->mutex);
2067 }
2068 
rtw89_core_txq_work(struct work_struct * w)2069 static void rtw89_core_txq_work(struct work_struct *w)
2070 {
2071 	struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
2072 	bool reinvoke = false;
2073 	u8 ac;
2074 
2075 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2076 		rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
2077 
2078 	if (reinvoke) {
2079 		/* reinvoke to process the last frame */
2080 		mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
2081 	}
2082 }
2083 
rtw89_core_txq_reinvoke_work(struct work_struct * w)2084 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
2085 {
2086 	struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2087 						txq_reinvoke_work.work);
2088 
2089 	queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
2090 }
2091 
rtw89_forbid_ba_work(struct work_struct * w)2092 static void rtw89_forbid_ba_work(struct work_struct *w)
2093 {
2094 	struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2095 						forbid_ba_work.work);
2096 	struct rtw89_txq *rtwtxq, *tmp;
2097 
2098 	spin_lock_bh(&rtwdev->ba_lock);
2099 	list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2100 		clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2101 		list_del_init(&rtwtxq->list);
2102 	}
2103 	spin_unlock_bh(&rtwdev->ba_lock);
2104 }
2105 
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)2106 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
2107 						 u32 throughput, u64 cnt)
2108 {
2109 	if (cnt < 100)
2110 		return RTW89_TFC_IDLE;
2111 	if (throughput > 50)
2112 		return RTW89_TFC_HIGH;
2113 	if (throughput > 10)
2114 		return RTW89_TFC_MID;
2115 	if (throughput > 2)
2116 		return RTW89_TFC_LOW;
2117 	return RTW89_TFC_ULTRA_LOW;
2118 }
2119 
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2120 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
2121 				     struct rtw89_traffic_stats *stats)
2122 {
2123 	enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
2124 	enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
2125 
2126 	stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
2127 	stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
2128 
2129 	ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
2130 	ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
2131 
2132 	stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
2133 	stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
2134 	stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
2135 						   stats->tx_cnt);
2136 	stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
2137 						   stats->rx_cnt);
2138 	stats->tx_avg_len = stats->tx_cnt ?
2139 			    DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
2140 	stats->rx_avg_len = stats->rx_cnt ?
2141 			    DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
2142 
2143 	stats->tx_unicast = 0;
2144 	stats->rx_unicast = 0;
2145 	stats->tx_cnt = 0;
2146 	stats->rx_cnt = 0;
2147 	stats->rx_tf_periodic = stats->rx_tf_acc;
2148 	stats->rx_tf_acc = 0;
2149 
2150 	if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
2151 		return true;
2152 
2153 	return false;
2154 }
2155 
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)2156 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
2157 {
2158 	struct rtw89_vif *rtwvif;
2159 	bool tfc_changed;
2160 
2161 	tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
2162 	rtw89_for_each_rtwvif(rtwdev, rtwvif)
2163 		rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
2164 
2165 	return tfc_changed;
2166 }
2167 
rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2168 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
2169 {
2170 	if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION &&
2171 	    rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT)
2172 		return;
2173 
2174 	if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE &&
2175 	    rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE)
2176 		rtw89_enter_lps(rtwdev, rtwvif);
2177 }
2178 
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)2179 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
2180 {
2181 	struct rtw89_vif *rtwvif;
2182 
2183 	rtw89_for_each_rtwvif(rtwdev, rtwvif)
2184 		rtw89_vif_enter_lps(rtwdev, rtwvif);
2185 }
2186 
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2187 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
2188 			      struct rtw89_traffic_stats *stats)
2189 {
2190 	stats->tx_unicast = 0;
2191 	stats->rx_unicast = 0;
2192 	stats->tx_cnt = 0;
2193 	stats->rx_cnt = 0;
2194 	ewma_tp_init(&stats->tx_ewma_tp);
2195 	ewma_tp_init(&stats->rx_ewma_tp);
2196 }
2197 
rtw89_track_work(struct work_struct * work)2198 static void rtw89_track_work(struct work_struct *work)
2199 {
2200 	struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2201 						track_work.work);
2202 	bool tfc_changed;
2203 
2204 	mutex_lock(&rtwdev->mutex);
2205 
2206 	if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
2207 		goto out;
2208 
2209 	ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
2210 				     RTW89_TRACK_WORK_PERIOD);
2211 
2212 	tfc_changed = rtw89_traffic_stats_track(rtwdev);
2213 	if (rtwdev->scanning)
2214 		goto out;
2215 
2216 	rtw89_leave_lps(rtwdev);
2217 
2218 	if (tfc_changed) {
2219 		rtw89_hci_recalc_int_mit(rtwdev);
2220 		rtw89_btc_ntfy_wl_sta(rtwdev);
2221 	}
2222 	rtw89_mac_bf_monitor_track(rtwdev);
2223 	rtw89_phy_stat_track(rtwdev);
2224 	rtw89_phy_env_monitor_track(rtwdev);
2225 	rtw89_phy_dig(rtwdev);
2226 	rtw89_chip_rfk_track(rtwdev);
2227 	rtw89_phy_ra_update(rtwdev);
2228 	rtw89_phy_cfo_track(rtwdev);
2229 	rtw89_phy_tx_path_div_track(rtwdev);
2230 
2231 	if (rtwdev->lps_enabled && !rtwdev->btc.lps)
2232 		rtw89_enter_lps_track(rtwdev);
2233 
2234 out:
2235 	mutex_unlock(&rtwdev->mutex);
2236 }
2237 
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)2238 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
2239 {
2240 	unsigned long bit;
2241 
2242 	bit = find_first_zero_bit(addr, size);
2243 	if (bit < size)
2244 		set_bit(bit, addr);
2245 
2246 	return bit;
2247 }
2248 
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)2249 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
2250 {
2251 	clear_bit(bit, addr);
2252 }
2253 
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)2254 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
2255 {
2256 	bitmap_zero(addr, nbits);
2257 }
2258 
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2259 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
2260 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
2261 {
2262 	const struct rtw89_chip_info *chip = rtwdev->chip;
2263 	struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2264 	struct rtw89_ba_cam_entry *entry = NULL, *tmp;
2265 	u8 idx;
2266 	int i;
2267 
2268 	lockdep_assert_held(&rtwdev->mutex);
2269 
2270 	idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
2271 	if (idx == chip->bacam_num) {
2272 		/* allocate a static BA CAM to tid=0/5, so replace the existing
2273 		 * one if BA CAM is full. Hardware will process the original tid
2274 		 * automatically.
2275 		 */
2276 		if (tid != 0 && tid != 5)
2277 			return -ENOSPC;
2278 
2279 		for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
2280 			tmp = &cam_info->ba_cam_entry[i];
2281 			if (tmp->tid == 0 || tmp->tid == 5)
2282 				continue;
2283 
2284 			idx = i;
2285 			entry = tmp;
2286 			list_del(&entry->list);
2287 			break;
2288 		}
2289 
2290 		if (!entry)
2291 			return -ENOSPC;
2292 	} else {
2293 		entry = &cam_info->ba_cam_entry[idx];
2294 	}
2295 
2296 	entry->tid = tid;
2297 	list_add_tail(&entry->list, &rtwsta->ba_cam_list);
2298 
2299 	*cam_idx = idx;
2300 
2301 	return 0;
2302 }
2303 
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2304 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
2305 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
2306 {
2307 	struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2308 	struct rtw89_ba_cam_entry *entry = NULL, *tmp;
2309 	u8 idx;
2310 
2311 	lockdep_assert_held(&rtwdev->mutex);
2312 
2313 	list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) {
2314 		if (entry->tid != tid)
2315 			continue;
2316 
2317 		idx = entry - cam_info->ba_cam_entry;
2318 		list_del(&entry->list);
2319 
2320 		rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
2321 		*cam_idx = idx;
2322 		return 0;
2323 	}
2324 
2325 	return -ENOENT;
2326 }
2327 
2328 #define RTW89_TYPE_MAPPING(_type)	\
2329 	case NL80211_IFTYPE_ ## _type:	\
2330 		rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type;	\
2331 		break
rtw89_vif_type_mapping(struct ieee80211_vif * vif,bool assoc)2332 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc)
2333 {
2334 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2335 
2336 	switch (vif->type) {
2337 	case NL80211_IFTYPE_STATION:
2338 		if (vif->p2p)
2339 			rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
2340 		else
2341 			rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION;
2342 		break;
2343 	case NL80211_IFTYPE_AP:
2344 		if (vif->p2p)
2345 			rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
2346 		else
2347 			rtwvif->wifi_role = RTW89_WIFI_ROLE_AP;
2348 		break;
2349 	RTW89_TYPE_MAPPING(ADHOC);
2350 	RTW89_TYPE_MAPPING(MONITOR);
2351 	RTW89_TYPE_MAPPING(MESH_POINT);
2352 	default:
2353 		WARN_ON(1);
2354 		break;
2355 	}
2356 
2357 	switch (vif->type) {
2358 	case NL80211_IFTYPE_AP:
2359 	case NL80211_IFTYPE_MESH_POINT:
2360 		rtwvif->net_type = RTW89_NET_TYPE_AP_MODE;
2361 		rtwvif->self_role = RTW89_SELF_ROLE_AP;
2362 		break;
2363 	case NL80211_IFTYPE_ADHOC:
2364 		rtwvif->net_type = RTW89_NET_TYPE_AD_HOC;
2365 		rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
2366 		break;
2367 	case NL80211_IFTYPE_STATION:
2368 		if (assoc) {
2369 			rtwvif->net_type = RTW89_NET_TYPE_INFRA;
2370 			rtwvif->trigger = vif->bss_conf.he_support;
2371 		} else {
2372 			rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
2373 			rtwvif->trigger = false;
2374 		}
2375 		rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
2376 		rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
2377 		break;
2378 	default:
2379 		WARN_ON(1);
2380 		break;
2381 	}
2382 }
2383 
rtw89_core_sta_add(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2384 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
2385 		       struct ieee80211_vif *vif,
2386 		       struct ieee80211_sta *sta)
2387 {
2388 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2389 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2390 	int i;
2391 
2392 	rtwsta->rtwdev = rtwdev;
2393 	rtwsta->rtwvif = rtwvif;
2394 	rtwsta->prev_rssi = 0;
2395 	INIT_LIST_HEAD(&rtwsta->ba_cam_list);
2396 
2397 	for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
2398 		rtw89_core_txq_init(rtwdev, sta->txq[i]);
2399 
2400 	ewma_rssi_init(&rtwsta->avg_rssi);
2401 	for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2402 		ewma_rssi_init(&rtwsta->rssi[i]);
2403 
2404 	if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
2405 		/* for station mode, assign the mac_id from itself */
2406 		rtwsta->mac_id = rtwvif->mac_id;
2407 		rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
2408 					 BTC_ROLE_MSTS_STA_CONN_START);
2409 		rtw89_chip_rfk_channel(rtwdev);
2410 	} else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
2411 		rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
2412 							    RTW89_MAX_MAC_ID_NUM);
2413 	}
2414 
2415 	return 0;
2416 }
2417 
rtw89_core_sta_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2418 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
2419 			    struct ieee80211_vif *vif,
2420 			    struct ieee80211_sta *sta)
2421 {
2422 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2423 
2424 	rtwdev->total_sta_assoc--;
2425 	rtwsta->disassoc = true;
2426 
2427 	return 0;
2428 }
2429 
rtw89_core_sta_disconnect(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2430 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
2431 			      struct ieee80211_vif *vif,
2432 			      struct ieee80211_sta *sta)
2433 {
2434 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2435 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2436 	int ret;
2437 
2438 	rtw89_mac_bf_monitor_calc(rtwdev, sta, true);
2439 	rtw89_mac_bf_disassoc(rtwdev, vif, sta);
2440 	rtw89_core_free_sta_pending_ba(rtwdev, sta);
2441 	rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta);
2442 	if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
2443 		rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam);
2444 	if (sta->tdls)
2445 		rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam);
2446 
2447 	if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls)
2448 		rtw89_vif_type_mapping(vif, false);
2449 
2450 	ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
2451 	if (ret) {
2452 		rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
2453 		return ret;
2454 	}
2455 
2456 	ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true);
2457 	if (ret) {
2458 		rtw89_warn(rtwdev, "failed to send h2c join info\n");
2459 		return ret;
2460 	}
2461 
2462 	if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
2463 		ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_REMOVE);
2464 		if (ret) {
2465 			rtw89_warn(rtwdev, "failed to send h2c role info\n");
2466 			return ret;
2467 		}
2468 	}
2469 
2470 	/* update cam aid mac_id net_type */
2471 	ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
2472 	if (ret) {
2473 		rtw89_warn(rtwdev, "failed to send h2c cam\n");
2474 		return ret;
2475 	}
2476 
2477 	return ret;
2478 }
2479 
rtw89_core_sta_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2480 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
2481 			 struct ieee80211_vif *vif,
2482 			 struct ieee80211_sta *sta)
2483 {
2484 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2485 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2486 	struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta);
2487 	int ret;
2488 
2489 	if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
2490 		ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false);
2491 		if (ret) {
2492 			rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
2493 			return ret;
2494 		}
2495 
2496 		ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, RTW89_ROLE_CREATE);
2497 		if (ret) {
2498 			rtw89_warn(rtwdev, "failed to send h2c role info\n");
2499 			return ret;
2500 		}
2501 
2502 		if (sta->tdls) {
2503 			ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr);
2504 			if (ret) {
2505 				rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
2506 				return ret;
2507 			}
2508 		}
2509 
2510 		ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam);
2511 		if (ret) {
2512 			rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
2513 			return ret;
2514 		}
2515 	}
2516 
2517 	ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
2518 	if (ret) {
2519 		rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
2520 		return ret;
2521 	}
2522 
2523 	ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false);
2524 	if (ret) {
2525 		rtw89_warn(rtwdev, "failed to send h2c join info\n");
2526 		return ret;
2527 	}
2528 
2529 	/* update cam aid mac_id net_type */
2530 	ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
2531 	if (ret) {
2532 		rtw89_warn(rtwdev, "failed to send h2c cam\n");
2533 		return ret;
2534 	}
2535 
2536 	ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id);
2537 	if (ret) {
2538 		rtw89_warn(rtwdev, "failed to send h2c general packet\n");
2539 		return ret;
2540 	}
2541 
2542 	rtwdev->total_sta_assoc++;
2543 	rtw89_phy_ra_assoc(rtwdev, sta);
2544 	rtw89_mac_bf_assoc(rtwdev, vif, sta);
2545 	rtw89_mac_bf_monitor_calc(rtwdev, sta, false);
2546 
2547 	if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
2548 		rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
2549 					 BTC_ROLE_MSTS_STA_CONN_END);
2550 		rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template);
2551 	}
2552 
2553 	return ret;
2554 }
2555 
rtw89_core_sta_remove(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2556 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
2557 			  struct ieee80211_vif *vif,
2558 			  struct ieee80211_sta *sta)
2559 {
2560 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2561 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2562 
2563 	if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls)
2564 		rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
2565 					 BTC_ROLE_MSTS_STA_DIS_CONN);
2566 	else if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
2567 		rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id);
2568 
2569 	return 0;
2570 }
2571 
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)2572 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
2573 				       struct ieee80211_sta *sta,
2574 				       struct cfg80211_tid_cfg *tid_conf)
2575 {
2576 	struct ieee80211_txq *txq;
2577 	struct rtw89_txq *rtwtxq;
2578 	u32 mask = tid_conf->mask;
2579 	u8 tids = tid_conf->tids;
2580 	int tids_nbit = BITS_PER_BYTE;
2581 	int i;
2582 
2583 	for (i = 0; i < tids_nbit; i++, tids >>= 1) {
2584 		if (!tids)
2585 			break;
2586 
2587 		if (!(tids & BIT(0)))
2588 			continue;
2589 
2590 		txq = sta->txq[i];
2591 		rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2592 
2593 		if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
2594 			if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
2595 				clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2596 			} else {
2597 				if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
2598 					ieee80211_stop_tx_ba_session(sta, txq->tid);
2599 				spin_lock_bh(&rtwdev->ba_lock);
2600 				list_del_init(&rtwtxq->list);
2601 				set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2602 				spin_unlock_bh(&rtwdev->ba_lock);
2603 			}
2604 		}
2605 
2606 		if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
2607 			if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
2608 				sta->max_amsdu_subframes = 0;
2609 			else
2610 				sta->max_amsdu_subframes = 1;
2611 		}
2612 	}
2613 }
2614 
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)2615 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
2616 			       struct ieee80211_sta *sta,
2617 			       struct cfg80211_tid_config *tid_config)
2618 {
2619 	int i;
2620 
2621 	for (i = 0; i < tid_config->n_tid_conf; i++)
2622 		_rtw89_core_set_tid_config(rtwdev, sta,
2623 					   &tid_config->tid_conf[i]);
2624 }
2625 
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)2626 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
2627 			      struct ieee80211_sta_ht_cap *ht_cap)
2628 {
2629 	static const __le16 highest[RF_PATH_MAX] = {
2630 		cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
2631 	};
2632 	struct rtw89_hal *hal = &rtwdev->hal;
2633 	u8 nss = hal->rx_nss;
2634 	int i;
2635 
2636 	ht_cap->ht_supported = true;
2637 	ht_cap->cap = 0;
2638 	ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
2639 		       IEEE80211_HT_CAP_MAX_AMSDU |
2640 		       IEEE80211_HT_CAP_TX_STBC |
2641 		       (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
2642 	ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
2643 	ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2644 		       IEEE80211_HT_CAP_DSSSCCK40 |
2645 		       IEEE80211_HT_CAP_SGI_40;
2646 	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2647 	ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
2648 	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
2649 	for (i = 0; i < nss; i++)
2650 		ht_cap->mcs.rx_mask[i] = 0xFF;
2651 	ht_cap->mcs.rx_mask[4] = 0x01;
2652 	ht_cap->mcs.rx_highest = highest[nss - 1];
2653 }
2654 
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)2655 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
2656 			       struct ieee80211_sta_vht_cap *vht_cap)
2657 {
2658 	static const __le16 highest_bw80[RF_PATH_MAX] = {
2659 		cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
2660 	};
2661 	static const __le16 highest_bw160[RF_PATH_MAX] = {
2662 		cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
2663 	};
2664 	const struct rtw89_chip_info *chip = rtwdev->chip;
2665 	const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80;
2666 	struct rtw89_hal *hal = &rtwdev->hal;
2667 	u16 tx_mcs_map = 0, rx_mcs_map = 0;
2668 	u8 sts_cap = 3;
2669 	int i;
2670 
2671 	for (i = 0; i < 8; i++) {
2672 		if (i < hal->tx_nss)
2673 			tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
2674 		else
2675 			tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
2676 		if (i < hal->rx_nss)
2677 			rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
2678 		else
2679 			rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
2680 	}
2681 
2682 	vht_cap->vht_supported = true;
2683 	vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
2684 		       IEEE80211_VHT_CAP_SHORT_GI_80 |
2685 		       IEEE80211_VHT_CAP_RXSTBC_1 |
2686 		       IEEE80211_VHT_CAP_HTC_VHT |
2687 		       IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
2688 		       0;
2689 	vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
2690 	vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
2691 	vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
2692 			IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
2693 	vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
2694 	if (chip->support_bw160)
2695 		vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
2696 				IEEE80211_VHT_CAP_SHORT_GI_160;
2697 	vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
2698 	vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
2699 	vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
2700 	vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
2701 }
2702 
2703 #define RTW89_SBAND_IFTYPES_NR 2
2704 
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)2705 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
2706 			      enum nl80211_band band,
2707 			      struct ieee80211_supported_band *sband)
2708 {
2709 	const struct rtw89_chip_info *chip = rtwdev->chip;
2710 	struct rtw89_hal *hal = &rtwdev->hal;
2711 	struct ieee80211_sband_iftype_data *iftype_data;
2712 	bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
2713 		       (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
2714 	u16 mcs_map = 0;
2715 	int i;
2716 	int nss = hal->rx_nss;
2717 	int idx = 0;
2718 
2719 	iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
2720 	if (!iftype_data)
2721 		return;
2722 
2723 	for (i = 0; i < 8; i++) {
2724 		if (i < nss)
2725 			mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
2726 		else
2727 			mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
2728 	}
2729 
2730 	for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
2731 		struct ieee80211_sta_he_cap *he_cap;
2732 		u8 *mac_cap_info;
2733 		u8 *phy_cap_info;
2734 
2735 		switch (i) {
2736 		case NL80211_IFTYPE_STATION:
2737 		case NL80211_IFTYPE_AP:
2738 			break;
2739 		default:
2740 			continue;
2741 		}
2742 
2743 		if (idx >= RTW89_SBAND_IFTYPES_NR) {
2744 			rtw89_warn(rtwdev, "run out of iftype_data\n");
2745 			break;
2746 		}
2747 
2748 		iftype_data[idx].types_mask = BIT(i);
2749 		he_cap = &iftype_data[idx].he_cap;
2750 		mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
2751 		phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
2752 
2753 		he_cap->has_he = true;
2754 		mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
2755 		if (i == NL80211_IFTYPE_STATION)
2756 			mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
2757 		mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
2758 				  IEEE80211_HE_MAC_CAP2_BSR;
2759 		mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
2760 		if (i == NL80211_IFTYPE_AP)
2761 			mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
2762 		mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
2763 				  IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
2764 		if (i == NL80211_IFTYPE_STATION)
2765 			mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
2766 		if (band == NL80211_BAND_2GHZ) {
2767 			phy_cap_info[0] =
2768 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
2769 		} else {
2770 			phy_cap_info[0] =
2771 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
2772 			if (chip->support_bw160)
2773 				phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
2774 		}
2775 		phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
2776 				  IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
2777 				  IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
2778 		phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
2779 				  IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
2780 				  IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
2781 				  IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
2782 		phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
2783 		if (i == NL80211_IFTYPE_STATION)
2784 			phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
2785 					   IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
2786 		if (i == NL80211_IFTYPE_AP)
2787 			phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
2788 		phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
2789 				  IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
2790 		if (chip->support_bw160)
2791 			phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
2792 		phy_cap_info[5] = no_ng16 ? 0 :
2793 				  IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
2794 				  IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
2795 		phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
2796 				  IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
2797 				  IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
2798 				  IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
2799 		phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
2800 				  IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
2801 				  IEEE80211_HE_PHY_CAP7_MAX_NC_1;
2802 		phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
2803 				  IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
2804 				  IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
2805 		if (chip->support_bw160)
2806 			phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
2807 					   IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
2808 		phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
2809 				  IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
2810 				  IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
2811 				  IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
2812 				  u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
2813 						 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
2814 		if (i == NL80211_IFTYPE_STATION)
2815 			phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
2816 		he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
2817 		he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
2818 		if (chip->support_bw160) {
2819 			he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
2820 			he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
2821 		}
2822 
2823 		if (band == NL80211_BAND_6GHZ) {
2824 			__le16 capa;
2825 
2826 			capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
2827 						IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
2828 			       le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
2829 						IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
2830 			       le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2831 						IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
2832 			iftype_data[idx].he_6ghz_capa.capa = capa;
2833 		}
2834 
2835 		idx++;
2836 	}
2837 
2838 	sband->iftype_data = iftype_data;
2839 	sband->n_iftype_data = idx;
2840 }
2841 
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)2842 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
2843 {
2844 	struct ieee80211_hw *hw = rtwdev->hw;
2845 	struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
2846 	struct ieee80211_supported_band *sband_6ghz = NULL;
2847 	u32 size = sizeof(struct ieee80211_supported_band);
2848 	u8 support_bands = rtwdev->chip->support_bands;
2849 
2850 	if (support_bands & BIT(NL80211_BAND_2GHZ)) {
2851 		sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
2852 		if (!sband_2ghz)
2853 			goto err;
2854 		rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
2855 		rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
2856 		hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
2857 	}
2858 
2859 	if (support_bands & BIT(NL80211_BAND_5GHZ)) {
2860 		sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
2861 		if (!sband_5ghz)
2862 			goto err;
2863 		rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
2864 		rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
2865 		rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
2866 		hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
2867 	}
2868 
2869 	if (support_bands & BIT(NL80211_BAND_6GHZ)) {
2870 		sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
2871 		if (!sband_6ghz)
2872 			goto err;
2873 		rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
2874 		hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
2875 	}
2876 
2877 	return 0;
2878 
2879 err:
2880 	hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
2881 	hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
2882 	hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
2883 	if (sband_2ghz)
2884 		kfree(sband_2ghz->iftype_data);
2885 	if (sband_5ghz)
2886 		kfree(sband_5ghz->iftype_data);
2887 	if (sband_6ghz)
2888 		kfree(sband_6ghz->iftype_data);
2889 	kfree(sband_2ghz);
2890 	kfree(sband_5ghz);
2891 	kfree(sband_6ghz);
2892 	return -ENOMEM;
2893 }
2894 
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)2895 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
2896 {
2897 	struct ieee80211_hw *hw = rtwdev->hw;
2898 
2899 	kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
2900 	kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
2901 	if (hw->wiphy->bands[NL80211_BAND_6GHZ])
2902 		kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
2903 	kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
2904 	kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
2905 	kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
2906 	hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
2907 	hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
2908 	hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
2909 }
2910 
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)2911 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
2912 {
2913 	int i;
2914 
2915 	for (i = 0; i < RTW89_PHY_MAX; i++)
2916 		skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
2917 	for (i = 0; i < RTW89_PHY_MAX; i++)
2918 		rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
2919 }
2920 
rtw89_core_update_beacon_work(struct work_struct * work)2921 void rtw89_core_update_beacon_work(struct work_struct *work)
2922 {
2923 	struct rtw89_dev *rtwdev;
2924 	struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
2925 						update_beacon_work);
2926 
2927 	if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE)
2928 		return;
2929 
2930 	rtwdev = rtwvif->rtwdev;
2931 	mutex_lock(&rtwdev->mutex);
2932 	rtw89_fw_h2c_update_beacon(rtwdev, rtwvif);
2933 	mutex_unlock(&rtwdev->mutex);
2934 }
2935 
rtw89_core_start(struct rtw89_dev * rtwdev)2936 int rtw89_core_start(struct rtw89_dev *rtwdev)
2937 {
2938 	int ret;
2939 
2940 	rtwdev->mac.qta_mode = RTW89_QTA_SCC;
2941 	ret = rtw89_mac_init(rtwdev);
2942 	if (ret) {
2943 		rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
2944 		return ret;
2945 	}
2946 
2947 	rtw89_btc_ntfy_poweron(rtwdev);
2948 
2949 	/* efuse process */
2950 
2951 	/* pre-config BB/RF, BB reset/RFC reset */
2952 	ret = rtw89_chip_disable_bb_rf(rtwdev);
2953 	if (ret)
2954 		return ret;
2955 	ret = rtw89_chip_enable_bb_rf(rtwdev);
2956 	if (ret)
2957 		return ret;
2958 
2959 	rtw89_phy_init_bb_reg(rtwdev);
2960 	rtw89_phy_init_rf_reg(rtwdev);
2961 
2962 	rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
2963 
2964 	rtw89_phy_dm_init(rtwdev);
2965 
2966 	rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
2967 	rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0);
2968 
2969 	ret = rtw89_hci_start(rtwdev);
2970 	if (ret) {
2971 		rtw89_err(rtwdev, "failed to start hci\n");
2972 		return ret;
2973 	}
2974 
2975 	ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
2976 				     RTW89_TRACK_WORK_PERIOD);
2977 
2978 	set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
2979 
2980 	rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
2981 	rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable);
2982 	rtw89_fw_h2c_init_ba_cam(rtwdev);
2983 
2984 	return 0;
2985 }
2986 
rtw89_core_stop(struct rtw89_dev * rtwdev)2987 void rtw89_core_stop(struct rtw89_dev *rtwdev)
2988 {
2989 	struct rtw89_btc *btc = &rtwdev->btc;
2990 
2991 	/* Prvent to stop twice; enter_ips and ops_stop */
2992 	if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
2993 		return;
2994 
2995 	rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
2996 
2997 	clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
2998 
2999 	mutex_unlock(&rtwdev->mutex);
3000 
3001 	cancel_work_sync(&rtwdev->c2h_work);
3002 	cancel_work_sync(&btc->eapol_notify_work);
3003 	cancel_work_sync(&btc->arp_notify_work);
3004 	cancel_work_sync(&btc->dhcp_notify_work);
3005 	cancel_work_sync(&btc->icmp_notify_work);
3006 	cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
3007 	cancel_delayed_work_sync(&rtwdev->track_work);
3008 	cancel_delayed_work_sync(&rtwdev->coex_act1_work);
3009 	cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
3010 	cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
3011 	cancel_delayed_work_sync(&rtwdev->cfo_track_work);
3012 	cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
3013 
3014 	mutex_lock(&rtwdev->mutex);
3015 
3016 	rtw89_btc_ntfy_poweroff(rtwdev);
3017 	rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
3018 	rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
3019 	rtw89_hci_stop(rtwdev);
3020 	rtw89_hci_deinit(rtwdev);
3021 	rtw89_mac_pwr_off(rtwdev);
3022 	rtw89_hci_reset(rtwdev);
3023 }
3024 
rtw89_core_init(struct rtw89_dev * rtwdev)3025 int rtw89_core_init(struct rtw89_dev *rtwdev)
3026 {
3027 	struct rtw89_btc *btc = &rtwdev->btc;
3028 	int ret;
3029 	u8 band;
3030 
3031 	INIT_LIST_HEAD(&rtwdev->ba_list);
3032 	INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
3033 	INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
3034 	INIT_LIST_HEAD(&rtwdev->early_h2c_list);
3035 	for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
3036 		if (!(rtwdev->chip->support_bands & BIT(band)))
3037 			continue;
3038 		INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
3039 	}
3040 	INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
3041 	INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
3042 	INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
3043 	INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
3044 	INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
3045 	INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
3046 	INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
3047 	INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
3048 	INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
3049 	rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
3050 	spin_lock_init(&rtwdev->ba_lock);
3051 	spin_lock_init(&rtwdev->rpwm_lock);
3052 	mutex_init(&rtwdev->mutex);
3053 	mutex_init(&rtwdev->rf_mutex);
3054 	rtwdev->total_sta_assoc = 0;
3055 
3056 	INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
3057 	INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
3058 	skb_queue_head_init(&rtwdev->c2h_queue);
3059 	rtw89_core_ppdu_sts_init(rtwdev);
3060 	rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
3061 
3062 	rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
3063 	rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
3064 
3065 	INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
3066 	INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
3067 	INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
3068 	INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
3069 
3070 	ret = rtw89_load_firmware(rtwdev);
3071 	if (ret) {
3072 		rtw89_warn(rtwdev, "no firmware loaded\n");
3073 		return ret;
3074 	}
3075 	rtw89_ser_init(rtwdev);
3076 	rtw89_entity_init(rtwdev);
3077 
3078 	return 0;
3079 }
3080 EXPORT_SYMBOL(rtw89_core_init);
3081 
rtw89_core_deinit(struct rtw89_dev * rtwdev)3082 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
3083 {
3084 	rtw89_ser_deinit(rtwdev);
3085 	rtw89_unload_firmware(rtwdev);
3086 	rtw89_fw_free_all_early_h2c(rtwdev);
3087 
3088 	destroy_workqueue(rtwdev->txq_wq);
3089 	mutex_destroy(&rtwdev->rf_mutex);
3090 	mutex_destroy(&rtwdev->mutex);
3091 }
3092 EXPORT_SYMBOL(rtw89_core_deinit);
3093 
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,const u8 * mac_addr,bool hw_scan)3094 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3095 			   const u8 *mac_addr, bool hw_scan)
3096 {
3097 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
3098 
3099 	rtwdev->scanning = true;
3100 	rtw89_leave_lps(rtwdev);
3101 	if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
3102 		rtw89_leave_ips(rtwdev);
3103 
3104 	ether_addr_copy(rtwvif->mac_addr, mac_addr);
3105 	rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type);
3106 	rtw89_chip_rfk_scan(rtwdev, true);
3107 	rtw89_hci_recalc_int_mit(rtwdev);
3108 
3109 	rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr);
3110 }
3111 
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)3112 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
3113 			      struct ieee80211_vif *vif, bool hw_scan)
3114 {
3115 	struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
3116 
3117 	if (!rtwvif)
3118 		return;
3119 
3120 	ether_addr_copy(rtwvif->mac_addr, vif->addr);
3121 	rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3122 
3123 	rtw89_chip_rfk_scan(rtwdev, false);
3124 	rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0);
3125 
3126 	rtwdev->scanning = false;
3127 	rtwdev->dig.bypass_dig = true;
3128 	if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
3129 		ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
3130 }
3131 
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)3132 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
3133 {
3134 	const struct rtw89_chip_info *chip = rtwdev->chip;
3135 	u8 cv;
3136 
3137 	cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
3138 	if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
3139 		if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
3140 			cv = CHIP_CAV;
3141 		else
3142 			cv = CHIP_CBV;
3143 	}
3144 
3145 	rtwdev->hal.cv = cv;
3146 }
3147 
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)3148 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
3149 {
3150 	rtwdev->hal.support_cckpd =
3151 		!(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
3152 		!(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
3153 	rtwdev->hal.support_igi =
3154 		rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
3155 }
3156 
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)3157 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
3158 {
3159 	int ret;
3160 
3161 	ret = rtw89_mac_partial_init(rtwdev);
3162 	if (ret)
3163 		return ret;
3164 
3165 	ret = rtw89_parse_efuse_map(rtwdev);
3166 	if (ret)
3167 		return ret;
3168 
3169 	ret = rtw89_parse_phycap_map(rtwdev);
3170 	if (ret)
3171 		return ret;
3172 
3173 	ret = rtw89_mac_setup_phycap(rtwdev);
3174 	if (ret)
3175 		return ret;
3176 
3177 	rtw89_core_setup_phycap(rtwdev);
3178 
3179 	rtw89_mac_pwr_off(rtwdev);
3180 
3181 	return 0;
3182 }
3183 
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)3184 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
3185 {
3186 	rtw89_chip_fem_setup(rtwdev);
3187 
3188 	return 0;
3189 }
3190 
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)3191 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
3192 {
3193 	int ret;
3194 
3195 	rtw89_read_chip_ver(rtwdev);
3196 
3197 	ret = rtw89_wait_firmware_completion(rtwdev);
3198 	if (ret) {
3199 		rtw89_err(rtwdev, "failed to wait firmware completion\n");
3200 		return ret;
3201 	}
3202 
3203 	ret = rtw89_fw_recognize(rtwdev);
3204 	if (ret) {
3205 		rtw89_err(rtwdev, "failed to recognize firmware\n");
3206 		return ret;
3207 	}
3208 
3209 	ret = rtw89_chip_efuse_info_setup(rtwdev);
3210 	if (ret)
3211 		return ret;
3212 
3213 	ret = rtw89_chip_board_info_setup(rtwdev);
3214 	if (ret)
3215 		return ret;
3216 
3217 	return 0;
3218 }
3219 EXPORT_SYMBOL(rtw89_chip_info_setup);
3220 
rtw89_core_register_hw(struct rtw89_dev * rtwdev)3221 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
3222 {
3223 	struct ieee80211_hw *hw = rtwdev->hw;
3224 	struct rtw89_efuse *efuse = &rtwdev->efuse;
3225 	int ret;
3226 	int tx_headroom = IEEE80211_HT_CTL_LEN;
3227 
3228 	hw->vif_data_size = sizeof(struct rtw89_vif);
3229 	hw->sta_data_size = sizeof(struct rtw89_sta);
3230 	hw->txq_data_size = sizeof(struct rtw89_txq);
3231 	hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
3232 
3233 	SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
3234 
3235 	hw->extra_tx_headroom = tx_headroom;
3236 	hw->queues = IEEE80211_NUM_ACS;
3237 	hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
3238 	hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
3239 	hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
3240 
3241 	ieee80211_hw_set(hw, SIGNAL_DBM);
3242 	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
3243 	ieee80211_hw_set(hw, MFP_CAPABLE);
3244 	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
3245 	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
3246 	ieee80211_hw_set(hw, RX_INCLUDES_FCS);
3247 	ieee80211_hw_set(hw, TX_AMSDU);
3248 	ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
3249 	ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
3250 	ieee80211_hw_set(hw, SUPPORTS_PS);
3251 	ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3252 	ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
3253 	ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
3254 
3255 	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
3256 				     BIT(NL80211_IFTYPE_AP) |
3257 				     BIT(NL80211_IFTYPE_P2P_CLIENT) |
3258 				     BIT(NL80211_IFTYPE_P2P_GO);
3259 
3260 	hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
3261 	hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
3262 
3263 	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
3264 			    WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
3265 			    WIPHY_FLAG_AP_UAPSD;
3266 	hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
3267 
3268 	hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
3269 	hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
3270 
3271 	hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
3272 	hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
3273 	hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
3274 	hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
3275 
3276 	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
3277 
3278 	ret = rtw89_core_set_supported_band(rtwdev);
3279 	if (ret) {
3280 		rtw89_err(rtwdev, "failed to set supported band\n");
3281 		return ret;
3282 	}
3283 
3284 	hw->wiphy->reg_notifier = rtw89_regd_notifier;
3285 	hw->wiphy->sar_capa = &rtw89_sar_capa;
3286 
3287 	ret = ieee80211_register_hw(hw);
3288 	if (ret) {
3289 		rtw89_err(rtwdev, "failed to register hw\n");
3290 		goto err;
3291 	}
3292 
3293 	ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
3294 	if (ret) {
3295 		rtw89_err(rtwdev, "failed to init regd\n");
3296 		goto err;
3297 	}
3298 
3299 	return 0;
3300 
3301 err:
3302 	return ret;
3303 }
3304 
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)3305 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
3306 {
3307 	struct ieee80211_hw *hw = rtwdev->hw;
3308 
3309 	ieee80211_unregister_hw(hw);
3310 	rtw89_core_clr_supported_band(rtwdev);
3311 }
3312 
rtw89_core_register(struct rtw89_dev * rtwdev)3313 int rtw89_core_register(struct rtw89_dev *rtwdev)
3314 {
3315 	int ret;
3316 
3317 	ret = rtw89_core_register_hw(rtwdev);
3318 	if (ret) {
3319 		rtw89_err(rtwdev, "failed to register core hw\n");
3320 		return ret;
3321 	}
3322 
3323 	rtw89_debugfs_init(rtwdev);
3324 
3325 	return 0;
3326 }
3327 EXPORT_SYMBOL(rtw89_core_register);
3328 
rtw89_core_unregister(struct rtw89_dev * rtwdev)3329 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
3330 {
3331 	rtw89_core_unregister_hw(rtwdev);
3332 }
3333 EXPORT_SYMBOL(rtw89_core_unregister);
3334 
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)3335 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
3336 					   u32 bus_data_size,
3337 					   const struct rtw89_chip_info *chip)
3338 {
3339 	struct ieee80211_hw *hw;
3340 	struct rtw89_dev *rtwdev;
3341 	struct ieee80211_ops *ops;
3342 	u32 driver_data_size;
3343 	u32 early_feat_map = 0;
3344 	bool no_chanctx;
3345 
3346 	rtw89_early_fw_feature_recognize(device, chip, &early_feat_map);
3347 
3348 	ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
3349 	if (!ops)
3350 		goto err;
3351 
3352 	no_chanctx = chip->support_chanctx_num == 0 ||
3353 		     !(early_feat_map & BIT(RTW89_FW_FEATURE_SCAN_OFFLOAD));
3354 
3355 	if (no_chanctx) {
3356 		ops->add_chanctx = NULL;
3357 		ops->remove_chanctx = NULL;
3358 		ops->change_chanctx = NULL;
3359 		ops->assign_vif_chanctx = NULL;
3360 		ops->unassign_vif_chanctx = NULL;
3361 	}
3362 
3363 	driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
3364 	hw = ieee80211_alloc_hw(driver_data_size, ops);
3365 	if (!hw)
3366 		goto err;
3367 
3368 	rtwdev = hw->priv;
3369 	rtwdev->hw = hw;
3370 	rtwdev->dev = device;
3371 	rtwdev->ops = ops;
3372 	rtwdev->chip = chip;
3373 
3374 	rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n",
3375 		    no_chanctx ? "without" : "with");
3376 
3377 	return rtwdev;
3378 
3379 err:
3380 	kfree(ops);
3381 	return NULL;
3382 }
3383 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
3384 
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)3385 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
3386 {
3387 	kfree(rtwdev->ops);
3388 	ieee80211_free_hw(rtwdev->hw);
3389 }
3390 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
3391 
3392 MODULE_AUTHOR("Realtek Corporation");
3393 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
3394 MODULE_LICENSE("Dual BSD/GPL");
3395