1 /* Driver for Realtek RTS51xx USB card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 * Maintainer:
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
24 */
25
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
29 #include <linux/workqueue.h>
30
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_eh.h>
33 #include <scsi/scsi_device.h>
34
35 #include "debug.h"
36 #include "rts51x.h"
37 #include "rts51x_chip.h"
38 #include "rts51x_card.h"
39 #include "rts51x_transport.h"
40 #include "rts51x_sys.h"
41 #include "xd.h"
42 #include "sd.h"
43 #include "ms.h"
44
do_remaining_work(struct rts51x_chip * chip)45 void do_remaining_work(struct rts51x_chip *chip)
46 {
47 struct sd_info *sd_card = &(chip->sd_card);
48 struct xd_info *xd_card = &(chip->xd_card);
49 struct ms_info *ms_card = &(chip->ms_card);
50
51 if (chip->card_ready & SD_CARD) {
52 if (sd_card->seq_mode) {
53 RTS51X_SET_STAT(chip, STAT_RUN);
54 sd_card->counter++;
55 } else {
56 sd_card->counter = 0;
57 }
58 }
59
60 if (chip->card_ready & XD_CARD) {
61 if (xd_card->delay_write.delay_write_flag) {
62 RTS51X_SET_STAT(chip, STAT_RUN);
63 xd_card->counter++;
64 } else {
65 xd_card->counter = 0;
66 }
67 }
68
69 if (chip->card_ready & MS_CARD) {
70 if (CHK_MSPRO(ms_card)) {
71 if (ms_card->seq_mode) {
72 RTS51X_SET_STAT(chip, STAT_RUN);
73 ms_card->counter++;
74 } else {
75 ms_card->counter = 0;
76 }
77 } else {
78 if (ms_card->delay_write.delay_write_flag) {
79 RTS51X_SET_STAT(chip, STAT_RUN);
80 ms_card->counter++;
81 } else {
82 ms_card->counter = 0;
83 }
84 }
85 }
86
87 if (sd_card->counter > POLLING_WAIT_CNT)
88 sd_cleanup_work(chip);
89
90 if (xd_card->counter > POLLING_WAIT_CNT)
91 xd_cleanup_work(chip);
92
93 if (ms_card->counter > POLLING_WAIT_CNT)
94 ms_cleanup_work(chip);
95 }
96
do_reset_xd_card(struct rts51x_chip * chip)97 void do_reset_xd_card(struct rts51x_chip *chip)
98 {
99 int retval;
100
101 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
102 return;
103
104 retval = reset_xd_card(chip);
105 if (retval == STATUS_SUCCESS) {
106 chip->card_ready |= XD_CARD;
107 chip->card_fail &= ~XD_CARD;
108 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
109 } else {
110 chip->card_ready &= ~XD_CARD;
111 chip->card_fail |= XD_CARD;
112 chip->capacity[chip->card2lun[XD_CARD]] = 0;
113 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
114
115 rts51x_init_cmd(chip);
116 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
117 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
118 POWER_OFF);
119 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
120 rts51x_send_cmd(chip, MODE_C, 100);
121 }
122 }
123
do_reset_sd_card(struct rts51x_chip * chip)124 void do_reset_sd_card(struct rts51x_chip *chip)
125 {
126 int retval;
127
128 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
129 return;
130
131 retval = reset_sd_card(chip);
132 if (retval == STATUS_SUCCESS) {
133 chip->card_ready |= SD_CARD;
134 chip->card_fail &= ~SD_CARD;
135 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
136 } else {
137 chip->card_ready &= ~SD_CARD;
138 chip->card_fail |= SD_CARD;
139 chip->capacity[chip->card2lun[SD_CARD]] = 0;
140 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
141
142 rts51x_init_cmd(chip);
143 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
144 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
145 POWER_OFF);
146 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
147 rts51x_send_cmd(chip, MODE_C, 100);
148 }
149 }
150
do_reset_ms_card(struct rts51x_chip * chip)151 void do_reset_ms_card(struct rts51x_chip *chip)
152 {
153 int retval;
154
155 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
156 return;
157
158 retval = reset_ms_card(chip);
159 if (retval == STATUS_SUCCESS) {
160 chip->card_ready |= MS_CARD;
161 chip->card_fail &= ~MS_CARD;
162 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
163 } else {
164 chip->card_ready &= ~MS_CARD;
165 chip->card_fail |= MS_CARD;
166 chip->capacity[chip->card2lun[MS_CARD]] = 0;
167 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
168
169 rts51x_init_cmd(chip);
170 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
171 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
172 POWER_OFF);
173 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
174 rts51x_send_cmd(chip, MODE_C, 100);
175 }
176 }
177
card_cd_debounce(struct rts51x_chip * chip,u8 * need_reset,u8 * need_release)178 void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
179 u8 *need_release)
180 {
181 int retval;
182 u8 release_map = 0, reset_map = 0;
183 u8 value;
184
185 retval = rts51x_get_card_status(chip, &(chip->card_status));
186 #ifdef SUPPORT_OCP
187 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
188 #endif
189
190 if (retval != STATUS_SUCCESS)
191 goto Exit_Debounce;
192
193 if (chip->card_exist) {
194 rts51x_clear_start_time(chip);
195 retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
196 if (retval != STATUS_SUCCESS) {
197 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
198 FIFO_FLUSH);
199 rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
200 value = 0;
201 }
202
203 if (chip->card_exist & XD_CARD) {
204 if (!(chip->card_status & XD_CD))
205 release_map |= XD_CARD;
206 } else if (chip->card_exist & SD_CARD) {
207 /* if (!(chip->card_status & SD_CD)) { */
208 if (!(chip->card_status & SD_CD) || (value & SD_INT))
209 release_map |= SD_CARD;
210 } else if (chip->card_exist & MS_CARD) {
211 /* if (!(chip->card_status & MS_CD)) { */
212 if (!(chip->card_status & MS_CD) || (value & MS_INT))
213 release_map |= MS_CARD;
214 }
215 } else {
216 if (chip->card_status & XD_CD) {
217 rts51x_clear_start_time(chip);
218 reset_map |= XD_CARD;
219 } else if (chip->card_status & SD_CD) {
220 rts51x_clear_start_time(chip);
221 reset_map |= SD_CARD;
222 } else if (chip->card_status & MS_CD) {
223 rts51x_clear_start_time(chip);
224 reset_map |= MS_CARD;
225 } else {
226 if (rts51x_check_start_time(chip))
227 rts51x_set_start_time(chip);
228 }
229 }
230
231 if (CHECK_PKG(chip, QFN24) && reset_map) {
232 if (chip->card_exist & XD_CARD) {
233 reset_map = 0;
234 goto Exit_Debounce;
235 }
236 }
237
238 if (reset_map) {
239 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
240 int i;
241
242 for (i = 0; i < (chip->option.debounce_num); i++) {
243 retval =
244 rts51x_get_card_status(chip, &(chip->card_status));
245 if (retval != STATUS_SUCCESS) {
246 reset_map = release_map = 0;
247 goto Exit_Debounce;
248 }
249 if (chip->card_status & XD_CD)
250 xd_cnt++;
251 else
252 xd_cnt = 0;
253 if (chip->card_status & SD_CD)
254 sd_cnt++;
255 else
256 sd_cnt = 0;
257 if (chip->card_status & MS_CD)
258 ms_cnt++;
259 else
260 ms_cnt = 0;
261 wait_timeout(30);
262 }
263
264 reset_map = 0;
265 if (!(chip->card_exist & XD_CARD)
266 && (xd_cnt > (chip->option.debounce_num - 1))) {
267 reset_map |= XD_CARD;
268 }
269 if (!(chip->card_exist & SD_CARD)
270 && (sd_cnt > (chip->option.debounce_num - 1))) {
271 reset_map |= SD_CARD;
272 }
273 if (!(chip->card_exist & MS_CARD)
274 && (ms_cnt > (chip->option.debounce_num - 1))) {
275 reset_map |= MS_CARD;
276 }
277 }
278 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
279 XD_INT | MS_INT | SD_INT);
280
281 Exit_Debounce:
282 if (need_reset)
283 *need_reset = reset_map;
284 if (need_release)
285 *need_release = release_map;
286 }
287
rts51x_init_cards(struct rts51x_chip * chip)288 void rts51x_init_cards(struct rts51x_chip *chip)
289 {
290 u8 need_reset = 0, need_release = 0;
291
292 card_cd_debounce(chip, &need_reset, &need_release);
293
294 if (need_release) {
295 RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
296
297 rts51x_prepare_run(chip);
298 RTS51X_SET_STAT(chip, STAT_RUN);
299
300 #ifdef SUPPORT_OCP
301 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
302 rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
303 MS_OCP_CLEAR);
304 chip->ocp_stat = 0;
305 RTS51X_DEBUGP("Clear OCP status.\n");
306 }
307 #endif
308
309 if (need_release & XD_CARD) {
310 chip->card_exist &= ~XD_CARD;
311 chip->card_ejected = 0;
312 if (chip->card_ready & XD_CARD) {
313 release_xd_card(chip);
314 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
315 clear_bit(chip->card2lun[XD_CARD],
316 &(chip->lun_mc));
317 }
318 }
319
320 if (need_release & SD_CARD) {
321 chip->card_exist &= ~SD_CARD;
322 chip->card_ejected = 0;
323 if (chip->card_ready & SD_CARD) {
324 release_sd_card(chip);
325 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
326 clear_bit(chip->card2lun[SD_CARD],
327 &(chip->lun_mc));
328 }
329 }
330
331 if (need_release & MS_CARD) {
332 chip->card_exist &= ~MS_CARD;
333 chip->card_ejected = 0;
334 if (chip->card_ready & MS_CARD) {
335 release_ms_card(chip);
336 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
337 clear_bit(chip->card2lun[MS_CARD],
338 &(chip->lun_mc));
339 }
340 }
341 }
342
343 if (need_reset && !chip->card_ready) {
344 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
345
346 rts51x_prepare_run(chip);
347 RTS51X_SET_STAT(chip, STAT_RUN);
348
349 if (need_reset & XD_CARD) {
350 chip->card_exist |= XD_CARD;
351 do_reset_xd_card(chip);
352 } else if (need_reset & SD_CARD) {
353 chip->card_exist |= SD_CARD;
354 do_reset_sd_card(chip);
355 } else if (need_reset & MS_CARD) {
356 chip->card_exist |= MS_CARD;
357 do_reset_ms_card(chip);
358 }
359 }
360 }
361
rts51x_release_cards(struct rts51x_chip * chip)362 void rts51x_release_cards(struct rts51x_chip *chip)
363 {
364 if (chip->card_ready & SD_CARD) {
365 sd_cleanup_work(chip);
366 release_sd_card(chip);
367 chip->card_ready &= ~SD_CARD;
368 }
369
370 if (chip->card_ready & XD_CARD) {
371 xd_cleanup_work(chip);
372 release_xd_card(chip);
373 chip->card_ready &= ~XD_CARD;
374 }
375
376 if (chip->card_ready & MS_CARD) {
377 ms_cleanup_work(chip);
378 release_ms_card(chip);
379 chip->card_ready &= ~MS_CARD;
380 }
381 }
382
double_depth(u8 depth)383 static inline u8 double_depth(u8 depth)
384 {
385 return ((depth > 1) ? (depth - 1) : depth);
386 }
387
switch_ssc_clock(struct rts51x_chip * chip,int clk)388 int switch_ssc_clock(struct rts51x_chip *chip, int clk)
389 {
390 struct sd_info *sd_card = &(chip->sd_card);
391 struct ms_info *ms_card = &(chip->ms_card);
392 int retval;
393 u8 N = (u8) (clk - 2), min_N, max_N;
394 u8 mcu_cnt, div, max_div, ssc_depth;
395 int sd_vpclk_phase_reset = 0;
396
397 if (chip->cur_clk == clk)
398 return STATUS_SUCCESS;
399
400 min_N = 60;
401 max_N = 120;
402 max_div = CLK_DIV_4;
403
404 RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
405
406 if ((clk <= 2) || (N > max_N))
407 TRACE_RET(chip, STATUS_FAIL);
408
409 mcu_cnt = (u8) (60 / clk + 3);
410 if (mcu_cnt > 15)
411 mcu_cnt = 15;
412 /* To make sure that the SSC clock div_n is
413 * equal or greater than min_N */
414 div = CLK_DIV_1;
415 while ((N < min_N) && (div < max_div)) {
416 N = (N + 2) * 2 - 2;
417 div++;
418 }
419 RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
420
421 if (chip->option.ssc_en) {
422 if (chip->cur_card == SD_CARD) {
423 if (CHK_SD_SDR104(sd_card)) {
424 ssc_depth = chip->option.ssc_depth_sd_sdr104;
425 } else if (CHK_SD_SDR50(sd_card)) {
426 ssc_depth = chip->option.ssc_depth_sd_sdr50;
427 } else if (CHK_SD_DDR50(sd_card)) {
428 ssc_depth =
429 double_depth(chip->option.
430 ssc_depth_sd_ddr50);
431 } else if (CHK_SD_HS(sd_card)) {
432 ssc_depth =
433 double_depth(chip->option.ssc_depth_sd_hs);
434 } else if (CHK_MMC_52M(sd_card)
435 || CHK_MMC_DDR52(sd_card)) {
436 ssc_depth =
437 double_depth(chip->option.
438 ssc_depth_mmc_52m);
439 } else {
440 ssc_depth =
441 double_depth(chip->option.
442 ssc_depth_low_speed);
443 }
444 } else if (chip->cur_card == MS_CARD) {
445 if (CHK_MSPRO(ms_card)) {
446 if (CHK_HG8BIT(ms_card)) {
447 ssc_depth =
448 double_depth(chip->option.
449 ssc_depth_ms_hg);
450 } else {
451 ssc_depth =
452 double_depth(chip->option.
453 ssc_depth_ms_4bit);
454 }
455 } else {
456 if (CHK_MS4BIT(ms_card)) {
457 ssc_depth =
458 double_depth(chip->option.
459 ssc_depth_ms_4bit);
460 } else {
461 ssc_depth =
462 double_depth(chip->option.
463 ssc_depth_low_speed);
464 }
465 }
466 } else {
467 ssc_depth =
468 double_depth(chip->option.ssc_depth_low_speed);
469 }
470
471 if (ssc_depth) {
472 if (div == CLK_DIV_2) {
473 /* If clock divided by 2, ssc depth must
474 * be multiplied by 2 */
475 if (ssc_depth > 1)
476 ssc_depth -= 1;
477 else
478 ssc_depth = SSC_DEPTH_2M;
479 } else if (div == CLK_DIV_4) {
480 /* If clock divided by 4, ssc depth must
481 * be multiplied by 4 */
482 if (ssc_depth > 2)
483 ssc_depth -= 2;
484 else
485 ssc_depth = SSC_DEPTH_2M;
486 }
487 }
488 } else {
489 /* Disable SSC */
490 ssc_depth = 0;
491 }
492
493 RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
494
495 rts51x_init_cmd(chip);
496 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
497 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
498 (div << 4) | mcu_cnt);
499 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
500 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
501 ssc_depth);
502 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
503 if (sd_vpclk_phase_reset) {
504 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
505 PHASE_NOT_RESET, 0);
506 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
507 PHASE_NOT_RESET, PHASE_NOT_RESET);
508 }
509
510 retval = rts51x_send_cmd(chip, MODE_C, 2000);
511 if (retval != STATUS_SUCCESS)
512 TRACE_RET(chip, retval);
513 if (chip->option.ssc_en && ssc_depth)
514 rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
515 else
516 rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
517 udelay(100);
518 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
519
520 chip->cur_clk = clk;
521
522 return STATUS_SUCCESS;
523 }
524
switch_normal_clock(struct rts51x_chip * chip,int clk)525 int switch_normal_clock(struct rts51x_chip *chip, int clk)
526 {
527 int retval;
528 u8 sel, div, mcu_cnt;
529 int sd_vpclk_phase_reset = 0;
530
531 if (chip->cur_clk == clk)
532 return STATUS_SUCCESS;
533
534 if (chip->cur_card == SD_CARD) {
535 struct sd_info *sd_card = &(chip->sd_card);
536 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
537 sd_vpclk_phase_reset = 1;
538 }
539
540 switch (clk) {
541 case CLK_20:
542 RTS51X_DEBUGP("Switch clock to 20MHz\n");
543 sel = SSC_80;
544 div = CLK_DIV_4;
545 mcu_cnt = 5;
546 break;
547
548 case CLK_30:
549 RTS51X_DEBUGP("Switch clock to 30MHz\n");
550 sel = SSC_60;
551 div = CLK_DIV_2;
552 mcu_cnt = 4;
553 break;
554
555 case CLK_40:
556 RTS51X_DEBUGP("Switch clock to 40MHz\n");
557 sel = SSC_80;
558 div = CLK_DIV_2;
559 mcu_cnt = 3;
560 break;
561
562 case CLK_50:
563 RTS51X_DEBUGP("Switch clock to 50MHz\n");
564 sel = SSC_100;
565 div = CLK_DIV_2;
566 mcu_cnt = 3;
567 break;
568
569 case CLK_60:
570 RTS51X_DEBUGP("Switch clock to 60MHz\n");
571 sel = SSC_60;
572 div = CLK_DIV_1;
573 mcu_cnt = 3;
574 break;
575
576 case CLK_80:
577 RTS51X_DEBUGP("Switch clock to 80MHz\n");
578 sel = SSC_80;
579 div = CLK_DIV_1;
580 mcu_cnt = 2;
581 break;
582
583 case CLK_100:
584 RTS51X_DEBUGP("Switch clock to 100MHz\n");
585 sel = SSC_100;
586 div = CLK_DIV_1;
587 mcu_cnt = 2;
588 break;
589
590 /* case CLK_120:
591 RTS51X_DEBUGP("Switch clock to 120MHz\n");
592 sel = SSC_120;
593 div = CLK_DIV_1;
594 mcu_cnt = 2;
595 break;
596
597 case CLK_150:
598 RTS51X_DEBUGP("Switch clock to 150MHz\n");
599 sel = SSC_150;
600 div = CLK_DIV_1;
601 mcu_cnt = 2;
602 break; */
603
604 default:
605 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
606 clk);
607 TRACE_RET(chip, STATUS_FAIL);
608 }
609
610 if (!sd_vpclk_phase_reset) {
611 rts51x_init_cmd(chip);
612
613 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
614 CLK_CHANGE);
615 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
616 (div << 4) | mcu_cnt);
617 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
618 sel);
619 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
620
621 retval = rts51x_send_cmd(chip, MODE_C, 100);
622 if (retval != STATUS_SUCCESS)
623 TRACE_RET(chip, retval);
624 } else {
625 rts51x_init_cmd(chip);
626
627 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
628 CLK_CHANGE);
629 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
630 PHASE_NOT_RESET, 0);
631 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
632 PHASE_NOT_RESET, 0);
633 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
634 (div << 4) | mcu_cnt);
635 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
636 sel);
637
638 retval = rts51x_send_cmd(chip, MODE_C, 100);
639 if (retval != STATUS_SUCCESS)
640 TRACE_RET(chip, retval);
641
642 udelay(200);
643
644 rts51x_init_cmd(chip);
645
646 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
647 PHASE_NOT_RESET, PHASE_NOT_RESET);
648 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
649 PHASE_NOT_RESET, PHASE_NOT_RESET);
650
651 retval = rts51x_send_cmd(chip, MODE_C, 100);
652 if (retval != STATUS_SUCCESS)
653 TRACE_RET(chip, retval);
654
655 udelay(200);
656
657 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
658 }
659
660 chip->cur_clk = clk;
661
662 return STATUS_SUCCESS;
663 }
664
card_rw(struct scsi_cmnd * srb,struct rts51x_chip * chip,u32 sec_addr,u16 sec_cnt)665 int card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
666 u16 sec_cnt)
667 {
668 int retval;
669 unsigned int lun = SCSI_LUN(srb);
670 int i;
671
672 if (chip->rw_card[lun] == NULL)
673 return STATUS_FAIL;
674
675 RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
676 (srb->sc_data_direction ==
677 DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
678
679 chip->rw_need_retry = 0;
680 for (i = 0; i < 3; i++) {
681 retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
682 if (retval != STATUS_SUCCESS) {
683 CATCH_TRIGGER(chip);
684 if (chip->option.reset_or_rw_fail_set_pad_drive) {
685 rts51x_write_register(chip, CARD_DRIVE_SEL,
686 SD20_DRIVE_MASK,
687 DRIVE_8mA);
688 }
689 }
690
691 if (!chip->rw_need_retry)
692 break;
693
694 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
695 }
696
697 return retval;
698 }
699
get_lun_card(struct rts51x_chip * chip,unsigned int lun)700 u8 get_lun_card(struct rts51x_chip *chip, unsigned int lun)
701 {
702 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
703 return (u8) XD_CARD;
704 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
705 return (u8) SD_CARD;
706 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
707 return (u8) MS_CARD;
708
709 return 0;
710 }
711
card_share_mode(struct rts51x_chip * chip,int card)712 int card_share_mode(struct rts51x_chip *chip, int card)
713 {
714 u8 value;
715
716 if (card == SD_CARD)
717 value = CARD_SHARE_SD;
718 else if (card == MS_CARD)
719 value = CARD_SHARE_MS;
720 else if (card == XD_CARD)
721 value = CARD_SHARE_XD;
722 else
723 TRACE_RET(chip, STATUS_FAIL);
724
725 RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
726
727 return STATUS_SUCCESS;
728 }
729
rts51x_select_card(struct rts51x_chip * chip,int card)730 int rts51x_select_card(struct rts51x_chip *chip, int card)
731 {
732 int retval;
733
734 if (chip->cur_card != card) {
735 u8 mod;
736
737 if (card == SD_CARD)
738 mod = SD_MOD_SEL;
739 else if (card == MS_CARD)
740 mod = MS_MOD_SEL;
741 else if (card == XD_CARD)
742 mod = XD_MOD_SEL;
743 else
744 TRACE_RET(chip, STATUS_FAIL);
745 RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
746 chip->cur_card = card;
747
748 retval = card_share_mode(chip, card);
749 if (retval != STATUS_SUCCESS)
750 TRACE_RET(chip, retval);
751 }
752
753 return STATUS_SUCCESS;
754 }
755
eject_card(struct rts51x_chip * chip,unsigned int lun)756 void eject_card(struct rts51x_chip *chip, unsigned int lun)
757 {
758 RTS51X_DEBUGP("eject card\n");
759 RTS51X_SET_STAT(chip, STAT_RUN);
760 do_remaining_work(chip);
761
762 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
763 release_sd_card(chip);
764 chip->card_ejected |= SD_CARD;
765 chip->card_ready &= ~SD_CARD;
766 chip->capacity[lun] = 0;
767 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
768 release_xd_card(chip);
769 chip->card_ejected |= XD_CARD;
770 chip->card_ready &= ~XD_CARD;
771 chip->capacity[lun] = 0;
772 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
773 release_ms_card(chip);
774 chip->card_ejected |= MS_CARD;
775 chip->card_ready &= ~MS_CARD;
776 chip->capacity[lun] = 0;
777 }
778 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
779 XD_INT | MS_INT | SD_INT);
780 }
781
trans_dma_enable(enum dma_data_direction dir,struct rts51x_chip * chip,u32 byte_cnt,u8 pack_size)782 void trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
783 u32 byte_cnt, u8 pack_size)
784 {
785 if (pack_size > DMA_1024)
786 pack_size = DMA_512;
787
788 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
789 RING_BUFFER);
790
791 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
792 (u8) (byte_cnt >> 24));
793 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
794 (u8) (byte_cnt >> 16));
795 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
796 (u8) (byte_cnt >> 8));
797 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
798
799 if (dir == DMA_FROM_DEVICE) {
800 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
801 0x03 | DMA_PACK_SIZE_MASK,
802 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
803 } else {
804 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
805 0x03 | DMA_PACK_SIZE_MASK,
806 DMA_DIR_TO_CARD | DMA_EN | pack_size);
807 }
808 }
809
enable_card_clock(struct rts51x_chip * chip,u8 card)810 int enable_card_clock(struct rts51x_chip *chip, u8 card)
811 {
812 u8 clk_en = 0;
813
814 if (card & XD_CARD)
815 clk_en |= XD_CLK_EN;
816 if (card & SD_CARD)
817 clk_en |= SD_CLK_EN;
818 if (card & MS_CARD)
819 clk_en |= MS_CLK_EN;
820
821 RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
822
823 return STATUS_SUCCESS;
824 }
825
disable_card_clock(struct rts51x_chip * chip,u8 card)826 int disable_card_clock(struct rts51x_chip *chip, u8 card)
827 {
828 u8 clk_en = 0;
829
830 if (card & XD_CARD)
831 clk_en |= XD_CLK_EN;
832 if (card & SD_CARD)
833 clk_en |= SD_CLK_EN;
834 if (card & MS_CARD)
835 clk_en |= MS_CLK_EN;
836
837 RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
838
839 return STATUS_SUCCESS;
840 }
841
card_power_on(struct rts51x_chip * chip,u8 card)842 int card_power_on(struct rts51x_chip *chip, u8 card)
843 {
844 u8 mask, val1, val2;
845
846 mask = POWER_MASK;
847 val1 = PARTIAL_POWER_ON;
848 val2 = POWER_ON;
849
850 #ifdef SD_XD_IO_FOLLOW_PWR
851 if ((card == SD_CARD) || (card == XD_CARD)) {
852 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
853 val1 | LDO_SUSPEND);
854 /* RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
855 LDO3318_PWR_MASK, LDO_SUSPEND); */
856 }
857 /* else if(card==XD_CARD)
858 {
859 RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
860 mask|LDO3318_PWR_MASK, val1|LDO_SUSPEND);
861 //RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
862 // LDO3318_PWR_MASK, LDO_SUSPEND);
863 } */
864 else {
865 #endif
866 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
867 #ifdef SD_XD_IO_FOLLOW_PWR
868 }
869 #endif
870 udelay(chip->option.pwr_delay);
871 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
872 #ifdef SD_XD_IO_FOLLOW_PWR
873 if (card == SD_CARD) {
874 rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
875 LDO_ON);
876 }
877 #endif
878
879 return STATUS_SUCCESS;
880 }
881
card_power_off(struct rts51x_chip * chip,u8 card)882 int card_power_off(struct rts51x_chip *chip, u8 card)
883 {
884 u8 mask, val;
885
886 mask = POWER_MASK;
887 val = POWER_OFF;
888 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
889
890 return STATUS_SUCCESS;
891 }
892
monitor_card_cd(struct rts51x_chip * chip,u8 card)893 int monitor_card_cd(struct rts51x_chip *chip, u8 card)
894 {
895 int retval;
896 u8 card_cd[32] = { 0 };
897
898 card_cd[SD_CARD] = SD_CD;
899 card_cd[XD_CARD] = XD_CD;
900 card_cd[MS_CARD] = MS_CD;
901
902 retval = rts51x_get_card_status(chip, &(chip->card_status));
903 if (retval != STATUS_SUCCESS)
904 return CD_NOT_EXIST;
905
906 if (chip->card_status & card_cd[card])
907 return CD_EXIST;
908
909 return CD_NOT_EXIST;
910 }
911
toggle_gpio(struct rts51x_chip * chip,u8 gpio)912 int toggle_gpio(struct rts51x_chip *chip, u8 gpio)
913 {
914 int retval;
915 u8 temp_reg;
916 u8 gpio_output[4] = {
917 0x01,
918 };
919 u8 gpio_oe[4] = {
920 0x02,
921 };
922 if (chip->rts5179) {
923 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
924 if (retval != STATUS_SUCCESS)
925 TRACE_RET(chip, STATUS_FAIL);
926 temp_reg ^= gpio_oe[gpio];
927 temp_reg &= 0xfe; /* bit 0 always set 0 */
928 retval =
929 rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
930 if (retval != STATUS_SUCCESS)
931 TRACE_RET(chip, STATUS_FAIL);
932 } else {
933 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
934 if (retval != STATUS_SUCCESS)
935 TRACE_RET(chip, STATUS_FAIL);
936 temp_reg ^= gpio_output[gpio];
937 retval =
938 rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
939 temp_reg | gpio_oe[gpio]);
940 if (retval != STATUS_SUCCESS)
941 TRACE_RET(chip, STATUS_FAIL);
942 }
943
944 return STATUS_SUCCESS;
945 }
946
turn_on_led(struct rts51x_chip * chip,u8 gpio)947 int turn_on_led(struct rts51x_chip *chip, u8 gpio)
948 {
949 int retval;
950 u8 gpio_oe[4] = {
951 0x02,
952 };
953 u8 gpio_mask[4] = {
954 0x03,
955 };
956
957 retval =
958 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
959 gpio_oe[gpio]);
960 if (retval != STATUS_SUCCESS)
961 TRACE_RET(chip, STATUS_FAIL);
962
963 return STATUS_SUCCESS;
964 }
965
turn_off_led(struct rts51x_chip * chip,u8 gpio)966 int turn_off_led(struct rts51x_chip *chip, u8 gpio)
967 {
968 int retval;
969 u8 gpio_output[4] = {
970 0x01,
971 };
972 u8 gpio_oe[4] = {
973 0x02,
974 };
975 u8 gpio_mask[4] = {
976 0x03,
977 };
978
979 retval =
980 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
981 gpio_oe[gpio] | gpio_output[gpio]);
982 if (retval != STATUS_SUCCESS)
983 TRACE_RET(chip, STATUS_FAIL);
984
985 return STATUS_SUCCESS;
986 }
987