1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "hw.h"
44
rtl92se_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46 {
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
83 break;
84 }
85 }
86 }
87
rtl92se_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89 {
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 "HW_VAR_SLOT_TIME %x\n", val[0]);
142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (u8 *)(&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*(u8 *) val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *((u8 *)val);
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *((u8 *) val);
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *((u8 *) val);
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *((u8 *) val);
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 (u8 *)(&e_aci));
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *((u8 *) val);
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 "switch case not processed\n");
301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = ((u8 *) (val))[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *((u8 *) val);
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 "switch case not processed\n");
406 break;
407 }
408
409 }
410
rtl92se_enable_hw_security_config(struct ieee80211_hw * hw)411 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
412 {
413 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 u8 sec_reg_value = 0x0;
415
416 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
417 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
418 rtlpriv->sec.pairwise_enc_algorithm,
419 rtlpriv->sec.group_enc_algorithm);
420
421 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
422 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
423 "not open hw encryption\n");
424 return;
425 }
426
427 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
428
429 if (rtlpriv->sec.use_defaultkey) {
430 sec_reg_value |= SCR_TXUSEDK;
431 sec_reg_value |= SCR_RXUSEDK;
432 }
433
434 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
435 sec_reg_value);
436
437 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
438
439 }
440
_rtl92ce_halset_sysclk(struct ieee80211_hw * hw,u8 data)441 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
442 {
443 struct rtl_priv *rtlpriv = rtl_priv(hw);
444 u8 waitcount = 100;
445 bool bresult = false;
446 u8 tmpvalue;
447
448 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
449
450 /* Wait the MAC synchronized. */
451 udelay(400);
452
453 /* Check if it is set ready. */
454 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
455 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
456
457 if ((data & (BIT(6) | BIT(7))) == false) {
458 waitcount = 100;
459 tmpvalue = 0;
460
461 while (1) {
462 waitcount--;
463
464 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
465 if ((tmpvalue & BIT(6)))
466 break;
467
468 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
469 if (waitcount == 0)
470 break;
471
472 udelay(10);
473 }
474
475 if (waitcount == 0)
476 bresult = false;
477 else
478 bresult = true;
479 }
480
481 return bresult;
482 }
483
rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw * hw)484 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
485 {
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 u8 u1tmp;
488
489 /* The following config GPIO function */
490 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
491 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
492
493 /* config GPIO3 to input */
494 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
495 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
496
497 }
498
_rtl92se_rf_onoff_detect(struct ieee80211_hw * hw)499 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
500 {
501 struct rtl_priv *rtlpriv = rtl_priv(hw);
502 u8 u1tmp;
503 u8 retval = ERFON;
504
505 /* The following config GPIO function */
506 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
507 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
508
509 /* config GPIO3 to input */
510 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
511 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
512
513 /* On some of the platform, driver cannot read correct
514 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
515 mdelay(10);
516
517 /* check GPIO3 */
518 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
519 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
520
521 return retval;
522 }
523
_rtl92se_macconfig_before_fwdownload(struct ieee80211_hw * hw)524 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
525 {
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
528 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
529
530 u8 i;
531 u8 tmpu1b;
532 u16 tmpu2b;
533 u8 pollingcnt = 20;
534
535 if (rtlpci->first_init) {
536 /* Reset PCIE Digital */
537 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
538 tmpu1b &= 0xFE;
539 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
540 udelay(1);
541 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
542 }
543
544 /* Switch to SW IO control */
545 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
546 if (tmpu1b & BIT(7)) {
547 tmpu1b &= ~(BIT(6) | BIT(7));
548
549 /* Set failed, return to prevent hang. */
550 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
551 return;
552 }
553
554 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
555 udelay(50);
556 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
557 udelay(50);
558
559 /* Clear FW RPWM for FW control LPS.*/
560 rtl_write_byte(rtlpriv, RPWM, 0x0);
561
562 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
563 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
564 tmpu1b &= 0x73;
565 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
566 /* wait for BIT 10/11/15 to pull high automatically!! */
567 mdelay(1);
568
569 rtl_write_byte(rtlpriv, CMDR, 0);
570 rtl_write_byte(rtlpriv, TCR, 0);
571
572 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
573 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
574 tmpu1b |= 0x08;
575 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
576 tmpu1b &= ~(BIT(3));
577 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
578
579 /* Enable AFE clock source */
580 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
581 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
582 /* Delay 1.5ms */
583 mdelay(2);
584 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
585 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
586
587 /* Enable AFE Macro Block's Bandgap */
588 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
589 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
590 mdelay(1);
591
592 /* Enable AFE Mbias */
593 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
594 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
595 mdelay(1);
596
597 /* Enable LDOA15 block */
598 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
599 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
600
601 /* Set Digital Vdd to Retention isolation Path. */
602 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
603 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
604
605 /* For warm reboot NIC disappera bug. */
606 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
607 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
608
609 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
610
611 /* Enable AFE PLL Macro Block */
612 /* We need to delay 100u before enabling PLL. */
613 udelay(200);
614 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
615 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
616
617 /* for divider reset */
618 udelay(100);
619 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
620 BIT(4) | BIT(6)));
621 udelay(10);
622 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
623 udelay(10);
624
625 /* Enable MAC 80MHZ clock */
626 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
627 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
628 mdelay(1);
629
630 /* Release isolation AFE PLL & MD */
631 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
632
633 /* Enable MAC clock */
634 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
635 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
636
637 /* Enable Core digital and enable IOREG R/W */
638 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
639 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
640
641 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
642 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
643
644 /* enable REG_EN */
645 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
646
647 /* Switch the control path. */
648 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
649 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
650
651 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
652 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
653 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
654 return; /* Set failed, return to prevent hang. */
655
656 rtl_write_word(rtlpriv, CMDR, 0x07FC);
657
658 /* MH We must enable the section of code to prevent load IMEM fail. */
659 /* Load MAC register from WMAc temporarily We simulate macreg. */
660 /* txt HW will provide MAC txt later */
661 rtl_write_byte(rtlpriv, 0x6, 0x30);
662 rtl_write_byte(rtlpriv, 0x49, 0xf0);
663
664 rtl_write_byte(rtlpriv, 0x4b, 0x81);
665
666 rtl_write_byte(rtlpriv, 0xb5, 0x21);
667
668 rtl_write_byte(rtlpriv, 0xdc, 0xff);
669 rtl_write_byte(rtlpriv, 0xdd, 0xff);
670 rtl_write_byte(rtlpriv, 0xde, 0xff);
671 rtl_write_byte(rtlpriv, 0xdf, 0xff);
672
673 rtl_write_byte(rtlpriv, 0x11a, 0x00);
674 rtl_write_byte(rtlpriv, 0x11b, 0x00);
675
676 for (i = 0; i < 32; i++)
677 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
678
679 rtl_write_byte(rtlpriv, 0x236, 0xff);
680
681 rtl_write_byte(rtlpriv, 0x503, 0x22);
682
683 if (ppsc->support_aspm && !ppsc->support_backdoor)
684 rtl_write_byte(rtlpriv, 0x560, 0x40);
685 else
686 rtl_write_byte(rtlpriv, 0x560, 0x00);
687
688 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
689
690 /* Set RX Desc Address */
691 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
692 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
693
694 /* Set TX Desc Address */
695 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
696 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
697 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
698 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
699 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
700 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
701 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
702 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
703 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
704
705 rtl_write_word(rtlpriv, CMDR, 0x37FC);
706
707 /* To make sure that TxDMA can ready to download FW. */
708 /* We should reset TxDMA if IMEM RPT was not ready. */
709 do {
710 tmpu1b = rtl_read_byte(rtlpriv, TCR);
711 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
712 break;
713
714 udelay(5);
715 } while (pollingcnt--);
716
717 if (pollingcnt <= 0) {
718 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
719 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
720 tmpu1b);
721 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
722 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
723 udelay(2);
724 /* Reset TxDMA */
725 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
726 }
727
728 /* After MACIO reset,we must refresh LED state. */
729 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
730 (ppsc->rfoff_reason == 0)) {
731 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
732 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
733 enum rf_pwrstate rfpwr_state_toset;
734 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
735
736 if (rfpwr_state_toset == ERFON)
737 rtl92se_sw_led_on(hw, pLed0);
738 }
739 }
740
_rtl92se_macconfig_after_fwdownload(struct ieee80211_hw * hw)741 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
742 {
743 struct rtl_priv *rtlpriv = rtl_priv(hw);
744 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
745 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
746 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
747 u8 i;
748 u16 tmpu2b;
749
750 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
751
752 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
753 /* Turn on 0x40 Command register */
754 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
755 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
756 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
757
758 /* Set TCR TX DMA pre 2 FULL enable bit */
759 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
760 TXDMAPRE2FULL);
761
762 /* Set RCR */
763 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
764
765 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
766
767 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
768 /* Set CCK/OFDM SIFS */
769 /* CCK SIFS shall always be 10us. */
770 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
771 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
772
773 /* Set AckTimeout */
774 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
775
776 /* Beacon related */
777 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
778 rtl_write_word(rtlpriv, ATIMWND, 2);
779
780 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
781 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
782 /* Firmware allocate now, associate with FW internal setting.!!! */
783
784 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
785 /* 5.3 Set driver info, we only accept PHY status now. */
786 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
787 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
788
789 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
790 /* Set RRSR to all legacy rate and HT rate
791 * CCK rate is supported by default.
792 * CCK rate will be filtered out only when associated
793 * AP does not support it.
794 * Only enable ACK rate to OFDM 24M
795 * Disable RRSR for CCK rate in A-Cut */
796
797 if (rtlhal->version == VERSION_8192S_ACUT)
798 rtl_write_byte(rtlpriv, RRSR, 0xf0);
799 else if (rtlhal->version == VERSION_8192S_BCUT)
800 rtl_write_byte(rtlpriv, RRSR, 0xff);
801 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
802 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
803
804 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
805 /* fallback to CCK rate */
806 for (i = 0; i < 8; i++) {
807 /*Disable RRSR for CCK rate in A-Cut */
808 if (rtlhal->version == VERSION_8192S_ACUT)
809 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
810 }
811
812 /* Different rate use different AMPDU size */
813 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
814 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
815 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
816 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
817 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
818 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
819 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
821 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
823
824 /* Set Data / Response auto rate fallack retry count */
825 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
826 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
827 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
828 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
829
830 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
831 /* Set all rate to support SG */
832 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
833
834 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
835 /* Set NAV protection length */
836 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
837 /* CF-END Threshold */
838 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
839 /* Set AMPDU minimum space */
840 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
841 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
842 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
843
844 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
845 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
846 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
847 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
848 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
849
850 /* 14. Set driver info, we only accept PHY status now. */
851 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
852
853 /* 15. For EEPROM R/W Workaround */
854 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
855 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
856 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
857 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
858 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
859
860 /* 17. For EFUSE */
861 /* We may R/W EFUSE in EEPROM mode */
862 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
863 u8 tempval;
864
865 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
866 tempval &= 0xFE;
867 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
868
869 /* Change Program timing */
870 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
871 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
872 }
873
874 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
875
876 }
877
_rtl92se_hw_configure(struct ieee80211_hw * hw)878 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
879 {
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
882 struct rtl_phy *rtlphy = &(rtlpriv->phy);
883 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
884
885 u8 reg_bw_opmode = 0;
886 u32 reg_rrsr = 0;
887 u8 regtmp = 0;
888
889 reg_bw_opmode = BW_OPMODE_20MHZ;
890 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
891
892 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
893 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
894 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
895 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
896
897 /* Set Retry Limit here */
898 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
899 (u8 *)(&rtlpci->shortretry_limit));
900
901 rtl_write_byte(rtlpriv, MLT, 0x8f);
902
903 /* For Min Spacing configuration. */
904 switch (rtlphy->rf_type) {
905 case RF_1T2R:
906 case RF_1T1R:
907 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
908 break;
909 case RF_2T2R:
910 case RF_2T2R_GREEN:
911 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
912 break;
913 }
914 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
915 }
916
rtl92se_hw_init(struct ieee80211_hw * hw)917 int rtl92se_hw_init(struct ieee80211_hw *hw)
918 {
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
920 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
921 struct rtl_phy *rtlphy = &(rtlpriv->phy);
922 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
923 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
924 u8 tmp_byte = 0;
925 unsigned long flags;
926 bool rtstatus = true;
927 u8 tmp_u1b;
928 int err = false;
929 u8 i;
930 int wdcapra_add[] = {
931 EDCAPARA_BE, EDCAPARA_BK,
932 EDCAPARA_VI, EDCAPARA_VO};
933 u8 secr_value = 0x0;
934
935 rtlpci->being_init_adapter = true;
936
937 /* As this function can take a very long time (up to 350 ms)
938 * and can be called with irqs disabled, reenable the irqs
939 * to let the other devices continue being serviced.
940 *
941 * It is safe doing so since our own interrupts will only be enabled
942 * in a subsequent step.
943 */
944 local_save_flags(flags);
945 local_irq_enable();
946
947 rtlpriv->intf_ops->disable_aspm(hw);
948
949 /* 1. MAC Initialize */
950 /* Before FW download, we have to set some MAC register */
951 _rtl92se_macconfig_before_fwdownload(hw);
952
953 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
954 PMC_FSM) >> 16) & 0xF);
955
956 rtl8192se_gpiobit3_cfg_inputmode(hw);
957
958 /* 2. download firmware */
959 rtstatus = rtl92s_download_fw(hw);
960 if (!rtstatus) {
961 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
962 "Failed to download FW. Init HW without FW now... "
963 "Please copy FW into /lib/firmware/rtlwifi\n");
964 err = 1;
965 goto exit;
966 }
967
968 /* After FW download, we have to reset MAC register */
969 _rtl92se_macconfig_after_fwdownload(hw);
970
971 /*Retrieve default FW Cmd IO map. */
972 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
973 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
974
975 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
976 if (!rtl92s_phy_mac_config(hw)) {
977 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
978 err = rtstatus;
979 goto exit;
980 }
981
982 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
983 /* We must set flag avoid BB/RF config period later!! */
984 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
985
986 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
987 if (!rtl92s_phy_bb_config(hw)) {
988 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
989 err = rtstatus;
990 goto exit;
991 }
992
993 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
994 /* Before initalizing RF. We can not use FW to do RF-R/W. */
995
996 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
997
998 /* RF Power Save */
999 #if 0
1000 /* H/W or S/W RF OFF before sleep. */
1001 if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
1002 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
1003
1004 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
1005 rtlpriv->psc.rfpwr_state = ERFON;
1006 /* FIXME: check spinlocks if this block is uncommented */
1007 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
1008 } else {
1009 /* gpio radio on/off is out of adapter start */
1010 if (rtlpriv->psc.hwradiooff == false) {
1011 rtlpriv->psc.rfpwr_state = ERFON;
1012 rtlpriv->psc.rfoff_reason = 0;
1013 }
1014 }
1015 #endif
1016
1017 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1018 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1019 if (rtlhal->version == VERSION_8192S_ACUT)
1020 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1021 else
1022 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1023
1024 if (!rtl92s_phy_rf_config(hw)) {
1025 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1026 err = rtstatus;
1027 goto exit;
1028 }
1029
1030 /* After read predefined TXT, we must set BB/MAC/RF
1031 * register as our requirement */
1032
1033 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1034 (enum radio_path)0,
1035 RF_CHNLBW,
1036 RFREG_OFFSET_MASK);
1037 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1038 (enum radio_path)1,
1039 RF_CHNLBW,
1040 RFREG_OFFSET_MASK);
1041
1042 /*---- Set CCK and OFDM Block "ON"----*/
1043 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1044 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1045
1046 /*3 Set Hardware(Do nothing now) */
1047 _rtl92se_hw_configure(hw);
1048
1049 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1050 /* TX power index for different rate set. */
1051 /* Get original hw reg values */
1052 rtl92s_phy_get_hw_reg_originalvalue(hw);
1053 /* Write correct tx power index */
1054 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1055
1056 /* We must set MAC address after firmware download. */
1057 for (i = 0; i < 6; i++)
1058 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1059
1060 /* EEPROM R/W workaround */
1061 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1062 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1063
1064 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1065
1066 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1067 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1068 tmp_byte = tmp_byte | BIT(5);
1069 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1070 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1071 }
1072
1073 /* We enable high power and RA related mechanism after NIC
1074 * initialized. */
1075 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1076
1077 /* Add to prevent ASPM bug. */
1078 /* Always enable hst and NIC clock request. */
1079 rtl92s_phy_switch_ephy_parameter(hw);
1080
1081 /* Security related
1082 * 1. Clear all H/W keys.
1083 * 2. Enable H/W encryption/decryption. */
1084 rtl_cam_reset_all_entry(hw);
1085 secr_value |= SCR_TXENCENABLE;
1086 secr_value |= SCR_RXENCENABLE;
1087 secr_value |= SCR_NOSKMC;
1088 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1089
1090 for (i = 0; i < 4; i++)
1091 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1092
1093 if (rtlphy->rf_type == RF_1T2R) {
1094 bool mrc2set = true;
1095 /* Turn on B-Path */
1096 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1097 }
1098
1099 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1100 rtl92s_dm_init(hw);
1101 exit:
1102 local_irq_restore(flags);
1103 rtlpci->being_init_adapter = false;
1104 return err;
1105 }
1106
rtl92se_set_mac_addr(struct rtl_io * io,const u8 * addr)1107 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1108 {
1109 }
1110
rtl92se_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1111 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1112 {
1113 struct rtl_priv *rtlpriv = rtl_priv(hw);
1114 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1115 u32 reg_rcr = rtlpci->receive_config;
1116
1117 if (rtlpriv->psc.rfpwr_state != ERFON)
1118 return;
1119
1120 if (check_bssid) {
1121 reg_rcr |= (RCR_CBSSID);
1122 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1123 } else if (!check_bssid) {
1124 reg_rcr &= (~RCR_CBSSID);
1125 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1126 }
1127
1128 }
1129
_rtl92se_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1130 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1131 enum nl80211_iftype type)
1132 {
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1135 u32 temp;
1136 bt_msr &= ~MSR_LINK_MASK;
1137
1138 switch (type) {
1139 case NL80211_IFTYPE_UNSPECIFIED:
1140 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1142 "Set Network type to NO LINK!\n");
1143 break;
1144 case NL80211_IFTYPE_ADHOC:
1145 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1146 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1147 "Set Network type to Ad Hoc!\n");
1148 break;
1149 case NL80211_IFTYPE_STATION:
1150 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1151 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1152 "Set Network type to STA!\n");
1153 break;
1154 case NL80211_IFTYPE_AP:
1155 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1157 "Set Network type to AP!\n");
1158 break;
1159 default:
1160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1161 "Network type %d not supported!\n", type);
1162 return 1;
1163 break;
1164
1165 }
1166
1167 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1168
1169 temp = rtl_read_dword(rtlpriv, TCR);
1170 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1171 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1172
1173
1174 return 0;
1175 }
1176
1177 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
rtl92se_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1178 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1179 {
1180 struct rtl_priv *rtlpriv = rtl_priv(hw);
1181
1182 if (_rtl92se_set_media_status(hw, type))
1183 return -EOPNOTSUPP;
1184
1185 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1186 if (type != NL80211_IFTYPE_AP)
1187 rtl92se_set_check_bssid(hw, true);
1188 } else {
1189 rtl92se_set_check_bssid(hw, false);
1190 }
1191
1192 return 0;
1193 }
1194
1195 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
rtl92se_set_qos(struct ieee80211_hw * hw,int aci)1196 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1197 {
1198 struct rtl_priv *rtlpriv = rtl_priv(hw);
1199 rtl92s_dm_init_edca_turbo(hw);
1200
1201 switch (aci) {
1202 case AC1_BK:
1203 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1204 break;
1205 case AC0_BE:
1206 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1207 break;
1208 case AC2_VI:
1209 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1210 break;
1211 case AC3_VO:
1212 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1213 break;
1214 default:
1215 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1216 break;
1217 }
1218 }
1219
rtl92se_enable_interrupt(struct ieee80211_hw * hw)1220 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1221 {
1222 struct rtl_priv *rtlpriv = rtl_priv(hw);
1223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1224
1225 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1226 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1227 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1228 }
1229
rtl92se_disable_interrupt(struct ieee80211_hw * hw)1230 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1231 {
1232 struct rtl_priv *rtlpriv;
1233 struct rtl_pci *rtlpci;
1234
1235 rtlpriv = rtl_priv(hw);
1236 /* if firmware not available, no interrupts */
1237 if (!rtlpriv || !rtlpriv->max_fw_size)
1238 return;
1239 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1240 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1241 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1242
1243 synchronize_irq(rtlpci->pdev->irq);
1244 }
1245
1246
_rtl92s_set_sysclk(struct ieee80211_hw * hw,u8 data)1247 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1248 {
1249 struct rtl_priv *rtlpriv = rtl_priv(hw);
1250 u8 waitcnt = 100;
1251 bool result = false;
1252 u8 tmp;
1253
1254 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1255
1256 /* Wait the MAC synchronized. */
1257 udelay(400);
1258
1259 /* Check if it is set ready. */
1260 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1261 result = ((tmp & BIT(7)) == (data & BIT(7)));
1262
1263 if ((data & (BIT(6) | BIT(7))) == false) {
1264 waitcnt = 100;
1265 tmp = 0;
1266
1267 while (1) {
1268 waitcnt--;
1269 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1270
1271 if ((tmp & BIT(6)))
1272 break;
1273
1274 pr_err("wait for BIT(6) return value %x\n", tmp);
1275
1276 if (waitcnt == 0)
1277 break;
1278 udelay(10);
1279 }
1280
1281 if (waitcnt == 0)
1282 result = false;
1283 else
1284 result = true;
1285 }
1286
1287 return result;
1288 }
1289
_rtl92s_phy_set_rfhalt(struct ieee80211_hw * hw)1290 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1291 {
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1294 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1295 u8 u1btmp;
1296
1297 if (rtlhal->driver_going2unload)
1298 rtl_write_byte(rtlpriv, 0x560, 0x0);
1299
1300 /* Power save for BB/RF */
1301 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1302 u1btmp |= BIT(0);
1303 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1304 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1305 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1306 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1307 udelay(100);
1308 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1309 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1310 udelay(10);
1311 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1312 udelay(10);
1313 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1314 udelay(10);
1315 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1316 rtl_write_word(rtlpriv, CMDR, 0x0000);
1317
1318 if (rtlhal->driver_going2unload) {
1319 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1320 u1btmp &= ~(BIT(0));
1321 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1322 }
1323
1324 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1325
1326 /* Add description. After switch control path. register
1327 * after page1 will be invisible. We can not do any IO
1328 * for register>0x40. After resume&MACIO reset, we need
1329 * to remember previous reg content. */
1330 if (u1btmp & BIT(7)) {
1331 u1btmp &= ~(BIT(6) | BIT(7));
1332 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1333 pr_err("Switch ctrl path fail\n");
1334 return;
1335 }
1336 }
1337
1338 /* Power save for MAC */
1339 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1340 !rtlhal->driver_going2unload) {
1341 /* enable LED function */
1342 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1343 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1344 } else {
1345 /* LED function disable. Power range is about 8mA now. */
1346 /* if write 0xF1 disconnet_pci power
1347 * ifconfig wlan0 down power are both high 35:70 */
1348 /* if write oxF9 disconnet_pci power
1349 * ifconfig wlan0 down power are both low 12:45*/
1350 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1351 }
1352
1353 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1354 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1355 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1356 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1357 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1358 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1359
1360 }
1361
_rtl92se_gen_refreshledstate(struct ieee80211_hw * hw)1362 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1363 {
1364 struct rtl_priv *rtlpriv = rtl_priv(hw);
1365 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1367 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1368
1369 if (rtlpci->up_first_time == 1)
1370 return;
1371
1372 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1373 rtl92se_sw_led_on(hw, pLed0);
1374 else
1375 rtl92se_sw_led_off(hw, pLed0);
1376 }
1377
1378
_rtl92se_power_domain_init(struct ieee80211_hw * hw)1379 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1380 {
1381 struct rtl_priv *rtlpriv = rtl_priv(hw);
1382 u16 tmpu2b;
1383 u8 tmpu1b;
1384
1385 rtlpriv->psc.pwrdomain_protect = true;
1386
1387 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1388 if (tmpu1b & BIT(7)) {
1389 tmpu1b &= ~(BIT(6) | BIT(7));
1390 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1391 rtlpriv->psc.pwrdomain_protect = false;
1392 return;
1393 }
1394 }
1395
1396 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1397 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1398
1399 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1400 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1401
1402 /* If IPS we need to turn LED on. So we not
1403 * not disable BIT 3/7 of reg3. */
1404 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1405 tmpu1b &= 0xFB;
1406 else
1407 tmpu1b &= 0x73;
1408
1409 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1410 /* wait for BIT 10/11/15 to pull high automatically!! */
1411 mdelay(1);
1412
1413 rtl_write_byte(rtlpriv, CMDR, 0);
1414 rtl_write_byte(rtlpriv, TCR, 0);
1415
1416 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1417 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1418 tmpu1b |= 0x08;
1419 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1420 tmpu1b &= ~(BIT(3));
1421 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1422
1423 /* Enable AFE clock source */
1424 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1425 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1426 /* Delay 1.5ms */
1427 udelay(1500);
1428 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1429 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1430
1431 /* Enable AFE Macro Block's Bandgap */
1432 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1433 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1434 mdelay(1);
1435
1436 /* Enable AFE Mbias */
1437 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1438 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1439 mdelay(1);
1440
1441 /* Enable LDOA15 block */
1442 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1443 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1444
1445 /* Set Digital Vdd to Retention isolation Path. */
1446 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1447 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1448
1449
1450 /* For warm reboot NIC disappera bug. */
1451 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1452 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1453
1454 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1455
1456 /* Enable AFE PLL Macro Block */
1457 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1458 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1459 /* Enable MAC 80MHZ clock */
1460 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1461 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1462 mdelay(1);
1463
1464 /* Release isolation AFE PLL & MD */
1465 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1466
1467 /* Enable MAC clock */
1468 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1469 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1470
1471 /* Enable Core digital and enable IOREG R/W */
1472 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1473 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1474 /* enable REG_EN */
1475 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1476
1477 /* Switch the control path. */
1478 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1479 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1480
1481 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1482 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1483 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1484 rtlpriv->psc.pwrdomain_protect = false;
1485 return;
1486 }
1487
1488 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1489
1490 /* After MACIO reset,we must refresh LED state. */
1491 _rtl92se_gen_refreshledstate(hw);
1492
1493 rtlpriv->psc.pwrdomain_protect = false;
1494 }
1495
rtl92se_card_disable(struct ieee80211_hw * hw)1496 void rtl92se_card_disable(struct ieee80211_hw *hw)
1497 {
1498 struct rtl_priv *rtlpriv = rtl_priv(hw);
1499 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1500 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1501 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1502 enum nl80211_iftype opmode;
1503 u8 wait = 30;
1504
1505 rtlpriv->intf_ops->enable_aspm(hw);
1506
1507 if (rtlpci->driver_is_goingto_unload ||
1508 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1509 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1510
1511 /* we should chnge GPIO to input mode
1512 * this will drop away current about 25mA*/
1513 rtl8192se_gpiobit3_cfg_inputmode(hw);
1514
1515 /* this is very important for ips power save */
1516 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1517 if (rtlpriv->psc.pwrdomain_protect)
1518 mdelay(20);
1519 else
1520 break;
1521 }
1522
1523 mac->link_state = MAC80211_NOLINK;
1524 opmode = NL80211_IFTYPE_UNSPECIFIED;
1525 _rtl92se_set_media_status(hw, opmode);
1526
1527 _rtl92s_phy_set_rfhalt(hw);
1528 udelay(100);
1529 }
1530
rtl92se_interrupt_recognized(struct ieee80211_hw * hw,u32 * p_inta,u32 * p_intb)1531 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1532 u32 *p_intb)
1533 {
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1536
1537 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1538 rtl_write_dword(rtlpriv, ISR, *p_inta);
1539
1540 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1541 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1542 }
1543
rtl92se_set_beacon_related_registers(struct ieee80211_hw * hw)1544 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1545 {
1546 struct rtl_priv *rtlpriv = rtl_priv(hw);
1547 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1548 u16 bcntime_cfg = 0;
1549 u16 bcn_cw = 6, bcn_ifs = 0xf;
1550 u16 atim_window = 2;
1551
1552 /* ATIM Window (in unit of TU). */
1553 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1554
1555 /* Beacon interval (in unit of TU). */
1556 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1557
1558 /* DrvErlyInt (in unit of TU). (Time to send
1559 * interrupt to notify driver to change
1560 * beacon content) */
1561 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1562
1563 /* BcnDMATIM(in unit of us). Indicates the
1564 * time before TBTT to perform beacon queue DMA */
1565 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1566
1567 /* Force beacon frame transmission even
1568 * after receiving beacon frame from
1569 * other ad hoc STA */
1570 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1571
1572 /* Beacon Time Configuration */
1573 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1574 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1575
1576 /* TODO: bcn_ifs may required to be changed on ASIC */
1577 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1578
1579 /*for beacon changed */
1580 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1581 }
1582
rtl92se_set_beacon_interval(struct ieee80211_hw * hw)1583 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1584 {
1585 struct rtl_priv *rtlpriv = rtl_priv(hw);
1586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1587 u16 bcn_interval = mac->beacon_interval;
1588
1589 /* Beacon interval (in unit of TU). */
1590 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1591 /* 2008.10.24 added by tynli for beacon changed. */
1592 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1593 }
1594
rtl92se_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1595 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1596 u32 add_msr, u32 rm_msr)
1597 {
1598 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1600
1601 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1602 add_msr, rm_msr);
1603
1604 if (add_msr)
1605 rtlpci->irq_mask[0] |= add_msr;
1606
1607 if (rm_msr)
1608 rtlpci->irq_mask[0] &= (~rm_msr);
1609
1610 rtl92se_disable_interrupt(hw);
1611 rtl92se_enable_interrupt(hw);
1612 }
1613
_rtl8192se_get_IC_Inferiority(struct ieee80211_hw * hw)1614 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1615 {
1616 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1617 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1618 u8 efuse_id;
1619
1620 rtlhal->ic_class = IC_INFERIORITY_A;
1621
1622 /* Only retrieving while using EFUSE. */
1623 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1624 !rtlefuse->autoload_failflag) {
1625 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1626
1627 if (efuse_id == 0xfe)
1628 rtlhal->ic_class = IC_INFERIORITY_B;
1629 }
1630 }
1631
_rtl92se_read_adapter_info(struct ieee80211_hw * hw)1632 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1633 {
1634 struct rtl_priv *rtlpriv = rtl_priv(hw);
1635 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1636 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1637 u16 i, usvalue;
1638 u16 eeprom_id;
1639 u8 tempval;
1640 u8 hwinfo[HWSET_MAX_SIZE_92S];
1641 u8 rf_path, index;
1642
1643 if (rtlefuse->epromtype == EEPROM_93C46) {
1644 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1645 "RTL819X Not boot from eeprom, check it !!\n");
1646 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1647 rtl_efuse_shadow_map_update(hw);
1648
1649 memcpy((void *)hwinfo, (void *)
1650 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1651 HWSET_MAX_SIZE_92S);
1652 }
1653
1654 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1655 hwinfo, HWSET_MAX_SIZE_92S);
1656
1657 eeprom_id = *((u16 *)&hwinfo[0]);
1658 if (eeprom_id != RTL8190_EEPROM_ID) {
1659 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1660 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1661 rtlefuse->autoload_failflag = true;
1662 } else {
1663 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1664 rtlefuse->autoload_failflag = false;
1665 }
1666
1667 if (rtlefuse->autoload_failflag)
1668 return;
1669
1670 _rtl8192se_get_IC_Inferiority(hw);
1671
1672 /* Read IC Version && Channel Plan */
1673 /* VID, DID SE 0xA-D */
1674 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1675 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1676 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1677 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1678 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1679
1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1681 "EEPROMId = 0x%4x\n", eeprom_id);
1682 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1683 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1685 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1687 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1689 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1690
1691 for (i = 0; i < 6; i += 2) {
1692 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1693 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1694 }
1695
1696 for (i = 0; i < 6; i++)
1697 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1698
1699 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1700
1701 /* Get Tx Power Level by Channel */
1702 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1703 /* 92S suupport RF A & B */
1704 for (rf_path = 0; rf_path < 2; rf_path++) {
1705 for (i = 0; i < 3; i++) {
1706 /* Read CCK RF A & B Tx power */
1707 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1708 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1709
1710 /* Read OFDM RF A & B Tx power for 1T */
1711 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1712 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1713
1714 /* Read OFDM RF A & B Tx power for 2T */
1715 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1716 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1717 rf_path * 3 + i];
1718 }
1719 }
1720
1721 for (rf_path = 0; rf_path < 2; rf_path++)
1722 for (i = 0; i < 3; i++)
1723 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1724 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1725 rf_path, i,
1726 rtlefuse->eeprom_chnlarea_txpwr_cck
1727 [rf_path][i]);
1728 for (rf_path = 0; rf_path < 2; rf_path++)
1729 for (i = 0; i < 3; i++)
1730 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1731 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1732 rf_path, i,
1733 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1734 [rf_path][i]);
1735 for (rf_path = 0; rf_path < 2; rf_path++)
1736 for (i = 0; i < 3; i++)
1737 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1738 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1739 rf_path, i,
1740 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1741 [rf_path][i]);
1742
1743 for (rf_path = 0; rf_path < 2; rf_path++) {
1744
1745 /* Assign dedicated channel tx power */
1746 for (i = 0; i < 14; i++) {
1747 /* channel 1~3 use the same Tx Power Level. */
1748 if (i < 3)
1749 index = 0;
1750 /* Channel 4-8 */
1751 else if (i < 8)
1752 index = 1;
1753 /* Channel 9-14 */
1754 else
1755 index = 2;
1756
1757 /* Record A & B CCK /OFDM - 1T/2T Channel area
1758 * tx power */
1759 rtlefuse->txpwrlevel_cck[rf_path][i] =
1760 rtlefuse->eeprom_chnlarea_txpwr_cck
1761 [rf_path][index];
1762 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1763 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1764 [rf_path][index];
1765 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1766 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1767 [rf_path][index];
1768 }
1769
1770 for (i = 0; i < 14; i++) {
1771 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1772 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1773 rf_path, i,
1774 rtlefuse->txpwrlevel_cck[rf_path][i],
1775 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1776 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1777 }
1778 }
1779
1780 for (rf_path = 0; rf_path < 2; rf_path++) {
1781 for (i = 0; i < 3; i++) {
1782 /* Read Power diff limit. */
1783 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1784 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1785 }
1786 }
1787
1788 for (rf_path = 0; rf_path < 2; rf_path++) {
1789 /* Fill Pwr group */
1790 for (i = 0; i < 14; i++) {
1791 /* Chanel 1-3 */
1792 if (i < 3)
1793 index = 0;
1794 /* Channel 4-8 */
1795 else if (i < 8)
1796 index = 1;
1797 /* Channel 9-13 */
1798 else
1799 index = 2;
1800
1801 rtlefuse->pwrgroup_ht20[rf_path][i] =
1802 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1803 0xf);
1804 rtlefuse->pwrgroup_ht40[rf_path][i] =
1805 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1806 0xf0) >> 4);
1807
1808 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1809 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1810 rf_path, i,
1811 rtlefuse->pwrgroup_ht20[rf_path][i]);
1812 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1813 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1814 rf_path, i,
1815 rtlefuse->pwrgroup_ht40[rf_path][i]);
1816 }
1817 }
1818
1819 for (i = 0; i < 14; i++) {
1820 /* Read tx power difference between HT OFDM 20/40 MHZ */
1821 /* channel 1-3 */
1822 if (i < 3)
1823 index = 0;
1824 /* Channel 4-8 */
1825 else if (i < 8)
1826 index = 1;
1827 /* Channel 9-14 */
1828 else
1829 index = 2;
1830
1831 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1832 index]) & 0xff;
1833 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1834 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1835 ((tempval >> 4) & 0xF);
1836
1837 /* Read OFDM<->HT tx power diff */
1838 /* Channel 1-3 */
1839 if (i < 3)
1840 index = 0;
1841 /* Channel 4-8 */
1842 else if (i < 8)
1843 index = 0x11;
1844 /* Channel 9-14 */
1845 else
1846 index = 1;
1847
1848 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1849 & 0xff;
1850 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1851 (tempval & 0xF);
1852 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1853 ((tempval >> 4) & 0xF);
1854
1855 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1856 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1857 }
1858
1859 rtlefuse->eeprom_regulatory = 0;
1860 if (rtlefuse->eeprom_version >= 2) {
1861 /* BIT(0)~2 */
1862 if (rtlefuse->eeprom_version >= 4)
1863 rtlefuse->eeprom_regulatory =
1864 (hwinfo[EEPROM_REGULATORY] & 0x7);
1865 else /* BIT(0) */
1866 rtlefuse->eeprom_regulatory =
1867 (hwinfo[EEPROM_REGULATORY] & 0x1);
1868 }
1869 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1870 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1871
1872 for (i = 0; i < 14; i++)
1873 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1874 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1875 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1876 for (i = 0; i < 14; i++)
1877 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1878 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1879 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1880 for (i = 0; i < 14; i++)
1881 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1882 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1883 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1884 for (i = 0; i < 14; i++)
1885 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1886 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1887 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1888
1889 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1890 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1891
1892 /* Read RF-indication and Tx Power gain
1893 * index diff of legacy to HT OFDM rate. */
1894 tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1895 rtlefuse->eeprom_txpowerdiff = tempval;
1896 rtlefuse->legacy_httxpowerdiff =
1897 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1898
1899 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1900 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1901
1902 /* Get TSSI value for each path. */
1903 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1904 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1905 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1906 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1907
1908 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1909 rtlefuse->eeprom_tssi[RF90_PATH_A],
1910 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1911
1912 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1913 /* and read ThermalMeter from EEPROM */
1914 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1915 rtlefuse->eeprom_thermalmeter = tempval;
1916 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1917 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1918
1919 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1920 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1921 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1922
1923 /* Read CrystalCap from EEPROM */
1924 tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1925 rtlefuse->eeprom_crystalcap = tempval;
1926 /* CrystalCap, BIT(12)~15 */
1927 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1928
1929 /* Read IC Version && Channel Plan */
1930 /* Version ID, Channel plan */
1931 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1932 rtlefuse->txpwr_fromeprom = true;
1933 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1934 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1935
1936 /* Read Customer ID or Board Type!!! */
1937 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1938 /* Change RF type definition */
1939 if (tempval == 0)
1940 rtlphy->rf_type = RF_2T2R;
1941 else if (tempval == 1)
1942 rtlphy->rf_type = RF_1T2R;
1943 else if (tempval == 2)
1944 rtlphy->rf_type = RF_1T2R;
1945 else if (tempval == 3)
1946 rtlphy->rf_type = RF_1T1R;
1947
1948 /* 1T2R but 1SS (1x1 receive combining) */
1949 rtlefuse->b1x1_recvcombine = false;
1950 if (rtlphy->rf_type == RF_1T2R) {
1951 tempval = rtl_read_byte(rtlpriv, 0x07);
1952 if (!(tempval & BIT(0))) {
1953 rtlefuse->b1x1_recvcombine = true;
1954 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1955 "RF_TYPE=1T2R but only 1SS\n");
1956 }
1957 }
1958 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1959 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1960
1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1962 rtlefuse->eeprom_oemid);
1963
1964 /* set channel paln to world wide 13 */
1965 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1966 }
1967
rtl92se_read_eeprom_info(struct ieee80211_hw * hw)1968 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1969 {
1970 struct rtl_priv *rtlpriv = rtl_priv(hw);
1971 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1972 u8 tmp_u1b = 0;
1973
1974 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1975
1976 if (tmp_u1b & BIT(4)) {
1977 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1978 rtlefuse->epromtype = EEPROM_93C46;
1979 } else {
1980 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1981 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1982 }
1983
1984 if (tmp_u1b & BIT(5)) {
1985 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1986 rtlefuse->autoload_failflag = false;
1987 _rtl92se_read_adapter_info(hw);
1988 } else {
1989 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1990 rtlefuse->autoload_failflag = true;
1991 }
1992 }
1993
rtl92se_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1994 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1995 struct ieee80211_sta *sta)
1996 {
1997 struct rtl_priv *rtlpriv = rtl_priv(hw);
1998 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1999 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2000 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2001 u32 ratr_value;
2002 u8 ratr_index = 0;
2003 u8 nmode = mac->ht_enable;
2004 u8 mimo_ps = IEEE80211_SMPS_OFF;
2005 u16 shortgi_rate = 0;
2006 u32 tmp_ratr_value = 0;
2007 u8 curtxbw_40mhz = mac->bw_40;
2008 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2009 1 : 0;
2010 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2011 1 : 0;
2012 enum wireless_mode wirelessmode = mac->mode;
2013
2014 if (rtlhal->current_bandtype == BAND_ON_5G)
2015 ratr_value = sta->supp_rates[1] << 4;
2016 else
2017 ratr_value = sta->supp_rates[0];
2018 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2019 sta->ht_cap.mcs.rx_mask[0] << 12);
2020 switch (wirelessmode) {
2021 case WIRELESS_MODE_B:
2022 ratr_value &= 0x0000000D;
2023 break;
2024 case WIRELESS_MODE_G:
2025 ratr_value &= 0x00000FF5;
2026 break;
2027 case WIRELESS_MODE_N_24G:
2028 case WIRELESS_MODE_N_5G:
2029 nmode = 1;
2030 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2031 ratr_value &= 0x0007F005;
2032 } else {
2033 u32 ratr_mask;
2034
2035 if (get_rf_type(rtlphy) == RF_1T2R ||
2036 get_rf_type(rtlphy) == RF_1T1R) {
2037 if (curtxbw_40mhz)
2038 ratr_mask = 0x000ff015;
2039 else
2040 ratr_mask = 0x000ff005;
2041 } else {
2042 if (curtxbw_40mhz)
2043 ratr_mask = 0x0f0ff015;
2044 else
2045 ratr_mask = 0x0f0ff005;
2046 }
2047
2048 ratr_value &= ratr_mask;
2049 }
2050 break;
2051 default:
2052 if (rtlphy->rf_type == RF_1T2R)
2053 ratr_value &= 0x000ff0ff;
2054 else
2055 ratr_value &= 0x0f0ff0ff;
2056
2057 break;
2058 }
2059
2060 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2061 ratr_value &= 0x0FFFFFFF;
2062 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2063 ratr_value &= 0x0FFFFFF0;
2064
2065 if (nmode && ((curtxbw_40mhz &&
2066 curshortgi_40mhz) || (!curtxbw_40mhz &&
2067 curshortgi_20mhz))) {
2068
2069 ratr_value |= 0x10000000;
2070 tmp_ratr_value = (ratr_value >> 12);
2071
2072 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2073 if ((1 << shortgi_rate) & tmp_ratr_value)
2074 break;
2075 }
2076
2077 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2078 (shortgi_rate << 4) | (shortgi_rate);
2079
2080 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2081 }
2082
2083 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2084 if (ratr_value & 0xfffff000)
2085 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2086 else
2087 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2088
2089 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2090 rtl_read_dword(rtlpriv, ARFR0));
2091 }
2092
rtl92se_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level)2093 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2094 struct ieee80211_sta *sta,
2095 u8 rssi_level)
2096 {
2097 struct rtl_priv *rtlpriv = rtl_priv(hw);
2098 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2099 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2100 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2101 struct rtl_sta_info *sta_entry = NULL;
2102 u32 ratr_bitmap;
2103 u8 ratr_index = 0;
2104 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2105 ? 1 : 0;
2106 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2107 1 : 0;
2108 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2109 1 : 0;
2110 enum wireless_mode wirelessmode = 0;
2111 bool shortgi = false;
2112 u32 ratr_value = 0;
2113 u8 shortgi_rate = 0;
2114 u32 mask = 0;
2115 u32 band = 0;
2116 bool bmulticast = false;
2117 u8 macid = 0;
2118 u8 mimo_ps = IEEE80211_SMPS_OFF;
2119
2120 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2121 wirelessmode = sta_entry->wireless_mode;
2122 if (mac->opmode == NL80211_IFTYPE_STATION)
2123 curtxbw_40mhz = mac->bw_40;
2124 else if (mac->opmode == NL80211_IFTYPE_AP ||
2125 mac->opmode == NL80211_IFTYPE_ADHOC)
2126 macid = sta->aid + 1;
2127
2128 if (rtlhal->current_bandtype == BAND_ON_5G)
2129 ratr_bitmap = sta->supp_rates[1] << 4;
2130 else
2131 ratr_bitmap = sta->supp_rates[0];
2132 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2133 sta->ht_cap.mcs.rx_mask[0] << 12);
2134 switch (wirelessmode) {
2135 case WIRELESS_MODE_B:
2136 band |= WIRELESS_11B;
2137 ratr_index = RATR_INX_WIRELESS_B;
2138 if (ratr_bitmap & 0x0000000c)
2139 ratr_bitmap &= 0x0000000d;
2140 else
2141 ratr_bitmap &= 0x0000000f;
2142 break;
2143 case WIRELESS_MODE_G:
2144 band |= (WIRELESS_11G | WIRELESS_11B);
2145 ratr_index = RATR_INX_WIRELESS_GB;
2146
2147 if (rssi_level == 1)
2148 ratr_bitmap &= 0x00000f00;
2149 else if (rssi_level == 2)
2150 ratr_bitmap &= 0x00000ff0;
2151 else
2152 ratr_bitmap &= 0x00000ff5;
2153 break;
2154 case WIRELESS_MODE_A:
2155 band |= WIRELESS_11A;
2156 ratr_index = RATR_INX_WIRELESS_A;
2157 ratr_bitmap &= 0x00000ff0;
2158 break;
2159 case WIRELESS_MODE_N_24G:
2160 case WIRELESS_MODE_N_5G:
2161 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2162 ratr_index = RATR_INX_WIRELESS_NGB;
2163
2164 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2165 if (rssi_level == 1)
2166 ratr_bitmap &= 0x00070000;
2167 else if (rssi_level == 2)
2168 ratr_bitmap &= 0x0007f000;
2169 else
2170 ratr_bitmap &= 0x0007f005;
2171 } else {
2172 if (rtlphy->rf_type == RF_1T2R ||
2173 rtlphy->rf_type == RF_1T1R) {
2174 if (rssi_level == 1) {
2175 ratr_bitmap &= 0x000f0000;
2176 } else if (rssi_level == 3) {
2177 ratr_bitmap &= 0x000fc000;
2178 } else if (rssi_level == 5) {
2179 ratr_bitmap &= 0x000ff000;
2180 } else {
2181 if (curtxbw_40mhz)
2182 ratr_bitmap &= 0x000ff015;
2183 else
2184 ratr_bitmap &= 0x000ff005;
2185 }
2186 } else {
2187 if (rssi_level == 1) {
2188 ratr_bitmap &= 0x0f8f0000;
2189 } else if (rssi_level == 3) {
2190 ratr_bitmap &= 0x0f8fc000;
2191 } else if (rssi_level == 5) {
2192 ratr_bitmap &= 0x0f8ff000;
2193 } else {
2194 if (curtxbw_40mhz)
2195 ratr_bitmap &= 0x0f8ff015;
2196 else
2197 ratr_bitmap &= 0x0f8ff005;
2198 }
2199 }
2200 }
2201
2202 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2203 (!curtxbw_40mhz && curshortgi_20mhz)) {
2204 if (macid == 0)
2205 shortgi = true;
2206 else if (macid == 1)
2207 shortgi = false;
2208 }
2209 break;
2210 default:
2211 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2212 ratr_index = RATR_INX_WIRELESS_NGB;
2213
2214 if (rtlphy->rf_type == RF_1T2R)
2215 ratr_bitmap &= 0x000ff0ff;
2216 else
2217 ratr_bitmap &= 0x0f8ff0ff;
2218 break;
2219 }
2220
2221 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2222 ratr_bitmap &= 0x0FFFFFFF;
2223 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2224 ratr_bitmap &= 0x0FFFFFF0;
2225
2226 if (shortgi) {
2227 ratr_bitmap |= 0x10000000;
2228 /* Get MAX MCS available. */
2229 ratr_value = (ratr_bitmap >> 12);
2230 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2231 if ((1 << shortgi_rate) & ratr_value)
2232 break;
2233 }
2234
2235 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2236 (shortgi_rate << 4) | (shortgi_rate);
2237 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2238 }
2239
2240 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2241
2242 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2243 mask, ratr_bitmap);
2244 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2245 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2246
2247 if (macid != 0)
2248 sta_entry->ratr_index = ratr_index;
2249 }
2250
rtl92se_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level)2251 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2252 struct ieee80211_sta *sta, u8 rssi_level)
2253 {
2254 struct rtl_priv *rtlpriv = rtl_priv(hw);
2255
2256 if (rtlpriv->dm.useramask)
2257 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2258 else
2259 rtl92se_update_hal_rate_table(hw, sta);
2260 }
2261
rtl92se_update_channel_access_setting(struct ieee80211_hw * hw)2262 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2263 {
2264 struct rtl_priv *rtlpriv = rtl_priv(hw);
2265 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2266 u16 sifs_timer;
2267
2268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2269 (u8 *)&mac->slot_time);
2270 sifs_timer = 0x0e0e;
2271 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2272
2273 }
2274
2275 /* this ifunction is for RFKILL, it's different with windows,
2276 * because UI will disable wireless when GPIO Radio Off.
2277 * And here we not check or Disable/Enable ASPM like windows*/
rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2278 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2279 {
2280 struct rtl_priv *rtlpriv = rtl_priv(hw);
2281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2282 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2283 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2284 unsigned long flag = 0;
2285 bool actuallyset = false;
2286 bool turnonbypowerdomain = false;
2287
2288 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2289 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2290 return false;
2291
2292 if (ppsc->swrf_processing)
2293 return false;
2294
2295 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2296 if (ppsc->rfchange_inprogress) {
2297 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2298 return false;
2299 } else {
2300 ppsc->rfchange_inprogress = true;
2301 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2302 }
2303
2304 /* cur_rfstate = ppsc->rfpwr_state;*/
2305
2306 /* because after _rtl92s_phy_set_rfhalt, all power
2307 * closed, so we must open some power for GPIO check,
2308 * or we will always check GPIO RFOFF here,
2309 * And we should close power after GPIO check */
2310 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2311 _rtl92se_power_domain_init(hw);
2312 turnonbypowerdomain = true;
2313 }
2314
2315 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2316
2317 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2318 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2319 "RFKILL-HW Radio ON, RF ON\n");
2320
2321 rfpwr_toset = ERFON;
2322 ppsc->hwradiooff = false;
2323 actuallyset = true;
2324 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2325 RT_TRACE(rtlpriv, COMP_RF,
2326 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2327
2328 rfpwr_toset = ERFOFF;
2329 ppsc->hwradiooff = true;
2330 actuallyset = true;
2331 }
2332
2333 if (actuallyset) {
2334 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2335 ppsc->rfchange_inprogress = false;
2336 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2337
2338 /* this not include ifconfig wlan0 down case */
2339 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2340 } else {
2341 /* because power_domain_init may be happen when
2342 * _rtl92s_phy_set_rfhalt, this will open some powers
2343 * and cause current increasing about 40 mA for ips,
2344 * rfoff and ifconfig down, so we set
2345 * _rtl92s_phy_set_rfhalt again here */
2346 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2347 turnonbypowerdomain) {
2348 _rtl92s_phy_set_rfhalt(hw);
2349 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2350 }
2351
2352 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2353 ppsc->rfchange_inprogress = false;
2354 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2355 }
2356
2357 *valid = 1;
2358 return !ppsc->hwradiooff;
2359
2360 }
2361
2362 /* Is_wepkey just used for WEP used as group & pairwise key
2363 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
rtl92se_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2364 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2365 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2366 {
2367 struct rtl_priv *rtlpriv = rtl_priv(hw);
2368 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2369 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2370 u8 *macaddr = p_macaddr;
2371
2372 u32 entry_id = 0;
2373 bool is_pairwise = false;
2374
2375 static u8 cam_const_addr[4][6] = {
2376 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2377 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2378 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2379 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2380 };
2381 static u8 cam_const_broad[] = {
2382 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2383 };
2384
2385 if (clear_all) {
2386 u8 idx = 0;
2387 u8 cam_offset = 0;
2388 u8 clear_number = 5;
2389
2390 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2391
2392 for (idx = 0; idx < clear_number; idx++) {
2393 rtl_cam_mark_invalid(hw, cam_offset + idx);
2394 rtl_cam_empty_entry(hw, cam_offset + idx);
2395
2396 if (idx < 5) {
2397 memset(rtlpriv->sec.key_buf[idx], 0,
2398 MAX_KEY_LEN);
2399 rtlpriv->sec.key_len[idx] = 0;
2400 }
2401 }
2402
2403 } else {
2404 switch (enc_algo) {
2405 case WEP40_ENCRYPTION:
2406 enc_algo = CAM_WEP40;
2407 break;
2408 case WEP104_ENCRYPTION:
2409 enc_algo = CAM_WEP104;
2410 break;
2411 case TKIP_ENCRYPTION:
2412 enc_algo = CAM_TKIP;
2413 break;
2414 case AESCCMP_ENCRYPTION:
2415 enc_algo = CAM_AES;
2416 break;
2417 default:
2418 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2419 "switch case not processed\n");
2420 enc_algo = CAM_TKIP;
2421 break;
2422 }
2423
2424 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2425 macaddr = cam_const_addr[key_index];
2426 entry_id = key_index;
2427 } else {
2428 if (is_group) {
2429 macaddr = cam_const_broad;
2430 entry_id = key_index;
2431 } else {
2432 if (mac->opmode == NL80211_IFTYPE_AP) {
2433 entry_id = rtl_cam_get_free_entry(hw,
2434 p_macaddr);
2435 if (entry_id >= TOTAL_CAM_ENTRY) {
2436 RT_TRACE(rtlpriv,
2437 COMP_SEC, DBG_EMERG,
2438 "Can not find free hw security cam entry\n");
2439 return;
2440 }
2441 } else {
2442 entry_id = CAM_PAIRWISE_KEY_POSITION;
2443 }
2444
2445 key_index = PAIRWISE_KEYIDX;
2446 is_pairwise = true;
2447 }
2448 }
2449
2450 if (rtlpriv->sec.key_len[key_index] == 0) {
2451 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2452 "delete one entry, entry_id is %d\n",
2453 entry_id);
2454 if (mac->opmode == NL80211_IFTYPE_AP)
2455 rtl_cam_del_entry(hw, p_macaddr);
2456 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2457 } else {
2458 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2459 "The insert KEY length is %d\n",
2460 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2461 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2462 "The insert KEY is %x %x\n",
2463 rtlpriv->sec.key_buf[0][0],
2464 rtlpriv->sec.key_buf[0][1]);
2465
2466 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2467 "add one entry\n");
2468 if (is_pairwise) {
2469 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2470 "Pairwise Key content",
2471 rtlpriv->sec.pairwise_key,
2472 rtlpriv->sec.
2473 key_len[PAIRWISE_KEYIDX]);
2474
2475 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2476 "set Pairwise key\n");
2477
2478 rtl_cam_add_one_entry(hw, macaddr, key_index,
2479 entry_id, enc_algo,
2480 CAM_CONFIG_NO_USEDK,
2481 rtlpriv->sec.key_buf[key_index]);
2482 } else {
2483 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2484 "set group key\n");
2485
2486 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2487 rtl_cam_add_one_entry(hw,
2488 rtlefuse->dev_addr,
2489 PAIRWISE_KEYIDX,
2490 CAM_PAIRWISE_KEY_POSITION,
2491 enc_algo, CAM_CONFIG_NO_USEDK,
2492 rtlpriv->sec.key_buf[entry_id]);
2493 }
2494
2495 rtl_cam_add_one_entry(hw, macaddr, key_index,
2496 entry_id, enc_algo,
2497 CAM_CONFIG_NO_USEDK,
2498 rtlpriv->sec.key_buf[entry_id]);
2499 }
2500
2501 }
2502 }
2503 }
2504
rtl92se_suspend(struct ieee80211_hw * hw)2505 void rtl92se_suspend(struct ieee80211_hw *hw)
2506 {
2507 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2508
2509 rtlpci->up_first_time = true;
2510 }
2511
rtl92se_resume(struct ieee80211_hw * hw)2512 void rtl92se_resume(struct ieee80211_hw *hw)
2513 {
2514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2515 u32 val;
2516
2517 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2518 if ((val & 0x0000ff00) != 0)
2519 pci_write_config_dword(rtlpci->pdev, 0x40,
2520 val & 0xffff00ff);
2521 }
2522