1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "reg.h"
32 #include "def.h"
33 #include "phy.h"
34 #include "rf.h"
35 #include "dm.h"
36
37
_rtl92s_get_powerbase(struct ieee80211_hw * hw,u8 * p_pwrlevel,u8 chnl,u32 * ofdmbase,u32 * mcsbase,u8 * p_final_pwridx)38 static void _rtl92s_get_powerbase(struct ieee80211_hw *hw, u8 *p_pwrlevel,
39 u8 chnl, u32 *ofdmbase, u32 *mcsbase,
40 u8 *p_final_pwridx)
41 {
42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43 struct rtl_phy *rtlphy = &(rtlpriv->phy);
44 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
45 u32 pwrbase0, pwrbase1;
46 u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
47 u8 i, pwrlevel[4];
48
49 for (i = 0; i < 2; i++)
50 pwrlevel[i] = p_pwrlevel[i];
51
52 /* We only care about the path A for legacy. */
53 if (rtlefuse->eeprom_version < 2) {
54 pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_httxpowerdiff & 0xf);
55 } else if (rtlefuse->eeprom_version >= 2) {
56 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff
57 [RF90_PATH_A][chnl - 1];
58
59 /* For legacy OFDM, tx pwr always > HT OFDM pwr.
60 * We do not care Path B
61 * legacy OFDM pwr diff. NO BB register
62 * to notify HW. */
63 pwrbase0 = pwrlevel[0] + legacy_pwrdiff;
64 }
65
66 pwrbase0 = (pwrbase0 << 24) | (pwrbase0 << 16) | (pwrbase0 << 8) |
67 pwrbase0;
68 *ofdmbase = pwrbase0;
69
70 /* MCS rates */
71 if (rtlefuse->eeprom_version >= 2) {
72 /* Check HT20 to HT40 diff */
73 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
74 for (i = 0; i < 2; i++) {
75 /* rf-A, rf-B */
76 /* HT 20<->40 pwr diff */
77 ht20_pwrdiff = rtlefuse->txpwr_ht20diff
78 [i][chnl - 1];
79
80 if (ht20_pwrdiff < 8) /* 0~+7 */
81 pwrlevel[i] += ht20_pwrdiff;
82 else /* index8-15=-8~-1 */
83 pwrlevel[i] -= (16 - ht20_pwrdiff);
84 }
85 }
86 }
87
88 /* use index of rf-A */
89 pwrbase1 = pwrlevel[0];
90 pwrbase1 = (pwrbase1 << 24) | (pwrbase1 << 16) | (pwrbase1 << 8) |
91 pwrbase1;
92 *mcsbase = pwrbase1;
93
94 /* The following is for Antenna
95 * diff from Ant-B to Ant-A */
96 p_final_pwridx[0] = pwrlevel[0];
97 p_final_pwridx[1] = pwrlevel[1];
98
99 switch (rtlefuse->eeprom_regulatory) {
100 case 3:
101 /* The following is for calculation
102 * of the power diff for Ant-B to Ant-A. */
103 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
104 p_final_pwridx[0] += rtlefuse->pwrgroup_ht40
105 [RF90_PATH_A][
106 chnl - 1];
107 p_final_pwridx[1] += rtlefuse->pwrgroup_ht40
108 [RF90_PATH_B][
109 chnl - 1];
110 } else {
111 p_final_pwridx[0] += rtlefuse->pwrgroup_ht20
112 [RF90_PATH_A][
113 chnl - 1];
114 p_final_pwridx[1] += rtlefuse->pwrgroup_ht20
115 [RF90_PATH_B][
116 chnl - 1];
117 }
118 break;
119 default:
120 break;
121 }
122
123 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
124 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
125 "40MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
126 p_final_pwridx[0], p_final_pwridx[1]);
127 } else {
128 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
129 "20MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
130 p_final_pwridx[0], p_final_pwridx[1]);
131 }
132 }
133
_rtl92s_set_antennadiff(struct ieee80211_hw * hw,u8 * p_final_pwridx)134 static void _rtl92s_set_antennadiff(struct ieee80211_hw *hw,
135 u8 *p_final_pwridx)
136 {
137 struct rtl_priv *rtlpriv = rtl_priv(hw);
138 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
139 struct rtl_phy *rtlphy = &(rtlpriv->phy);
140 char ant_pwr_diff = 0;
141 u32 u4reg_val = 0;
142
143 if (rtlphy->rf_type == RF_2T2R) {
144 ant_pwr_diff = p_final_pwridx[1] - p_final_pwridx[0];
145
146 /* range is from 7~-8,
147 * index = 0x0~0xf */
148 if (ant_pwr_diff > 7)
149 ant_pwr_diff = 7;
150 if (ant_pwr_diff < -8)
151 ant_pwr_diff = -8;
152
153 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
154 "Antenna Diff from RF-B to RF-A = %d (0x%x)\n",
155 ant_pwr_diff, ant_pwr_diff & 0xf);
156
157 ant_pwr_diff &= 0xf;
158 }
159
160 /* Antenna TX power difference */
161 rtlefuse->antenna_txpwdiff[2] = 0;/* RF-D, don't care */
162 rtlefuse->antenna_txpwdiff[1] = 0;/* RF-C, don't care */
163 rtlefuse->antenna_txpwdiff[0] = (u8)(ant_pwr_diff); /* RF-B */
164
165 u4reg_val = rtlefuse->antenna_txpwdiff[2] << 8 |
166 rtlefuse->antenna_txpwdiff[1] << 4 |
167 rtlefuse->antenna_txpwdiff[0];
168
169 rtl_set_bbreg(hw, RFPGA0_TXGAINSTAGE, (BXBTXAGC | BXCTXAGC | BXDTXAGC),
170 u4reg_val);
171
172 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n",
173 RFPGA0_TXGAINSTAGE, u4reg_val);
174 }
175
_rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw * hw,u8 chnl,u8 index,u32 pwrbase0,u32 pwrbase1,u32 * p_outwrite_val)176 static void _rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw *hw,
177 u8 chnl, u8 index,
178 u32 pwrbase0,
179 u32 pwrbase1,
180 u32 *p_outwrite_val)
181 {
182 struct rtl_priv *rtlpriv = rtl_priv(hw);
183 struct rtl_phy *rtlphy = &(rtlpriv->phy);
184 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
185 u8 i, chnlgroup, pwrdiff_limit[4];
186 u32 writeval, customer_limit;
187
188 /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
189 switch (rtlefuse->eeprom_regulatory) {
190 case 0:
191 /* Realtek better performance increase power diff
192 * defined by Realtek for large power */
193 chnlgroup = 0;
194
195 writeval = rtlphy->mcs_txpwrlevel_origoffset
196 [chnlgroup][index] +
197 ((index < 2) ? pwrbase0 : pwrbase1);
198
199 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
200 "RTK better performance, writeval = 0x%x\n", writeval);
201 break;
202 case 1:
203 /* Realtek regulatory increase power diff defined
204 * by Realtek for regulatory */
205 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
206 writeval = ((index < 2) ? pwrbase0 : pwrbase1);
207
208 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
209 "Realtek regulatory, 40MHz, writeval = 0x%x\n",
210 writeval);
211 } else {
212 if (rtlphy->pwrgroup_cnt == 1)
213 chnlgroup = 0;
214
215 if (rtlphy->pwrgroup_cnt >= 3) {
216 if (chnl <= 3)
217 chnlgroup = 0;
218 else if (chnl >= 4 && chnl <= 8)
219 chnlgroup = 1;
220 else if (chnl > 8)
221 chnlgroup = 2;
222 if (rtlphy->pwrgroup_cnt == 4)
223 chnlgroup++;
224 }
225
226 writeval = rtlphy->mcs_txpwrlevel_origoffset
227 [chnlgroup][index]
228 + ((index < 2) ?
229 pwrbase0 : pwrbase1);
230
231 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
232 "Realtek regulatory, 20MHz, writeval = 0x%x\n",
233 writeval);
234 }
235 break;
236 case 2:
237 /* Better regulatory don't increase any power diff */
238 writeval = ((index < 2) ? pwrbase0 : pwrbase1);
239 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
240 "Better regulatory, writeval = 0x%x\n", writeval);
241 break;
242 case 3:
243 /* Customer defined power diff. increase power diff
244 defined by customer. */
245 chnlgroup = 0;
246
247 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
248 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
249 "customer's limit, 40MHz = 0x%x\n",
250 rtlefuse->pwrgroup_ht40
251 [RF90_PATH_A][chnl - 1]);
252 } else {
253 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
254 "customer's limit, 20MHz = 0x%x\n",
255 rtlefuse->pwrgroup_ht20
256 [RF90_PATH_A][chnl - 1]);
257 }
258
259 for (i = 0; i < 4; i++) {
260 pwrdiff_limit[i] =
261 (u8)((rtlphy->mcs_txpwrlevel_origoffset
262 [chnlgroup][index] & (0x7f << (i * 8)))
263 >> (i * 8));
264
265 if (rtlphy->current_chan_bw ==
266 HT_CHANNEL_WIDTH_20_40) {
267 if (pwrdiff_limit[i] >
268 rtlefuse->pwrgroup_ht40
269 [RF90_PATH_A][chnl - 1]) {
270 pwrdiff_limit[i] =
271 rtlefuse->pwrgroup_ht40
272 [RF90_PATH_A][chnl - 1];
273 }
274 } else {
275 if (pwrdiff_limit[i] >
276 rtlefuse->pwrgroup_ht20
277 [RF90_PATH_A][chnl - 1]) {
278 pwrdiff_limit[i] =
279 rtlefuse->pwrgroup_ht20
280 [RF90_PATH_A][chnl - 1];
281 }
282 }
283 }
284
285 customer_limit = (pwrdiff_limit[3] << 24) |
286 (pwrdiff_limit[2] << 16) |
287 (pwrdiff_limit[1] << 8) |
288 (pwrdiff_limit[0]);
289 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
290 "Customer's limit = 0x%x\n", customer_limit);
291
292 writeval = customer_limit + ((index < 2) ?
293 pwrbase0 : pwrbase1);
294 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
295 "Customer, writeval = 0x%x\n", writeval);
296 break;
297 default:
298 chnlgroup = 0;
299 writeval = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index] +
300 ((index < 2) ? pwrbase0 : pwrbase1);
301 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
302 "RTK better performance, writeval = 0x%x\n", writeval);
303 break;
304 }
305
306 if (rtlpriv->dm.dynamic_txhighpower_lvl == TX_HIGH_PWR_LEVEL_LEVEL1)
307 writeval = 0x10101010;
308 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
309 TX_HIGH_PWR_LEVEL_LEVEL2)
310 writeval = 0x0;
311
312 *p_outwrite_val = writeval;
313
314 }
315
_rtl92s_write_ofdm_powerreg(struct ieee80211_hw * hw,u8 index,u32 val)316 static void _rtl92s_write_ofdm_powerreg(struct ieee80211_hw *hw,
317 u8 index, u32 val)
318 {
319 struct rtl_priv *rtlpriv = rtl_priv(hw);
320 struct rtl_phy *rtlphy = &(rtlpriv->phy);
321 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
322 u16 regoffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
323 u8 i, rfa_pwr[4];
324 u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0;
325 u32 writeval = val;
326
327 /* If path A and Path B coexist, we must limit Path A tx power.
328 * Protect Path B pwr over or under flow. We need to calculate
329 * upper and lower bound of path A tx power. */
330 if (rtlphy->rf_type == RF_2T2R) {
331 rf_pwr_diff = rtlefuse->antenna_txpwdiff[0];
332
333 /* Diff=-8~-1 */
334 if (rf_pwr_diff >= 8) {
335 /* Prevent underflow!! */
336 rfa_lower_bound = 0x10 - rf_pwr_diff;
337 /* if (rf_pwr_diff >= 0) Diff = 0-7 */
338 } else {
339 rfa_upper_bound = RF6052_MAX_TX_PWR - rf_pwr_diff;
340 }
341 }
342
343 for (i = 0; i < 4; i++) {
344 rfa_pwr[i] = (u8)((writeval & (0x7f << (i * 8))) >> (i * 8));
345 if (rfa_pwr[i] > RF6052_MAX_TX_PWR)
346 rfa_pwr[i] = RF6052_MAX_TX_PWR;
347
348 /* If path A and Path B coexist, we must limit Path A tx power.
349 * Protect Path B pwr over or under flow. We need to calculate
350 * upper and lower bound of path A tx power. */
351 if (rtlphy->rf_type == RF_2T2R) {
352 /* Diff=-8~-1 */
353 if (rf_pwr_diff >= 8) {
354 /* Prevent underflow!! */
355 if (rfa_pwr[i] < rfa_lower_bound)
356 rfa_pwr[i] = rfa_lower_bound;
357 /* Diff = 0-7 */
358 } else if (rf_pwr_diff >= 1) {
359 /* Prevent overflow */
360 if (rfa_pwr[i] > rfa_upper_bound)
361 rfa_pwr[i] = rfa_upper_bound;
362 }
363 }
364
365 }
366
367 writeval = (rfa_pwr[3] << 24) | (rfa_pwr[2] << 16) | (rfa_pwr[1] << 8) |
368 rfa_pwr[0];
369
370 rtl_set_bbreg(hw, regoffset[index], 0x7f7f7f7f, writeval);
371 }
372
rtl92s_phy_rf6052_set_ofdmtxpower(struct ieee80211_hw * hw,u8 * p_pwrlevel,u8 chnl)373 void rtl92s_phy_rf6052_set_ofdmtxpower(struct ieee80211_hw *hw,
374 u8 *p_pwrlevel, u8 chnl)
375 {
376 u32 writeval, pwrbase0, pwrbase1;
377 u8 index = 0;
378 u8 finalpwr_idx[4];
379
380 _rtl92s_get_powerbase(hw, p_pwrlevel, chnl, &pwrbase0, &pwrbase1,
381 &finalpwr_idx[0]);
382 _rtl92s_set_antennadiff(hw, &finalpwr_idx[0]);
383
384 for (index = 0; index < 6; index++) {
385 _rtl92s_get_txpower_writeval_byregulatory(hw, chnl, index,
386 pwrbase0, pwrbase1, &writeval);
387
388 _rtl92s_write_ofdm_powerreg(hw, index, writeval);
389 }
390 }
391
rtl92s_phy_rf6052_set_ccktxpower(struct ieee80211_hw * hw,u8 pwrlevel)392 void rtl92s_phy_rf6052_set_ccktxpower(struct ieee80211_hw *hw, u8 pwrlevel)
393 {
394 struct rtl_priv *rtlpriv = rtl_priv(hw);
395 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
396 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
397 u32 txagc = 0;
398 bool dont_inc_cck_or_turboscanoff = false;
399
400 if (((rtlefuse->eeprom_version >= 2) &&
401 (rtlefuse->txpwr_safetyflag == 1)) ||
402 ((rtlefuse->eeprom_version >= 2) &&
403 (rtlefuse->eeprom_regulatory != 0)))
404 dont_inc_cck_or_turboscanoff = true;
405
406 if (mac->act_scanning) {
407 txagc = 0x3f;
408 if (dont_inc_cck_or_turboscanoff)
409 txagc = pwrlevel;
410 } else {
411 txagc = pwrlevel;
412
413 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
414 TX_HIGH_PWR_LEVEL_LEVEL1)
415 txagc = 0x10;
416 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
417 TX_HIGH_PWR_LEVEL_LEVEL2)
418 txagc = 0x0;
419 }
420
421 if (txagc > RF6052_MAX_TX_PWR)
422 txagc = RF6052_MAX_TX_PWR;
423
424 rtl_set_bbreg(hw, RTXAGC_CCK_MCS32, BTX_AGCRATECCK, txagc);
425
426 }
427
rtl92s_phy_rf6052_config(struct ieee80211_hw * hw)428 bool rtl92s_phy_rf6052_config(struct ieee80211_hw *hw)
429 {
430 struct rtl_priv *rtlpriv = rtl_priv(hw);
431 struct rtl_phy *rtlphy = &(rtlpriv->phy);
432 u32 u4reg_val = 0;
433 u8 rfpath;
434 bool rtstatus = true;
435 struct bb_reg_def *pphyreg;
436
437 /* Initialize RF */
438 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
439
440 pphyreg = &rtlphy->phyreg_def[rfpath];
441
442 /* Store original RFENV control type */
443 switch (rfpath) {
444 case RF90_PATH_A:
445 case RF90_PATH_C:
446 u4reg_val = rtl92s_phy_query_bb_reg(hw,
447 pphyreg->rfintfs,
448 BRFSI_RFENV);
449 break;
450 case RF90_PATH_B:
451 case RF90_PATH_D:
452 u4reg_val = rtl92s_phy_query_bb_reg(hw,
453 pphyreg->rfintfs,
454 BRFSI_RFENV << 16);
455 break;
456 }
457
458 /* Set RF_ENV enable */
459 rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfe,
460 BRFSI_RFENV << 16, 0x1);
461
462 /* Set RF_ENV output high */
463 rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
464
465 /* Set bit number of Address and Data for RF register */
466 rtl92s_phy_set_bb_reg(hw, pphyreg->rfhssi_para2,
467 B3WIRE_ADDRESSLENGTH, 0x0);
468 rtl92s_phy_set_bb_reg(hw, pphyreg->rfhssi_para2,
469 B3WIRE_DATALENGTH, 0x0);
470
471 /* Initialize RF fom connfiguration file */
472 switch (rfpath) {
473 case RF90_PATH_A:
474 rtstatus = rtl92s_phy_config_rf(hw,
475 (enum radio_path)rfpath);
476 break;
477 case RF90_PATH_B:
478 rtstatus = rtl92s_phy_config_rf(hw,
479 (enum radio_path)rfpath);
480 break;
481 case RF90_PATH_C:
482 break;
483 case RF90_PATH_D:
484 break;
485 }
486
487 /* Restore RFENV control type */
488 switch (rfpath) {
489 case RF90_PATH_A:
490 case RF90_PATH_C:
491 rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfs, BRFSI_RFENV,
492 u4reg_val);
493 break;
494 case RF90_PATH_B:
495 case RF90_PATH_D:
496 rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfs,
497 BRFSI_RFENV << 16,
498 u4reg_val);
499 break;
500 }
501
502 if (!rtstatus) {
503 pr_err("Radio[%d] Fail!!\n", rfpath);
504 goto fail;
505 }
506
507 }
508
509 return rtstatus;
510
511 fail:
512 return rtstatus;
513 }
514
rtl92s_phy_rf6052_set_bandwidth(struct ieee80211_hw * hw,u8 bandwidth)515 void rtl92s_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
516 {
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
518 struct rtl_phy *rtlphy = &(rtlpriv->phy);
519
520 switch (bandwidth) {
521 case HT_CHANNEL_WIDTH_20:
522 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
523 0xfffff3ff) | 0x0400);
524 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
525 rtlphy->rfreg_chnlval[0]);
526 break;
527 case HT_CHANNEL_WIDTH_20_40:
528 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
529 0xfffff3ff));
530 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
531 rtlphy->rfreg_chnlval[0]);
532 break;
533 default:
534 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
535 "unknown bandwidth: %#X\n", bandwidth);
536 break;
537 }
538 }
539