1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #define _HCI_HAL_INIT_C_
5
6 #include "../include/osdep_service.h"
7 #include "../include/drv_types.h"
8 #include "../include/rtw_efuse.h"
9 #include "../include/rtw_fw.h"
10 #include "../include/rtl8188e_hal.h"
11 #include "../include/rtw_iol.h"
12 #include "../include/usb_ops.h"
13 #include "../include/usb_osintf.h"
14 #include "../include/HalPwrSeqCmd.h"
15
one_out_pipe(struct adapter * adapter)16 static void one_out_pipe(struct adapter *adapter)
17 {
18 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
19
20 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
21 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
22 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
23 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
24 }
25
two_out_pipe(struct adapter * adapter,bool wifi_cfg)26 static void two_out_pipe(struct adapter *adapter, bool wifi_cfg)
27 {
28 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
29
30 /* 0:H, 1:L */
31
32 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
33 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
34
35 if (wifi_cfg) {
36 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
37 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
38 } else {
39 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
40 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
41 }
42 }
43
three_out_pipe(struct adapter * adapter,bool wifi_cfg)44 static void three_out_pipe(struct adapter *adapter, bool wifi_cfg)
45 {
46 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
47
48 /* 0:H, 1:N, 2:L */
49
50 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
51 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
52 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
53
54 pdvobjpriv->Queue2Pipe[3] = wifi_cfg ?
55 pdvobjpriv->RtOutPipe[1] : pdvobjpriv->RtOutPipe[2];/* BK */
56 }
57
rtl8188eu_interface_configure(struct adapter * adapt)58 int rtl8188eu_interface_configure(struct adapter *adapt)
59 {
60 struct registry_priv *pregistrypriv = &adapt->registrypriv;
61 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
62 struct hal_data_8188e *haldata = &adapt->haldata;
63 bool wifi_cfg = pregistrypriv->wifi_spec;
64
65 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
66 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
67 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
68 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
69
70 switch (pdvobjpriv->RtNumOutPipes) {
71 case 3:
72 haldata->out_ep_extra_queues = TX_SELE_LQ | TX_SELE_NQ;
73 three_out_pipe(adapt, wifi_cfg);
74 break;
75 case 2:
76 haldata->out_ep_extra_queues = TX_SELE_NQ;
77 two_out_pipe(adapt, wifi_cfg);
78 break;
79 case 1:
80 one_out_pipe(adapt);
81 break;
82 default:
83 return -ENXIO;
84 }
85
86 return 0;
87 }
88
rtl8188eu_InitPowerOn(struct adapter * adapt)89 u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
90 {
91 u16 value16;
92 int res;
93
94 /* HW Power on sequence */
95 struct hal_data_8188e *haldata = &adapt->haldata;
96 if (haldata->bMacPwrCtrlOn)
97 return _SUCCESS;
98
99 if (!HalPwrSeqCmdParsing(adapt, PWR_ON_FLOW))
100 return _FAIL;
101
102 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
103 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
104 rtw_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
105
106 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
107 res = rtw_read16(adapt, REG_CR, &value16);
108 if (res)
109 return _FAIL;
110
111 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
112 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
113 /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
114
115 rtw_write16(adapt, REG_CR, value16);
116 haldata->bMacPwrCtrlOn = true;
117
118 return _SUCCESS;
119 }
120
121 /* Shall USB interface init this? */
_InitInterrupt(struct adapter * Adapter)122 static void _InitInterrupt(struct adapter *Adapter)
123 {
124 u32 imr, imr_ex;
125 u8 usb_opt;
126 int res;
127
128 /* HISR write one to clear */
129 rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
130 /* HIMR - */
131 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
132 rtw_write32(Adapter, REG_HIMR_88E, imr);
133
134 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
135 rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
136
137 /* REG_USB_SPECIAL_OPTION - BIT(4) */
138 /* 0; Use interrupt endpoint to upload interrupt pkt */
139 /* 1; Use bulk endpoint to upload interrupt pkt, */
140 res = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION, &usb_opt);
141 if (res)
142 return;
143
144 if (adapter_to_dvobj(Adapter)->pusbdev->speed == USB_SPEED_HIGH)
145 usb_opt = usb_opt | (INT_BULK_SEL);
146 else
147 usb_opt = usb_opt & (~INT_BULK_SEL);
148
149 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
150 }
151
_InitQueueReservedPage(struct adapter * Adapter)152 static void _InitQueueReservedPage(struct adapter *Adapter)
153 {
154 struct hal_data_8188e *haldata = &Adapter->haldata;
155 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
156 u8 numLQ = 0;
157 u8 numNQ = 0;
158 u8 numPubQ;
159
160 if (pregistrypriv->wifi_spec) {
161 if (haldata->out_ep_extra_queues & TX_SELE_LQ)
162 numLQ = 0x1C;
163
164 /* NOTE: This step shall be proceed before writing REG_RQPN. */
165 if (haldata->out_ep_extra_queues & TX_SELE_NQ)
166 numNQ = 0x1C;
167
168 rtw_write8(Adapter, REG_RQPN_NPQ, numNQ);
169
170 numPubQ = 0xA8 - NUM_HQ - numLQ - numNQ;
171
172 /* TX DMA */
173 rtw_write32(Adapter, REG_RQPN, LD_RQPN | numPubQ << 16 | numLQ << 8 | NUM_HQ);
174 } else {
175 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
176 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
177 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
178 }
179 }
180
_InitTxBufferBoundary(struct adapter * Adapter,u8 txpktbuf_bndy)181 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
182 {
183 rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
184 rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
185 rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
186 rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
187 rtw_write8(Adapter, REG_TDECTRL + 1, txpktbuf_bndy);
188 }
189
_InitPageBoundary(struct adapter * Adapter)190 static void _InitPageBoundary(struct adapter *Adapter)
191 {
192 /* RX Page Boundary */
193 /* */
194 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E - 1;
195
196 rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
197 }
198
_InitNormalChipRegPriority(struct adapter * Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)199 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
200 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
201 u16 hiQ)
202 {
203 u16 value16;
204 int res;
205
206 res = rtw_read16(Adapter, REG_TRXDMA_CTRL, &value16);
207 if (res)
208 return;
209
210 value16 &= 0x7;
211
212 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
213 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
214 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
215
216 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
217 }
218
_InitNormalChipTwoOutEpPriority(struct adapter * Adapter)219 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
220 {
221 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
222 u16 bkQ, voQ;
223
224 if (!pregistrypriv->wifi_spec) {
225 bkQ = QUEUE_NORMAL;
226 voQ = QUEUE_HIGH;
227 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
228 bkQ = QUEUE_HIGH;
229 voQ = QUEUE_NORMAL;
230 }
231 _InitNormalChipRegPriority(Adapter, QUEUE_NORMAL, bkQ, QUEUE_HIGH,
232 voQ, QUEUE_HIGH, QUEUE_HIGH);
233 }
234
_InitNormalChipThreeOutEpPriority(struct adapter * Adapter)235 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
236 {
237 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
238 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
239
240 if (!pregistrypriv->wifi_spec) {/* typical setting */
241 beQ = QUEUE_LOW;
242 bkQ = QUEUE_LOW;
243 viQ = QUEUE_NORMAL;
244 voQ = QUEUE_HIGH;
245 mgtQ = QUEUE_HIGH;
246 hiQ = QUEUE_HIGH;
247 } else {/* for WMM */
248 beQ = QUEUE_LOW;
249 bkQ = QUEUE_NORMAL;
250 viQ = QUEUE_NORMAL;
251 voQ = QUEUE_HIGH;
252 mgtQ = QUEUE_HIGH;
253 hiQ = QUEUE_HIGH;
254 }
255 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
256 }
257
_InitQueuePriority(struct adapter * Adapter)258 static void _InitQueuePriority(struct adapter *Adapter)
259 {
260 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
261
262 switch (pdvobjpriv->RtNumOutPipes) {
263 case 1:
264 _InitNormalChipRegPriority(Adapter, QUEUE_HIGH, QUEUE_HIGH, QUEUE_HIGH,
265 QUEUE_HIGH, QUEUE_HIGH, QUEUE_HIGH);
266 break;
267 case 2:
268 _InitNormalChipTwoOutEpPriority(Adapter);
269 break;
270 case 3:
271 _InitNormalChipThreeOutEpPriority(Adapter);
272 break;
273 default:
274 break;
275 }
276 }
277
_InitNetworkType(struct adapter * Adapter)278 static void _InitNetworkType(struct adapter *Adapter)
279 {
280 u32 value32;
281 int res;
282
283 res = rtw_read32(Adapter, REG_CR, &value32);
284 if (res)
285 return;
286
287 /* TODO: use the other function to set network type */
288 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
289
290 rtw_write32(Adapter, REG_CR, value32);
291 }
292
_InitTransferPageSize(struct adapter * Adapter)293 static void _InitTransferPageSize(struct adapter *Adapter)
294 {
295 /* Tx page size is always 128. */
296
297 u8 value8;
298 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
299 rtw_write8(Adapter, REG_PBP, value8);
300 }
301
_InitDriverInfoSize(struct adapter * Adapter,u8 drvInfoSize)302 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
303 {
304 rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
305 }
306
_InitWMACSetting(struct adapter * Adapter)307 static void _InitWMACSetting(struct adapter *Adapter)
308 {
309 u32 receive_config = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
310 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
311 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
312 RCR_APP_MIC | RCR_APP_PHYSTS;
313
314 /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
315 rtw_write32(Adapter, REG_RCR, receive_config);
316
317 /* Accept all multicast address */
318 rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
319 rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
320 }
321
_InitAdaptiveCtrl(struct adapter * Adapter)322 static void _InitAdaptiveCtrl(struct adapter *Adapter)
323 {
324 u16 value16;
325 u32 value32;
326 int res;
327
328 /* Response Rate Set */
329 res = rtw_read32(Adapter, REG_RRSR, &value32);
330 if (res)
331 return;
332
333 value32 &= ~RATE_BITMAP_ALL;
334 value32 |= RATE_RRSR_CCK_ONLY_1M;
335 rtw_write32(Adapter, REG_RRSR, value32);
336
337 /* CF-END Threshold */
338
339 /* SIFS (used in NAV) */
340 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
341 rtw_write16(Adapter, REG_SPEC_SIFS, value16);
342
343 /* Retry Limit */
344 value16 = _LRL(0x30) | _SRL(0x30);
345 rtw_write16(Adapter, REG_RL, value16);
346 }
347
_InitEDCA(struct adapter * Adapter)348 static void _InitEDCA(struct adapter *Adapter)
349 {
350 /* Set Spec SIFS (used in NAV) */
351 rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
352 rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
353
354 /* Set SIFS for CCK */
355 rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
356
357 /* Set SIFS for OFDM */
358 rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
359
360 /* TXOP */
361 rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
362 rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
363 rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
364 rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
365 }
366
_InitRetryFunction(struct adapter * Adapter)367 static void _InitRetryFunction(struct adapter *Adapter)
368 {
369 u8 value8;
370 int res;
371
372 res = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL, &value8);
373 if (res)
374 return;
375
376 value8 |= EN_AMPDU_RTY_NEW;
377 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
378
379 /* Set ACK timeout */
380 rtw_write8(Adapter, REG_ACKTO, 0x40);
381 }
382
383 /*-----------------------------------------------------------------------------
384 * Function: usb_AggSettingTxUpdate()
385 *
386 * Overview: Separate TX/RX parameters update independent for TP detection and
387 * dynamic TX/RX aggreagtion parameters update.
388 *
389 * Input: struct adapter *
390 *
391 * Output/Return: NONE
392 *
393 * Revised History:
394 * When Who Remark
395 * 12/10/2010 MHC Separate to smaller function.
396 *
397 *---------------------------------------------------------------------------*/
usb_AggSettingTxUpdate(struct adapter * Adapter)398 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
399 {
400 u32 value32;
401 int res;
402
403 if (Adapter->registrypriv.wifi_spec)
404 return;
405
406 res = rtw_read32(Adapter, REG_TDECTRL, &value32);
407 if (res)
408 return;
409
410 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
411 value32 |= ((USB_TXAGG_DESC_NUM & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
412
413 rtw_write32(Adapter, REG_TDECTRL, value32);
414 }
415
416 /*-----------------------------------------------------------------------------
417 * Function: usb_AggSettingRxUpdate()
418 *
419 * Overview: Separate TX/RX parameters update independent for TP detection and
420 * dynamic TX/RX aggreagtion parameters update.
421 *
422 * Input: struct adapter *
423 *
424 * Output/Return: NONE
425 *
426 * Revised History:
427 * When Who Remark
428 * 12/10/2010 MHC Separate to smaller function.
429 *
430 *---------------------------------------------------------------------------*/
431 static void
usb_AggSettingRxUpdate(struct adapter * Adapter)432 usb_AggSettingRxUpdate(
433 struct adapter *Adapter
434 )
435 {
436 u8 valueDMA;
437 u8 valueUSB;
438 int res;
439
440 res = rtw_read8(Adapter, REG_TRXDMA_CTRL, &valueDMA);
441 if (res)
442 return;
443
444 res = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION, &valueUSB);
445 if (res)
446 return;
447
448 valueDMA |= RXDMA_AGG_EN;
449 valueUSB &= ~USB_AGG_EN;
450
451 rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
452 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
453
454 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, USB_RXAGG_PAGE_COUNT);
455 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, USB_RXAGG_PAGE_TIMEOUT);
456 }
457
InitUsbAggregationSetting(struct adapter * Adapter)458 static void InitUsbAggregationSetting(struct adapter *Adapter)
459 {
460 /* Tx aggregation setting */
461 usb_AggSettingTxUpdate(Adapter);
462
463 /* Rx aggregation setting */
464 usb_AggSettingRxUpdate(Adapter);
465 }
466
467 /* FIXME: add error handling in callers */
_InitBeaconParameters(struct adapter * Adapter)468 static int _InitBeaconParameters(struct adapter *Adapter)
469 {
470 struct hal_data_8188e *haldata = &Adapter->haldata;
471 int res;
472
473 rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
474
475 /* TODO: Remove these magic number */
476 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
477 rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */
478 rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */
479
480 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
481 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
482 rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
483
484 res = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL + 2, &haldata->RegFwHwTxQCtrl);
485 if (res)
486 return res;
487
488 res = rtw_read8(Adapter, REG_TBTT_PROHIBIT + 2, &haldata->RegReg542);
489 if (res)
490 return res;
491
492 res = rtw_read8(Adapter, REG_CR + 1, &haldata->RegCR_1);
493 if (res)
494 return res;
495
496 return 0;
497 }
498
_BeaconFunctionEnable(struct adapter * Adapter)499 static void _BeaconFunctionEnable(struct adapter *Adapter)
500 {
501 rtw_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1)));
502
503 rtw_write8(Adapter, REG_RD_CTRL + 1, 0x6F);
504 }
505
506 /* Set CCK and OFDM Block "ON" */
_BBTurnOnBlock(struct adapter * Adapter)507 static void _BBTurnOnBlock(struct adapter *Adapter)
508 {
509 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
510 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
511 }
512
_InitAntenna_Selection(struct adapter * Adapter)513 static void _InitAntenna_Selection(struct adapter *Adapter)
514 {
515 struct hal_data_8188e *haldata = &Adapter->haldata;
516 int res;
517 u32 reg;
518
519 if (haldata->AntDivCfg == 0)
520 return;
521
522 res = rtw_read32(Adapter, REG_LEDCFG0, ®);
523 if (res)
524 return;
525
526 rtw_write32(Adapter, REG_LEDCFG0, reg | BIT(23));
527 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
528
529 if (rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
530 haldata->CurAntenna = Antenna_A;
531 else
532 haldata->CurAntenna = Antenna_B;
533 }
534
hw_var_set_macaddr(struct adapter * Adapter,u8 * val)535 static void hw_var_set_macaddr(struct adapter *Adapter, u8 *val)
536 {
537 u8 idx = 0;
538 u32 reg_macid;
539
540 reg_macid = REG_MACID;
541
542 for (idx = 0; idx < 6; idx++)
543 rtw_write8(Adapter, (reg_macid + idx), val[idx]);
544 }
545
rtl8188eu_hal_init(struct adapter * Adapter)546 u32 rtl8188eu_hal_init(struct adapter *Adapter)
547 {
548 u8 value8 = 0;
549 u16 value16;
550 u32 status = _SUCCESS;
551 int res;
552 struct hal_data_8188e *haldata = &Adapter->haldata;
553 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
554 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
555 u32 reg;
556
557 if (Adapter->pwrctrlpriv.bkeepfwalive) {
558 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
559 PHY_IQCalibrate_8188E(Adapter, true);
560 } else {
561 PHY_IQCalibrate_8188E(Adapter, false);
562 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
563 }
564
565 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
566 PHY_LCCalibrate_8188E(Adapter);
567
568 goto exit;
569 }
570
571 status = rtl8188eu_InitPowerOn(Adapter);
572 if (status == _FAIL)
573 goto exit;
574
575 /* Save target channel */
576 haldata->CurrentChannel = 6;/* default set to 6 */
577
578 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
579 /* HW GPIO pin. Before PHY_RFConfig8192C. */
580 /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
581
582 _InitQueueReservedPage(Adapter);
583 _InitQueuePriority(Adapter);
584 _InitPageBoundary(Adapter);
585 _InitTransferPageSize(Adapter);
586
587 _InitTxBufferBoundary(Adapter, 0);
588
589 status = rtl8188e_firmware_download(Adapter);
590
591 if (status != _SUCCESS) {
592 Adapter->bFWReady = false;
593 haldata->fw_ractrl = false;
594 return status;
595 } else {
596 Adapter->bFWReady = true;
597 haldata->fw_ractrl = false;
598 }
599 /* Initialize firmware vars */
600 Adapter->pwrctrlpriv.bFwCurrentInPSMode = false;
601 haldata->LastHMEBoxNum = 0;
602
603 status = PHY_MACConfig8188E(Adapter);
604 if (status == _FAIL)
605 goto exit;
606
607 /* */
608 /* d. Initialize BB related configurations. */
609 /* */
610 status = PHY_BBConfig8188E(Adapter);
611 if (status == _FAIL)
612 goto exit;
613
614 status = phy_RF6052_Config_ParaFile(Adapter);
615 if (status == _FAIL)
616 goto exit;
617
618 status = rtl8188e_iol_efuse_patch(Adapter);
619 if (status == _FAIL)
620 goto exit;
621
622 _InitTxBufferBoundary(Adapter, TX_PAGE_BOUNDARY_88E);
623
624 status = InitLLTTable(Adapter, TX_PAGE_BOUNDARY_88E);
625 if (status == _FAIL)
626 goto exit;
627
628 /* Get Rx PHY status in order to report RSSI and others. */
629 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
630
631 _InitInterrupt(Adapter);
632 hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr);
633 _InitNetworkType(Adapter);/* set msr */
634 _InitWMACSetting(Adapter);
635 _InitAdaptiveCtrl(Adapter);
636 _InitEDCA(Adapter);
637 _InitRetryFunction(Adapter);
638 InitUsbAggregationSetting(Adapter);
639 _InitBeaconParameters(Adapter);
640
641 /* */
642 /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
643 /* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
644 /* */
645 /* Enable MACTXEN/MACRXEN block */
646 res = rtw_read16(Adapter, REG_CR, &value16);
647 if (res)
648 return _FAIL;
649
650 value16 |= (MACTXEN | MACRXEN);
651 rtw_write8(Adapter, REG_CR, value16);
652
653 /* Enable TX Report */
654 /* Enable Tx Report Timer */
655 res = rtw_read8(Adapter, REG_TX_RPT_CTRL, &value8);
656 if (res)
657 return _FAIL;
658
659 rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0)));
660 /* Set MAX RPT MACID */
661 rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
662 /* Tx RPT Timer. Unit: 32us */
663 rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
664
665 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
666
667 rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
668 rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
669
670 /* Keep RfRegChnlVal for later use. */
671 haldata->RfRegChnlVal = rtl8188e_PHY_QueryRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask);
672
673 _BBTurnOnBlock(Adapter);
674
675 invalidate_cam_all(Adapter);
676
677 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
678 PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
679
680 /* Move by Neo for USB SS to below setp */
681 /* _RfPowerSave(Adapter); */
682
683 _InitAntenna_Selection(Adapter);
684
685 /* */
686 /* Disable BAR, suggested by Scott */
687 /* 2010.04.09 add by hpfan */
688 /* */
689 rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
690
691 /* HW SEQ CTRL */
692 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
693 rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
694
695 if (pregistrypriv->wifi_spec)
696 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
697
698 /* Nav limit , suggest by scott */
699 rtw_write8(Adapter, 0x652, 0x0);
700
701 rtl8188e_InitHalDm(Adapter);
702
703 /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
704 /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
705 /* call initstruct adapter. May cause some problem?? */
706 /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
707 /* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
708 /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
709 /* Added by tynli. 2010.03.30. */
710 pwrctrlpriv->rf_pwrstate = rf_on;
711
712 /* enable Tx report. */
713 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL + 1, 0x0F);
714
715 /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
716 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL + 3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
717
718 /* tynli_test_tx_report. */
719 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
720
721 /* enable tx DMA to drop the redundate data of packet */
722 res = rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK, &value16);
723 if (res)
724 return _FAIL;
725
726 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (value16 | DROP_DATA_EN));
727
728 /* 2010/08/26 MH Merge from 8192CE. */
729 if (pwrctrlpriv->rf_pwrstate == rf_on) {
730 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
731 PHY_IQCalibrate_8188E(Adapter, true);
732 } else {
733 PHY_IQCalibrate_8188E(Adapter, false);
734 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
735 }
736
737 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
738
739 PHY_LCCalibrate_8188E(Adapter);
740 }
741
742 /* _InitPABias(Adapter); */
743 rtw_write8(Adapter, REG_USB_HRPWM, 0);
744
745 /* ack for xmit mgmt frames. */
746 res = rtw_read32(Adapter, REG_FWHW_TXQ_CTRL, ®);
747 if (res)
748 return _FAIL;
749
750 rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, reg | BIT(12));
751
752 exit:
753 return status;
754 }
755
CardDisableRTL8188EU(struct adapter * Adapter)756 static void CardDisableRTL8188EU(struct adapter *Adapter)
757 {
758 u8 val8;
759 struct hal_data_8188e *haldata = &Adapter->haldata;
760 int res;
761
762 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
763 res = rtw_read8(Adapter, REG_TX_RPT_CTRL, &val8);
764 if (res)
765 return;
766
767 rtw_write8(Adapter, REG_TX_RPT_CTRL, val8 & (~BIT(1)));
768
769 /* stop rx */
770 rtw_write8(Adapter, REG_CR, 0x0);
771
772 /* Run LPS WL RFOFF flow */
773 HalPwrSeqCmdParsing(Adapter, LPS_ENTER_FLOW);
774
775 /* 2. 0x1F[7:0] = 0 turn off RF */
776
777 res = rtw_read8(Adapter, REG_MCUFWDL, &val8);
778 if (res)
779 return;
780
781 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
782 /* Reset MCU 0x2[10]=0. */
783 res = rtw_read8(Adapter, REG_SYS_FUNC_EN + 1, &val8);
784 if (res)
785 return;
786
787 val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
788 rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, val8);
789 }
790
791 /* reset MCU ready status */
792 rtw_write8(Adapter, REG_MCUFWDL, 0);
793
794 /* YJ,add,111212 */
795 /* Disable 32k */
796 res = rtw_read8(Adapter, REG_32K_CTRL, &val8);
797 if (res)
798 return;
799
800 rtw_write8(Adapter, REG_32K_CTRL, val8 & (~BIT(0)));
801
802 /* Card disable power action flow */
803 HalPwrSeqCmdParsing(Adapter, DISABLE_FLOW);
804
805 /* Reset MCU IO Wrapper */
806 res = rtw_read8(Adapter, REG_RSV_CTRL + 1, &val8);
807 if (res)
808 return;
809
810 rtw_write8(Adapter, REG_RSV_CTRL + 1, (val8 & (~BIT(3))));
811
812 res = rtw_read8(Adapter, REG_RSV_CTRL + 1, &val8);
813 if (res)
814 return;
815
816 rtw_write8(Adapter, REG_RSV_CTRL + 1, val8 | BIT(3));
817
818 /* YJ,test add, 111207. For Power Consumption. */
819 res = rtw_read8(Adapter, GPIO_IN, &val8);
820 if (res)
821 return;
822
823 rtw_write8(Adapter, GPIO_OUT, val8);
824 rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
825
826 res = rtw_read8(Adapter, REG_GPIO_IO_SEL, &val8);
827 if (res)
828 return;
829
830 rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8 << 4));
831 res = rtw_read8(Adapter, REG_GPIO_IO_SEL + 1, &val8);
832 if (res)
833 return;
834
835 rtw_write8(Adapter, REG_GPIO_IO_SEL + 1, val8 | 0x0F);/* Reg0x43 */
836 rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
837 haldata->bMacPwrCtrlOn = false;
838 Adapter->bFWReady = false;
839 }
840
rtl8188eu_hal_deinit(struct adapter * Adapter)841 u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
842 {
843 rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
844 rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
845
846 if (!Adapter->pwrctrlpriv.bkeepfwalive) {
847 if (Adapter->hw_init_completed) {
848 CardDisableRTL8188EU(Adapter);
849 }
850 }
851 return _SUCCESS;
852 }
853
rtl8188eu_inirp_init(struct adapter * Adapter)854 unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
855 {
856 u8 i;
857 struct recv_buf *precvbuf;
858 uint status;
859 struct recv_priv *precvpriv = &Adapter->recvpriv;
860
861 status = _SUCCESS;
862
863 /* issue Rx irp to receive data */
864 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
865 for (i = 0; i < NR_RECVBUFF; i++) {
866 if (!rtw_read_port(Adapter, (unsigned char *)precvbuf)) {
867 status = _FAIL;
868 goto exit;
869 }
870
871 precvbuf++;
872 precvpriv->free_recv_buf_queue_cnt--;
873 }
874
875 exit:
876 return status;
877 }
878
879 /* */
880 /* */
881 /* EEPROM/EFUSE Content Parsing */
882 /* */
883 /* */
884
Hal_EfuseParseMACAddr_8188EU(struct adapter * adapt,u8 * hwinfo,bool AutoLoadFail)885 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
886 {
887 struct eeprom_priv *eeprom = &adapt->eeprompriv;
888
889 if (AutoLoadFail) {
890 eth_random_addr(eeprom->mac_addr);
891 } else {
892 /* Read Permanent MAC address */
893 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
894 }
895 }
896
ReadAdapterInfo8188EU(struct adapter * Adapter)897 int ReadAdapterInfo8188EU(struct adapter *Adapter)
898 {
899 struct eeprom_priv *eeprom = &Adapter->eeprompriv;
900 struct led_priv *ledpriv = &Adapter->ledpriv;
901 u8 *efuse_buf;
902 u8 eeValue;
903 int res;
904
905 /* check system boot selection */
906 res = rtw_read8(Adapter, REG_9346CR, &eeValue);
907 if (res)
908 return res;
909
910 eeprom->bautoload_fail_flag = !(eeValue & EEPROM_EN);
911
912 efuse_buf = kmalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL);
913 if (!efuse_buf)
914 return -ENOMEM;
915 memset(efuse_buf, 0xFF, EFUSE_MAP_LEN_88E);
916
917 if (!(eeValue & BOOT_FROM_EEPROM) && !eeprom->bautoload_fail_flag) {
918 rtl8188e_EfusePowerSwitch(Adapter, true);
919 rtl8188e_ReadEFuse(Adapter, EFUSE_MAP_LEN_88E, efuse_buf);
920 rtl8188e_EfusePowerSwitch(Adapter, false);
921 }
922
923 /* parse the eeprom/efuse content */
924 Hal_EfuseParseIDCode88E(Adapter, efuse_buf);
925 Hal_EfuseParseMACAddr_8188EU(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
926
927 Hal_ReadPowerSavingMode88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
928 Hal_ReadTxPowerInfo88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
929 rtl8188e_EfuseParseChnlPlan(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
930 Hal_EfuseParseXtal_8188E(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
931 Hal_ReadAntennaDiversity88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
932 Hal_ReadThermalMeter_88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag);
933
934 ledpriv->bRegUseLed = true;
935 kfree(efuse_buf);
936 return 0;
937 }
938
UpdateHalRAMask8188EUsb(struct adapter * adapt,u32 mac_id,u8 rssi_level)939 void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
940 {
941 u8 init_rate = 0;
942 u8 networkType, raid;
943 u32 mask, rate_bitmap;
944 u8 shortGIrate = false;
945 int supportRateNum = 0;
946 struct sta_info *psta;
947 struct hal_data_8188e *haldata = &adapt->haldata;
948 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
949 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
950 struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
951
952 if (mac_id >= NUM_STA) /* CAM_SIZE */
953 return;
954 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
955 if (!psta)
956 return;
957 switch (mac_id) {
958 case 0:/* for infra mode */
959 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
960 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
961 raid = networktype_to_raid(networkType);
962 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
963 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0;
964 if (support_short_GI(adapt, &pmlmeinfo->HT_caps))
965 shortGIrate = true;
966 break;
967 case 1:/* for broadcast/multicast */
968 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
969 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
970 networkType = WIRELESS_11B;
971 else
972 networkType = WIRELESS_11G;
973 raid = networktype_to_raid(networkType);
974 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
975 break;
976 default: /* for each sta in IBSS */
977 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
978 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
979 raid = networktype_to_raid(networkType);
980 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
981
982 /* todo: support HT in IBSS */
983 break;
984 }
985
986 rate_bitmap = 0x0fffffff;
987 rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
988
989 mask &= rate_bitmap;
990
991 init_rate = get_highest_rate_idx(mask) & 0x3f;
992
993 if (haldata->fw_ractrl) {
994 mask |= ((raid << 28) & 0xf0000000);
995 psta->ra_mask = mask;
996 mask |= ((raid << 28) & 0xf0000000);
997
998 /* to do ,for 8188E-SMIC */
999 rtl8188e_set_raid_cmd(adapt, mask);
1000 } else {
1001 ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv,
1002 mac_id,
1003 raid,
1004 mask,
1005 shortGIrate
1006 );
1007 }
1008 /* set ra_id */
1009 psta->raid = raid;
1010 psta->init_rate = init_rate;
1011 }
1012
SetBeaconRelatedRegisters8188EUsb(struct adapter * adapt)1013 void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
1014 {
1015 u32 value32;
1016 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
1017 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1018 u32 bcn_ctrl_reg = REG_BCN_CTRL;
1019 int res;
1020 u8 reg;
1021 /* reset TSF, enable update TSF, correcting TSF On Beacon */
1022
1023 /* BCN interval */
1024 rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
1025 rtw_write8(adapt, REG_ATIMWND, 0x02);/* 2ms */
1026
1027 _InitBeaconParameters(adapt);
1028
1029 rtw_write8(adapt, REG_SLOT, 0x09);
1030
1031 res = rtw_read32(adapt, REG_TCR, &value32);
1032 if (res)
1033 return;
1034
1035 value32 &= ~TSFRST;
1036 rtw_write32(adapt, REG_TCR, value32);
1037
1038 value32 |= TSFRST;
1039 rtw_write32(adapt, REG_TCR, value32);
1040
1041 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
1042 rtw_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
1043 rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
1044
1045 _BeaconFunctionEnable(adapt);
1046
1047 rtw_resume_tx_beacon(adapt);
1048
1049 res = rtw_read8(adapt, bcn_ctrl_reg, ®);
1050 if (res)
1051 return;
1052
1053 rtw_write8(adapt, bcn_ctrl_reg, reg | BIT(1));
1054 }
1055
rtl8188eu_init_default_value(struct adapter * adapt)1056 void rtl8188eu_init_default_value(struct adapter *adapt)
1057 {
1058 struct hal_data_8188e *haldata = &adapt->haldata;
1059 struct pwrctrl_priv *pwrctrlpriv;
1060 u8 i;
1061
1062 pwrctrlpriv = &adapt->pwrctrlpriv;
1063
1064 /* init default value */
1065 haldata->fw_ractrl = false;
1066 if (!pwrctrlpriv->bkeepfwalive)
1067 haldata->LastHMEBoxNum = 0;
1068
1069 /* init dm default value */
1070 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
1071 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
1072 haldata->pwrGroupCnt = 0;
1073 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
1074 for (i = 0; i < HP_THERMAL_NUM; i++)
1075 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
1076 }
1077