1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "reg_helper.h"
29 #include <linux/delay.h>
30
31 #include "renoir_ip_offset.h"
32
33 #include "mp/mp_12_0_0_offset.h"
34 #include "mp/mp_12_0_0_sh_mask.h"
35
36 #include "rn_clk_mgr_vbios_smu.h"
37
38 #define REG(reg_name) \
39 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
40
41 #define FN(reg_name, field) \
42 FD(reg_name##__##field)
43
44 #include "logger_types.h"
45 #undef DC_LOGGER
46 #define DC_LOGGER \
47 CTX->logger
48 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
49
50 #define VBIOSSMC_MSG_TestMessage 0x1
51 #define VBIOSSMC_MSG_GetSmuVersion 0x2
52 #define VBIOSSMC_MSG_PowerUpGfx 0x3
53 #define VBIOSSMC_MSG_SetDispclkFreq 0x4
54 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5
55 #define VBIOSSMC_MSG_PowerDownGfx 0x6
56 #define VBIOSSMC_MSG_SetDppclkFreq 0x7
57 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x8
58 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x9
59 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA
60 #define VBIOSSMC_MSG_GetFclkFrequency 0xB
61 #define VBIOSSMC_MSG_SetDisplayCount 0xC
62 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
63 #define VBIOSSMC_MSG_UpdatePmeRestore 0xE
64 #define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF
65
66 #define VBIOSSMC_Status_BUSY 0x0
67 #define VBIOSSMC_Result_OK 0x1
68 #define VBIOSSMC_Result_Failed 0xFF
69 #define VBIOSSMC_Result_UnknownCmd 0xFE
70 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
71 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC
72
73 /*
74 * Function to be used instead of REG_WAIT macro because the wait ends when
75 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
76 * won't work with REG_WAIT.
77 */
rn_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)78 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
79 {
80 uint32_t res_val = VBIOSSMC_Status_BUSY;
81
82 do {
83 res_val = REG_READ(MP1_SMN_C2PMSG_91);
84 if (res_val != VBIOSSMC_Status_BUSY)
85 break;
86
87 if (delay_us >= 1000)
88 msleep(delay_us/1000);
89 else if (delay_us > 0)
90 udelay(delay_us);
91 } while (max_retries--);
92
93 return res_val;
94 }
95
96
rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,unsigned int msg_id,unsigned int param)97 static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
98 unsigned int msg_id,
99 unsigned int param)
100 {
101 uint32_t result;
102
103 result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
104
105 if (result != VBIOSSMC_Result_OK)
106 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
107
108 if (result == VBIOSSMC_Status_BUSY) {
109 return -1;
110 }
111
112 /* First clear response register */
113 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
114
115 /* Set the parameter register for the SMU message, unit is Mhz */
116 REG_WRITE(MP1_SMN_C2PMSG_83, param);
117
118 /* Trigger the message transaction by writing the message ID */
119 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
120
121 result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
122
123 ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
124
125 /* Actual dispclk set is returned in the parameter register */
126 return REG_READ(MP1_SMN_C2PMSG_83);
127 }
128
rn_vbios_smu_get_smu_version(struct clk_mgr_internal * clk_mgr)129 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
130 {
131 return rn_vbios_smu_send_msg_with_param(
132 clk_mgr,
133 VBIOSSMC_MSG_GetSmuVersion,
134 0);
135 }
136
137
rn_vbios_smu_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_dispclk_khz)138 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
139 {
140 int actual_dispclk_set_mhz = -1;
141 struct dc *dc = clk_mgr->base.ctx->dc;
142 struct dmcu *dmcu = dc->res_pool->dmcu;
143
144 /* Unit of SMU msg parameter is Mhz */
145 actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
146 clk_mgr,
147 VBIOSSMC_MSG_SetDispclkFreq,
148 khz_to_mhz_ceil(requested_dispclk_khz));
149
150 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
151 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
152 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
153 dmcu->funcs->set_psr_wait_loop(dmcu,
154 actual_dispclk_set_mhz / 7);
155 }
156 }
157
158 // pmfw always set clock more than or equal requested clock
159 if (!IS_DIAG_DC(dc->ctx->dce_environment))
160 ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz));
161
162 return actual_dispclk_set_mhz * 1000;
163 }
164
rn_vbios_smu_set_dprefclk(struct clk_mgr_internal * clk_mgr)165 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
166 {
167 int actual_dprefclk_set_mhz = -1;
168
169 actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(
170 clk_mgr,
171 VBIOSSMC_MSG_SetDprefclkFreq,
172 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));
173
174 /* TODO: add code for programing DP DTO, currently this is down by command table */
175
176 return actual_dprefclk_set_mhz * 1000;
177 }
178
rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_dcfclk_khz)179 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
180 {
181 int actual_dcfclk_set_mhz = -1;
182
183 if (clk_mgr->smu_ver < 0x370c00)
184 return actual_dcfclk_set_mhz;
185
186 actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
187 clk_mgr,
188 VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
189 khz_to_mhz_ceil(requested_dcfclk_khz));
190
191 #ifdef DBG
192 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
193 #endif
194
195 return actual_dcfclk_set_mhz * 1000;
196 }
197
rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_min_ds_dcfclk_khz)198 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
199 {
200 int actual_min_ds_dcfclk_mhz = -1;
201
202 if (clk_mgr->smu_ver < 0x370c00)
203 return actual_min_ds_dcfclk_mhz;
204
205 actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
206 clk_mgr,
207 VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
208 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
209
210 return actual_min_ds_dcfclk_mhz * 1000;
211 }
212
rn_vbios_smu_set_phyclk(struct clk_mgr_internal * clk_mgr,int requested_phyclk_khz)213 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
214 {
215 rn_vbios_smu_send_msg_with_param(
216 clk_mgr,
217 VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
218 khz_to_mhz_ceil(requested_phyclk_khz));
219 }
220
rn_vbios_smu_set_dppclk(struct clk_mgr_internal * clk_mgr,int requested_dpp_khz)221 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
222 {
223 int actual_dppclk_set_mhz = -1;
224 struct dc *dc = clk_mgr->base.ctx->dc;
225
226 actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
227 clk_mgr,
228 VBIOSSMC_MSG_SetDppclkFreq,
229 khz_to_mhz_ceil(requested_dpp_khz));
230
231 if (!IS_DIAG_DC(dc->ctx->dce_environment))
232 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));
233
234 return actual_dppclk_set_mhz * 1000;
235 }
236
rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal * clk_mgr,enum dcn_pwr_state state)237 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state)
238 {
239 int disp_count;
240
241 if (state == DCN_PWR_STATE_LOW_POWER)
242 disp_count = 0;
243 else
244 disp_count = 1;
245
246 rn_vbios_smu_send_msg_with_param(
247 clk_mgr,
248 VBIOSSMC_MSG_SetDisplayCount,
249 disp_count);
250 }
251
rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal * clk_mgr,bool enable)252 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
253 {
254 rn_vbios_smu_send_msg_with_param(
255 clk_mgr,
256 VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
257 enable);
258 }
259
rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal * clk_mgr)260 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
261 {
262 rn_vbios_smu_send_msg_with_param(
263 clk_mgr,
264 VBIOSSMC_MSG_UpdatePmeRestore,
265 0);
266 }
267
rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal * clk_mgr)268 int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)
269 {
270 return rn_vbios_smu_send_msg_with_param(
271 clk_mgr,
272 VBIOSSMC_MSG_IsPeriodicRetrainingDisabled,
273 1); // if PMFW doesn't support this message, assume retraining is disabled
274 // so we only use most optimal watermark if we know retraining is enabled.
275 }
276